Signal test

Abstract

To provide a method and a system, for testing at least one source by a destination.SOLUTION: A method includes the steps of: supplying, by a destination 601, a test signal T toward at least one source 602; at the at least one source 602, determining a second output signal o2 based on a first output signal o1 and the test signal T via a first function f1; conveying the second output signal o2 to the destination 601; at the destination 601, determining a received signal rS based on the second output signal o2 received from the at least one source 602 and based on the test signal T via a second function f2; and determining whether an error has occurred based on the received signal rS.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] In a communication system, a plurality of transmitters transmit information towards a destination. Each transmitter can include a driver which may be a safety-critical logic circuit or may include a safety-critical logic circuit. This safety-critical logic circuit can include a safety mechanism that enables detection of internal faults of the driver.

[0002] Furthermore, it is also an issue to be aware of possible faults that can occur on the communication link between the transmitter and the destination. There are multiple possibilities for such faults on the signal line, and a prominent one is the stack during a fault. This is associated with a permanent logic state that is transmitted across the line without being able to switch to another logic state. Particularly with regard to safety requirements, it is also extremely important to be aware of such a stack during any such fault. If the line is used to transmit an alarm notification indicated by the logic state 1, and the line is stacked at the logic state 0, the destination will not be able to become aware of any alarm via this line.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Therefore, here, the problem is to enable an improved signal test that particularly enhances the safety of a device, system, or any type of implementation. In particular, here, the problem is to effectively become aware of a stack during a fault that can occur on the connection of a communication system.

Means for Solving the Problems

[0004] This problem is solved by the characterizing part of the independent claims. Further embodiments will become apparent from the dependent claims.

[0005] The examples proposed herein may, in particular, be based on at least one of the following solutions. Combinations of the following features may be used to obtain the desired results. The features of the method can be combined with any features of a device, apparatus, or system, and vice versa.

[0006] A method is provided for testing at least one sender based on the destination, and this method comprises the following steps: - The destination supplies a test signal to at least one source, - The steps of determining a second output signal based on a first output signal and a test signal via a first function at at least one source, - A step of transporting the second output signal to the destination, - The steps of determining a received signal at the destination based on a second output signal received from at least one source and based on a test signal via a second function, - A step of determining whether or not an error has occurred based on the received signal, Includes.

[0007] Such testing of the sender may, in particular, be directed towards the connection between the sender and the destination. In this relationship, if an error occurs in the connection to the destination, it may appear that the sender is faulty.

[0008] Particularly preferably, the first function is implemented at the signal source boundary toward the destination line. Thereafter, the first output signal is converted to a second output signal using the first function (and a test signal).

[0009] In particular, the proposed solution makes it possible to detect any jamming of signals in the event of any fault in the signal being carried over the entire connection (line) from at least one source to the destination.

[0010] This approach enhances reliability for safety-critical applications, particularly with respect to alarm notifications transmitted from at least one source to a destination.

[0011] Therefore, the first function f1 can be expressed as a function of the test signal and the first output signal, as follows: o2=f1(T,o1) Here, f1 is the first function, T is the test signal, o1 is the first output signal, and o2 is the second output signal.

[0012] The operations based on the second function f2 can be summarized as follows: rS=f2(T,o2) Here, f2 is a second function, and rS is a received signal that can be used for further processing. If function f1 is the inverse function of function f2, then the signal rS can be used for further processing.

[0013] If the test signal is switched, i.e., changed from 0 to 1 or vice versa, the two subsequent test periods can reveal the stack in case of failure. This is because signals rS and o2 should be inverted between the two subsequent test periods having different test values ​​T.

[0014] According to one embodiment, this method is The process further includes determining whether an error occurred based on the received signal and on preceding received signals for different values ​​of the test signal.

[0015] According to one embodiment, this method is - The destination supplies different test signals to at least one source to switch the test mode on and off. - A step of determining a second output signal for each test signal at at least one source, - A step of transporting the second output signal to the destination, - At the destination, determining a received signal for each test signal based on the second output signal; - When the received signals for different test signals satisfy a predetermined condition, determining that an error has occurred, and when not, determining that no error has occurred; and further including.

[0016] According to one embodiment, the predetermined condition is inversion or non - inversion of the received signal.

[0017] According to one embodiment, the first function is the inverse function of the second function.

[0018] According to one embodiment, the first function is an XOR function, and the second function is also an XOR function.

[0019] According to one embodiment, the test signal is a binary signal.

[0020] According to one embodiment, the method is - The destination supplying a test signal including at least two binary signals to at least one source; - At at least one source, determining a test signal combined by a logic function circuit; - At at least one source, determining a second output signal based on the first output signal and the test signal combined via the first function; - Carrying the second output signal to the destination; - At the destination, determining a received signal based on the second output signal received from at least one source and based on the test signal via the second function; - Determining whether an error has occurred based on the received signal; and further including.

[0021] For example, the test signal can include binary signals A and B. The logic function circuit at the source determines a test signal combined as a logic function of binary signals A and B. Then, this combined test signal is used by a first function to determine a second output signal. At the destination, binary signals A and B can be used to determine whether an error has occurred according to the received signal. This approach advantageously enables determination of the stack in case of a failure of either binary signal A or B.

[0022] According to one embodiment, the method further includes - determining whether an error has occurred based on the received signal by applying a time delay filter that takes into account the time delay until the signal reaches at least one source and destination.

[0023] According to one embodiment, the time delay filter is provided at the destination.

[0024] According to one embodiment, the test period is determined such that the test mode is activated or deactivated over a duration long enough for the signal to reach at least one source and / or destination.

[0025] According to one embodiment, the destination is one of the following, namely - a microcontroller, - a security management unit, - an electronic control unit, and is one of these.

[0026] According to one embodiment, the source is one of the following, namely - a driver, - a sensor, - an alarm device, - an integrated circuit function unit, and is one of these or includes at least one of these.

[0027] Furthermore, a system is provided for testing at least one source depending on the destination, where the destination is configured to supply a test signal to at least one source. -Here, at least one sender, -The second output signal is determined based on the first output signal and the test signal via the first function. - Arranged to carry the second output signal to the destination, -Here, the recipient is, - Based on a second output signal received from at least one source, and based on a test signal via a second function, the received signal is determined. - Further configuration is in place to determine whether or not an error has occurred based on the received signal.

[0028] According to one embodiment, the system is one of the following, namely, - Safety-related data recording unit, -Safety-related data processing unit, - Data calculation safety-related control unit, It includes at least one of the following.

[0029] Multiple embodiments are shown in the drawings and described with reference to these drawings. These drawings are for illustrative purposes only, and therefore only the embodiments necessary to understand the basic principles are described. These drawings are not necessarily to scale. In these drawings, the same reference numerals represent similar functional parts. [Brief explanation of the drawing]

[0030] [Figure 1] This diagram illustrates communication between multiple sources and destinations. [Figure 2] A block diagram is shown that enables safety-critical testing of various source-to-destination 201 circuits. [Figure 3]An exemplary block diagram is shown, including a destination and two sources, where the test signal is switched in combination with an XOR function at each of the sources. [Figure 4] In particular, an exemplary signal diagram for the arrangement configuration of Figure 3, showing test signal T, signal X, and signal Y over time, is provided. [Figure 5] An alternative and exemplary block diagram is shown, including a destination and two sources, where binary signals A and B are carried from the destination to the sources and coupled to a signal T that feeds into an XOR function in the logic function circuit at each source. [Figure 6] A schematic block diagram is shown illustrating a single source communicating with a destination via a circuit. [Modes for carrying out the invention]

[0031] Figure 1 shows an exemplary diagram visualizing communication between source 102 and destination 101, and between source 104 and destination 101. Source 102 includes driver 103 connected to destination 101 via line 111. Source 104 includes driver 105 connected to destination 101 via line 112. Destination 101 receives signal X from driver 103 and signal Y from driver 105. For destination 101, it is a common motivation to notice any fault occurring on lines 111 and 112 (see exemplary fault 121 on line 111).

[0032] Figure 2 shows a block diagram that enables safety-critical testing of various source 202,204 and destination 201 circuits.

[0033] Source 202 and Source 204 each communicate with Destination 201 via a signaling line. Source 202 includes driver 203, and Source 204 includes driver 205. Destination 201 receives signal X from driver 203 and signal Y from driver 205.

[0034] Additionally, the destination may provide test signals T to sources 202 and 204.

[0035] The logic function circuit 211 is implemented in the transmitter 202, and in particular at the signal source boundary of the transmitter 202.

[0036] The logic function circuit 212 is implemented in the transmitter 204, and in particular at the signal source boundary of the transmitter 204.

[0037] The logic function circuits 213a and 213b are implemented at destination 201, and in particular at the signal destination boundary of destination 201 toward sources 202 and 204. Note that logic function circuits 213a and 213b can be implemented as a single circuit.

[0038] Logic function circuits 211 and 212 can each implement the function FUNC, and logic function circuits 213a and 213b can each implement the inverse function I_FUNC, in this case, FUNC display I FUNC -1 That is the case.

[0039] For example, the exclusive OR function (XOR) can be used as a function, and here, the XOR function is also its inverse function.

[0040] The function FUNC uses the output of each driver and the test signal T to derive the signal to be carried toward destination 201. If there are no errors, the signal received at the destination is a valid signal.

[0041] As an optional option, the following signal execution time (time delay, TD) across various lines, i.e., -Time delay a for signal X from source 202 to destination 201 (see box 221), -Time delay b (see box 222) for the test signal T from destination 201 to source 202, -Time delay c for signal Y from source 204 to destination 201 (see box 223), -Time delay d for the test signal T from destination 201 to source 204 (see box 224) This may be taken into consideration.

[0042] To synchronize the effects of the test signal T at the sources 202 and 204 and the destination 201, the logic function circuits 213a and 213b are each provided with signal execution time compensation filters (time delay filters, TDFs) 225 and 226, respectively. Filter 225 compensates for a time delay a+b, and filter 226 compensates for a time delay c+d.

[0043] Signal T is also carried to, or available to, the functional circuits 213a and 213b, as well as filters 225 and 226, respectively.

[0044] A signal line test can be initiated at destination 201 using a test signal T, which may be switched between test mode (also referred to as "test mode on") and normal mode (also referred to as "test mode off"). Preferably, the effects induced by the test signal T are completely transparent through the implementation of functions FUNC and I_FUNC, as will be shown in more detail below.

[0045] Figure 3 shows an exemplary block diagram including a destination 301, a source 302 with driver 303, and a source 304 with driver 305. A logic function circuit 311 is provided in source 302, and a logic function circuit 312 is provided in source 304. Each logic function circuit 311, 312 implements an exclusive OR (XOR) function as the function FUNC, supplied by a test signal T from destination 301.

[0046] Destination 301 includes a signal line test function that implements the function I_FUNC, which is also an XOR function. This signal line test function may be implemented in hardware and / or software.

[0047] The logic function circuits 311 and 312 are preferably implemented at the signal source boundaries of each source 302 and 304 toward the line toward the destination 301.

[0048] A signaling circuit test can be initiated by the destination via a test signal T. The test signal T can be used to switch between test mode and normal mode (i.e., switch test mode on and off).

[0049] Signal X is received at destination 301 from source 302, and signal Y is received at destination 301 from source 304.

[0050] This solution has the advantage of improving coverage of potential failures, particularly the ability to recognize stacks during failures. Another advantage is that this solution has little to no impact on driver startup time, and the test is transparent to the use of communication lines between each source 302, 304 and destination 301. Furthermore, the setup does not require error intervention or individual line evaluations that would lead to wasted dedicated time.

[0051] Optionally, destination 301 may be a safety management unit (SMU), and signals X and Y may be alarm signals provided by sources 302 and 304, respectively. Each of drivers 303 and 305 may implement at least one safety mechanism (SM). This safety mechanism then issues an alarm that is XOR-coupled with test signal T by logic function circuits 311 and 312. The SMU may utilize a bit that is used as test signal T and to be carried to sources 302 and 304. This bit (test signal T) can be switched to detect a stack in the event of a fault on the communication line.

[0052] Figure 4 shows an exemplary signal circuit diagram for the apparatus in Figure 3. This signal circuit diagram includes test signal T, signal X, and signal Y over time.

[0053] According to the XOR function, the signals supplied by each transmitter 302,304 remain unchanged if the test signal T is 0, and are inverted if the test signal T is 1.

[0054] In the example shown in Figure 4, the starting point is T=X=Y=0. At time t1, the test signal T is set to 1. Due to a time delay TD1 introduced by the connection between destination 301 and source 302, signal X is inverted to X=1 at time t2. Consequently, due to a time delay TD2 introduced by the connection between destination 301 and source 304, signal Y is inverted to Y=1 at time t3.

[0055] At time t4, the test signal T is set to 0. Due to time delay TD1, signal X is inverted to X=0 at time t5, and due to time delay TD2, signal Y is inverted to Y=0 at time t6.

[0056] The signal may be sampled at time intervals after the longest time delay has elapsed and before the next test signal T is switched to 0 or 1. In the example in Figure 4, the sampling times are shown as s1, s2, and s3. In the case of periodic or clock-based approaches, s1 may be referred to as the first sampling interval, s2 as the second sampling interval, and so on. The time difference between sampling times may be constant or substantially constant.

[0057] It should be noted that any periodicity can be used to perform the circuit tests described herein, that is, to switch the test signal T between consecutive time intervals.

[0058] The following tests can be performed by destination 301. Test 1: Compare the signal value at sampling time s2 with the signal value at sampling time s1. This test passes if each signal X and Y is inverted. If inversion cannot be determined at destination 301, a fault has occurred (for example, a fault-induced stack on each line, or an actual signal transition in X or Y indicating a fault at the source). Test 2: Compare the signal value at sampling time s3 with the signal value at sampling time s2. This test passes if each signal X and Y is not inverted. If inversion is determined at destination 301, a fault has occurred (e.g., a fault-induced stack on each line, or an actual signal transition in X or Y indicating a fault).

[0059] It should be noted that signals T, X, and Y may be synchronized with the clock signal CLK, particularly by utilizing the falling and / or rising edges of the clock signal, or may be synchronized based on the clock signal CLK.

[0060] The test signal T is switched to "test mode," meaning T=1 for sampling at time s2. Therefore, the signal X at time s1 is expected to be different from the signal X at time s2. X[s1]≠X[s2]? (1)

[0061] This can be easily checked by combining the received signal X with the test signal T via the XOR function, using destination 301. If the results are identical, no error exists; otherwise, an error has occurred. That is,

number

[0062] If no error occurs, equation (2) is true. If signal X is stacked at 0 at time t2, equation (2) is false. If signal Y is stacked at 1 before time t1, no inversion occurs for test signal T to switch from 0 to 1 at time t1, and equation (2) is false.

[0063] Therefore, this mechanism works not only for other test periods but also for other signals such as signal Y.

[0064] Furthermore, a stack in the event of a failure in test signal T can be detected because the inversion by logic function circuits 311 and 312 is not triggered. However, since destination 301 expects such an inversion, equation (2) subsequently becomes false for both signals X and Y.

[0065] Detecting a potential stack in case of failure based on the connection between sources 302,304 and destination 301 is advantageous because destination 301 can still be used even if at least one connection to sources 302,304 is poor.

[0066] Please note that the destination may be a management system or a (multipurpose) device such as a microcontroller.

[0067] Figure 5 shows an alternative and exemplary block diagram including a destination 501, a source 502 with a driver 503, and a source 504 with a driver 505. A logic function circuit 511a and a test logic circuit 511b are provided in source 502, and a logic function circuit 512a and a test logic circuit 512b are provided in source 504. Each logic function circuit 511a, 512a implements an XOR function as the function FUNC. The inverse function I_FUNC may also be an XOR function and may be part of the implementation of destination 501.

[0068] Test signals A and B are supplied to test logic circuits 511b and 512b by destination 501. Test logic circuit 511b determines test signal T based on signals A and B and supplies this test signal T to logic function circuit 511a. Similarly, test logic circuit 512b determines test signal T based on signals A and B and supplies this test signal T to logic function circuit 512a. If both test logic circuits 511b and 512b receive the same test signals A and B, then test signal T may be the same.

[0069] The test signal T may be determined based on test signals A and B as follows:

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[0070] Signal X is received at destination 501 from source 502, and signal Y is received at destination 501 from source 504.

[0071] Therefore, destination 501 generates signals A and B, and test logic circuits 511b, 512b determine a test signal T based on signals A and B. This test signal T is used by logic function circuits 511a, 512a to trigger either normal mode (T=0) or test mode (T=1). At destination 501, the received X,Y signals are used to obtain the same test signal, i.e., the same signal provided by drivers 503, 505, i.e.,

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number

number

[0072] According to the XOR function of logic circuits 511a and 512a, the signals supplied by each transmitter 502 and 504 remain unchanged when the test signal T is 0 (normal mode), and are inverted when the test signal T is 1 (test mode). As shown in the table above, the test mode is initiated by destination 501 with the settings A=1 and B=0, and the normal mode is initiated by destination 501 with the settings A=0 and B=1.

[0073] Preferably, some kind of stacking in the event of a fault in test signals A and / or B becomes apparent, namely, -If signal A is stuck at 0, it is not possible to enter test mode. This is evident by applying the inverse function I_FUNC to the received signals X and Y in the initiated test mode (but not converted to T=1 due to the failure of signal A) at destination 501. -If signal A is stuck at 1, it cannot enter normal mode. This is evident by applying the inverse function I_FUNC to the received signals X and Y in normal mode, which have been initiated at destination 501 (but are not converted to T=0 due to the fault of signal A). -If signal B is stuck at 0, it cannot enter normal mode. This is evident by applying the inverse function I_FUNC to the received signals X and Y in normal mode, which have been initiated at destination 501 (but are not converted to T=0 due to the failure of signal B). -If signal B is stuck at 1, it is not possible to enter test mode. This is evident by applying the inverse function I_FUNC to the received signals X and Y in the initiated test mode (but not converted to T=1 due to the fault of signal B) at destination 501.

[0074] As shown above, the inverse function I_FUNC applied at the destination is also an XOR function. If test mode is triggered, signals X and Y are XORed by 1 (i.e., if test mode is set to 1, signals X and Y are inverted). Otherwise (i.e., in normal mode), the inverse function I_FUNC does not change signals X and Y.

[0075] Figure 6 is a block diagram illustrating an exemplary solution provided by the approach described herein. Here, only a single source 602 is shown communicating with destination 601 via line 605. This line 605 may be implemented as a physical or logical connection path.

[0076] However, this approach can be applied depending on the number of sources communicating with destination 601.

[0077] The source 602 includes a driver 603, and a logic function circuit 612 is provided as an interface to line 605. On the other side of line 605, a logic function circuit 611 is provided as an interface to destination 601.

[0078] The test signal T is supplied to the logic function circuit 612 via destination 601. The test signal T is also made available to the logic function circuit 611 (indicated by a dashed line). The test signal T can be carried to the source via a dedicated or shared medium. In some embodiments, bus messages may be used for the transmission of the test signal T.

[0079] In the example shown in Figure 6, the driver 603 provides a first output o1 to the logic function circuit 611, which then determines a second output o2 based on a function f1 based on a test signal T, as follows: o2=f1(T,o1)

[0080] Next, the second output o2 is carried across the line 605 to the logic function circuit 612 in the receiver, which determines the received signal rS based on the second function f2 as follows: rS=f2(T,o2)

[0081] The second function f2 may be inverted relative to the first function f1. If an XOR function is used, this XOR function can be used as both function f1 and function f2.

[0082] The test can be performed using two successive time intervals with different test signals T (T=0 and T=1). Switching the test signal T should also invert the second output signal o2 during the second time interval. If the second output signal o2 is not inverted during the second time interval, this can be detected at the destination and may be an indication of a fault-tolerant stack.

[0083] Optionally, time delays introduced by the signal execution time may be considered in order to determine an appropriate time for sampling the signal.

[0084] Alternatively, the test signal T may include multiple signals, and additional logic circuits may be provided at the source to derive the test signal based on these multiple signals. See Figure 5 above.

[0085] In one or more examples, the functions described herein may be implemented in hardware, such as a specific hardware component or processor, at least in part. More generally, these techniques may be implemented in hardware, a processor, software, firmware, or any combination thereof. When implemented in software, these functions may be stored on a computer-readable medium or transmitted as one or more instructions or codes and executed by a hardware-based processing unit. The computer-readable medium may include a computer-readable medium corresponding to a tangible medium such as a data recording medium, or a communication medium including any medium that facilitates the transfer of a computer program from one location to another, for example, according to a communication protocol. Thus, the computer-readable medium can generally correspond to (1) a non-transient, tangible computer-readable recording medium, or (2) a communication medium such as a signal or carrier wave. The data recording medium may be any available medium that can be accessed by one or more computers or by one or more processors to retrieve instructions, codes and / or data structures for implementing the techniques described herein. A computer program product may include a computer-readable medium.

[0086] Such computer-readable recording media may include, but are not limited to, RAM, ROM, EEPROM, CD-ROM, or other optical recording disks, magnetic recording disks or other magnetic recording devices, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and is accessible by a computer. Any connection is also preferably referred to as a computer-readable medium, i.e., a computer-readable transfer medium. For example, if instructions are transferred from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted-pair cable, digital subscriber line (DSL), or wireless technologies such as infrared, radio, or microwave, these coaxial cables, fiber optic cables, twisted-pair cables, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of a medium. However, it should be understood that computer-readable recording media and data recording media do not include connections, carriers, signals, or other transient mediums, but rather are directed toward non-transient, tangible recording media. As used herein, the terms "disk" and "disc" include compact discs (CDs), laser discs, optical discs, digital multipurpose discs (DVDs), floppy disks, and Blu-ray discs, where a "disk" typically reproduces data magnetically, while a "disc" reproduces data optically using a laser. The above combinations should also be included within the scope of computer-readable media.

[0087] Instructions may be executed by one or more processors, such as a central processing unit (CPU), a digital signal processor (DSP), a general-purpose microprocessor, an application-specific integrated circuit (ASIC), a field-programmable logic array (FPGA), or other equivalent integrated or discrete logic circuits. Thus, the term “processor” as used herein may refer to any of the aforementioned structures, or any other structure suitable for implementing the technologies described herein. Additionally, in some embodiments, the functions described herein may be provided within dedicated hardware and / or software modules configured for encoding and decoding, or incorporated into a composite codec. Furthermore, these technologies can also be fully implemented in one or more circuits or logic elements.

[0088] The technology of this disclosure may be implemented in a wide variety of devices or apparatus, including wireless handsets, integrated circuits (ICs), or sets of ICs (e.g., chipsets). Various components, modules, or units are described in this disclosure to highlight the functional aspects of a device configured to perform the disclosed technology, but implementation by different hardware units is not necessarily required. Rather, as described above, the various units may be combined into a single hardware unit, or they may be provided by a collection of interoperable hardware units, including one or more processors as described above, in combination with appropriate software and / or firmware.

[0089] While various exemplary embodiments of the present invention have been disclosed, it will be apparent to those skilled in the art that various changes and modifications can be made to achieve some of the advantages of the present invention without departing from the spirit and scope of the invention. It will also be apparent to those skilled in the art that these may be appropriately replaced with other components that perform the same function. It should be noted that features described with reference to specific drawings may be combined with features of other drawings, even if this is not explicitly mentioned. Furthermore, the methods of the present invention may be achieved in an all-software implementation using appropriate processor instructions, or in a hybrid implementation utilizing a combination of hardware and software logic circuits to achieve the same result. Such modifications to the concept of the present invention are intended to be covered by the appended claims.

Claims

1. A method for testing at least one source by a destination, said method comprising the steps of: - providing, by said destination, a test signal towards said at least one source; - determining, at said at least one source, a second output signal based on the first output signal and on a test signal via a first function; - conveying said second output signal to said destination; - determining, at the destination, a received signal based on the second output signal received from the at least one source and based on a test signal via a second function; - determining whether an error has occurred based on said received signal; The method includes:

2. The method comprises: determining whether an error has occurred based on the received signal and based on previous received signals for different values ​​of the test signal; The method of claim 1.

3. The method comprises: - said destination providing towards said at least one source different test signals for switching a test mode on and off; - determining, at said at least one source, a second output signal for each said test signal; - conveying said second output signal to said destination; - determining, at the destination, a received signal for each of the test signals based on the second output signal; - determining that an error has occurred if the received signals for the different test signals satisfy a predetermined condition and that no error has occurred otherwise; Further comprising: The method of claim 2.

4. the predetermined condition being an inversion of the received signal or a non-inversion of the received signal; The method of claim 3.

5. The first function is an inverse function of the second function.

5. The method according to any one of claims 1 to 4.

6. the first function is an XOR function and the second function is also an XOR function; 5. The method according to any one of claims 1 to 4.

7. the test signal is a binary signal; 5. The method according to any one of claims 1 to 4.

8. The method comprises: - said destination providing said test signal comprising at least two binary signals towards said at least one source; - determining, at said at least one source, a test signal coupled by a logic function circuit; - determining, at said at least one source, a second output signal based on said first output signal and said test signal combined via a first function; - conveying said second output signal to said destination; - determining, at the destination, a received signal based on the second output signal received from the at least one source and based on the test signal via a second function; - determining whether an error has occurred based on said received signal; Further comprising:

5. The method according to any one of claims 1 to 4.

9. The method comprises: - determining whether an error has occurred based on the received signal by applying a time delay filter that takes into account the time delay for the signal to reach the at least one source and the destination, 5. The method according to any one of claims 1 to 4.

10. the time delay filter is provided at the destination; 10. The method of claim 9.

11. a test period is determined such that the test mode is activated or deactivated for a duration long enough for a signal to reach the at least one source and / or the destination; 10. The method of claim 9.

12. The destination may be one of the following: A microcontroller; - a safety management unit; an electronic control unit; One of the 5. The method according to any one of claims 1 to 4.

13. The source may be one of the following: - a driver; A sensor; - an alarm device; - an integrated circuit functional part, or including at least one of 5. The method according to any one of claims 1 to 4.

14. 1. A system for testing at least one source with a destination, comprising: said destination is arranged to provide a test signal towards said at least one source; said at least one source - determining a second output signal based on the first output signal and on the test signal via a first function; - arranged to convey said second output signal to said destination; said destination is - determining a received signal based on the second output signal received from the at least one source and based on a test signal via a second function, - further arranged to determine whether an error has occurred based on the received signal; system.

15. The system comprises: - a safety-related data recorder; - a safety-related data processing unit, - a safety-related control unit for the data calculations; At least one of:

15. The system of claim 14.

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