Global shutter analog binning pixel matrix

Abstract

To provide a global shutter analog binning pixel matrix.SOLUTION: A pixel matrix according to an embodiment of the present invention includes a submatrix of four adjacent pixels. Each pixel of the submatrix includes a set of a photoelectric effect element and a memory point, a detection node, and a transfer gate. A binning stage is connected to the set and common to adjacent pixels of the submatrix. At least one detection node per submatrix is common to two adjacent pixels of the submatrix. The pixel matrix further includes at least one readout stage connected to a common detection node for each submatrix.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an image sensor based on an active pixel matrix using CMOS technology. [Background technology]

[0002] This type of sensor uses the photoelectric effect of semiconductor materials to convert the received photons into an electrical signal in order to reproduce the captured image. There are two main families of image sensors: sensors based on CCD (charge-coupled device) technology and sensors based on CMOS (complementary metal-oxide semiconductor) technology.

[0003] Compared to CCD sensors, CMOS sensors offer easier integration into integrated circuits on a large scale, combined with lower manufacturing costs. Furthermore, higher processing speeds can be achieved with lower energy consumption, which is why this technology is being adopted in mass-produced products such as mobile phones. Therefore, there is a major advantage in improving CMOS technology by adding the advantages of CCD technology to CMOS technology to reach or exceed the performance of baseline CCD technology, while still retaining the above-mentioned advantages of CMOS technology.

[0004] Pixel binning involves binning the output signals from a group of adjacent pixels to form a larger virtual macropixel consisting of n × m pixels, where at least one of n and m is greater than or equal to 2. This technique improves the sensitivity of image sensors incorporating this feature by regenerating signals from a group of unit pixels, thereby improving the image sensor's signal-to-noise ratio. Pixel binning is commonly used in CCD sensors, where the addition of charges generated during charge transfer is the key. However, implementing this feature in CMOS image sensors is more difficult because output signals from pixels are traditionally added in the voltage domain rather than the charge domain. In the voltage domain, the binned signal is quadratically supplemented by noise generated by each pixel and associated with each readout channel. As a result, the signal-to-noise ratio of a binned pixel is worse by the square root of n × m compared to that of a uniform pixel of the same size as a non-binned macropixel.

[0005] Due to technical and economic circumstances in the field of image sensors, there is a natural interest in developing solutions to implement pixel binning in image sensors based on active pixel matrices using CMOS technology.

[0006] New applications for image sensors are emerging, including commercial vision, robotics and autonomous vehicles, and night vision. These applications require the superior performance of CMOS technology image sensors under conditions of low light and / or moving targets. These new applications also require high dynamic range (HDR) imaging, which refers to the sensor's ability to integrate a large number of charges while maintaining low read noise compared to conventional technologies.

[0007] Based on the above discussion, it can be inferred that implementing pixel binning functionality in image sensors based on CMOS technology poses a technical challenge, especially since a compromise must be found between the advantages of this functionality, namely high sensitivity and high signal-to-noise ratio, and the disadvantages associated with increased channel noise when performing this binning in the voltage domain.

[0008] Furthermore, CMOS technology image sensors can be used in two different operating modes. The first is a rotating shutter mode, in which the integration, charge transfer and readout phases are time-shifted row by row. The second is a global shutter mode, in which simultaneous capture of photons is possible for all pixels in the matrix. This operating mode is more suitable for moving targets. Therefore, in the same situation, another constraint arises: adapting the binning solution to the pixel charge area of ​​the CMOS image sensor while remaining compatible with the global shutter operation.

[0009] Therefore, there is a need to implement pixel binning functionality in the charge domain of a CMOS image sensor while still retaining the advantages offered by CMOS technology using pinned photodiodes, and to do so in a manner compatible with global shutter operation, in order to achieve signal-to-noise performance with pixels of equivalent size to the binned macro-pixels.

[0010] U.S. Patent Application Publication No. 2014 / 0263964A1 describes a CMOS image sensor including a pixel matrix capable of performing pixel binning by pooling the detection nodes of a set of n×n pixels. The drawback of this solution is that pooling the detection nodes of a large number of pixels increases the capacitance of the nodes relative to the overall mass obtained through the accumulation of stray capacitance inherent in the various MOS transistors that form the set of pixels. This reduces the conversion factor (commonly denoted CVF, which represents the conversion gain in terms of voltage relative to electrons) of the image sensor, which in turn increases the channel noise returned at the input. This solution therefore presents the drawback of degrading the image sensor's performance under low-light conditions in terms of signal-to-noise ratio.

[0011] U.S. Patent Application Publication No. 2014 / 00218580A1 describes a CMOS image sensor including a pixel matrix capable of performing pixel binning using an asymmetric charge-storing gate disposed between a photodiode of a first pixel and a photodiode of a second pixel. However, the solution proposed in U.S. Patent Application Publication No. 2014 / 00218580A1 is not compatible with a global shutter operating mode and is limited to a rotating shutter operation. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] US Patent Application Publication No. 2014 / 0263964A1 [Patent Document 2] US Patent Application Publication No. 2014 / 00218580A1 Summary of the Invention [Means for solving the problem]

[0013] In order to overcome the limitations of existing solutions for implementing pixel binning functionality with the aim of improving the sensitivity of CMOS image sensors, the present invention proposes an improved pixel matrix structure, which consists of a pixel matrix formed using CMOS technology integrated into the image sensor and including at least one 2x2 pixel sub-matrix with means for charge binning, making it possible to perform pixel binning in the charge domain.

[0014] The present solution differs from previously developed pixel binning solutions in that it has a more compact physical implementation while providing superior conversion capabilities, combined with low channel noise levels, which improves the performance of image sensors in low light conditions requiring high sensitivity and a high signal-to-noise ratio.

[0015] The present invention also has the advantage of allowing the pixel binning function to be associated with a global shutter operation, thus providing superior performance in the case of moving targets.

[0016] The present invention remains compatible with operation without binning the charges of the macro-pixels of the pixel matrix by adapting the control signals that control the readout phase of reading out the output signals from the set of pixels of the matrix, which provides convenience to those skilled in the art in terms of using this functionality in imaging conditions and environments.

[0017] One subject of the invention is a pixel matrix of N rows and M columns produced on a semiconductor substrate, said matrix comprising at least one sub-matrix of four adjacent pixels.

[0018] Each pixel of the sub-matrix includes a photoelectric effect element for generating charge in response to incident electromagnetic radiation and a set of memory points connected to the output of the photoelectric effect element for storing the generated charge, a detection node, a transfer gate connected between the output of the memory point and the detection node, and a binning stage. The binning stage is connected to the set and is common to adjacent pixels belonging to the same row of the sub-matrix. At least one detection node per sub-matrix is ​​common to two adjacent pixels belonging to the same column of the sub-matrix. The pixel matrix further includes at least one readout stage per sub-matrix connected to the common detection node.

[0019] According to one particular aspect of the invention, each of the photoelectric effect elements is a pinned photodiode.

[0020] According to one particular aspect of the invention, each of the binning stages is formed by a pair of deep isolation trenches arranged in parallel.

[0021] According to one particular aspect of the invention, each memory point is formed by the placement of a deep isolation trench that forms two charge traps, a first trap that constitutes the input of the memory point and a second trap that is doped with charge carriers at a higher dose than the first trap and constitutes the body of the memory point.

[0022] According to one particular aspect of the invention, each memory point is formed by the arrangement of two pairs of deep isolation trenches, which form two charge traps: a first trap constituting the input of the memory point and formed by the first pair of trenches arranged in parallel and separated by a first distance, and a second trap constituting the body of the memory point and formed by the second pair of trenches arranged in parallel and separated by a second distance, the first distance being smaller than the second distance.

[0023] According to a particular aspect of the invention, the binning stage is connected between the outputs of the photoelectric effect elements and the outputs of the photoelectric effect elements of adjacent pixels of the sub-matrix belonging to the same row, and in addition, the pixels of the sub-matrix belonging to the same column have a common detection node and a common readout stage.

[0024] According to a particular aspect of the present invention, the control means of the above-described embodiment is configured to apply, for each pixel of the same column, a high potential to the deep isolation trenches forming memory points for receiving charges generated by the photoelectric effect elements, a low potential to the deep isolation trenches forming memory points belonging to adjacent pixels of the sub-matrix belonging to the same row, and a low potential to the deep isolation trenches forming the binning stages.

[0025] According to a particular aspect of the present invention, the control means of the above-described embodiment is configured to apply, simultaneously for each pixel of the same column, a high potential to the deep isolation trenches forming the memory points, a low potential to the deep isolation trenches forming the memory points belonging to adjacent pixels of the sub-matrix belonging to the same row and a high potential to the deep isolation trenches forming the binning stages in order to bin the charges generated by the pixels belonging to the same row of the sub-matrix.

[0026] According to a particular aspect of the invention, the binning stage of a pixel of a sub-matrix is ​​connected between the output of the memory point and the output of the memory point of the pixel of the sub-matrix belonging to the same row, and in addition, the pixels of the sub-matrix belonging to the same column have a common detection node and a common readout stage.

[0027] According to a particular aspect of the invention, the binning stage of a pixel of a sub-matrix is ​​connected between the output of the memory point and the output of the memory point of the pixel of the sub-matrix belonging to the same column, and the first pair of pixels of the sub-matrix belonging to the same row share a common detection node and a common readout stage.

[0028] A second pair of pixels of the submatrix that belongs to the same column is shared with another adjacent submatrix, and the first pair of pixels of the adjacent submatrix is ​​located in a different row than the first pair of pixels of the submatrix.

[0029] According to one particular aspect of the invention, the control means is configured to apply, for each pixel of the sub-matrix, a high potential to the deep isolation trenches forming the memory points for receiving the charges generated by the photoelectric effect elements and a low potential to the deep isolation trenches forming the binning stages.

[0030] According to one particular aspect of the invention, the control means are configured to simultaneously apply to pairs of adjacent pixels in a first direction a high potential to the deep isolation trenches forming the memory points, a low potential to the deep isolation trenches forming the memory points belonging to adjacent pixels of a sub-matrix in a second direction different from the first direction and a high potential to the deep isolation trenches forming the binning stages, thereby enabling binning of the charges generated by adjacent pixels in the second direction.

[0031] According to one particular aspect of the invention, the control means is configured to apply a high potential to the transfer gates of pairs of adjacent pixels in the first direction, for example two pixels in the same column, in order to bin the charges generated in a common readout stage.

[0032] According to one particular aspect of the invention, each readout stage includes a reset transistor connected to the detection node for resetting the detection node to a selected supply voltage, an amplifying transistor connected in a common drain configuration with its gate connected to the detection node, and a select transistor connected to the output of the amplifying transistor for sampling the output signal.

[0033] One subject of the present invention is in particular an image sensor comprising a pixel matrix according to the various embodiments of the invention described above, a control signal generation circuit for generating control signals for the pixels, a sampling circuit arranged at the base of each column of the pixel matrix and connected to the output of the readout stage of each pixel of the corresponding column, and a power supply circuit for supplying power to each column of the pixel matrix.

[0034] According to one particular aspect of the invention, the sampling circuit is a correlated double sampling circuit.

[0035] According to one particular aspect of the invention, the sensor is designed for global shutter operation.

[0036] Other features and advantages of the present invention will become more apparent from a review of the following description taken in conjunction with the accompanying drawings, in which: [Brief explanation of the drawings]

[0037] [Figure 1] FIG. 2 shows a functional block diagram of a pixel submatrix according to the first embodiment of the present invention. [Figure 2a] 10A shows a cross-sectional view of one embodiment of a binning stage caused by facing capacitive deep isolation trenches. [Figure 2b] 2b shows a plan view of a binning stage according to the embodiment of FIG. 2a; [Figure 2c] 2b shows a horizontal cross section of a graph of the electrostatic potential of the binning stage shown in FIG. 2a. [Figure 3a]1 shows a plan view of a first embodiment of a memory point created by a face-to-face capacitive deep isolation trench. [Figure 3b] 10 shows a plan view of a second embodiment of a memory point created by facing capacitive deep isolation trenches. [Figure 3c] 3b shows a graph of the electrostatic potential at the trap of the memory point shown in FIG. 3a. [Figure 4] 1 shows an example of a circuit diagram of a read stage. [Figure 5] 2 shows a plan view of an example of a physical implementation of a pixel sub-matrix according to a first embodiment of the present invention; [Figure 6a] 2 shows a timing diagram of operation during charge binning of the sub-matrix shown in FIG. 1; [Figure 6b] 2 illustrates a first step of charge binning in a sub-matrix according to the first embodiment shown in FIG. 1; [Figure 6c] 2 shows a graph of electrostatic potential illustrating a first step of charge binning in a sub-matrix according to the first embodiment shown in FIG. 1; [Figure 6d] 2 illustrates a second step of charge binning in sub-matrices according to the first embodiment shown in FIG. 1; [Figure 6e] 2 shows a graph of electrostatic potential illustrating a second step of charge binning in a sub-matrix according to the first embodiment shown in FIG. 1; [Figure 6f] 2 illustrates a third step of charge binning in sub-matrices according to the first embodiment shown in FIG. 1; [Figure 6g] 2 shows a graph of electrostatic potential illustrating a third step of charge binning in a sub-matrix according to the first embodiment shown in FIG. 1; [Figure 6h] 10 illustrates a fourth step of charge binning in sub-matrices according to the first embodiment illustrated in FIG. [Figure 6i] 2 shows a graph of electrostatic potential illustrating a fourth step of charge binning in sub-matrices according to the first embodiment shown in FIG. 1; [Figure 7] 2 shows a timing diagram of the operation of the sub-matrix shown in FIG. 1 in operation without charge binning. [Figure 8] FIG. 10 shows a functional block diagram of a pixel submatrix according to a second embodiment of the present invention. [Figure 9a] FIG. 9 illustrates a timing diagram of operation during charge binning of the sub-matrix shown in FIG. 8. [Figure 9b] 9 shows a first step of the operation by charge binning on the sub-matrix according to the second embodiment shown in FIG. 8. [Figure 9c] 9 shows a second step of the operation by charge binning on the sub-matrix according to the second embodiment shown in FIG. 8. [Figure 9d] 9 shows a third step of the operation by charge binning on the sub-matrix according to the second embodiment shown in FIG. 8. [Figure 9e] 9 shows a fourth step of the operation by charge binning on the sub-matrix according to the second embodiment shown in FIG. 8. [Figure 10] FIG. 10 shows a functional block diagram of a pixel submatrix according to a third embodiment of the present invention. [Figure 11] 2 illustrates an exemplary implementation of a pixel matrix including pixel sub-matrices according to the first embodiment of the present invention illustrated in FIG. 1; [Figure 12] 9 illustrates an exemplary implementation of a pixel matrix including pixel sub-matrices according to a variant of the second embodiment of the present invention illustrated in FIG. 8. [Figure 13] FIG. 1 illustrates a functional block diagram of an image sensor for integrating a pixel matrix according to an optional embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0038] FIG. 1 shows a diagram of N rows L of rank i formed on a semiconductor substrate. i (i=1~N) and M columns C of rank j j The functional configuration diagram shows the architecture of a set of four pixels belonging to a pixel matrix consisting of j (j=1 to M). The four pixels are respectively designated as Pxl ij , Pxl (i+1),j , Pxl i,(j+1) and Pxl (i+1),(j+1) It is written as follows.

[0039] Pxl for 4 pixels i,j , Pxl i+1,j , Pxl i,j+1 and Pxl i+1,j+1 are identical and form a 2x2 dimensional symmetric submatrix denoted S that is simulated onto the virtual macropixel.

[0040] The four pixels of the submatrix S are the same as the two pixels of the submatrix S that belong to the same row (for example, Pxl i,j , Pxl i,j+1 ) and two pixels of the submatrix that belong to the same column (e.g., Pxl i,j , Pxl i+1,j ) and a charge transfer means for performing a second operation of binning the charges generated by the submatrix S. The symmetry of the structure of the submatrix S allows the possibility of performing binning in both directions, from one unit pixel to another.

[0041] Pixels Pxl that form the submatrix S i,j , Pxl i+1,j , Pxl i,j+1 and Pxl i+1,j+1 To illustrate the architecture, let us use the pixel Pxl i,j The configuration of the above will be described below with an example.

[0042] Pixel Pxl i,j is a photoelectric effect element (EPE) that generates and stores charge in response to incident electromagnetic radiation. i,j and photoelectric effect element EPE i,j a memory point POINT_MEM controlled by signal MEM1 connected to the output of i,j and the common detection node SN i,j , the adjacent pixels Pxl belonging to the same row of the submatrix S i+1,j Connect to the signal TG i and the adjacent pixel Pxl belonging to the same row of the submatrix S. i,j+1 and a binning stage SOM1 controlled by a common signal BIN.

[0043] Also, the readout stage LECTi,j is the detection node SN that makes the transition from the charge domain to the voltage domain. i,j Connected to the readout stage LECT i,j The LECT stage formats a signal corresponding to the charge collected in the associated pixel. i,j are the pixels Pxl that belong to the same column of the submatrix S. i+1,j and shared.

[0044] As mentioned above, the photoelectric effect element EPE i,j to generate charge in response to incident electromagnetic radiation. An exemplary embodiment of this device is a pinned photodiode. This photodiode is generally constructed by joining a thin P+ doped layer with an N-doped diffusion region in a P-doped semiconductor substrate. When exposed to electromagnetic radiation, incident photons interact with the semiconductor substrate to generate a space charge region at the junction, or more specifically, electron-hole pairs in the case of electrons, which are collected at the cathode. Here, we refer to the charge integration phase.

[0045] The binning stage SOM1 is controlled by a signal BIN, and the photoelectric effect element EPE i,j The output of the submatrix S is i Photoelectric effect element EPE i,j+1 Applying a positive pulse to the signal BIN activates the binning stage and thus the two adjacent photoelectric effect elements EPE i,j , E.P.E. i,j+1 This leads to the establishment of an electrical connection between the outputs of the photoelectric effect element EPE, which, following the integration phase, i,j+1 The charges generated by the adjacent photoelectric effect element EPE i,j+1 It is possible to move in the same direction and in the opposite direction.

[0046] A second binning stage SOM2, identical to the first binning stage SOM1 and controlled by the same signal BIN, includes two photoelectric effect elements EPE i+1,j , E.P.E. i+1,j+1 The output of the photoelectric effect element EPE is connected betweeni+1,j and EPE i+1,j+1 Therefore, between the lines Pxl i+1,j , Pxl i+1,j+1 The successive rows L of the submatrix S are used together to provide the same function of binning charges between two adjacent pixels of i+1 Belongs to.

[0047] The memory points POINT_MEMi,j controlled by the signal MEM1 are designed to store the charge collected in the substrate of the photoelectric effect element EPEi,j following the application of a pulse to the signal MEM1. Each of the pixels of the submatrix S comprises a memory point identical to the memory point POINT_MEMi,j connected to the output of the corresponding photoelectric effect element. The implementation of the memory points POINT_MEMi,j, POINT_MEMi,j+1, POINT_MEMi+1,j, POINT_MEMi+1,j+1 ensures a global shutter operation of the image sensor, making it possible to simultaneously perform a charge integration phase for all pixels to store said charge in the memory points and then initiate a sequential row-by-row readout of the stored charge.

[0048] Column C of rank j j The memory point POINT_MEM belongs to the pixel i,j , POINT_MEM i+1,j are controlled by the same signal MEM1, while the column C of rank j+1 j+1 The memory point POINT_MEM belongs to the pixel i,j+1 , POINT_MEM i+1,j+1 are controlled by the same signal MEM2.

[0049] Transfer gate T3 is connected to memory point POINT_MEM i,j and the detection node SN i,j This gate is connected between the output of the detection node SN i,j Specifically, the external signal TG of the pixel connected to the transfer gate i When is at a high level, the generated charge is transferred to the detection node SN i,j The gate is generally located at the detection node SN i,jThis corresponds to the polysilicon gate, which is an N-type floating diffusion region connected to the detection node, and thus the readout stage LECT ij This refers to the charge transfer phase that transfers the charge to the input of

[0050] Due to symmetry, transfer gates T5, T6 and T4 are connected to pixel Pxl i,j+1 , Pxl i+1,j+1 and Pxl i+1,j Control signal TG i is the row L of rank i i The control signal TG is passed to the row addresses of the transfer gates T3 and T5. i+1 is the row L of rank i+1 i+1 The detection node SN is shared by transfer gates T4 and T6 belonging to i,j is the pixel Pxl i,j and Pxl i+1,j Since the charge transfer gates T4 and T3 are common to both pixels, the charges arriving from these two pixels are transferred to a common detection node SN i,j and then a common readout stage is selected. i,j This can then be read out via the column C of rank j. j This allows binning of the charges generated by pixels belonging to

[0051] By symmetry, the same vertical binning function is applied to column C of rank j+1 via simultaneous activation of transfer gates T5 and T6. j+1 Pixels Pxl belonging to i,j+1 , Pxl i+1,j+1 This can be achieved.

[0052] Readout stage LECT i,j , LECT i,j+1 The main role of the node SN is to detect the converted signal. i,j , S.N. i,j+1 , and are propagated to the associated columns. These thus provide reset and sequential addressing functions during the readout of the various pixels of the matrix.

[0053] 2a, 2b show an example of the physical implementation of a binning stage SOM1 or SOM2 in cross section along axis x and in plan view.

[0054] 2b shows a plan view of a binning stage SOM1 or SOM2 formed on a semiconductor substrate using deep trench isolation (commonly abbreviated as DTI). Deep isolation trenches are elements compatible with microelectronic manufacturing processes used to isolate certain regions of a semiconductor substrate, for example to reduce leakage currents in integrated circuits. There is a variant of such elements called capacitive deep isolation trenches (also called CDTI for short, capacitive deep trench isolation). This variant will be used to describe the present invention without loss of generality.

[0055] To better understand the implementation of the binning stage using capacitive deep isolation trenches (CDTIs), Figure 2a shows a cross-sectional view of a pair of capacitive deep isolation trenches (CDTIs), denoted dti1 and dti2, along axis x in Figure 2b. The CDTI trench structure is fabricated by etching a semiconductor substrate 4 to create deep trenches several micrometers (3 μM-6 μM) deep and hundreds of nanometers (100 nm-300 nm) wide. An insulating layer 2, e.g., oxide, is formed on the inner walls of the trenches through an oxidation process, and the trenches are then filled with polysilicon 3. Metal contacts 1 are deposited on the surfaces of the fabricated CDTI trenches to apply an electrical potential to the resulting structure.

[0056] As shown in Figures 2a and 2b, placing a pair of CDTI trenches face-to-face, applying the same potential to the metal contacts in each trench, and providing N-type doping between the two CDTI trenches creates an electrostatic potential well along axis x between the two trenches, which can store charge, specifically electrons in this case, along with the N-type doping. The depth of the potential well obtained by placing two CDTI trenches face-to-face depends on two factors: the distance d1 between the two trenches and the level of doping confined in the space between the pair of trenches dti1 and dti2. Increasing the distance d1 leads to an increase in the depth of the resulting potential well. The greater the N-type doping, the greater the increase in the depth of the potential well.

[0057] Advantageously, the use of CDTI trenches allows all of the charge from two adjacent photodiodes to be transferred to a single memory node, which is not possible when using transistors for binning. The use of CDTI trenches also allows for the elimination of thermal noise (kTC), which is not possible when using transistors to control the charge flow.

[0058] Figure 2c shows the electrostatic potential well 21 in a section along axis x between two CDTI trenches (dti1, dti2), forming a binning stage following application of a low potential to these CDTI trenches via signal BIN. Figure 2c also shows the electrostatic potential well 21 in a section along axis x between two CDTI trenches (dti1, dti2), forming a binning stage following application of a high potential to these CDTI trenches. Following the commonly chosen convention, increasing potential is depicted on the electrostatic potential axis extending from top to bottom. The electron potential well therefore corresponds, by adopted convention, to a downward parabolic function of electrostatic potential, whose maximum value is the bottom of the potential well. The higher the maximum potential, the deeper the electron potential well. Applying a positive pulse to CDTI trenches dti1, dti2 via signal BIN shifts the level of electrostatic potential well 21 to the position of electrostatic potential well 22. This corresponds to moving the potential barrier so that, if the electrostatic wells of the diodes are appropriately positioned, charge can be transferred through the binning stage formed by the structure described above.

[0059] By implementing this CDTI trench structure dti1, dti2 between two photodiodes corresponding to the photoelectric effect elements, it becomes possible to control the transfer of charges from one pixel to another, which constitutes a step in the process of binning the charges of the 2x2 dimensional submatrix S.

[0060] FIG. 3a shows a plan view of an example of the physical implementation of memory points used in the pixels of the submatrix S according to the invention.

[0061] Memory point POINT_MEM i,jconsists of two pairs of CDTI trenches, (dti3, dti4) and (dti5, dti6), arranged face-to-face, as described in FIG. 3a. The deep isolation trenches create two charge traps in two perpendicular directions. The first trap constitutes the input of the memory point, doped with N-type charge carriers, and the second trap, doped with a higher amount of charge carriers so that it is N+-doped, constitutes the body of the memory point. The set of CDTI trenches forming the memory point, dti1, dti2, dti3, and dti4, are controlled by the same control signal MEM1 (or MEM2). The doping difference between the input and body of the memory point creates an electrostatic potential difference between the traps created by the two regions, resulting in the electrostatic potential graph 31 shown in FIG. 3c.

[0062] Alternatively, it is possible to implement the input of the memory point in a different direction, but not perpendicular to the direction of the body of the memory point, while maintaining the doping difference between the two regions.

[0063] Alternatively, it is possible to implement the input of the memory point in the same direction as the body of the memory point as shown in Figure 3b, while still maintaining the doping difference between the two regions.

[0064] Alternatively, a memory point consisting of an input and a body can be defined based on the difference in distance between the trenches forming each region (input and body) rather than the difference in substrate doping. i,j3c. Specifically, let d2 be the distance between trenches dti3 and dt4, which form the inputs of the memory point, and let d3 be the distance between trenches dti5 and dt6, which form the body of the memory point. Recall that for a pair of trenches arranged face-to-face, an increase in the distance between the two trenches leads to an increase in the depth of the potential well formed between the two trenches. Thus, assuming equal doping, if the distance d3 between the trenches forming the inputs of the memory point is shorter than the distance d4 between the trenches forming the body of the memory point, an electrostatic potential graph identical to that depicted in FIG. 3c is obtained. Thus, the memory point is formed based on a geometric change in the structure, rather than a change in doping.

[0065] Similar to the principles described for the CDTI trench based binning stage, applying a high potential to the trenches constituting the memory point shifts the potential barrier 31 to the barrier position shown in graph 32, allowing charges to move through the traps at the input of the memory point; these charges are then stored in traps in the body region, thus forming the memory function.

[0066] FIG. 4 illustrates a readout stage LECT used on a submatrix S according to one embodiment of the present invention. i,j 1 shows a circuit diagram of an exemplary implementation of the

[0067] Readout stage LECT i,j is the same row L of rank i i Two input signals RST are common to all other readout stages of the pixel matrix belonging to i ,SEL i Receives the LECT read stage. i,j The reference voltage VREF is also supplied to the read stage LECT. i,j is the detection node SN i,j The charge collected by the conductive column COL j converts it into an output voltage Vout that is propagated to

[0068] Readout stage LECT i,j is the detection node SNi,j and an external reference voltage VREF that resets the detection node to enable correlated double sampling to be performed on a global scale of the image sensor.

[0069] Readout stage LECT i,j also includes an amplifier transistor Q2 connected in a common drain configuration to match the output signal with the conductive row of the associated column.

[0070] Readout stage LECT i,j The select switch T5 includes a select transistor Q3 connected to the output of the amplifier transistor Q2 for sampling the output signal from the amplifier transistor Q2. i When the row to which the pixel belongs is selected for reading, transistor Q3 is in the on state and therefore signal Vout is applied to the conductive row COL j to the output of the readout stage of this column via

[0071] Figure 5 shows a plan view of an example of a physical implementation (layout) of the submatrix S according to the first embodiment described in Figure 1. Those skilled in the art will be able to distinguish between the various elements of the submatrix S described in this particular diagram of the description of Figure 1, which reflect the masks used in the various steps of the microelectronic manufacturing process of a semiconductor substrate.

[0072] FIG. 6a shows a timing diagram of the operation of the sub-matrices in the charge binning shown in FIG.

[0073] Figures 6b-6i show the various steps of the operation by charge binning in the sub-matrix according to the first embodiment shown in Figure 1. For each step, the path of the charges generated by the pixels of the sub-matrix S is shown not only on the scale of the circuit diagram of the sub-matrix S, but also on the scale of the potential graph of the potentials in the semiconductor substrate of the various elements of the pixel sub-matrix S. This approach allows a better understanding of the physical phenomena governing the operation by binning in the structure described according to the present invention.

[0074] In FIG. 6a the following steps can be identified: 1. Step PH0: Reset the readout stage. 2. Step PH1: Charge integration by photodiode. 3. Step PH2: Pixel Pxl of the receiving column i,j and Pxl i+1,j Conservation of charge. 4. Step PH3: Horizontal charge binning. 5. Step PH4: Vertical charge binning and readout.

[0075] This process is described step by step.

[0076] At t0, the external control signal RST i A rising edge at initiates a reset step PH0, forcing the value of the detection node SN of each pixel to a predetermined voltage. While this step is not directly involved in the function of pixel charge binning, it will be clear to those skilled in the art that reset is essential for operation compatible with correlated double sampling.

[0077] Next, the charge integration phase PH1 is initiated and all control signals are set to a low potential (corresponding to logic level 0) for a duration sufficient to allow charge to accumulate in the photodiodes following exposure to incident light.

[0078] FIG. 6b shows the charge packets (dashed ovals CH i,j , C.H. i,j+1 , C.H. i+1,j , C.H. i+1,j+1 ) is generated.

[0079] Figure 6c shows the state of the electrostatic potential graph during the execution of an integration step PH1, which integrates the various elements of the submatrix S as shown in Figure 6b within the volume of the semiconductor substrate. i,j , POINT_MEM i,j+1The application of a low potential (MEM1=0 and MEM2=0) to the CDTI trenches constituting the binning stage SOM1 leads to the establishment of a potential barrier at the input of the memory point. The application of a low potential (BIN=0) to the CDTI trenches constituting the binning stage SOM1 leads to the establishment of a potential barrier that inhibits charge propagation in the binning stage. This therefore leads to the establishment of a potential barrier at the input of the photoelectric effect element EPE, as shown in FIG. 6c. i,j , E.P.E. i,j+1 This creates a potential well within the volume of the charge CH i,j , C.H. i,j+1 It can be clearly seen that the photodiode is confined to a potential well. Due to symmetry, during the integration step, the Pxl i+1,j , Pxl i+1,j+1 The same electrostatic potential graph is obtained for

[0080] After a certain time, the integration phase PH1 ends and the rising edge of the signal MEM1 is detected by the received sequence C, denoted PH2. j Pxl i,j , Pxl i+1,j At the same time, the control signal MEM2 is maintained at a low logic level, thereby storing the charge of the receiving column C j Pxl i,j+1 , Pxl i+1,j+1 A potential barrier is maintained between the photodiode of the pixel and the input of the memory point belonging to the same pixel.

[0081] 6d and 6e show the received sequence C following the rising edge of signal MEM1. j Pxl i,j , Pxl i+1,j From memory point POINT_MEM i,j , POINT_MEM i,j The electrostatic potential graph in Figure 6e shows the movement of charge from column C j This transfer of charge to the memory point of the pixel (memory point and C j (lowering the potential barrier between the photodiodes) and column C where MEM2=0 (low logic state) j+1 Charge confinement in the photodiode of a pixel (memory point and C j+1(maintaining a potential barrier between the photodiode and the

[0082] Step PH3 is initiated by activating the control signal BIN that controls the binning stages SOM1 and SOM2 and by keeping MEM2 at a low potential level. i,j+1 , Pxl i+1,j+1 Charge CH trapped in the photodiode i,j+1 , C.H. i+1,j+1 passes through each of the binning stages SOM1 and SOM2. The control signal MEM1 is maintained at a high potential (POINT_MEM i,j , POINT_MEM i,+1+j Since the input of is in the ON state, the column C of rank j+1 j+1 The charges passing through the binning stage from are then sorted into column C of rank j as shown in Figure 6f. j The pixel is stored in the memory point POINT_MEM. i,j , POINT_MEM i,+1+j This has the advantage that the gain of the readout stage is maintained while limiting the stray capacitance at the input of the readout stage.

[0083] The electrostatic potential graph 601 in FIG. 6g shows the electrostatic potential of the photoelectric effect element EPE i,j+1 From the intermediate step, the photoelectric effect element EPE i,j , and then approaches POINT_MEM as shown in graph 602 of FIG. 6g. i,j symmetry, an identical configuration of potential barriers is obtained in the substrate of the row of rank i+1, so that the pixel Pxl i,j+1 From the photodiode to pixel Pxl i,j+1 Charge can be moved up to the memory point.

[0084] Thus, upon completion of phase PH3, horizontal binning is performed row by row within submatrix S. The symmetry of the structure allows one skilled in the art to perform horizontal binning in both directions by adjusting the sequence of control signals BIN, MEM1 and MEM2.

[0085] The falling edge of the control signal MEM1 at t4 initiates the subsequent horizontal binning and readout phase PH4, which is compatible with correlated double sampling, so that the reset value is maintained by the reset signal RST i At t6, the two signals TG i , T.G. i+1 Two simultaneous pulses (or RST i is maintained in a low logic state (successive pulses in response to programming) activates the two transfer gates T3 and T4 by lowering their potential barriers, as shown in Figures 6h and 6i. i,j , POINT_MEM i+1,j The charge previously stored in the detection node SN i,j All charges generated by the four pixels of the submatrix S are summed and sent to the same detection node SN i,j The signal is stored in the i,j where correlated double sampling is performed at the system level of the image sensor after the payload signal is sampled.

[0086] To facilitate understanding of the process of binning the charges of pixels in sub-matrices (binning), the details of the correlated double sampling process will not be described here, as those skilled in the art will have all the necessary elements to implement pixel charge binning according to the present invention using this type of sampling.

[0087] FIG. 7 shows a timing diagram for the operation of the sub-matrix shown in FIG. 1 without charge binning.

[0088] The reset and integration phases PH'0, PH'1 are identical to the timing diagram of FIG. 6a.

[0089] At time t'1, two pulses of the control signals MEM1, MEM2 open access to all memory points belonging to the pixels forming the sub-matrix S. The charge generated by each photodiode is therefore transferred to the associated memory point, thus executing the charge storage phase PH'2 of the global shutter operation. In order to maintain the potential barrier between two adjacent photoelectric elements belonging to the same row, the signal BIN is kept at a low logic state.

[0090] From t'2, the control signal TG i , T.G. i+1 The two successive pulses above activate the transfer gates T3, T4, T5, and T6 successively, thus (read stage LECT i,j , LECT i,j+1 Pixel Pxl i,j The charge of the node SN i,j And Pxl i+1,j The charge of the node SN i,j+1 and then in the second (read-out stage) i,j , LECT i,j+1 Pixel Pxl i,j+1 The charge of the node SN i,j And Pxl i+1,j+1 The charge of the node SN i,j+1 can be accumulated in

[0091] This therefore results in a global shutter operation with no binning within the pixels forming the sub-matrix S.

[0092] One advantage of the present invention is that the proposed implementation allows operation with or without charge binning.

[0093] FIG. 8 shows a functional block diagram of a pixel submatrix according to a second embodiment of the present invention.

[0094] The second embodiment of the submatrix S is the row L of rank i of the submatrix S. i The memory point POINT_MEM belongs to i,j, POINT_MEM i,j+1 Connections between outputs of the binning stage SOM1 and the rank of the submatrix S i+1 Row L i+1 The memory point POINT_MEM belongs to i+1,j , POINT_MEM i+1,j+1 The connection between the outputs of the binning stage SOM2 is different from that in the first embodiment.

[0095] The second embodiment described in Figure 8 has the technical advantage that rows and columns can be reversed during implementation. i,j , POINT_MEM i,j+1 The charges that can be stored in the memory points POINT_MEM are separated from each other by the binning stage SOM1, so the number can be increased. i,j , POINT_MEM i,j+1 can be said to be).

[0096] FIG. 9a shows a timing diagram of the operation of the sub-matrix shown in FIG. 8 with binning charges according to a second embodiment of the present invention.

[0097] 9b to 9e show the path of charges during various binning steps in the submatrix S according to the second embodiment.

[0098] The reset and integration phases PH''0, PH''1 are identical to those in the timing diagram of FIG. 6a (especially PH0, PH1).

[0099] Following charge integration by the photodiodes of the pixels of submatrix S as shown in Figure 9b, at time t''1, two pulses of signals MEM1, MEM2 open the potential barriers at the inputs of the memory points of all pixels of submatrix S. Charge is thus stored in the various memory points as shown in Figure 9c, and step PH''2 is terminated by a falling edge of signals MEM1, MEM2 at time t''2.

[0100] At time t''3, the horizontal binning phase PH''3 is activated by two simultaneous pulses of the signals BIN and MEM1 to generate a signal at memory point POINT_MEM i,j+1 , POINT_MEM i+1,j+1 The charge stored at memory point POINT_MEM is calculated based on the same physical mechanism as described above. i,j , POINT_MEM i+1,j Horizontal binning is therefore performed after phase PH''3, as shown in Figure 9d.

[0101] At t''4, the final readout and vertical binning phase, PH''4, is identical to phase PH4 described in the binning operation of the first embodiment. The result of this phase is shown in Figure 9e.

[0102] 10 shows a third embodiment of a pixel sub-matrix according to the invention. Each pixel additionally integrates an anti-reflection transistor T7 controlled by an input signal AB and connected to the photoelectric effect element belonging to the same pixel. The control signal AB is common to the anti-reflection transistors of all pixels of the sub-matrix S, and this transistor provides a detection node SN i,j , S.N. i,j+1 This allows the photodiodes to be reset to zero without passing through the . It also allows the integration of the following image to be started before the end of the readout of the current image. Here we refer to "integrate while reading" (IWR).

[0103] 11 shows an exemplary implementation of the sub-matrix S according to the first embodiment of the present invention to obtain a pixel matrix MP capable of binning 2x2 pixels so as to obtain virtual macro-pixels of the same size and with a square shape factor. The abutment of the sub-matrix S belonging to the same column results in a main conductive row COL j To form the readout stage (LECT i,j , LECT i+1,j , etc.) (j is an arbitrary value from 1 to M) i,j , COL i,j+1, etc.) The pixel matrix MP is obtained by repeating the fitting operation over both spatial dimensions.

[0104] FIG. 12 shows an exemplary implementation of a pixel matrix including pixel sub-matrices according to a variant of the second embodiment of the present invention shown in FIG.

[0105] The submatrices do not abut each other, but share common parts as can be seen in the submatrices S1 and S2 in Figure 12. The submatrix S1 has a column C' j-1 , C' j The submatrix S2 consists of the pixels in column C' j , C' j+1 The submatrix S3 consists of the pixels in column C' j+1 , C' j+2 It consists of pixels.

[0106] Taking submatrix S1 as an example, binning stages 121 and 122 connect pixels belonging to the same column, not the same row, as shown in Figure 8. Also, submatrix S2 connects pixels belonging to row L of rank i+1 of submatrix S2. i+1 On the other hand, the adjacent submatrix S1 includes a single readout stage 123 connected to a common detection node 124 of two pixels belonging to the submatrix S1. i+1 The sub-matrix S1 includes a single readout stage 125 connected to a detection node 126 common to the two pixels of S1, S2, and S3. An identical configuration is obtained for the sub-matrix S3, producing an alternating symmetric structure between adjacent sub-matrices S1, S2, and S3.

[0107] It is emphasized that although this embodiment cannot perform binning in both directions between rows within the same pixel sub-matrix, it has the advantage of providing a more compact implementation compared to other embodiments.

[0108] Figure 13 shows a functional block diagram of an image sensor IMG for integrating a pixel matrix according to one of several embodiments of the present invention. The active pixel image sensor described in Figure 13 includes the following elements:

[0109] The active pixel matrix MP includes at least one sub-matrix S formed according to the present invention. This matrix consists of rows and columns of pixels. In Figure 13, for simplicity of illustration, only a single sub-matrix S is shown in the matrix.

[0110] The image sensor IMG also includes a control signal generation circuit CONT for generating control signals for the pixels. This circuit is used to generate a signal SEL for the readout phase for each pixel. i (i is 1 to N / 2), TG for charge transfer phase i (i is 1 to N) and RST for resetting the detection node i (i between 1 and N / 2) to control the various operating phases of the active pixels of the matrix MP. The control circuit CONT also generates the signals MEM1, MEM2 and BIN that manage the horizontal and vertical binning phases. This block additionally generates two other control signals, in particular SHR and SHS, that control the sampling phase.

[0111] The image sensor also includes a sampling circuit B1 located at the base of each column of the pixel matrix and connected to the output of the readout stage of each pixel in the corresponding column. A correlated double sampling circuit B1 can be used to implement this function. This correlated double sampling solution allows for the simultaneous reading of signals while removing the kTC noise generated by the pixels in the column of interest. First, the output signal from the pixel sampled following reset is saved. The saved sample corresponds to the reset signal. Second, the signal sampled after exposing the pixel to light is saved. The saved sample corresponds to the payload signal. Subtraction of the two sampled signals allows for the removal of the kTC noise. The result of this difference measurement, out_diff, is sent to an analog-to-digital converter, which is not shown in FIG. 13 for simplicity. Note that in the case of a global or rotating shutter, samples are always read out row by row.

[0112] The image sensor also includes a power supply circuit B2 that supplies power to each column of the pixel matrix. In Figure 13, this is a current source connected to the column conductor. This current source is common to all pixels of the column and is used to bias the transistors of the amplification stage during pixel readout.

[0113] Other variations of image sensors incorporating active pixel matrices according to the present invention will be readily apparent to those skilled in the art.

[0114] The present invention allows the implementation of a CMOS image sensor whose matrix array is formed via a 2x2 sub-matrix that allows the implementation of a pixel binning function in the charge domain. This feature allows the sensitivity of the image sensor to be improved under low light conditions while also reducing the channel noise within the pixel matrix. This in turn allows the signal-to-noise ratio of the image sensor to be increased.

[0115] The solution described in this invention thus differs from the prior art in terms of pixel binning performance at least in the charge domain, while maintaining compatibility with global shutter operation. The invention also has the advantage of reducing the capacitance of the detection node compared to the four pooled output node sharing technique used in prior art implementations. Since the image sensor according to the invention still retains the possibility of operating without charge binning, it offers those skilled in the art the flexibility to adapt the operation of the sensor to the conditions of the imaging environment by modifying the sequence of control signals that govern the activation of the analog pixel binning. [Explanation of symbols]

[0116] 1 Metal contacts 2. Insulation layer 3 Polysilicon 4. Semiconductor substrate 21, 22 Electrostatic potential well 31, 601 Electrostatic potential graph 32,602 graphs 121, 122 Binning stage 123, 125 Readout stage 124, 126 Detecting nodes AB control signal B1 Sampling Circuit B2 Power supply circuit BIN control signal CH i,j Charge Packet COL j Conductive row CONT control circuit C j column d1 distance dti1~dti6 trenches EPE i,j Photoelectric effect element IMG Image Sensor LECT i,j Read stage L i line MEM1, MEM2 control signals MP active pixel matrix PH0 Reset PH1 charge integral PH2 charge conservation PH3 horizontal charge binning PH4 Vertical Charge Binning and Readout POINT_MEM i,j Memory Points Pxl i,j pixel Q1 Reset transistor Q2 Amplifying transistor Q3 Select transistor RST i Input signal S, S1, S2, S3 submatrix SEL i Row Select Signal SHR, SHS control signal SN i,j Detecting Node SOM1, SOM2 binning stage T3~T6 Transfer gates T7 anti-reflective transistor T.G. i Control Signal VREF Reference voltage Vout Output voltage

Claims

1. N rows (L ｉ ) and M column (C ｊ ) pixel matrix (MP) of four adjacent pixels (Pxl ｉｊ , Pxl （ｉ＋１），ｊ , Pxl ｉ，（ｊ＋１） , Pxl （ｉ＋１），（ｊ＋１） ) Each of the pixels of the submatrix (S) is A photoelectric effect element (EPE) for generating an electric charge in response to incident electromagnetic radiation. ｉ，ｊ , E.P.E. ｉ＋１，ｊ , E.P.E. ｉ，ｊ＋１ , E.P.E. ｉ＋１，ｊ＋１ ) and the photoelectric effect element (EPE) for storing the generated charge. ｉ，ｊ , E.P.E. ｉ＋１，ｊ , E.P.E. ｉ，ｊ＋１ , E.P.E. ｉ＋１，ｊ＋１ ) connected to the output of the memory point (POINT_MEM ｉ，ｊ , POINT_MEM ｉ，ｊ＋１ , POINT_MEM ｉ＋１，ｊ , POINT_MEM ｉ＋１，ｊ＋１ ) group, - Detecting node (SN ｉｊ , S.N. ｉ，ｊ＋１ ), - the memory point (POINT_MEM ｉ，ｊ , POINT_MEM ｉ，ｊ＋１ , POINT_MEM ｉ＋１，ｊ , POINT_MEM ｉ＋１，ｊ＋１ ) and the detection node (SN ｉｊ , S.N. ｉ，ｊ＋１ ) and transfer gates (T3, T5, T6, T4) connected between them; - Binning stage (SOM1, SOM2) Including, The binning stage is connected to the set and the pixels (Pxl ｉｊ ) in the same row (L ｉ ) of the adjacent pixels (Pxl ｉ，ｊ＋１ ) and At least one detection node (SN) for each submatrix (S) ｉｊ , S.N. ｉ，ｊ＋１ ) is the same column (C ｊ ) of the submatrix (S) belonging to two adjacent pixels (Pxl ｉｊ , Pxl （ｉ＋１），ｊ ) is common to The pixel matrix is ​​divided into sub-matrices (S) by the common detection node (SN ｉｊ , S.N. ｉ，ｊ＋１ At least one read stage (LECT) connected to ｉｊ , L.E.C.T. ｉ，ｊ＋１ ) the pixel matrix (MP).

2. The photoelectric effect element (EPE ｉ，ｊ , E.P.E. ｉ＋１，ｊ , E.P.E. ｉ，ｊ＋１ , E.P.E. ｉ＋１，ｊ＋１ 2. The pixel matrix (MP) of claim 1, wherein each of the first and second photodiodes is a pinned photodiode.

3. 2. The pixel matrix (MP) according to claim 1, wherein each of said binning stages (SOM1, SOM2) is formed by a pair of deep isolation trenches (dti1, dti2) arranged in parallel.

4. The memory point (POINT_MEM ｉ，ｊ 4. A pixel matrix (MP) according to claim 1, wherein each of said memory points is formed by an arrangement of deep isolation trenches (dti3, dti4, dti5, dti6), said deep isolation trenches forming two charge traps, a first trap constituting the input of said memory point and a second trap doped with charge carriers in a larger amount than that of the first trap constituting the body of said memory point.

5. The memory point (POINT_MEM ｉ，ｊ 4. A pixel matrix (MP) according to claim 1, wherein each of said memory points is formed by the arrangement of two pairs of deep isolation trenches (dti3, dti4, dti5, dti6), said deep isolation trenches forming two charge traps, a first trap constituting the input of said memory point being formed by a first pair of trenches arranged in parallel and separated by a first distance, and a second trap constituting the body of said memory point being formed by a second pair of trenches arranged in parallel and separated by a second distance, said first distance being smaller than said second distance.

6. The binning stages (SOM1, SOM2) are ｉ，ｊ ) and the outputs of the photoelectric effect elements of adjacent pixels of the submatrix (S) belonging to the same row, The pixels (Pxl ｉｊ , Pxl （ｉ＋１），ｊ , Pxl ｉ，（ｊ＋１） , Pxl （ｉ＋１），（ｊ＋１） ) is a common detection node (SN ｉｊ , S.N. ｉ，ｊ＋１ ) and a common read stage (LECT ｉｊ , L.E.C.T. ｉ，ｊ＋１ 5. The pixel matrix (MP) of claim 4, having a pixel matrix (MP) of 100x ....

7. The same column (C ｊ ) for each pixel, said photoelectric effect element (EPE ｉ，ｊ ) for receiving the charge generated by the memory point (POINT_MEM ｉ，ｊ , POINT_MEM ｉ＋１，ｊ a high potential to said deep isolation trench forming The adjacent pixels (Pxl) of the submatrix (S) that belong to the same row ｉ，ｊ＋１ The memory point (POINT_MEM ｉ，ｊ＋１ , POINT_MEM ｉ＋１，ｊ＋１ a low potential to said deep isolation trench forming - a low potential to the deep isolation trenches forming the binning stage (SOM1) 7. A pixel matrix (MP) according to claim 6, comprising control means (CONT) adapted to apply:

8. The control means (CONT) ｊ ) simultaneously for each pixel - the memory point (POINT_MEM ｉ，ｊ , POINT_MEM ｉ＋１，ｊ a high potential to said deep isolation trench forming - Same row (L ｉ The adjacent pixels (Pxl ｉ，ｊ＋１ The memory point (POINT_MEM ｉ，ｊ＋１ , POINT_MEM ｉ＋１，ｊ＋１ a low potential to said deep isolation trench forming - high potential to the deep isolation trenches forming the binning stages (SOM1, SOM2) , the same row (L ｉ , L ｉ＋１ The pixel (Pxl ｉ，ｊ , Pxl ｉ，ｊ＋１ 8. A pixel matrix (MP) according to claim 7, configured to apply for binning the charges generated by said pixel matrix (MP).

9. The binning stages (SOM1, SOM2) of the pixels of the submatrix (S) are ｉ，ｊ , POINT_MEM ｉ，ｊ＋１ , POINT_MEM ｉ＋１，ｊ , POINT_MEM ｉ＋１，ｊ＋１ ) and the outputs of the memory points of the pixels of the submatrix (S) belonging to the same row, The pixels (Pxl ｉｊ , Pxl （ｉ＋１），ｊ , Pxl ｉ，（ｊ＋１） , Pxl （ｉ＋１），（ｊ＋１） ) is a common detection node (SN ｉｊ ) and a common read stage (LECT ｉｊ 5. The pixel matrix (MP) of claim 4, having a pixel matrix (MP) of 100x ....

10. The binning stages (SOM1, SOM2) of the pixels of the submatrix (S2) are ｉ，ｊ , POINT_MEM ｉ，ｊ＋１ , POINT_MEM ｉ＋１，ｊ , POINT_MEM ｉ＋１，ｊ＋１ ) and the output of the memory point of the pixel of the submatrix (S2) belonging to the same column, and the first pixel (Pxl) of the submatrix (S2) belonging to the same row ｉ＋１，ｊ , Pxl ｉ＋１，ｊ＋１ ) pair has a common detection node (SN ｉｊ ) and a common read stage (LECT ｉｊ ) and share The second pixel (Pxl ｉｊ , Pxl ｉ＋１，ｊ ) is shared with the adjacent submatrix (S1), The first pixel (Pxl ｉ，ｊ , Pxl ｉ＋１，ｊ＋１ 5. A pixel matrix (MP) according to claim 4, wherein the pair of pixels of the first pixel (S1) is located in a different row than the pair of pixels of the second pixel (S2) of the sub-matrix (S3).

11. The control means (CONT) performs, for each pixel of the submatrix (S), said photoelectric effect element (EPE ｉ，ｊ , E.P.E. ｉ＋１，ｊ , E.P.E. ｉ，ｊ＋１ , E.P.E. ｉ＋１，ｊ＋１ ) for receiving the charge generated by the memory point (POINT_MEM ｉ，ｊ , POINT_MEM ｉ＋１，ｊ , POINT_MEM ｉ，ｊ＋１ , POINT_MEM ｉ＋１，ｊ＋１ a high potential to said deep isolation trench forming a low potential to the deep isolation trenches forming the binning stages (SOM1, SOM2) 10. A pixel matrix (MP) according to claim 9, configured to apply:

12. The control means (CONT) simultaneously controls pairs of adjacent pixels in a first direction, - the memory point (POINT_MEM ｉ，ｊ , POINT_MEM ｉ＋１，ｊ a high potential to said deep isolation trench forming the neighboring pixels (Pxl) of the submatrix (S) in a second direction different from the first direction; ｉ，ｊ＋１ The memory point (POINT_MEM ｉ，ｊ＋１、 POINT_MEM ｉ＋１，ｊ＋１ a low potential to said deep isolation trench forming - high potential to the deep isolation trenches forming the binning stages (SOM1, SOM2) to bin the charges generated by the adjacent pixels in the second direction.

13. The control means (CONT) controls a pair of adjacent pixels in a first direction, for example in the same column (C ｊ ) for two pixels of the common readout stage (LECT ｉ，ｊ 9. A pixel matrix (MP) according to claim 8, configured to apply a high potential to said transfer gates (T3, T4) for binning the charges generated in said pixel matrix (MP).

14. Each read stage (LECT ｉｊ , L.E.C.T. ｉ，ｊ＋１ )teeth, The detection node (SN ｉｊ a reset transistor (T7) connected to said detection node for resetting said first detection node to a selected supply voltage (VREF); An amplifying transistor (T8) connected in a common drain configuration, the gate of which is connected to the detection node (SN ｉｊ ), an amplifying transistor (T8), A selection transistor (T9) connected to the output of the amplifier transistor (T8) for sampling the output signal. A pixel matrix (MP) according to any one of claims 1 to 3, comprising:

15. An image sensor (IMG), A pixel matrix (MP) according to any one of claims 1 to 3, a control signal generating circuit (CONT) for generating control signals for said pixels; a sampling circuit (B1) arranged at the base of each column of the pixel matrix, the sampling circuit (B1) being connected to the output of the readout stage of each pixel of the corresponding column; a power supply circuit (B2) for supplying power to each column of said pixel matrix; An image sensor (IMG) including:

16. 16. An image sensor (IMG) according to claim 15, wherein said sampling circuit (B1) is a correlated double sampling circuit.

17. 16. An image sensor (IMG) according to claim 15, designed for global shutter operation.

Images