Image Sensor

Abstract

To provide an image sensor having a pixel structure sharing a floating diffusion region.SOLUTION: A pixel array provided to an image sensor, contains a plurality of column lines connected to a pixel arranged in a pixel PX arranged in a matrix shape and a pixel arranged in a same column in common. Each pixel contains four subpixels SPX. Each of the four subpixels, contains: four photoelectric conversion elements PD; a floating defusion region FD which stores an electric charge generated in the four photoelectric conversion elements, and four transmission gates TG. In each pixel, four FD regions are electric connected via an inner wiring WR. In each pixel, a reset gate RG that resets four floating defusion regions, a first driving gate SFG1 that receives a first voltage via the inner wiring, and a first selection gate SG1 that is arranged so as to be adjacent to the first driving gata are included.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to an image sensor, and more particularly to a pixel array having a pixel structure in which a plurality of photoelectric conversion elements share a floating diffusion region, and an image sensor including the pixel array. [Background technology]

[0002] An image sensor is a device that captures a two-dimensional or three-dimensional image of an object. The image sensor generates an image of the object using a photoelectric conversion element that reacts to the intensity of light reflected from the object. Recently, with the development of CMOS (complementary metal oxide semiconductor) technology, CMOS image sensors using CMOS are widely used. As the resolution of image sensors increases, the spacing between pixels in the pixel array of the image sensor becomes narrower, and a pixel structure with a reduced area is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-057898 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in consideration of the above-mentioned problems in the conventional art, and an object of the present invention is to provide a pixel array having a pixel structure in which 16 photoelectric conversion elements share a floating diffusion region, and an image sensor including the same. [Means for solving the problem]

[0005] According to one aspect of the present invention, a pixel array provided in an image sensor includes pixels arranged in a matrix and a plurality of column lines commonly connected to pixels arranged in the same column among the pixels, each of the pixels includes four sub-pixels, each of the four sub-pixels includes four photoelectric conversion elements, a floating diffusion region in which charges generated in the four photoelectric conversion elements are stored, and four transmission gates for transmitting the charges generated in the four photoelectric conversion elements to the floating diffusion region, the four floating diffusion regions provided in each of the four sub-pixels in each of the pixels are electrically connected to each other via internal wiring, and each of the pixels includes a reset gate providing a power supply voltage to the internal wiring and resetting the four floating diffusion regions, a first drive gate receiving a first voltage via the internal wiring, and a first selection gate arranged adjacent to the first drive gate in a first direction.

[0006] According to one aspect of the present invention, an image sensor includes a pixel array, each of which includes a first sub-pixel, a second sub-pixel, a third sub-pixel, a fourth sub-pixel, and a first circuit, and a plurality of column lines commonly connected to pixels arranged in the same column among the pixels, each of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel includes four photoelectric conversion elements arranged in a matrix and a floating diffusion region in which charges generated by the four photoelectric conversion elements are stored, and the first floating diffusion region of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel each include a floating diffusion region in which charges generated by the four photoelectric conversion elements are stored, and The second floating diffusion region of the cell, the third floating diffusion region of the third subpixel, and the fourth floating diffusion region of the fourth subpixel are electrically connected through wiring, the wiring being formed in a pixel area in which pixels are formed, each of the pixels being connected to a corresponding column line among the plurality of column lines and the wiring, and the first circuit includes a reset transistor providing a reset voltage to the wiring, at least one driving transistor having a gate connected to the wiring, and at least one selection transistor connected to the one driving transistor and the column line.

[0007] According to one aspect of the present invention, there is provided an image sensor including pixels, each of the pixels including a plurality of floating diffusion regions disposed between a plurality of transfer transistors, the plurality of floating diffusion regions being connected to each other via wiring; a row driver that drives the pixels in units of a row; and an analog-to-digital conversion circuit that receives a plurality of sensing signals from a plurality of column lines connected to the pixel array and performs analog-to-digital conversion of the plurality of sensing signals.

[0008] A pixel array according to the technical concept of the present invention includes a semiconductor substrate having a first surface and a second surface, the semiconductor substrate including a plurality of floating diffusion regions adjacent to the first surface, and a wiring structure disposed on the first surface, the wiring structure including a plurality of transmission gates symmetrically disposed about each of the plurality of floating diffusion regions, and wiring electrically connecting four adjacent floating diffusion regions among the plurality of floating diffusion regions. Effect of the Invention

[0009] In the pixel array and image sensor including the same according to the present invention, a plurality of sub-pixels, each including a plurality of photoelectric conversion elements, share a floating diffusion region and an output circuit, thereby reducing the size of the unit pixel and increasing the resolution and sensing sensitivity of the pixel array. [Brief description of the drawings]

[0010] [Figure 1] 1 is a block diagram illustrating an image sensor according to one embodiment of the present invention. [Diagram 2] FIG. 2 illustrates a pixel array according to one embodiment of the present invention. [Diagram 3] 2 is a circuit diagram illustrating an example of a pixel included in a pixel array according to an embodiment of the present invention; [Figure 4] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Diagram 5] 2 is a vertical cross-sectional view of a pixel array according to an embodiment of the present invention; [Figure 6A] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 6B] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 7] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 8] 1 is a circuit diagram illustrating an example of a pixel according to an embodiment of the present invention; [Figure 9A] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 9B] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 9C] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 10A] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 10B] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 11A] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 11B] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 11C] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 12A] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 12B] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 12C] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 13A] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 13B] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 13C] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 13D] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 13E] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 13F] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 14A] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 14B] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 14C] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 14D] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 14E] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 14F] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 15A] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 15B] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 15C] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 16A] FIG. 2 illustrates a microlens disposed in a pixel according to an embodiment of the present invention. [Figure 16B] FIG. 2 illustrates a microlens disposed in a pixel according to an embodiment of the present invention. [Figure 16C] FIG. 2 illustrates a microlens disposed in a pixel according to an embodiment of the present invention. [Figure 16D] FIG. 2 illustrates a microlens disposed in a pixel according to an embodiment of the present invention. [Figure 17A] FIG. 2 illustrates a color filter disposed in a pixel array according to one embodiment of the present invention. [Figure 17B] FIG. 2 illustrates a color filter disposed in a pixel array according to one embodiment of the present invention. [Figure 17C] FIG. 2 illustrates a color filter disposed in a pixel array according to one embodiment of the present invention. [Figure 17D] FIG. 2 illustrates a color filter disposed in a pixel array according to one embodiment of the present invention. [Figure 17E]FIG. 2 illustrates a color filter disposed in a pixel array according to one embodiment of the present invention. [Figure 17F] FIG. 2 illustrates a color filter disposed in a pixel array according to one embodiment of the present invention. [Figure 18] FIG. 1 is a block diagram of an electronic device including a multi-camera module. [Figure 19] FIG. 19 is a detailed block diagram of the camera module of FIG. 18. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] FIG. 1 is a block diagram illustrating an image sensor according to one embodiment of the present invention.

[0012] The image sensor 100 is mounted on an electronic device having an image sensing function or an optical sensing function. For example, the image sensor 100 is mounted on electronic devices such as a camera, a smartphone, a wearable device, an Internet of Things (IoT), a tablet PC (personal computer), a PDA (personal digital assistant), a PMP (portable multimedia player), and a navigation device. The image sensor 100 is also mounted on electronic devices provided as components in vehicles, furniture, manufacturing equipment, doors, various measuring instruments, and the like.

[0013] The image sensor 100 includes a pixel array 110, a row driver 120, a ramp signal generator 130, an analog-to-digital converter (ADC) circuit 140, a data output circuit 150, and a timing controller 160. The image sensor 100 may further include a signal processing unit 170.

[0014] The pixel array 110 includes a plurality of row lines RL, a plurality of column lines CL, and a plurality of pixels PX connected to the row lines RL and the column lines CL and arranged in a matrix. The pixels PX arranged at the same position in the column direction are connected to the same column line CL.

[0015] The pixel PX senses light using a photoelectric conversion element and outputs an image signal, which is an electrical signal based on the sensed light. The photoelectric conversion element is a light sensing element made of organic or inorganic materials, such as an inorganic photodiode, an organic photodiode, a perovskite photodiode, a phototransistor, a photogate, or a pinned photodiode.

[0016] In the pixel array 110 according to an embodiment of the present invention, the pixel PX includes a plurality of sub-pixels, each of which includes a plurality of photoelectric conversion elements. The sub-pixels include floating diffusion regions in which charges generated by the plurality of photoelectric conversion elements are stored, and the floating diffusion regions included in each of the plurality of sub-pixels are electrically connected to each other via internal wiring. Thus, the plurality of sub-pixels included in the pixel PX can share the plurality of floating diffusion regions.

[0017] In one embodiment, pixel PX includes four sub-pixels, each of which includes four photoelectric conversion elements arranged in a matrix and four transfer transistors respectively connected to the four photoelectric conversion elements. A floating diffusion region is disposed at the center of the sub-pixel, and the four floating diffusion regions included in the four sub-pixels are electrically connected to each other via internal wiring to form a floating diffusion node.

[0018] The pixel PX includes an output circuit for outputting an image signal based on charges stored in the floating diffusion regions to a column line. The output circuit includes a number of transistors, such as a reset transistor, a drive transistor, and a selection transistor.

[0019] The pixel array 110 and the pixels PX included in the pixel array 110 according to an embodiment of the present invention will be described in detail below with reference to FIGS. 2 to 17F.

[0020] The row driver 120 drives the pixel array 110 on a row-by-row basis. The row driver 120 decodes a row control signal (e.g., an address signal) received from the timing controller 160, and selects at least one row line constituting the pixel array 110 in response to the decoded row control signal. For example, the row driver 120 generates a selection signal for selecting one of a plurality of rows. Then, the pixel array 110 outputs a pixel signal, for example, a pixel voltage, from a row selected by the selection signal provided from the row driver 120. The pixel signal includes a reset signal and an image signal.

[0021] The row driver 120 transmits control signals for outputting pixel signals to the pixel array 110, and the pixels PX operate in response to the control signals to output the pixel signals.

[0022] The ramp signal generator 130 generates a ramp signal (e.g., a ramp voltage) whose level rises and falls at a predetermined gradient under the control of the timing controller 160. The ramp signal RAMP is provided to each of a plurality of correlated double sampling (CDS) circuits 141 provided in an analog-to-digital converter (ADC) circuit 140.

[0023] The ADC circuit 140 includes a plurality of CDS circuits 141 and a plurality of counters 142. The ADC circuit 140 converts pixel signals (e.g., pixel voltages) input from the pixel array 110 into pixel values ​​that are digital signals. Each pixel signal received via each of the plurality of column lines CL is converted by the CDS circuit 141 and the counter 142 into a pixel value that is a digital signal.

[0024] The CDS circuit 141 compares a pixel signal, e.g., a pixel voltage, received via a column line CL with a ramp signal RAMP and outputs the comparison result as a comparison result signal. When the level of the ramp signal RAMP is the same as the level of the pixel signal, the CDS circuit 141 outputs a comparison signal that transitions from a first level (e.g., logic high) to a second level (e.g., logic low). The point in time at which the level of the comparison signal transitions is determined by the level of the pixel signal.

[0025] The CDS circuit 141 samples the pixel signal provided from the pixel PX by a correlated double sampling (CDS) method. The CDS circuit 141 samples a reset signal received as a pixel signal, compares the reset signal with a ramp signal RAMP, and generates a comparison signal based on the reset signal. The CDS circuit 141 stores the reset signal. Then, the CDS circuit 141 samples an image signal correlated with the reset signal, compares the image signal with the ramp signal RAMP, and generates a comparison signal based on the image signal.

[0026] The counter 142 counts the time points of level transition of the comparison result signal output from the CDS circuit 141, and outputs the count value as a pixel value.

[0027] In one embodiment, the counter circuit 142 is implemented by an up counter and an arithmetic circuit, an up / down counter, or a bit-wise inversion counter whose count value sequentially increases based on a counting clock signal provided from the timing controller 160. In one embodiment, the image sensor 100 further includes a code generator that generates a plurality of code values ​​having a resolution according to a set number of bits as a counting code, and the counter 142 includes a latch circuit that latches the value of the counting code based on the comparison result signal, and an arithmetic circuit.

[0028] The data output circuit 150 temporarily stores and then outputs the pixel values ​​output from the ADC circuit 140. The data output circuit 150 includes a plurality of column memories 151 and a column decoder 152. The column memory 151 stores the pixel values ​​received from the counter 142. In one embodiment, each of the plurality of column memories 151 is included in the counter 142. The plurality of pixel values ​​stored in the plurality of column memories 151 are output as image data IDTA under the control of the column decoder 152.

[0029] The timing controller 160 outputs control signals to each of the row driver 120, the ramp signal generator 130, the ADC circuit 140, and the data output circuit 150, and controls the operation or timing of the row driver 120, the ramp signal generator 130, the ADC circuit 140, and the data output circuit 150.

[0030] The signal processing unit 170 performs noise reduction processing, gain adjustment, waveform shaping processing, interpolation processing, white balance processing, gamma processing, edge enhancement processing, binning, etc. on the image data IDTA. In one embodiment, the signal processing unit 170 is provided in an external processor of the image sensor 100.

[0031] FIG. 2 is a diagram illustrating a pixel array according to one embodiment of the present invention.

[0032] 2, the pixel array 110 is in a matrix form and includes a plurality of pixels, for example, a first pixel PX1 to a fourth pixel PX4. The plurality of pixels are arranged in a plurality of rows and columns. In FIG. 2, the first pixel PX1 to the fourth pixel PX4 arranged in a first row R1 and a second row R2 and a first column C1 and a second column C2 are illustrated, but this is merely for convenience of explanation, and the pixel array 110 may include more pixels, and the number of the plurality of pixels is determined by the resolution of the pixel array 110.

[0033] A number of row lines RL (FIG. 1) extend in a first direction, e.g., the X-axis direction, and pixels arranged in the same row are connected to the same row line. For example, a first pixel PX1 and a second pixel PX2 arranged in a first row R1 are connected to the same row line, and a third pixel PX3 and a fourth pixel PX4 arranged in a second row R2 are connected to another row line.

[0034] A plurality of column lines CL (FIG. 1) extend in a second direction, for example, the Y-axis direction, and pixels arranged in the same column are connected to the same column line. For example, the first pixel PX1 and the third pixel PX3 arranged in the first column C1 are connected to the same column line, and the second pixel PX2 and the fourth pixel PX4 arranged in the second column C2 are connected to another same column line. Pixel signals are read from the plurality of pixels in row units via the column lines.

[0035] Each of the first pixel PX1 to the fourth pixel PX4 includes a plurality of floating diffusion regions FD in which charges are stored, and the plurality of floating diffusion regions FD are electrically connected via internal wiring WR extending in a first direction and a second direction within the pixel. The first pixel PX1 to the fourth pixel PX4 have the same pixel structure, which will be described in detail with reference to FIG.

[0036] 3 is a circuit diagram showing an example of a pixel included in a pixel array according to an embodiment of the present invention, in which the pixel PXa in FIG. 3 is applied to the first pixel PX1 to the fourth pixel PX4 in the pixel array 110 in FIG.

[0037] 3, the pixel PXa includes a first subpixel SPX1 to a fourth subpixel SPX4, a reset transistor RX, a first drive transistor DX1 and a second drive transistor DX2, and a first selection transistor SX1 and a second selection transistor SX2. The reset transistor RX, the first drive transistor DX1 and the second drive transistor DX2, and the first selection transistor SX1 and the second selection transistor SX2 configure an output circuit of the pixel PXa.

[0038] The first sub-pixel SPX1 includes a first photoelectric conversion element PD11 to a fourth photoelectric conversion element PD14 and a first transfer transistor TX11 to a fourth transfer transistor TX14.

[0039] The first photoelectric conversion element PD11 to the fourth photoelectric conversion element PD14 each generate a photoelectric charge (hereinafter, simply referred to as charge) corresponding to a received optical signal.

[0040] The first through fourth photoelectric conversion elements PD11 through PD14 are respectively connected to the first through fourth transmission transistors TX11 through TX14 of the first sub-pixel SPX1. The first through fourth transmission transistors TX11 through TX14 of the first sub-pixel SPX1 are turned on in response to the active levels (e.g., logic high) of the transmission signals TS11 through TS14, respectively.

[0041] The second sub-pixel SPX2 includes a first photoelectric conversion element PD21 through a fourth photoelectric conversion element PD24 and a first transmission transistor TX21 through a fourth transmission transistor TX24 connected to the first photoelectric conversion element PD21 through the fourth photoelectric conversion element PD24, respectively. The first transmission transistor TX21 through the fourth transmission transistor TX24 of the second sub-pixel SPX2 are turned on in response to an active level (e.g., logic high) of the transmission signals TS21 through TS24, respectively.

[0042] The third sub-pixel SPX3 includes first through fourth photoelectric conversion elements PD31 through PD34 and first through fourth transmission transistors TX31 through TX34 connected to the first through fourth photoelectric conversion elements PD31 through PD34, respectively. The first through fourth transmission transistors TX31 through TX34 of the third sub-pixel SPX3 are turned on in response to the active levels (e.g., logic high) of the transmission signals TS31 through TS34, respectively.

[0043] The fourth sub-pixel SPX4 includes first through fourth photoelectric conversion elements PD41 through PD44 and first through fourth transmission transistors TX41 through TX44 connected to the first through fourth photoelectric conversion elements PD41 through PD44, respectively. The first through fourth transmission transistors TX41 through TX44 of the fourth sub-pixel SPX4 are turned on in response to the active levels (e.g., logic high) of the transmission signals TS41 through TS44, respectively.

[0044] The multiple transmission signals TS11-TS14, TS21-TS24, TS3-TS3, and TS41-TS44 have active levels at the same time or at different times depending on the read mode. For example, in a first read mode, the multiple transmission signals TS11-TS14, TS21-TS24, TS31-TS34, and TS41-TS44 are different signals and have active levels at different times. In a second read mode (for example, a charge summing mode), the multiple transmission signals TS11-TS14, TS21-TS24, TS31-TS34, and TS41-TS44 are the same signals and have active levels at the same time. In the third reading mode, the transmission signals TS11 to TS14 of the first subpixel SPX1 are the same signal, the transmission signals TS21 to TS24 of the second subpixel SPX2 are the same signal, the transmission signals TS31 to TS34 of the third subpixel SPX3 are the same signal, and the transmission signals TS41 to TS44 of the fourth subpixel SPX4 are the same signal.

[0045] The first to fourth transfer transistors TX11 to TX14, TX21 to TX24, TX31 to TX34, and TX41 to TX44 provided in the first to fourth sub-pixels SPX1 to SPX4, respectively, are turned on and transfer the charges generated in the corresponding photoelectric conversion elements to the floating diffusion node FN.

[0046] The first to fourth floating diffusion regions FD1 (FIG. 4) to FD4 (FIG. 4) included in the first to fourth sub-pixels SPX1 to SPX4, respectively, are electrically connected via the internal wiring WR to form a floating diffusion node FN. Therefore, the capacitance of the capacitor formed in the floating diffusion node FN is four times the capacitance of each of the first to fourth floating diffusion regions FD1 (FIG. 4) to FD4 (FIG. 4).

[0047] A pixel power supply voltage VDDP is applied to the drain of the reset transistor RX, and a source of the reset transistor RX is connected to a floating diffusion node FN. The reset transistor RX is turned on in response to an active level of a reset signal RS to provide the pixel power supply voltage VDDP to the floating diffusion node FN as a reset voltage, thereby resetting the floating diffusion node FN.

[0048] The pixel power supply voltage VDDP is applied to the drains of the first and second driving transistors DX1 and DX2, and the sources are connected to the drains of the first and second selection transistors SX1 and SX2. The gates of the first and second driving transistors DX1 and DX2 are connected to a floating diffusion node FN. The first and second driving transistors DX1 and DX2 operate as source followers. The first and second driving transistors DX1 and DX2 receive a voltage corresponding to the potential of the floating diffusion node FN applied to their gates, and output a pixel signal corresponding to the received voltage.

[0049] The sources of the first and second selection transistors SX1 and SX2 are connected to a column line CL, and the first and second selection transistors SX1 and SX2 are turned on in response to an active level of a selection signal SEL applied to their gates to output pixel signals output from the first and second driving transistors DX1 and DX2 to the column line CL. When the first and second selection transistors SX1 and SX2 are turned on, pixel signals output from the sources of the first and second driving transistors DX1 and DX2 are output to the column line.

[0050] 3, pixel PXa is illustrated as including two drive transistors (DX1, DX2) and two select transistors (SX1, SX2), but is not limited thereto. Each pixel in pixel array 110 (FIG. 2) may include one drive transistor and one select transistor. Alternatively, each pixel may include three or more drive transistors and three or more select transistors.

[0051] 4 is a plan view showing an example of a pixel according to an embodiment of the present invention, in which the pixel PXa in FIG. 4 corresponds to the first pixel PX1 to the fourth pixel PX4 in the pixel array 110 in FIG.

[0052] 4, the pixel PXa includes a first sub-pixel SPX1 to a fourth sub-pixel SPX4, which have the same pixel structure.

[0053] The first sub-pixel SPX1 includes a first photoelectric conversion element PD11 to a fourth photoelectric conversion element PD14, a first transfer gate TG11 to a fourth transfer gate TG14, and a first floating diffusion region FD1.

[0054] The first through fourth transmission gates TG11 through TG14 are the gates of the first through fourth transmission transistors TX11 (FIG. 3) through TX14 (FIG. 3), respectively, and the first through fourth transmission transistors TX11 through TX14 transmit the charges generated in the first through fourth photoelectric conversion elements PD11 through PD14, respectively, to the first floating diffusion region FD1. The charges received by the first floating diffusion region FD1 are stored.

[0055] The first photoelectric conversion element PD11 to the fourth photoelectric conversion element PD14 are arranged in a matrix. The first floating diffusion region FD1 is arranged at the center of the first subpixel SPX1. The first transmission gate TG11 to the fourth transmission gate TG14 are arranged symmetrically with respect to the first floating diffusion region FD1. In one embodiment, the first transmission gate TG11 to the fourth transmission gate TG14 are arranged to surround the first floating diffusion region FD1.

[0056] The second subpixel SPX2 includes the first to fourth photoelectric conversion elements PD21 to PD24, the first to fourth transfer gates TG21 to TG24, and the second floating diffusion region FD2. The third subpixel SPX3 includes the first to fourth photoelectric conversion elements PD31 to PD34, the first to fourth transfer gates TG31 to TG34, and the third floating diffusion region FD3. The fourth subpixel SPX4 includes the first to fourth photoelectric conversion elements PD41 to PD44, the first to fourth transfer gates TG41 to TG44, and the fourth floating diffusion region FD4. The pixel structures of the second subpixel SPX2, the third subpixel SPX3, and the fourth subpixel SX4 are the same as that of the first subpixel SPX1, so that the overlapping description will be omitted.

[0057] The internal wiring WR is connected to the first floating diffusion region FD1 to the fourth floating diffusion region FD4 through the contact CT. The first floating diffusion region FD1 to the fourth floating diffusion region FD4 are electrically connected to each other through the internal wiring WR to form a floating diffusion node FN (FIG. 3). The internal wiring WR is formed, for example, in a pixel region in which the pixel PXa is formed on a two-dimensional plane along the first direction (X-axis direction) and the second direction (Y-axis direction). For example, in FIG. 2, the internal wiring WR provided in the first pixel PX1 is formed in the pixel region of the first pixel PX1 and is not extended to other pixels, for example, the second pixel PX2 to the fourth pixel PX4.

[0058] In one embodiment, the internal wiring WR extends in a first direction, for example, the X-axis direction, to connect the first floating diffusion region FD1 and the second floating diffusion region FD2, and connect the third floating diffusion region FD3 and the fourth floating diffusion region FD4. The internal wiring WR extends in a second direction, for example, the Y-axis direction, to connect the first floating diffusion region FD1 and the second floating diffusion region FD2, and the third floating diffusion region FD3 and the fourth floating diffusion region FD4. As a result, the first sub-pixel SPX1 to the fourth sub-pixel SPX4 share the first floating diffusion region FD1 to the fourth floating diffusion region FD4. Therefore, the useful area of ​​the pixel PXa is expanded.

[0059] The pixel PXa may further include a reset gate RG, a first drive gate SFG1 and a second drive gate SFG2, and a first select gate SG1 and a second select gate SG2. In one embodiment, the pixel PXa may further include a dummy gate DMY.

[0060] The reset gate RG is the gate of the reset transistor RX (FIG. 3), and a pixel power supply voltage VDDP (FIG. 3) is applied to the drain of the reset transistor RX, and the source of the reset transistor RX is connected to the internal wiring WR via a contact CT. When the reset transistor RX is turned on, the pixel power supply voltage is applied to the first floating diffusion region FD1 through the fourth floating diffusion region FD4 via the internal wiring WR, thereby resetting the first floating diffusion region FD1 through the fourth floating diffusion region FD4. In other words, the charges remaining in the first floating diffusion region FD1 through the fourth floating diffusion region FD4 are removed.

[0061] The first driving gate SFG1 and the second driving gate SFG2 are the gates of the first driving transistor DX1 (FIG. 3) and the second driving transistor DX2 (FIG. 3), respectively, and the first selection gate SG1 and the second selection gate SG2 are the gates of the first selection transistor SX1 (FIG. 3) and the second selection transistor SX2 (FIG. 3). The first driving gate SFG1 and the second driving gate SFG2 are connected to the internal wiring WR via the contact CT.

[0062] The drains of the first and second selection transistors SX1 and SX2 are connected to the sources of the first and second driving transistors DX1 and DX2, respectively, and the sources of the first and second selection transistors SX1 and SX2 are connected to a column line via a contact CT. When the first and second selection transistors SX1 and SX2 are turned on, pixel signals output from the sources of the first and second driving transistors DX1 and DX2 are output to the column line.

[0063] The first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are arranged side by side in a first direction, for example, the X-axis direction, on one side of the pixel PXa, for example, the upper or lower portion. The first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are arranged parallel to the row line RL (FIG. 1).

[0064] The first drive gate SFG1 and the second drive gate SFG2 are connected to the internal wiring WR via contacts CT. The first drive gate SFG1 is connected to a first end T1 of the internal wiring WR, and the second drive gate SFG2 is connected to a second end T2 of the internal wiring WR.

[0065] The first select gate SG1 and the second select gate SG2 are disposed between the first drive gate SFG1 and the second drive gate SFG2. In one embodiment, the first select gate SG1 and the second select gate SG2 are disposed outside the first drive gate SFG1 and the second drive gate SFG2.

[0066] The reset gate RG is disposed at the center of the pixel PXa, and the dummy gate DMY is disposed alongside the reset gate RG in the first direction. The reset gate RG and the dummy gate DMY are disposed between the first subpixel SPX1 and the second subpixel SPX2 and the third subpixel SPX3 and the fourth subpixel SPX4. In one embodiment, the reset gate RG and the dummy gate DMY are disposed symmetrically in the first direction with respect to the center of the pixel PXa. In one embodiment (not shown in FIG. 4), the pixel PXa does not include a dummy gate DMY.

[0067] As described above, in the pixel PXa, the first subpixel SPX1 to the fourth subpixel SPX4 share the first floating diffusion region FD1 to the fourth floating diffusion region FD4. In addition, the first subpixel SPX1 to the fourth subpixel SPX4 share an output circuit. This expands the useful area of ​​the pixel PXa and reduces the size of the pixel PXa. Since the first floating diffusion region FD1 to the fourth floating diffusion region FD4 are shared in the pixel PXa, the sensing sensitivity of the pixel PXa is increased. Therefore, the resolution and sensing sensitivity of the pixel array 110 (FIG. 2) are increased.

[0068] 5 is a vertical cross-sectional view of a pixel array according to an embodiment of the present invention taken along line AA' in FIG.

[0069] Referring to FIG. 5, the pixel array 110 includes a semiconductor substrate 111 (hereinafter referred to as the "substrate") having a first surface 111B and a second surface 111F facing each other, an incident layer 112 arranged on the first surface 111B of the substrate 111, and a wiring layer 113 (or a wiring structure) arranged on the second surface 111F of the substrate 111.

[0070] The substrate 111 includes at least one selected from the group consisting of, for example, Si, Ge, SiGe, SiC, GaAs, InAs, and InP. In one embodiment, the substrate 111 is doped with impurities of a first conductivity type. For example, the first conductivity type is P-type, and the impurities of the first conductivity type are boron.

[0071] A first deep trench isolation (DTI) portion DTI1 and a second deep trench isolation (DTI) portion DTI2 are disposed on the substrate 111. The first deep trench isolation (DTI) portion DTI1 penetrates the substrate 111 and reaches the second surface 111F from the first surface 111B. The second deep trench isolation (DTI2) portion DTI2 extends from the first surface 111B toward the second surface 111F but is separated from the second surface 111F. The first deep trench isolation (DTI1) portion DTI1 and the second deep trench isolation (DTI2) portion include at least one of a silicon oxide film, a hafnium oxide film, an aluminum oxide film, and a polysilicon film doped with an impurity. Each of the first deep trench isolation (DTI1) portion DTI1 and the second deep trench isolation (DTI2) portion has a single-layer structure or a multi-layer structure.

[0072] The first DTI1 portion DTI1 separates subpixels, e.g., the first subpixel SPX1 and the second subpixel SPX2, and the second DTI portion DTI2 separates regions within the subpixels. For example, the second DTI portion DTI2 separates the first region AR11 and the second region AR12 in a first direction, e.g., the X-axis direction, within the first subpixel SPX1, and separates the first region AR21 and the second region AR22 within the second subpixel SPX2. The first DTI1 portion DTI1 and the second DTI portion DTI2 prevent cross-talk between pixels PXa, between subpixels, and between regions of the subpixels.

[0073] A first photoelectric conversion element PD11 and a second photoelectric conversion element PD12 are disposed in the first region AR11 and the second region AR12 of the first subpixel SPX1, respectively. A first photoelectric conversion element PD21 and a second photoelectric conversion element PD22 are disposed in the first region AR21 and the second region AR22 of the second subpixel SPX2, respectively. The photoelectric conversion elements (PD11, PD12, PD21, PD22) each include a region doped with a second conductivity type impurity opposite to the first conductivity type, for example, the second conductivity type is N type, and the second conductivity type impurity includes impurities such as phosphorus, arsenic, bismuth, and / or antimony. The region doped with the second conductivity type impurity forms a PN junction with an adjacent region doped with the first conductivity type impurity of the substrate 111, thereby constituting the photoelectric conversion elements (PD11, PD12, PD21, PD22).

[0074] The first surface 111B of the substrate 111 is an incident surface of light, and light is incident via the incident layer 112 and the first surface 111B. The incident layer 112 includes a microlens ML and a color filter CF. In one embodiment, an antireflection layer AF is disposed between the first surface 111B of the substrate 111 and the color filter CF. In one embodiment, the antireflection layer AF, the color filter CF, and the microlens ML are sequentially stacked and disposed on the first surface 110B of the semiconductor substrate 111.

[0075] 5, one microlens ML is illustrated as being arranged on each of a plurality of photoelectric conversion elements, for example, the first photoelectric conversion element PD11 and the second photoelectric conversion element PD12 of the first subpixel SPX1, and the first photoelectric conversion element PD21 and the second photoelectric conversion element PD22 of the second subpixel SPX2, but the present invention is not limited thereto. In one embodiment, one microlens ML is arranged on each of two or four photoelectric conversion elements. For example, one microlens ML may be arranged on each of the first photoelectric conversion element PD11 and the second photoelectric conversion element PD12 of the first subpixel SPX1, and another microlens ML may be arranged on each of the first photoelectric conversion element PD21 and the second photoelectric conversion element PD22 of the second subpixel SPX2. As another example, for each subpixel, for example, one microlens ML may be arranged on top of the fourth photoelectric conversion element included in one subpixel (the first subpixel SPX1 consisting of the first photoelectric conversion element PD11 to the fourth photoelectric conversion element PD14).

[0076] The color filter CF transmits light in a specific spectrum band, in other words, light of a specific color. The color filters CF constitute a color filter array. In one embodiment, the color filter array has a Bayer pattern. The color filters include a red filter, a blue filter, and two green filters, and the red filter, the blue filter, and the two green filters are arranged in a 2×2 array, and the two green filters are arranged diagonally. In one embodiment, the color filters CF include a red filter, a blue filter, a green filter, and a white filter arranged in a 2×2 array. In one embodiment, the color filters CF include a red filter, two yellow filters, and a blue filter arranged in a 2×2 array, and the two yellow filters are arranged diagonally. However, the color filters are not limited thereto, and the color filters include filters combined with other hues. For example, the color filters may include a yellow filter, a cyan filter, and a green filter.

[0077] A first color filter CF1 is disposed on the first sub-pixel SPX1, and a second color filter CF2 is disposed on the second sub-pixel SPX2. The first color filter CF1 and the second color filter CF2 transmit light of the same color or different colors. The color of light transmitted by the color filter CF determines the hue sensed by the corresponding sub-pixel (the first sub-pixel SPX1 or the second sub-pixel SPX2) or the corresponding pixel PXa.

[0078] The floating diffusion regions, for example, the first floating diffusion region FD1 and the second floating diffusion region FD2, are formed adjacent to the second surface 111F of the substrate 111 and are located at the centers of the first sub-pixel SPX1 and the second sub-pixel SPX2, respectively. The first floating diffusion region FD1 and the second floating diffusion region FD2 are regions doped with impurities of a second conductive type.

[0079] In the wiring layer 113, transistor gates, for example, first transmission gates (TG11, TG21) and second transmission gates (TG12, TG22), are formed adjacent to the second surface 111F of the substrate 111. The first transmission gates (TG11, TG21) and second transmission gates (TG12, TG22) are formed adjacent to the first floating diffusion region FD1 and the second floating diffusion region FD2. Although only the transmission gates, for example, the first transmission gates (TG11, TG21) and second transmission gates (TG12, TG22), are illustrated in FIG. 5, the reset gate RG (FIG. 4), drive gates SFG1, SFG2 (FIG. 4), select gates SG1, SG2 (FIG. 4), and dummy gate DMY (FIG. 4) are formed adjacent to the second surface 111F of the substrate 111.

[0080] Well regions (not shown) are formed around the gates, e.g., the first transmission gates (TG11, TG21) and the second transmission gates (TG12, TG22). The well regions are formed in the substrate 111 adjacent to the second face 111F. The well regions act as drains and sources of the transistors.

[0081] The wiring layer 113 includes multi-layer conductive lines 113-2 disposed in an interlayer insulating film 113-1. The conductive lines 113-2 transmit control signals supplied to each transistor or signals between the pixel and the outside. The conductive lines 113-2 are formed by patterning a conductive material including a metal material such as copper or aluminum, and extend in a first direction (X-axis direction) and a second direction (Y-axis direction), for example.

[0082] Of the conductive lines 113-2, the internal wiring WR formed in the pixel PXa (FIG. 4) is connected to the first floating diffusion region FD1 and the second floating diffusion region FD2 via the contact CT penetrating the interlayer insulating film 113-1, and electrically connects the first floating diffusion region FD1 and the second floating diffusion region FD2. The internal wiring WR is formed in the pixel region AR_PX.

[0083] In this manner, the internal wiring WR electrically connects multiple floating diffusion regions (e.g., the first floating diffusion region FD1 to the fourth floating diffusion region FD4 (FIG. 4)) between multiple subpixels (e.g., the first subpixel SPX1 to the fourth subpixel SPX4 (FIG. 3)) within the pixel PXa.

[0084] 6A and 6B are plan views showing an example of a pixel according to an embodiment of the present invention. The pixels PXb and PXc in Fig. 6A and 6B are modified versions of the pixel PXa in Fig. 4. Therefore, the differences from Fig. 4 will be mainly described.

[0085] 6A and 6B, a pixel (PXb, PXc) includes a first sub-pixel SPX1 to a fourth sub-pixel SPX4, and the first sub-pixel SPX1 to the fourth sub-pixel SPX4 have the same structure. Each of the first sub-pixel SPX1 to the fourth sub-pixel SPX4 includes a first photoelectric conversion element PD1 to a fourth photoelectric conversion element PD4, a first transmission gate TG1 to a fourth transmission gate TG4, and a floating diffusion region. A first floating diffusion region FD1 to a fourth floating diffusion region FD4 are disposed in the center of each of the first sub-pixel SPX1 to the fourth sub-pixel SPX4. An internal wiring WR is connected to the first floating diffusion region FD1 to the fourth floating diffusion region FD4 via a contact CT.

[0086] The pixel (PXb, PXc) includes a reset gate RG, a first drive gate SFG1, a second drive gate SFG2, and a first select gate SG1, a second select gate SG2. In one embodiment, the pixel (PXb, PXc) may further include a dummy gate DMY. The first drive gate SFG1 and the second drive gate SFG2 are connected to the internal wiring WR via the contact CT.

[0087] 6A, the internal wiring WR extends in the second direction to connect the first floating diffusion region FD1 and the third floating diffusion region FD3 and connect the second floating diffusion region FD2 and the fourth floating diffusion region FD4, and also extends in the first direction to connect the first floating diffusion region FD1 and the second floating diffusion region FD2.

[0088] The first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are arranged side by side in a first direction, for example, the X-axis direction, at the center of the pixel PXb. The first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are arranged between the first subpixel SPX1 and the second subpixel SPX2 and the third subpixel SPX3 and the fourth subpixel SPX4.

[0089] The reset gate RG is disposed at the top or bottom of the pixel PXb, and the dummy gate DMY is disposed symmetrically with the reset gate RG in the first direction with respect to the center of the pixel PXb. In one embodiment, the reset gate RG and the dummy gate DMY are disposed symmetrically with respect to the internal wiring WR in the first direction.

[0090] 6B, the internal wiring WR extends in the second direction to connect the first floating diffusion region FD1 and the third floating diffusion region FD3 and connect the second floating diffusion region FD2 and the fourth floating diffusion region FD4. The internal wiring WR extends in the first direction to connect the first floating diffusion region FD1 and the third floating diffusion region FD3 and the second floating diffusion region FD2 and the fourth floating diffusion region FD4.

[0091] The first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are arranged side by side in a second direction, for example, the Y-axis direction, on one side of the pixel PXc, for example, the left side or the right side. The first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are arranged parallel to the column line CL (FIG. 1).

[0092] The reset gate RG and the dummy gate DMY are disposed at the center of the pixel PXc, and are disposed symmetrically in the second direction with respect to the center of the pixel PXc.

[0093] In one embodiment, as described with reference to Fig. 6A, the first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are disposed at the center of the pixel PXc, and the dummy gate DMY is disposed outside the pixel PXc, for example, at the left or right side of the pixel PXc. The first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are disposed side by side in the second direction at the center of the pixel PXc, and the reset gate RG and the dummy gate DMY are disposed side by side in the second direction at the left or right side of the pixel PXc.

[0094] 7 is a plan view showing an example of a pixel according to an embodiment of the present invention. The pixel PXd in Fig. 7 is a modified example of the pixel PXa in Fig. 4. Therefore, the following description will focus on the differences from Fig. 4.

[0095] 7, pixel PXd includes first to fourth sub-pixels SPX1 to SPX4, which have the same structure. First to fourth floating diffusion regions FD1 to FD4 are disposed at the centers of the first to fourth sub-pixels SPX1 to SPX4, respectively. Internal wiring WR is connected to the first to fourth floating diffusion regions FD1 to FD4 via contacts CT.

[0096] The pixel PXd further includes a reset gate RG, a drive gate SFG, and a selection gate SG. In one embodiment, the pixel PXd may further include a dummy gate DMY. The drive gate SFG is coupled to the internal wiring WR via a contact CT.

[0097] Unlike pixel PXa in Fig. 4, pixel PXd includes one drive gate SFG and one select gate SG. The drive gate SFG and the select gate SG are disposed at the top center of pixel PXd. In one embodiment, a dummy gate is disposed symmetrically with the select gate SG in the first direction around the drive gate SFG.

[0098] The internal wiring WR extends in a first direction to connect the first floating diffusion region FD1 and the second floating diffusion region FD2 and connect the third floating diffusion region FD3 and the fourth floating diffusion region FD4. The internal wiring WR extends in a second direction to connect the first floating diffusion region FD1 and the second floating diffusion region FD2 and the third floating diffusion region FD3 and the fourth floating diffusion region FD4. A first end T1 of the internal wiring WR is connected to the driving gate SFG via a contact CT.

[0099] 8 is a circuit diagram showing an example of a pixel according to an embodiment of the present invention, in which the pixel PXf in FIG. 8 is applied to the first pixel PX1 to the fourth pixel PX4 in the pixel array 110 in FIG.

[0100] 8, the pixel PXf includes a first subpixel SPX1 to a fourth subpixel SPX4, a reset transistor RX, a gain control transistor CX, a first drive transistor DX1 and a second drive transistor DX2, and a first selection transistor SX1 and a second selection transistor SX2. The reset transistor RX, the gain control transistor CX, the first drive transistor DX1 and the second drive transistor DX2, and the first selection transistor SX1 and the second selection transistor SX2 configure an output circuit of the pixel PXf.

[0101] Compared with pixel PXa of FIG. 3, pixel PXf further includes a gain control transistor CX. The gain control transistor CX is turned on in response to a gain control signal CS. A capacitor is formed at the drain of the gain control transistor CX to store charge. The drain of the gain control transistor CX is referred to as a floating diffusion node FN1. When the reset transistor RX is turned off and the gain control transistor CX is turned on, the floating diffusion node FN1 is electrically connected to the floating diffusion node FN, and the capacitance of the floating diffusion node FN increases.

[0102] The conversion gain of the pixel PXf is inversely proportional to the capacitance of the floating diffusion node FN, and therefore the conversion gain when the gain control transistor CX is turned off is higher than the conversion gain when the gain control transistor CX is turned on. When the gain control transistor CX is turned off, it is called HCG (high conversion gain) mode, and when the gain control transistor CX is turned on, it is called LCG (low conversion gain) mode.

[0103] At night or in a dark environment, when the amount of light incident on the pixel array 110 of the image sensor 100 (FIG. 1) is small, the pixel array 110 operates in HCG mode. The signal to noise ratio (SNR) of the image sensor 100 (FIG. 1) increases, the minimum detectable light level decreases, and the low light sensing performance of the image sensor 100 improves. During the day or in a bright environment, when the amount of light incident on the pixel array 110 of the image sensor 100 is large, the pixel array 110 operates in LCG mode. The full well capacity (FWC) of the pixel PXf increases, and therefore the high light sensing performance of the image sensor 100 improves.

[0104] In this way, pixel PXf provides dual conversion gain, and image sensor 100 can generate high quality images in bright and dark environments. Image sensor 100 can also generate a first image generated in HCG mode and a second image generated in LCG mode in succession, and merge the first and second images to generate an image with a high dynamic range.

[0105] 8, the pixel PXf is illustrated as including one gain control transistor CX, but is not limited thereto. In one embodiment, the pixel PXf includes two or more gain control transistors CX connected in series, and the conversion gain of the pixel PXf is determined by the number of gain control transistors CX that are turned on. For example, when the pixel PXf includes two gain control transistors CX, if both of the two gain control transistors CX are turned off, it is called an HCG mode, if one gain control transistor CX is turned on, it is called an MCG mode (middle conversion gain), and if two gain control transistors CX are turned on, it is called an LCG mode.

[0106] 9A, 9B, and 9C are plan views showing an example of a pixel according to an embodiment of the present invention. The pixels (PXf1, PXf2, and PXf3) in Fig. 9A to Fig. 9C are modified versions of the pixel PXa in Fig. 4. Therefore, the differences from Fig. 4 will be mainly described.

[0107] 9A, pixel PXf1 includes first to fourth sub-pixels SPX1 to SPX4, which have the same structure. First to fourth floating diffusion regions FD1 to FD4 are disposed at the centers of the first to fourth sub-pixels SPX1 to SPX4, respectively. Internal wiring WR is connected to the first to fourth floating diffusion regions FD1 to FD4 via contacts CT.

[0108] The pixel PXf1 further includes a first driving gate SFG1 and a second driving gate SFG2, a first selection gate SG1 and a second selection gate SG2, a reset gate RG, a gain control gate CG, and a dummy gate DMY. The first driving gate SFG1 and the second driving gate SFG2 are connected to the internal wiring WR via a contact CT.

[0109] The first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are arranged side by side in a first direction at the top or bottom of the pixel PXf1, the reset gate RG, the gain control gate CG, and the dummy gate DMY are arranged side by side in the first direction between the first subpixel SPX1 and the second subpixel SPX2 and the third subpixel SPX3 and the fourth subpixel SPX4, the reset gate RG is arranged in the center of the pixel PXf1, and the gain control gate CG and the dummy gate DMY are arranged symmetrically around the reset gate RG.

[0110] A wiring WRfd is connected to a well region between the gain control gate CG and the reset gate RG, in other words, to a floating diffusion node FN1 (FIG. 8) via a contact CT. The wiring WRfd is extended in a first direction and / or a second direction, thereby forming a capacitor at the floating diffusion node FN1. The longer the length of the wiring WRfd, the greater the capacitance of the floating diffusion node FN1. In one embodiment, the wiring WRfd is connected to the floating diffusion node FN1 of an adjacent pixel PXf1. The floating diffusion node FN1 is shared between the adjacent pixels PXf1.

[0111] In one embodiment (not shown in FIG. 9A), the first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are arranged side by side in the second direction on the left or right side of the pixel PXf1, and the reset gate RG, the gain control gate CG, and the dummy gate DMY are arranged side by side in the second direction between the first subpixel SPX1 and the third subpixel SPX3 and the second subpixel SPX2 and the fourth subpixel SPX4.

[0112] Referring to FIG. 9B, pixel PXf2 includes a first subpixel SPX1 to a fourth subpixel SPX4, a first drive gate SFG1 and a second drive gate SFG2, a first select gate SG1 and a second select gate SG2, a first drive gate SFG1 and a second drive gate SFG2, a reset gate RG, a gain control gate CG, and a dummy gate DMY.

[0113] The first and second select gates SG1 and SG2 are arranged side by side in the first direction between the first and second subpixels SPX1 and SPX2 and the third and fourth subpixels SPX3 and SPX4. The reset gate RG, the gain control gate CG, and the dummy gate DMY are arranged side by side in the first direction at the top or bottom of the pixel PXf2.

[0114] In one embodiment (not shown in FIG. 9B), the first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are arranged side by side in the second direction between the first subpixel SPX1 and the third subpixel SPX3 and the second subpixel SPX2 and the fourth subpixel SPX4, and the reset gate RG, the gain control gate CG, and the dummy gate DMY are arranged side by side in the second direction on the left or right side of the pixel PXf2.

[0115] Referring to FIG. 9C, pixel PXf3 includes first to fourth subpixels SPX1 to SPX4, a first drive gate SFG1 and a second drive gate SFG2, a first select gate SG1 and a second select gate SG2, a reset gate RG, and a gain control gate CG.

[0116] The structure of pixel PXf3 in Fig. 9C is similar to the structure of pixel PXf1 in Fig. 9A, except that pixel PXf3 does not include a dummy gate DMY, and the reset gate RG and the gain control gate CG are arranged symmetrically in the first direction with respect to the center of pixel PXf3.

[0117] 10A and 10B are plan views showing an example of a pixel according to an embodiment of the present invention. The pixel PXg1 in Fig. 10A is a modified example of the pixel PXf1 in Fig. 9A. Therefore, the following description will focus on the differences from Fig. 9A.

[0118] 10A, pixel PXg1 includes first to fourth sub-pixels SPX1 to SPX4, which have the same structure. First to fourth floating diffusion regions FD1 to FD4 are disposed at the centers of the first to fourth sub-pixels SPX1 to SPX4, respectively. Internal wiring WR is connected to the first to fourth floating diffusion regions FD1 to FD4 via contacts CT.

[0119] The pixel PXg1 may further include a drive gate SFG, a select gate SG, a reset gate RG, and a gain control gate CG. In one embodiment, the pixel PXg1 may further include a dummy gate DMY. The drive gate SFG is coupled to the internal wiring WR via a contact CT.

[0120] The reset gate RG, the gain control gate CG, and the dummy gate DMY are arranged side by side in the first direction between the first subpixel SPX1 and the second subpixel SPX2 and the third subpixel SPX3 and the fourth subpixel SPX4. The gain control gate CG and the dummy gate DMY are arranged symmetrically in the first direction with the reset gate RG at the center.

[0121] Unlike pixel PXf1 of FIG. 9A, pixel PXg1 includes one drive gate SFG and one select gate SG. The drive gate SFG and the select gate SG are centrally located at the top or bottom of pixel PXg1. In one embodiment (not shown in FIG. 10A), a dummy gate DMY is located symmetrically with the select gate SG in the first direction around the drive gate SFG.

[0122] In one embodiment (not shown in FIG. 10A), the drive gate SFG and the select gate SG are arranged side by side in the first direction between the first subpixel SPX1 and the second subpixel SPX2 and the third subpixel SPX3 and the fourth subpixel SPX4, and the reset gate RG, the gain control gate CG, and the dummy gate DMY are arranged side by side in the first direction at the top or bottom of the pixel PXg1.

[0123] In one embodiment (not shown in FIG. 10A ), the reset gate RG, the gain control gate CG, and the dummy gate DMY are arranged side by side in the second direction between the first and third subpixels SPX1 and SPX3 and the second and fourth subpixels SPX2 and SPX4, and the drive gate SFG and the select gate SG are arranged side by side in the second direction at the center of the left or right side of the pixel PXg1. Alternatively, the drive gate SFG and the select gate SG are arranged side by side in the second direction between the first and third subpixels SPX1 and SPX3 and the second and fourth subpixels SPX2 and SPX4, and the reset gate RG, the gain control gate CG, and the dummy gate DMY are arranged side by side in the second direction at the center of the left or right side of the pixel PXg1.

[0124] Referring to FIG. 10B, the pixel PXg2 does not include a dummy gate DMY, and the reset gate RG and the gain control gate CG are arranged symmetrically in the first direction with respect to the center of the pixel PXg2.

[0125] 11A, 11B, and 11C are plan views showing an example of a pixel according to an embodiment of the present invention. The pixel PXh1 in FIG 11A is a modified example of the pixel PXf1 in FIG 9A. Therefore, the following description will focus on the differences from FIG 9A.

[0126] 11A, pixel PXh1 includes first to fourth sub-pixels SPX1 to SPX4, which have the same structure. First to fourth floating diffusion regions FD1 to FD4 are disposed at the centers of the first to fourth sub-pixels SPX1 to SPX4, respectively. Internal wiring WR is connected to the first to fourth floating diffusion regions FD1 to FD4 via contacts CT.

[0127] The pixel PXh1 further includes a first driving gate SFG1 and a second driving gate SFG2, a first selection gate SG1 and a second selection gate SG2, a reset gate RG, a first gain control gate CG1, a second gain control gate CG2, and a dummy gate DMY. The first driving gate SFG1 and the second driving gate SFG2 are connected to the internal wiring WR via a contact CT.

[0128] The first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are arranged side by side in the first direction at the top or bottom of the pixel PXh1, and the second gain control gate CG2, the first gain control gate CG1, the reset gate RG, and the dummy gate DMY are arranged side by side in the first direction between the first subpixel SPX1 and the second subpixel SPX2 and the third subpixel SPX3 and the fourth subpixel SPX4. With the center of the pixel PXh1 as a reference, the second gain control gate CG2 and the dummy gate DMY are arranged symmetrically in the first direction, and the first gain control gate CG1 and the reset gate RG are arranged symmetrically in the first direction.

[0129] A wiring WRfd1 is connected to a well region between the first gain control gate CG1 and the reset gate RG via a contact CT, and a wiring WRfd2 is connected to a well region between the second gain control gate CG2 and the first gain control gate CG1. The wirings (WRfd1, WRfd2) extend in a first direction and / or a second direction. In one embodiment, at least one of the wirings (WRfd1, WRfd2) is connected to one of the floating diffusion nodes of the adjacent pixel PXh1.

[0130] In one embodiment (not shown in FIG. 11A), the first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are arranged side by side in the second direction on the left or right side of the pixel PXh1, and the second gain control gate CG2, the first gain control gate CG1, the reset gate RG, and the dummy gate DMY are arranged side by side in the second direction between the first subpixel SPX1 and the third subpixel SPX3 and the second subpixel SPX2 and the fourth subpixel SPX4.

[0131] Referring to FIG. 11B, pixel PXh2 includes a first subpixel SPX1 to a fourth subpixel SPX4, a first drive gate SFG1 and a second drive gate SFG2, a first select gate SG1 and a second select gate SG2, a first drive gate SFG1 and a second drive gate SFG2, a reset gate RG, a second gain control gate CG2, a first gain control gate CG1, a second gain control gate CG2, and a dummy gate DMY.

[0132] The first and second select gates SG1 and SG2, and the first and second drive gates SFG1 and SFG2 are arranged side by side in the first direction between the first and second subpixels SPX1 and SPX2 and the third and fourth subpixels SPX3 and SPX4. The second gain control gate CG2, the first gain control gate CG1, the reset gate RG, and the dummy gate DMY are arranged side by side in the first direction at the top or bottom of the pixel PXh2.

[0133] In one embodiment (not shown in FIG. 11B), the first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are arranged side by side in the second direction between the first subpixel SPX1 and the third subpixel SPX3 and the second subpixel SPX2 and the fourth subpixel SPX4, and the second gain control gate CG2, the first gain control gate CG1, the reset gate RG, and the dummy gate DMY are arranged side by side in the second direction on the left or right side of the pixel PXh2.

[0134] Referring to FIG. 11C, pixel PXh3 includes a first subpixel SPX1 to a fourth subpixel SPX4, a first drive gate SFG1 and a second drive gate SFG2, a first select gate SG1 and a second select gate SG2, a reset gate RG, and a first gain control gate CG1 and a second gain control gate CG2.

[0135] The structure of pixel PXh3 in Fig. 11C is similar to that of pixel PXh1 in Fig. 11A. However, pixel PXh3 does not include a dummy gate DMY, and the second gain control gate CG2, the first gain control gate CG1, and the reset gate RG are arranged side by side in the first direction at the center of pixel PXh3. In one embodiment, the first gain control gate CG1 is arranged at the center of pixel PXh3, and the second gain control gate CG2 and the reset gate RG are arranged symmetrically in the first direction around the first gain control gate CG1.

[0136] 12A, 12B, and 12C are plan views showing an example of a pixel according to an embodiment of the present invention. The pixel PXil in Fig. 12A is a modified example of the pixel PXh1 in Fig. 11A. Therefore, the following description will focus on the differences from Fig. 11A.

[0137] 12A, pixel PXi1 includes first to fourth sub-pixels SPX1 to SPX4, which have the same structure. First to fourth floating diffusion regions FD1 to FD4 are disposed at the centers of the first to fourth sub-pixels SPX1 to SPX4, respectively. Internal wiring WR is connected to the first to fourth floating diffusion regions FD1 to FD4 via contacts CT.

[0138] The pixel PXi1 includes a drive gate SFG, a selection gate SG, a reset gate RG, a first gain control gate CG1, a second gain control gate CG2, and a dummy gate DMY. The drive gate SFG is connected to the internal wiring WR via a contact CT.

[0139] The drive gate SFG and the select gate SG are arranged side by side in the first direction at the top or bottom of the pixel PXil. In one embodiment (not shown in FIG. 12A), the dummy gate DMY is arranged symmetrically in the first direction with the select gate SG around the drive gate SFG.

[0140] The second gain control gate CG2, the first gain control gate CG1, the reset gate RG, and the dummy gate DMY are arranged in a line in the first direction between the first subpixel SPX1 and the second subpixel SPX2 and the third subpixel SPX3 and the fourth subpixel SPX4.

[0141] In one embodiment (not shown in FIG. 12A), the drive gate SFG and the select gate SG are arranged side by side in the second direction on the left or right side of the pixel PXi1, and the second gain control gate CG2, the first gain control gate CG1, the reset gate RG, and the dummy gate DMY are arranged side by side in the second direction between the first subpixel SPX1 and the third subpixel SPX3, and the second subpixel SPX2 and the fourth subpixel SPX4.

[0142] Referring to FIG. 12B, pixel PXi2 includes a first subpixel SPX1 to a fourth subpixel SPX4, a drive gate SFG, a selection gate SG, a reset gate RG, a second gain control gate CG2, a first gain control gate CG1, a second gain control gate CG2, and a dummy gate DMY.

[0143] The drive gate SFG and the selection gate SG are arranged side by side in the first direction between the first and second subpixels SPX1 and SPX2 and the third and fourth subpixels SPX3 and SPX4. The second gain control gate CG2, the first gain control gate CG1, the reset gate RG, and the dummy gate DMY are arranged side by side in the first direction at the top or bottom of the pixel PXi2.

[0144] In one embodiment (not shown in FIG. 12B), the drive gate SFG and the select gate SG are arranged side by side in the second direction between the first subpixel SPX1 and the third subpixel SPX3 and the second subpixel SPX2 and the fourth subpixel SPX4, and the second gain control gate CG2, the first gain control gate CG1, the reset gate RG, and the dummy gate DMY are arranged side by side in the second direction on the left or right side of the pixel PXi2.

[0145] Referring to FIG. 12C, a pixel PXi3 includes a first subpixel SPX1 to a fourth subpixel SPX4, a drive gate SFG, a selection gate SG, a second gain control gate CG2, a first gain control gate CG1, and a reset gate RG.

[0146] The structure of pixel PXi3 in Fig. 12C is similar to that of pixel PXi1 in Fig. 12A, except that pixel PXi3 does not include a dummy gate DMY, and the second gain control gate CG2, the first gain control gate CG1, and the reset gate RG are arranged side by side in the first direction at the center of pixel PXi3. In one embodiment, the first gain control gate CG1 is arranged at the center of pixel PXi3, and the second gain control gate CG2 and the reset gate RG are arranged symmetrically in the first direction around the first gain control gate CG1.

[0147] 13A, 13B, 13C, 13D, 13E, and 13F are plan views illustrating examples of pixels according to an embodiment of the present invention.

[0148] 13A to 13F, pixels PXj1, PXj2, PXj3, PXj4, PXj5, and PXj6 include first to fourth subpixels SPX1 to SPX4, which are arranged in a first direction, for example, the X-axis direction. Here, the first direction is the row direction of the pixel array 110 (FIG. 1). Each of the first to fourth subpixels SPX1 to SPX4 includes a first to fourth photoelectric conversion element PD1 to PD4, a first to fourth transmission gate TG1 to TG4, and a floating diffusion region FD. A first to fourth floating diffusion region FD1 to FD4 are arranged in the center of each of the first to fourth subpixels SPX1 to SPX4. An internal wiring WR is connected to the first to fourth floating diffusion regions FD1 to FD4 via a contact CT.

[0149] 13A, the pixel PXj1 further includes a drive gate SFG, a select gate SG, a reset gate RG, and a dummy gate DMY, which are arranged side by side in the first direction at the top or bottom of the pixel PXj1.

[0150] The drive gate SFG, the select gate SG, the reset gate RG, and the dummy gate DMY are disposed in the center of the upper or lower part of the pixel PXj1, but are not limited thereto, and the positions of the drive gate SFG, the select gate SG, the reset gate RG, and the dummy gate DMY can be adjusted.

[0151] The source of the reset gate RG and the drive gate SFG are each coupled to an internal wiring WR via a contact CT.

[0152] 13B, the pixel PXj2 further includes a drive gate SFG, a select gate SG, a reset gate RG, a gain control gate CG, and a dummy gate DMY, which are arranged side by side in the first direction at the top or bottom of the pixel PXj2.

[0153] A gain control gate CG and a dummy gate DMY are disposed on both sides of the reset gate RG. A wiring WRfd1 is connected to a well region between the reset gate RG and the gain control gate CG via a contact CT, and the wiring WRfd1 extends in a first direction and a second direction.

[0154] Referring to FIG. 13C, the pixel PXj3 further includes a drive gate SFG, a select gate SG, a reset gate RG, a first control gate CG1, a second gain control gate CG2, and a dummy gate DMY.

[0155] The drive gate SFG, the selection gate SG, the reset gate RG, the first control gate CG1, the second gain control gate CG2, and the dummy gate DMY are arranged side by side in the first direction above or below the pixel PXj3.

[0156] Wirings WRfd1 and WRfd2 are connected to the well region between the reset gate RG and the first gain control gate CG1, and to the well region between the first gain control gate CG1 and the second gain control gate CG2, respectively, via contacts CT, and the wirings WRfd1 and WRfd2 extend in a first direction and a second direction.

[0157] Referring to FIG. 13D, the pixel PXj4 further includes a first drive gate SFG1 and a second drive gate SFG2, a first select gate SG1 and a second select gate SG2, a reset gate RG, and a dummy gate DMY.

[0158] The first drive gate SFG1 and the second drive gate SFG2, the first select gate SG1 and the second select gate SG2, the reset gate RG, and the dummy gate DMY are arranged side by side in the first direction at the top or bottom of the pixel PXj4. The first select gate SG1 and the second select gate SG2 are arranged between the first drive gate SFG1 and the second drive gate SFG2.

[0159] The source of the reset gate RG, the first driving gate SFG1, and the second driving gate SFG2 are each connected to the internal wiring WR via a contact CT.

[0160] 13E, the pixel PXj5 may further include a first drive gate SFG1 and a second drive gate SFG2, a first select gate SG1 and a second select gate SG2, a reset gate RG, a gain control gate CG, and a dummy gate DMY. The first drive gate SFG1 and the second drive gate SFG2, the first select gate SG1 and the second select gate SG2, the reset gate RG, the gain control gate CG, and the dummy gate DMY are arranged side by side in the first direction at the top or bottom of the pixel PXj5.

[0161] Referring to FIG. 13F, pixel PXj6 may further include a first drive gate SFG1 and a second drive gate SFG2, a first select gate SG1 and a second select gate SG2, a reset gate RG, a first control gate CG1 and a second gain control gate CG2, and a dummy gate DMY.

[0162] The first drive gate SFG1 and the second drive gate SFG2, the first select gate SG1 and the second select gate SG2, the reset gate RG, the first control gate CG1 and the second gain control gate CG2, and the dummy gate DMY are arranged in a row in the first direction at the top or bottom of the pixel PXj6.

[0163] 14A, 14B, 14C, 14D, 14E, and 14F are plan views illustrating examples of pixels according to embodiments of the present invention.

[0164] 14A to 14F, the pixels PXk1, PXk2, PXk3, PXk4, PXk5, and PXk6 include the first subpixel SPX1 to the fourth subpixel SPX4, which are arranged in a second direction, for example, the Y-axis direction. Here, the second direction is the column direction of the pixel array 110 (FIG. 1). Each of the first subpixel SPX1 to the fourth subpixel SPX4 includes the first photoelectric conversion element PD1 to the fourth photoelectric conversion element PD4, the first transmission gate TG1 to the fourth transmission gate TG4, and a floating diffusion region. The first floating diffusion region FD1 to the fourth floating diffusion region FD4 are arranged in the center of each of the first subpixel SPX1 to the fourth subpixel SPX4. The internal wiring WR is connected to the first floating diffusion region FD1 to the fourth floating diffusion region FD4 via the contact CT.

[0165] 14A, pixel PXk1 may further include a drive gate SFG, a select gate SG, a reset gate RG, and a dummy gate DMY, which are arranged side by side in the second direction on the left or right side of pixel PXk1.

[0166] The drive gate SFG, the select gate SG, the reset gate RG, and the dummy gate DMY are disposed in the center of the left or right side of the pixel PXk1, but are not limited thereto, and the positions of the drive gate SFG, the select gate SG, the reset gate RG, and the dummy gate DMY are adjusted.

[0167] The source of the reset gate RG and the drive gate SFG are each coupled to an internal wiring WR via a contact CT.

[0168] 14B, pixel PXk2 may further include a drive gate SFG, a select gate SG, a reset gate RG, a gain control gate CG, and a dummy gate DMY, which are arranged side by side in the second direction on the left or right side of pixel PXk2.

[0169] A gain control gate CG and a dummy gate DMY are disposed above and below the reset gate RG, respectively. A wiring WRfd is connected to a well region between the reset gate RG and the gain control gate CG via a contact CT, and the wiring WRfd extends in a first direction and a second direction.

[0170] Referring to FIG. 14C, pixel PXk3 may further include a drive gate SFG, a select gate SG, a reset gate RG, a first control gate CG1 and a second gain control gate CG2, and a dummy gate DMY.

[0171] The drive gate SFG, the selection gate SG, the reset gate RG, the first control gate CG1, the second gain control gate CG2, and the dummy gate DMY are arranged side by side in the second direction on the left or right side of the pixel PXk3.

[0172] Wirings WRfd1 and WRfd2 are connected to the well region between the reset gate RG and the first gain control gate CG1, and to the well region between the first gain control gate CG1 and the second gain control gate CG2, respectively, via contacts CT, and the wirings WRfd1 and WRfd2 extend in a first direction and a second direction.

[0173] Referring to FIG. 14D, pixel PXk4 may further include a first drive gate SFG1 and a second drive gate SFG2, a first select gate SG1 and a second select gate SG2, a reset gate RG, and a dummy gate DMY.

[0174] The first drive gate SFG1 and the second drive gate SFG2, the first select gate SG1 and the second select gate SG2, the reset gate RG, and the dummy gate DMY are arranged side by side in the second direction on the left or right side of the pixel PXk4. The first select gate SG1 and the second select gate SG2 are arranged between the first drive gate SFG1 and the second drive gate SFG2.

[0175] The source of the reset gate RG, the first drive gate SFG1 and the second drive gate SFG2 are each coupled to the internal wiring WR via a contact CT.

[0176] 14E, pixel PXk5 further includes a first drive gate SFG1 and a second drive gate SFG2, a first select gate SG1 and a second select gate SG2, a reset gate RG, a gain control gate CG, and a dummy gate DMY. The first drive gate SFG1 and the second drive gate SFG2, the first select gate SG1 and the second select gate SG2, the reset gate RG, the gain control gate CG, and the dummy gate DMY are arranged side by side in the second direction on the left or right side of pixel PXk5.

[0177] Referring to FIG. 14F, the pixel PXj6 further includes a first drive gate SFG1 and a second drive gate SFG2, a first select gate SG1 and a second select gate SG2, a reset gate RG, a first control gate CG1 and a second gain control gate CG2, and a dummy gate DMY.

[0178] The first drive gate SFG1 and the second drive gate SFG2, the first select gate SG1 and the second select gate SG2, the reset gate RG, the first control gate CG1 and the second gain control gate CG2, and the dummy gate DMY are arranged in a line in the second direction on the left or right side of the pixel PXk6.

[0179] 15A, 15B, and 15C are plan views illustrating examples of pixels according to embodiments of the present invention.

[0180] 15A to 15C, the pixels PXl1, PXl2, and PXl3 include the first subpixel SPX1 to the fourth subpixel SPX4, which are arranged in a second direction, for example, the Y-axis direction. Here, the second direction is the column direction of the pixel array 110 (FIG. 1). Each of the first subpixel SPX1 to the fourth subpixel SPX4 includes the first photoelectric conversion element PD1 to the fourth photoelectric conversion element PD4, the first transmission gate TG1 to the fourth transmission gate TG4, and a floating diffusion region. The first floating diffusion region FD1 to the fourth floating diffusion region FD4 are arranged in the center of each of the first subpixel SPX1 to the fourth subpixel SPX4. The internal wiring WR is connected to the first floating diffusion region FD1 to the fourth floating diffusion region FD4 via the contact CT.

[0181] Referring to FIG. 15A, the pixel PXl1 further includes a first drive gate SFG1 and a second drive gate SFG2, a first select gate SG1 and a second select gate SG2, a reset gate RG, and a first dummy gate DMY1 to a third dummy gate DMY3.

[0182] The first drive gate SFG1 and the second drive gate SFG2, the first select gate SG1 and the second select gate SG2, the reset gate RG, and the first dummy gate DMY1 to the third dummy gate DMY3 are arranged side by side in the second direction on the left or right side of the pixel PXl1.

[0183] A first drive gate SFG1 and a first select gate SG1 are arranged between the first dummy gate DMY1 and the second dummy gate DMY, and a reset gate RG, a second drive gate SFG2, and a second select gate SG are arranged in that order between the second dummy gate DMY2 and the third dummy gate DMY3.

[0184] The source of the reset gate RG, the first drive gate SFG1 and the second drive gate SFG2 are each coupled to the internal wiring WR via a contact CT.

[0185] 15B, compared with pixel PXl1 of FIG. 15A, pixel PXl2 further includes a gain control gate CG. The gain control gate CG is disposed between the reset gate RG and the second drive gate SFG2. A well region between the reset gate RG and the gain control gate CG is connected to a wiring WRfd via a contact CT, and the wiring WRfd extends in the first and second directions.

[0186] 15C, compared with pixel PXl1 of FIG. 15A, pixel PXl3 further includes a first control gate CG1 and a second gain control gate CG2. The first control gate CG1 and the second gain control gate CG2 are disposed between the reset gate RG and the second drive gate SFG2. A well region between the reset gate RG and the first gain control gate CG1, and a well region between the first gain control gate CG1 and the second gain control gate CG2 are respectively connected to wirings WRfd1 and WRfd2 via contacts CT, and the wirings WRfd1 and WRfd2 extend in a first direction and a second direction.

[0187] 16A, 16B, 16C, and 16D show microlenses disposed in pixels according to one embodiment of the present invention.

[0188] The pixels according to the various embodiments described above may be applied as the pixel PX of the present embodiment. The pixel PX includes first to fourth sub-pixels SPX1 to SPX4, each of which includes a plurality of photoelectric conversion elements PD and a floating diffusion region FD. The photoelectric conversion elements PD included in the first to fourth sub-pixels SPX1 to SPX4 are electrically connected to each other via internal wiring.

[0189] 16A, a microlens ML is disposed on the upper part of the photoelectric conversion element PD. A plurality of microlenses ML are disposed on a plurality of photoelectric conversion elements PD included in a pixel PX. The pixel PX outputs a pixel signal based on charges generated in each of the plurality of photoelectric conversion elements PD, or outputs a pixel signal based on charges generated in some or all of the plurality of photoelectric conversion elements PD.

[0190] 16B, a plurality of microlenses ML are disposed on the four photoelectric conversion elements PD provided in each of the first to fourth sub-pixels SPX1 to SPX4. In other words, a microlens ML is disposed in each of the first to fourth sub-pixels SPX1 to SPX4. The pixel PX outputs a pixel signal according to charges generated in each of the first to fourth sub-pixels SPX1 to SPX4, or outputs a pixel signal according to charges generated in some or all of the first to fourth sub-pixels SPX1 to SPX4.

[0191] 16C and 16D, a microlens ML is disposed on every two adjacent photoelectric conversion elements among the plurality of photoelectric conversion elements PD. As shown in Fig. 16C, a microlens ML is disposed on two adjacent photoelectric conversion elements in a first direction, or as shown in Fig. 16D, a microlens ML is disposed on two adjacent photoelectric conversion elements in a second direction.

[0192] In one embodiment, in some of the first subpixel SPX1 to the fourth subpixel SPX4, a microlens ML is arranged on two photoelectric conversion elements adjacent in the first direction, and in some of the other subpixels, a microlens ML is arranged on two photoelectric conversion elements adjacent in the second direction.

[0193] 17A, 17B, 17C, 17D, 17E, and 17F show color filters disposed on pixel array 110 according to one embodiment of the present invention.

[0194] The pixel PX according to the above-described various embodiments is applied as the pixel PX of the present embodiment. The pixel PX includes the first sub-pixel SPX1 to the fourth sub-pixel SPX4, and each of the first sub-pixel SPX1 to the fourth sub-pixel SPX4 includes a plurality of photoelectric conversion elements PD and a floating diffusion region FD. The plurality of photoelectric conversion elements PD included in the first sub-pixel SPX1 to the fourth sub-pixel SPX4 are electrically connected to each other via internal wiring.

[0195] Referring to FIG. 17A, the first pixel PX1 to the fourth pixel PX4 are arranged in a 2X2 matrix, and a red color filter CF_R is arranged on the first pixel PX1, a green color filter CF_G is arranged on the second pixel PX2 and the third pixel PX3, and a blue color filter CF_B is arranged on the fourth pixel X4. In this manner, a combination of one red color filter CF_R, two green color filters CF_G, and one blue color filter CF_G is called a Bayer pattern. In the pixel array 110, every four pixels arranged in a 2X2 matrix have a Bayer pattern. In one embodiment, the color combination of the color filters arranged on the first pixel PX1 to the fourth pixel PX4 may be changed. For example, a white color filter may be arranged on one of the second pixel PX2 and the third pixel PX3. As another example, a white color filter may be arranged on the second pixel PX2 and the third pixel PX3. As another example, a yellow color filter may be disposed over the second pixel PX2 and the third pixel PX3.

[0196] 17B, ​​the first sub-pixel SPX1 to the fourth sub-pixel SPX4 are arranged in a 2X2 matrix, with a red color filter CF_R arranged on the first sub-pixel SPX1, a green color filter CF_G arranged on the second sub-pixel SPX2 and the third sub-pixel SPX3, and a blue color filter CF_B arranged on the fourth sub-pixel SPX4. Each of the pixels PX arranged in the pixel array 110 has a Bayer pattern.

[0197] Referring to FIG. 17C, the first pixel PX1 to the fourth pixel PX4 are arranged side by side in the second direction, and each of the first pixel PX1 to the fourth pixel PX4 includes the first sub-pixel SPX1 to the fourth sub-pixel SPX4 arranged side by side in the first direction.

[0198] A red color filter CF_R is arranged in the first sub-pixel SPX1 and the second sub-pixel SPX2 of the first pixel PX1 and the second pixel PX2, and a green color filter CF_G is arranged in the third sub-pixel SPX3 and the fourth sub-pixel SPX4 of the first pixel PX1 and the second pixel PX2 and the first sub-pixel SPX1 and the second sub-pixel SPX2 of the third pixel PX3 and the fourth pixel PX4. A blue color filter CF_B is arranged in the third sub-pixel SPX3 and the fourth sub-pixel SPX4 of the third pixel PX3 and the fourth pixel X4. In this way, in the pixel array 110, each of the 16 sub-pixels arranged in a 4X4 matrix has a Bayer pattern.

[0199] Referring to FIG. 17D, a first pixel PX1 and a second pixel PX2 are arranged side by side in the second direction, and each of the first pixel PX1 and the second pixel PX2 includes a first sub-pixel SPX1 to a fourth sub-pixel SPX4 arranged side by side in the first direction.

[0200] A red color filter CF_R is arranged in the first sub-pixel SPX1 and the third sub-pixel SPX3 of the first pixel PX1, and a green color filter CF_G is arranged in the second sub-pixel SPX2 and the fourth sub-pixel PSX4 of the first pixel PX1. A green color filter CF_G is arranged in the first sub-pixel SPX1 and the third sub-pixel SPX3 of the second pixel PX2, and a blue color filter CF_B is arranged in the second sub-pixel SPX2 and the fourth sub-pixel PSX4 of the second pixel PX1. In this way, a Bayer pattern is formed for every four sub-pixels arranged in a 2X2 matrix.

[0201] Referring to FIG. 17E, the first pixel PX1 to the fourth pixel PX4 are arranged side by side in a first direction, and each of the first pixel PX1 to the fourth pixel PX4 includes the first sub-pixel SPX1 to the fourth sub-pixel SPX4 arranged side by side in a second direction.

[0202] A red color filter CF_R is arranged in the first sub-pixel SPX1 and the second sub-pixel SPX2 of the first pixel PX1 and the second pixel PX2, and a green color filter CF_G is arranged in the third sub-pixel SPX3 and the fourth sub-pixel SPX4 of the first pixel PX1 and the second pixel PX2, and the first sub-pixel SPX1 and the second sub-pixel SPX2 of the third pixel PX3 and the fourth pixel PX4. A blue color filter CF_B is arranged in the third sub-pixel SPX3 and the fourth sub-pixel SPX4 of the third and fourth pixels PX3 and PX4. In this way, the pixel array 110 has a Bayer pattern for each of the 16 sub-pixels arranged in a 4X4 matrix.

[0203] Referring to FIG. 17F, a first pixel PX1 and a second pixel PX2 are arranged side by side in a first direction, and each of the first pixel PX1 and the second pixel PX2 includes a first sub-pixel SPX1 to a fourth sub-pixel SPX4 arranged side by side in a second direction.

[0204] A red color filter CF_R is arranged in the first sub-pixel SPX1 and the third sub-pixel SPX3 of the first pixel PX1, and a green color filter CF_G is arranged in the second sub-pixel SPX2 and the fourth sub-pixel PSX4 of the first pixel PX1. A green color filter CF_G is arranged in the first sub-pixel SPX1 and the third sub-pixel SPX3 of the second pixel PX2, and a blue color filter CF_B is arranged in the second sub-pixel SPX2 and the fourth sub-pixel PSX4 of the second pixel PX2. In this way, every four sub-pixels arranged in a 2X2 matrix have a Bayer pattern.

[0205] 18 and 19 are block diagrams of an electronic device including a multi-camera module, and FIG 19 is a detailed block diagram of the camera module of FIG 18.

[0206] Referring to FIG. 18, an electronic device 1000 includes a camera module group 1100, an application processor 1200, a power management integrated circuit (PMIC) 1300, and an external memory 1400.

[0207] The camera module group 1100 includes multiple camera modules (1100a, 1100b, 1100c). Although FIG. 18 illustrates an embodiment in which three camera modules (1100a, 1100b, 1100c) are arranged, the embodiment is not limited thereto. In some embodiments, the camera module group 1100 is modified to include only two camera modules. Also, in some embodiments, the camera module group 1100 is modified to include k camera modules (k is a natural number equal to or greater than 4).

[0208] The detailed configuration of camera module 1100b will be described in more detail below with reference to FIG. 19, but the following description also applies equally to other camera modules (1100a, 1100c) depending on the embodiment.

[0209] Referring to FIG. 19, a camera module 1100b includes a prism 1105, an optical path folding element (OPFE) 1110, an actuator 1130, an image sensing device 1140, and a storage unit 1150.

[0210] The prism 1105 includes a reflecting surface 1107 made of a light reflecting material, and changes the path of light L incident from the outside.

[0211] In some embodiments, the prism 1105 changes the path of the light L incident from a first direction X to a second direction Y perpendicular to the first direction X. The prism 1105 also rotates a reflecting surface 1107 of a light reflecting material about a central axis 1106 in a direction A and rotates the central axis 1106 in a direction B to change the path of the light L incident in the first direction X to a second direction Y perpendicular thereto. At this time, the OPFE 1110 also moves in a third direction Z perpendicular to the first direction X and the second direction Y.

[0212] In some embodiments, as shown, the maximum rotation angle of prism 1105 in the A direction is less than or equal to 15° in the positive (+) A direction and greater than or equal to 15° in the negative (-) A direction, although the embodiments are not so limited.

[0213] In some embodiments, prism 1105 moves in the plus (+) B direction or the minus (-) B direction by around 20°, or between 10° and 20°, or between 15° and 20°, where the angle of movement is the same angle in the plus (+) B direction or the minus (-) B direction, or to a similar angle within a range of around 1°.

[0214] In some embodiments, the prism 1105 moves the reflective surface 1107 of the light-reflective material in a third direction (eg, the Z direction) parallel to the extension direction of the central axis 1106 .

[0215] The OPFE 1110 includes, for example, m (where m is a natural number) optical lenses in a group. The m lenses move in the second direction Y to change the optical zoom ratio of the camera module 1100b. For example, when the basic optical zoom ratio of the camera module 1100b is Z, when the m optical lenses included in the OPFE 1110 are moved, the optical zoom ratio of the camera module 1100b is changed to an optical zoom ratio of 3Z or 5Z, or 5Z or more.

[0216] The actuator 1130 moves the OPFE 1110 (or the optical lens) to a specific position. For example, the actuator 1130 adjusts the position of the optical lens so that the image sensor 1142 is located at the focal length of the optical lens for accurate sensing.

[0217] The image sensing device 1140 includes an image sensor 1142, a control logic 1144, and a memory 1146. The image sensor 1142 senses an image of a sensing target using light L provided through an optical lens. The pixel and pixel array described with reference to Figs. 2 to 17F are applied to the image sensor 1142. The pixel includes a plurality of sub-pixels (e.g., four sub-pixels) each including a plurality of photoelectric conversion elements and a floating diffusion region, and the plurality of floating diffusion regions of the plurality of sub-pixels are electrically connected via wiring. The plurality of sub-pixels have a plurality of sensitivities. Therefore, the resolution and image quality of the image sensor 1142 are improved.

[0218] The control logic 1144 controls the overall operation of the camera module 1100b, for example, via control signals provided over the control signal line CSLb.

[0219] The memory 1146 stores information required for the operation of the camera module 1100b, such as calibration data 1147. The calibration data 1147 includes information required for the camera module 1100b to generate image data using light L provided from the outside. For example, the calibration data 1147 includes information related to a degree of rotation, a focal length, an optical axis, etc. If the camera module 1100b is implemented in the form of a multi-state camera in which the focal length changes depending on the position of an optical lens, the calibration data 1147 includes a focal length value for each position (or each state) of the optical lens and information related to auto focusing.

[0220] The storage unit 1150 stores image data sensed through the image sensor 1142. The storage unit 1150 is disposed outside the image sensing device 1140 and is implemented in a form stacked on a sensor chip constituting the image sensing device 1140.

[0221] In some embodiments, the storage unit 1150 is implemented by an EEPROM (electrically erasable programmable read-only memory), but the present embodiment is not limited thereto. In some embodiments, the image sensor 1142 is implemented by a pixel array, and the control logic 1144 includes an analog to digital converter and an image signal processor for processing the sensed image.

[0222] 18 and 19 together, in some embodiments, each of the multiple camera modules (1100a, 1100b, 1100c) includes an actuator 1130. As a result, each of the multiple camera modules (1100a, 1100b, 1100c) includes calibration data 1147 that is the same as or different from each other due to the operation of the actuator 1130 included therein.

[0223] In some embodiments, among the multiple camera modules (1100a, 1100b, 1100c), for example, one camera module 1100b is a folded lens type camera module including the above-mentioned prism 1105 and OPFE 1110, and the remaining camera modules (1100a, 1100c) are vertical type camera modules that do not include the prism 1105 and OPFE 1110, but this embodiment is not limited to these.

[0224] In some embodiments, one of the camera modules (1100a, 1100b, 1100c), for example the camera module 1100c, is a vertical depth camera that extracts depth information using infrared ray (IR). In this case, the application processor 1200 merges image data provided by such a depth camera with image data provided by a different camera module (1100a or 1100b) to generate a 3D depth image.

[0225] In some embodiments, for example, at least two of the camera modules (1100a, 1100b, 1100c) have different observation fields of view (field of view angles). In this case, for example, at least two of the camera modules (1100a, 1100b, 1100c) have different optical lenses from each other, but are not limited thereto.

[0226] In some embodiments, the viewing angles of the camera modules (1100a, 1100b, 1100c) are different from each other. For example, but not limited to, the camera module 1100a is an ultrawide camera, the camera module 1100b is a wide camera, and the camera module 1100c is a tele camera. In this case, the optical lenses included in the camera modules (1100a, 1100b, 1100c) are also different from each other, but are not limited to this.

[0227] In some embodiments, each of the multiple camera modules (1100a, 1100b, 1100c) is arranged to be physically separated from each other. That is, instead of the multiple camera modules (1100a, 1100b, 1100c) sharing the sensing area of ​​one image sensor 1142, an independent image sensor 1142 is arranged inside each of the multiple camera modules (1100a, 1100b, 1100c).

[0228] 18, the application processor 1200 includes an image processing unit 1210, a memory controller 1220, and an internal memory 1230. The application processor 1200 is implemented separately from the camera modules (1100a, 1100b, 1100c). For example, the application processor 1200 and the camera modules (1100a, 1100b, 1100c) are implemented separately from each other as separate semiconductor chips.

[0229] The image processing device 1210 includes multiple sub-image processors (1212a, 1212b, 1212c), an image generator 1214, and a camera module controller 1216.

[0230] The image processing device 1210 includes a number of sub-image processors (1212a, 1212b, 1212c) corresponding to the number of the camera modules (1100a, 1100b, 1100c).

[0231] Image data generated from each camera module (1100a, 1100b, 1100c) is provided to the corresponding sub-image processor (1212a, 1212b, 1212c) via image signal lines (ISLa, ISLb, ISLc) that are separated from each other. For example, image data generated from the camera module 1100a is provided to the sub-image processor 1212a via the image signal line ISLa, image data generated from the camera module 1100b is provided to the sub-image processor 1212b via the image signal line ISLb, and image data generated from the camera module 1100c is provided to the sub-image processor 1212c via the image signal line ISLc. Such image data transmission is performed, for example, using a camera serial interface (CSI) based on the mobile industry processor interface (MIPI), but the present embodiment is not limited thereto.

[0232] In some embodiments, one sub-image processor is arranged to correspond to a plurality of camera modules. For example, the sub-image processor 1212a and the sub-image processor 1212c are not embodied separately from each other as shown in the figure, but are integrated into one sub-image processor, and the image data provided from the camera module 1100a and the camera module 1100c are selected through a selection element (e.g., a multiplexer) and then provided to the integrated sub-image processor. At this time, the sub-image processor 1212b is not integrated and is provided with image data from the camera module 1100b.

[0233] In some embodiments, image data generated from camera module 1100a is provided to sub-image processor 1212a via image signal line ISLa, image data generated from camera module 1100b is provided to sub-image processor 1212b via image signal line ISLb, and image data generated from camera module 1100c is provided to sub-image processor 1212c via image signal line ISLc. The image data processed by sub-image processor 1212b is immediately provided to image generator 1214, but the image data processed by sub-image processor 1212a and the image data processed by sub-image processor 1212c are provided to image generator 1214 after one of them is selected via a selection element (e.g., a multiplexer) or the like.

[0234] Each sub-image processor (1212a, 1212b, 1212c) performs image processing such as bad pixel correction, 3A (auto-focus correction, auto-white balance, auto-exposure) adjustment, noise reduction, sharpening, gamma control, and remosaic on the image data provided by the camera modules (1100a, 1100b, 1100c).

[0235] In some embodiments, the re-mosaic signal processing is performed in each camera module (1100a, 1100b, 1100c) and then provided to the sub-image processors (1212a, 1212b, 1212c).

[0236] The image data processed by each of the sub-image processors (1212a, 1212b, 1212c) is provided to an image generator 1214. The image generator 1214 generates an output image using the image data provided from each of the sub-image processors (1212a, 1212b, 1212c) according to image generation information or a mode signal.

[0237] Specifically, the image generator 1214 generates an output image by combining at least a portion of the image data generated from the camera modules (1100a, 1100b, 1100c) having different viewing angles according to the image generation information or the mode signal. Also, the image generator 1214 selects one of the image data generated from the camera modules (1100a, 1100b, 1100c) having different viewing angles according to the image generation information or the mode signal, and generates an output image.

[0238] In some embodiments, the image generation information includes a zoom signal (or zoom factor), and in some embodiments the mode signal is based on a mode selected by a user, for example.

[0239] When the image generation information is a zoom signal (zoom factor) and each camera module (1100a, 1100b, 1100c) has a different observation field of view (viewing angle), the image generator 1214 performs different operations according to the type of zoom signal. For example, when the zoom signal is a first signal, the image generator 1214 generates an output image using the image data output from the sub-image processor 1212a and the image data output from the sub-image processor 1212b among the image data output from the sub-image processor 1212a and the image data output from the sub-image processor 1212c. If the zoom signal is a second signal different from the first signal, the image generator 1214 generates an output image using the image data output from the sub-image processor 1212c and the image data output from the sub-image processor 1212b among the image data output from the sub-image processor 1212a and the image data output from the sub-image processor 1212c. If the zoom signal is a third signal different from the first and second signals, the image generator 1214 does not perform such image data merging, but selects one of the image data output from each of the sub-image processors (1212a, 1212b, 1212c) to generate an output image. However, this embodiment is not limited to this, and the method of processing the image data can be modified in any way as necessary.

[0240] In some embodiments, the image processing device 1210 may further include a selection unit that selects the output of the sub-image processors (1212a, 1212b, 1212c) and transmits it to the image generator 1214.

[0241] In this case, the selector performs different operations depending on the zoom signal or the zoom factor. For example, when the zoom signal is a fourth signal (the zoom factor is the first factor), the selector selects one of the outputs of the sub-image processors (1212a, 1212b, 1212c) and transmits it to the image generator 1214.

[0242] Also, for example, when the zoom signal is a fifth signal (zoom magnification is second magnification) different from the fourth signal, the selection unit sequentially transmits p outputs (p is a natural number equal to or greater than 2) of the outputs of the sub-image processors (1212a, 1212b, 1212c) to the image generator 1214. For example, the selection unit sequentially transmits the outputs of the sub-image processor 1212b and the sub-image processor 1212c to the image generator 1214. Also, the selection unit sequentially transmits the outputs of the sub-image processor 1212a and the sub-image processor 1212b to the image generator 1214. The image generator 1214 merges the p outputs provided sequentially to generate one output image.

[0243] Here, image processing such as demosaic, video / preview, resolution size downscaling, gamma correction, and high dynamic range (HDR) processing is performed in advance in the sub-image processors 1212a, 1212b, and 1212c, and then the processed image data is transmitted to the image generator 1214. Therefore, even if the processed image data is provided to the image generator 1214 through a single signal line via a selection unit, the image merging operation of the image generator 1214 can be performed at high speed.

[0244] In some embodiments, the image generator 1214 receives multiple image data with different exposure times from at least one of the multiple sub-image processors (1212a, 1212b, 1212c) and generates merged image data with an increased dynamic range by performing HDR processing on the multiple image data.

[0245] The camera module controller 1216 provides control signals to each of the camera modules (1100a, 1100b, 1100c). The control signals generated by the camera module controller 1216 are provided to the corresponding camera modules (1100a, 1100b, 1100c) via mutually separated control signal lines (CSLa, CSLb, CSLc).

[0246] One of the multiple camera modules (1100a, 1100b, 1100c) is designated as, for example, a master camera 1100b by image generation information including a zoom signal or a mode signal, and the remaining camera modules (1100a, 1100c) are designated as slave cameras, for example. Such information is included in a control signal and provided to the corresponding camera modules (1100a, 1100b, 1100c) via separate control signal lines (CSLa, CSLb, CSLc).

[0247] The camera module acting as the master and the slave is changed depending on the zoom factor or the operation mode signal. For example, when the viewing angle of the camera module 1100a is wider than that of the camera module 1100b and the zoom factor indicates a low zoom ratio, the camera module 1100b acts as the master and the camera module 1100a acts as the slave. Conversely, when the zoom factor indicates a high zoom ratio, the camera module 1100a acts as the master and the camera module 1100b acts as the slave.

[0248] In some embodiments, the control signals provided from the camera module controller 1216 to each of the camera modules (1100a, 1100b, 1100c) include a sync enable signal. For example, if the camera module 1100b is a master camera and the camera modules 1100a and 1100c are slave cameras, the camera module controller 1216 transmits a sync enable signal to the camera module 1100b. The camera module 1100b that has received such a sync enable signal generates a sync signal based on the provided sync enable signal and provides the generated sync signal to the camera modules 1100a and 1100c via a sync signal line SSL. The camera modules 1100b and the camera modules 1100a and 1100c are synchronized with such a sync signal and transmit image data to the application processor 1200.

[0249] In some embodiments, the control signals provided to the camera modules (1100a, 1100b, 1100c) from the camera module controller 1216 include mode information in the form of a mode signal, and based on such mode information, the camera modules (1100a, 1100b, 1100c) operate in a first operation mode or a second operation mode associated with a sensing speed.

[0250] In a first operation mode, the camera modules (1100a, 1100b, 1100c) generate, for example, an image signal (an image signal having a first frame rate) at a first rate, encode the image signal at, for example, a second rate (a second frame rate higher than the first frame rate) higher than the first rate, and transmit the encoded image signal to the application processor 1200. In this case, the second rate is 30 times or less than the first rate.

[0251] The application processor 1200 stores the received image signal, in other words, the encoded image signal, in an internal memory 1230 provided therein or an external memory 1400 outside the application processor 1200, and then reads and decodes the encoded image signal from the internal memory 1230 or the external memory 1400, and displays image data generated based on the decoded image signal. For example, a corresponding sub-processor among a plurality of sub-processors (1212a, 1212b, 1212c) of the image processing device 1210 performs decoding and image processing on the decoded image signal.

[0252] In the second operation mode, the multiple camera modules (1100a, 1100b, 1100c) generate image signals at a third speed, for example, slower than the first speed (image signals having a third frame rate slower than the first frame rate), and transmit the image signals to the application processor 1200. The image signals provided to the application processor 1200 are unencoded signals. The application processor 1200 performs image processing on the received image signals or stores the image signals in the internal memory 1230 or the external memory 1400.

[0253] The PMIC 1300 supplies power, for example, a power supply voltage, to each of the multiple camera modules (1100a, 1100b, 1100c). For example, under the control of the application processor 1200, the PMIC 1300 supplies a first power to the camera module 1100a via a power signal line PSLa, supplies a second power to the camera module 1100b via a power signal line PSLb, and supplies a third power to the camera module 1100c via a power signal line PSLc.

[0254] The PMIC 1300 generates power and adjusts the power level corresponding to each of the camera modules (1100a, 1100b, 1100c) in response to a power control signal PCON from the application processor 1200. The power control signal PCON includes a power adjustment signal for each operation mode of the camera modules (1100a, 1100b, 1100c). For example, the operation mode includes a low power mode, and in this case, the power control signal PCON includes information related to the camera module operating in the low power mode and the power level to be set. The levels of power provided to each of the camera modules (1100a, 1100b, 1100c) may be the same or different from each other. Also, the power levels may be dynamically changed.

[0255] As above, exemplary embodiments have been disclosed with reference to the drawings and the specification. In this specification, specific terms are used to describe the embodiments, but they are used only for the purpose of describing the technical idea of ​​the present invention, and are not used to limit the meaning or the technical scope of the present invention. Therefore, a person skilled in the art can understand that various modifications and equivalent other embodiments are possible. [Explanation of symbols]

[0256] 100, 1142 Image sensor 110 pixel array 111 Substrate 112 Incidence layer 113 Wiring layer 120 Row Driver 130 Ramp Signal Generator 140 Analog-to-Digital Conversion Circuit 141 CDS circuit 142 Counter (CNTR) 150 Data output circuit 151 Column Memory (BF) 152 Column Decoder 160 Timing Controller 170 Signal Processing Section 1000 electronic devices 1100 Camera Module Group 1105 Prism 1106 Center axis 1107 Reflective surface 1110 OPEF 1130 Actuator 1140 Image sensing device 1144 Control logic 1146 Memory 1147 Calibration Data 1150 Preservation Department 1200 Application Processor 1210 Image Processing Device 1212a, 1212b, 1212c Sub-Image Processors 1214 Image Generator 1216 Camera module controller 1220 Memory Controller 1230 Internal Memory 1300 PMIC 1400 External Memory PX Pixels SPX1 1st subpixel SPX2 Second subpixel SPX3 3rd subpixel SPX4 4th subpixel

Claims

1. A substrate including a first surface and a second surface opposite to the first surface; a first pixel including first four photoelectric conversion elements (PD) in the substrate and a first floating diffusion region (FD) shared by the first four PDs; a second pixel including a second four PDs in the substrate and a second FD shared by the second four PDs; a third pixel including a third four PDs in the substrate and a third FD shared by the third four PDs; a fourth pixel including a fourth four PDs in the substrate and a fourth FD shared by the fourth four PDs; a red color filter on the first to fourth pixels; The first to fourth pixels are arranged in a clockwise direction, The first FD is connected to the fourth FD via a first internal wiring, The second FD is connected to the third FD via a second internal wiring, The image sensor, wherein the first four PDs to the fourth four PDs are arranged in a 2×2 matrix.

2. A fifth pixel including 16 PDs arranged in a 4×4 matrix in the substrate; a green color filter on the 16 PDs of the fifth pixel; and 2. The image sensor of claim 1, wherein the fifth pixel is disposed immediately adjacent to the second pixel and the third pixel.

3. A first microlens on the first four PDs; a second microlens on the second four PDs; a third microlens on the third four PDs; The image sensor of claim 2 , further comprising: a fourth microlens over the fourth four PDs.

4. Further comprising a deep trench isolation layer separating the first pixel and the second pixel; 2. The image sensor of claim 1, wherein the deep trench isolation layer contacts the first side and the second side of the substrate.

5. The image sensor as described in claim 1, characterized in that the first pixel is connected to the second pixel via a third internal wiring.

6. The first internal wiring and the second internal wiring extend in a first direction, The image sensor of claim 5 , wherein the third internal wiring extends in a second direction perpendicular to the first direction.

7. The image sensor as described in claim 1, characterized in that each of the first to fourth FDs is positioned at the center of the corresponding first to fourth pixel in a plan view.

8. A first via contact arranged vertically to the first FD; a second via contact arranged vertically to the fourth FD; 2. The image sensor of claim 1, wherein the first FD is connected to the fourth FD through the first via contact, the first internal wiring, and the second via contact.

9. An image sensor comprising: a substrate including a first surface and a second surface opposite the first surface; a first pixel including first four photoelectric conversion elements (PD) in the substrate and a first floating diffusion region (FD) shared by the first four PDs; a second pixel including a second four PDs in the substrate and a second FD shared by the second four PDs; a third pixel including a third four PDs in the substrate and a third FD shared by the third four PDs; a fourth pixel including a fourth four PDs in the substrate and a fourth FD shared by the fourth four PDs; a red color filter on the first to fourth pixels; The first FD is connected to the fourth FD via a first internal wiring, The second FD is connected to the third FD via a second internal wiring, The first internal wiring and the second internal wiring extend in a first direction, The first four PDs to the fourth four PDs are arranged in a 2×2 matrix, The image sensor is configured to receive light through the first surface of the substrate.

10. A gain control transistor configured to be coupled to the first four PDs and the fourth four PDs; The image sensor of claim 9 , further comprising: a reset transistor configured to be serially coupled with the gain control transistor.

11. The semiconductor device further includes a deep trench isolation layer separating the first pixel and the second pixel; 10. The image sensor of claim 9, wherein the deep trench isolation layer contacts the first side and the second side of the substrate.

12. A fifth pixel including 16 PDs arranged in a 4×4 matrix in the substrate; a green color filter on the 16 PDs of the fifth pixel; and The image sensor of claim 9 , wherein the fifth pixel is disposed directly adjacent to the first pixel and the fourth pixel in the first direction.

13. A first microlens on the first four PDs; a second microlens on the second four PDs; a third microlens on the third four PDs; The image sensor of claim 12 , further comprising: a fourth microlens on the fourth four PDs.

14. A first four microlenses on the first four PDs; second four microlenses on the second four PDs; a third four microlenses on the third four PDs; 10. The image sensor of claim 9, further comprising: a fourth four microlenses on the fourth four PDs.

15. The image sensor of claim 9, wherein the first pixel is connected to the second pixel via a third internal wiring.

16. The image sensor of claim 15, wherein the third internal wiring extends in a second direction perpendicular to the first direction.

17. A first via contact arranged vertically to the first FD; a second via contact arranged vertically to the fourth FD; 10. The image sensor of claim 9, wherein the first FD is connected to the fourth FD through the first via contact, the first internal wiring, and the second via contact.

18. An image sensor comprising: a substrate including a first surface and a second surface opposite the first surface; a first pixel including first four photoelectric conversion elements (PD) in the substrate and a first floating diffusion region (FD) shared by the first four PDs; a second pixel including a second four PDs in the substrate and a second FD shared by the second four PDs; a third pixel including a third four PDs in the substrate and a third FD shared by the third four PDs; a fourth pixel including a fourth four PDs in the substrate and a fourth FD shared by the fourth four PDs; The first four PDs to the fourth four PDs are arranged in a 2×2 matrix, The image sensor is configured to receive light through the first surface of the substrate.

19. A fifth pixel including 16 PDs arranged in a 4×4 matrix in the substrate; a green color filter on the 16 PDs of the fifth pixel; and 20. The image sensor of claim 18, wherein the fifth pixel is disposed immediately adjacent to the first pixel and the fourth pixel in a first direction.

20. A method for manufacturing a semiconductor laser comprising: a first microlens on the first four PDs; and a second microlens on the second four PDs; a third microlens on the third four PDs; 20. The image sensor of claim 19, further comprising: a fourth microlens on the fourth four PDs.

Images