Avoiding Garbage Collection in High-Performance Memory Management Systems.

Abstract

In one example, the memory region is a heap region, and the reclamation bypasses at least the pause and copy phases of a garbage collection process for the heap region.

Description

Technical Field

[0001] Embodiments generally relate to memory management in the computerization of architectures. More specifically, embodiments relate to the avoidance of garbage collection in high-performance memory management systems.

Background Art

[0002] During operation, a computer program may allocate memory to various objects to perform operations involved in the execution of the program. When the computer program does not deallocate memory from objects that are no longer used, the available memory is unnecessarily reduced, which can negatively affect performance and lead to system failures (e.g., when no additional memory is available). Programs such as managed runtime applications 「 garbage collector 」 may be used , automatically frees up memory that is no longer in use but there is still room for significant improvement. For example, conventional garbage collector can negatively affect performance in terms of processor usage, unexpected pauses in the user interface, additional power consumption (e.g., reduced battery life), etc.

Brief Description of the Drawings

[0003] Various advantages of the present embodiments will become apparent to those skilled in the art by reading the following specification and appended claims and by referring to the following drawings. [Figure 1] An example of the allocation space after a thread is created according to an embodiment is shown. [Figure 2] It is a flowchart of an example of the specialization of the memory area of an object associated with a thread according to an embodiment. [Figure 3] An example of the allocation space after memory is freed according to an embodiment is shown. [Figure 4] It is a flowchart of an example of memory freeing according to an embodiment. [Figure 5] This is a flowchart illustrating an example of a method for managing memory according to the embodiment. [Figure 6] This is a flowchart illustrating an example of a method for managing memory according to the embodiment. [Figure 7] This is a block diagram of an example of a performance-enhanced computing system according to an embodiment. [Figure 8] An example of a semiconductor packaging device according to the embodiment is shown. [Figure 9] This is a block diagram of an example processor according to the embodiment. [Figure 10] This is a block diagram of an example of a multiprocessor-based computing system according to an embodiment. [Modes for carrying out the invention]

[0004] Returning to Figure 1, the allocation space 20 (20a-20e) is shown after the thread has been created. In some embodiments, the allocation space 20 is a portion of heap memory used to perform dynamic memory allocation during the runtime operation of a computer program that creates and terminates (e.g., destroys) threads. The heap memory may also include other memory areas (not shown), such as large object areas (e.g., storing relatively large primitive arrays and / or string arrays), image areas (e.g., storing executable files, resource files, etc.), shared areas (e.g., storing objects shared by multiple processes), and static areas (e.g., storing long-lived objects). In one example, the allocation space 20 stores relatively short-lived objects that may be targeted during the garbage collection process. Furthermore, threads may accommodate user interface activities that provide rich special effects and cause short-lived objects to consume relatively large amounts of memory.

[0005] In the illustrated example, the allocation space 20 includes a first region 20a ("region 1"), a second region 20b ("region 2"), a third region 20c ("region 3"), a fourth region 20d ("region 4"), and a fifth region 20e ("region 5"). The number of regions shown is for illustrative purposes only and may vary depending on the circumstances. The regions of the shown allocation space 20 are individually and exclusively dedicated to specific threads and / or activities. For example, the second region 20b and the third region 20c may be exclusively dedicated to the first thread ("thread 1"), the fourth region 20d may be exclusively dedicated to the second thread ("thread 2"), and so on. In the embodiment, objects in the second region 20b and the third region 20c may be shared between the first thread and the associated functions without performing extraneous copying operations. Similarly, objects in the fourth region 20d can be shared between the second thread and associated functions without performing extraneous copy operations. As will be described in more detail, the presented solution enables performance enhancement.

[0006] Figure 2 shows the memory allocation mechanism (e.g., the framework layer runtime manager) creating a new thread function 24( Callback method "onCreate() ") Flowchart 22 shows how to detect this. In the illustrated example, the memory allocation means triggers the dedication of a memory region to a thread by issuing a first command 26 ("StartMemoryRegion()"). When the application calls function 24, all objects associated with the new thread (e.g., "object a", "object b") are allocated to the dedicated memory region. In addition to calling function 24, the memory allocation means activates thread-based allocation, The A flag may be set on the thread object. In an embodiment, the memory allocation means also maps the thread to a dedicated memory region. Table 1 below shows an example of such a mapping. Table 1 [Table 1]

[0007] O Project of allocation Function 24 When this is done, the indicated memory allocation means is the memory region in question. of object To make it exclusively for that purpose To interrupt it, a second command 28 ("StopMemoryRegion()") is issued. The memory allocation mechanism also deactivates thread-based allocation in response to the thread stopping. The Thread object of The flag may be cleared. In the embodiment, the memory allocation means also the appropriate thread Opposite domain Clear the table mapping entries. Below is an example of pseudocode that implements the first command 26 and the second command 28. StartMemoryRegion(){ threadId = GetThreadId(); SetActivityModeAllocate(threadId); regionId=AllocateNewRegion(); Record the threadId and regionId in the table; StopMemoryRegion(){ threadId = GetThreadId(); UnsetActivityModeAllocate(threadId);

[0008] If the size of the selected area is insufficient, additional unused areas may be dedicated to the objects associated with the thread. In an embodiment, the memory allocation means checks whether the thread is in the thread allocation mode. If not, the memory allocation means may switch to the normal allocation mode. Otherwise, the memory allocation means searches the table to find a specific area identifier and attempts to allocate an object to the specified area. If the area is full, the memory allocation means may allocate another area to the thread and update the corresponding table. An example of pseudo-code implementing the selection of additional areas is shown below. AllocateObject(){ threadId=GetThreadId(); checkActivityMode(threadId);

[0009] If not true: / / Otherwise, the original code path for allocating to the object: regionid=FindRegionID(threadid); AllocateObject(regionid); If not enough space: newRegionId=AllocateNewRegion(); Update the table with newRegionId. AllocateObject(newRegionid); }

[0010] Continuing to refer to FIGS. 1 and 3, the suspension of a thread may trigger the release of all areas dedicated to the thread. For example, the suspension of thread 1 , the All objects in the second area 20b and the third area 20c of 2 liberationThis results in the following: In some embodiments, thread termination is detected based on information from a higher level (e.g., upper layers) of the application. Of particular note is the garbage disposal behavior, such as a pause operation, where all other threads pause (e.g., so that the GC can collect the root object set and determine which areas should be freed). collector The (GC) operation may be bypassed. Other GC operations, such as the copy operation in which the GC scans all living objects starting from the root set and copies those objects to unused areas (e.g., the destination area), are also bypassed in the indicated solution. In fact, if a thread generates only short-lived objects, the frequency of performing GC operations may approach zero. This thus enhances performance in terms of processor usage, unexpected pauses in the user interface, and additional power consumption (e.g., reduced battery life).

[0011] Figure 4 shows the memory allocation means, which has a function 32 that terminates existing threads. Callback method "onDestroy() ") Flowchart 33 shows how to detect the background. In this embodiment, function 32 is background And many Too many applications What is being done , for example, closing the application and removing it from the list of active applications. resulting from In the illustrated example, the memory allocation means triggers the release of one or more memory regions dedicated to a thread by issuing command 34 ("ReclaimMemoryRegion()"). When the application calls function 32, all memory regions dedicated to the thread will be released. In the embodiment, the memory allocation means identifies the selected region for the thread, for example, by searching a table such as Table 1 for appropriate thread identifiers. Regions may be released one at a time. An example of pseudocode implementing command 34 is shown below.

[0012] ReclaimMemoryRegion(){ threadid=GetThreadId(); allRegionIds=FindAllRegionIDs(threadid); For each ID in allRegionIds: FreeRegion(id); }

[0013] Figure 5 shows a method 40 for managing memory. Method 40 can generally be implemented in memory allocation means, for example, the memory allocation means described above (Figure 1). More specifically, method 40 can be implemented as one or more modules in a set of logic instructions stored in machine or computer-readable storage media such as random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), firmware, flash memory, configurable logic such as programmable logic arrays (PLA), field-programmable gate arrays (FPGA), complex-programmable logic devices (CPLD), fixed-function hardware logic using circuit technologies such as application-specific integrated circuits (ASICs), complementary metal-oxide-semiconductor (CMOS), or transistor-transistor logic (TTL) technology, or any combination thereof.

[0014] For example, computer program code that performs the operations shown in Method 40 may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java®, Smalltalk®, and C++, and traditional procedural programming languages ​​such as the "C" programming language or similar programming languages. Furthermore, logic instructions may include assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, state setting data, configuration data for integrated circuits, state information to personalize electronic circuits, and / or other hardware-specific structural components (e.g., host processor, central processing unit (CPU), microcontroller, etc.).

[0015] The illustrated processing block 42 detects the start of a thread, where the first memory region is dedicated to the object associated with the thread in block 44. In the embodiment, block 44 includes activating thread-based allocation and mapping the thread to the first memory region. Block 46 may determine whether a thread shutdown has started. If not, the illustrated method 40 iterates through block 46. It should be noted that objects associated with the same thread are expected to have similar lifecycles. Therefore, upon detection of a thread shutdown, block 48 responds to the shutdown by mapping the first memory region to the first release The method further includes deactivating thread-based allocation in response to thread termination and unmapping the thread from a first memory region. In one example, the first memory region is a heap region, and the first releaseThis bypasses the garbage collection process's pause and copy operations related to the heap area. Furthermore, the thread can handle user interface (UI) activity. Method 40 can therefore enhance performance in terms of processor usage, unexpected pauses in the user interface, and additional power consumption (e.g., reduced battery life).

[0016] The illustrated method 40 is for native applications such as C or C++ applications, and also for automatically freeing garbage memory that is no longer in use. collector It may be used for managed runtime applications that have [specific features / frameworks]. Managed runtime applications may include, but are not limited to, HTML5 (Hypertext Markup Language 5, e.g., HTML5.2, W3C Recommendation, December 14, 2017), JAVASCRIPT®, C# (e.g., C#7.3, MICROSOFT® Corp., May 7, 2018), Ruby (e.g., Ruby2.6.3, Y.Matsumoto, April 17, 2019), Perl (e.g., Perl5.28.2, Perl.org, April 19, 2019), Python® (e.g., Python® 3.7.3, Python® Software Foundation, March 25, 2019), Java® (e.g., Java® 10, Oracle Corp., March 20, 2018), etc.

[0017] Figure 6 shows another method 50 for managing memory. Method 50 can generally be implemented in memory allocation means, for example, the memory allocation means described above (Figure 1). More specifically, Method 50 can be implemented as one or more modules of a set of logic instructions stored in a machine- or computer-readable storage medium such as RAM, ROM, PROM, firmware, or flash memory; configurable logic such as PLA, FPGA, or CPLD; fixed-function hardware logic using circuit technology such as ASIC, CMOS, or TTL technology; or any combination thereof.

[0018] The shown processing block 52 determines whether the first memory region is full. If it is full, the second memory region may be reserved for the object associated with the thread in block 54. Furthermore, block 56 may determine whether the thread has started to terminate. If it has not started, the illustrated method 50 repeats block 56. When a thread termination is detected, block 58 reserves the second memory region in response to the thread termination. release Therefore, method 50 further enhances performance by supporting threads that allocate a relatively large number of objects (e.g., much larger than the stack, thus eliminating concerns about stack overflow).

[0019] Returning to Figure 7, we see the performance-enhanced computing system 150. The system 150 may be part of an electronic device / platform having computing functions (e.g., personal digital assistants (PDAs), notebook computers, tablet computers, convertible tablets, servers), communication functions (e.g., smartphones), imaging functions (e.g., cameras, camcorders), media playback functions (e.g., smart televisions (TVs)), wearable functions (e.g., watches, glasses, hats, shoes, jewelry), vehicle functions (e.g., cars, trucks, motorcycles), robotic functions (e.g., autonomous robots), or any combination thereof. In the illustrated example, the system 150 includes a host processor 152 (e.g., a central processing unit / CPU) having an integrated memory controller (IMC) 154 coupled to a system memory 156.

[0020] The illustrated system 150 also includes an input / output (IO) module 158 implemented on a semiconductor die 162 as a system-on-a-chip (SoC) together with a host processor 152 and a graphics processor 160. For example, the illustrated IO module 158 communicates with a display 164 (e.g., a touchscreen, liquid crystal display (LCD), or light-emitting diode (LED) display), a network controller 166 (e.g., a wired and / or wireless NIC), and mass storage 168 (e.g., a hard disk drive (HDD), optical disc, solid-state drive (SSD), or flash memory).

[0021] In the embodiment, the host processor 152 and / or the IO module 158 execute program instructions 170 retrieved from system memory 156 and / or mass storage 168 to perform one or more aspects of the previously described method 40 (Figure 5) and / or method 50 (Figure 6). Thus, the execution of the indicated instructions 170 causes the computing system 150 to detect the creation of a thread, dedicate a first memory region in system memory 156 to the object associated with the thread, and in response to the cessation of the thread, the first memory region release This may be done. In this embodiment, the first memory area is the heap area, and the first release This bypasses at least the pause and copy operations of the garbage collection process with respect to the heap area. Furthermore, the thread may handle UI activities (e.g., in a high-performance game application) that make objects short-lived and consume a relatively large amount of system memory 156. In such cases, the indicated display 164 visually represents the information associated with the UI activity.

[0022] As already noted, GC operations such as pause operations, which pause all other threads (for example, to allow the GC to collect the root object set and determine which areas should be freed), may be bypassed. Other GC operations, such as copy operations, which scan all living objects starting from the root set and copy those objects to unused areas (e.g., destination areas), are also bypassed in the indicated solution. Thus, the performance of computing system 150 is enhanced in terms of processor usage, unexpected pauses in the user interface, and additional power consumption (e.g., reduced battery life).

[0023] Figure 8 shows a semiconductor device 172 (e.g., a chip, die, or package). The illustrated device 172 comprises one or more substrates 174 (e.g., silicon, sapphire, or gallium arsenide) and logic 176 (e.g., transistor arrays and other integrated circuit (IC) components) coupled to one or more substrates 174. In embodiments, the logic 176 implements one or more aspects of the previously described method 40 (Figure 5) and / or method 50 (Figure 6). Thus, the logic 176 detects the creation of a thread, dedicates a first memory region to the object associated with the thread, and, in response to the cessation of the thread, dedicates the first memory region to the first release This may be done. In this embodiment, the first memory area is the heap area, and the first release This bypasses (e.g., avoids) at least the pause and copy operations of the garbage collection process with respect to the heap area. Thus, the performance of device 172 is enhanced in terms of processor usage, unexpected pauses in the user interface, and additional power consumption (e.g., reduced battery life).

[0024] Logic 176 can be implemented, at least partially, in configurable logic or fixed-function hardware logic. In one example, logic 176 includes a transistor channel region located (e.g., embedded) within the substrate 174. Thus, the interface between logic 176 and the substrate 174 may not be a step junction. Logic 176 can also be considered to comprise an epitaxial layer growing on the initial wafer of the substrate 174.

[0025] Figure 9 shows a processor core 200 according to one embodiment. The processor core 200 may be a core for any type of processor, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, or any other device that executes code. Although only one processor core 200 is shown in Figure 9, the processing elements may alternatively include more than one of the processor cores 200 shown in Figure 9. The processor core 200 may be a single-threaded core, or, in at least one embodiment, the processor core 200 may be multi-threaded in the sense that it may include one or more hardware thread contexts (or “logical processors”) per core.

[0026] Figure 9 also shows memory 270 coupled to the processor core 200. Memory 270 may be any of the many types of memory known to those skilled in the art or otherwise available to those skilled in the art (including various layers of the memory hierarchy). As already described, memory 270 may contain one or more code 213 instructions executed by the processor core 200, and code 213 may implement method 40 (Figure 5) and / or method 50 (Figure 6). The processor core 200 follows a program sequence of instructions indicated by code 213. Each instruction may enter a front-end unit 210 and be processed by one or more decoders 220. The decoders 220 may produce microoperations as their output, such as fixed-width microoperations in a predefined format, or they may produce other instructions, microinstructions, or control signals that reflect the original code instruction. The shown front-end unit 210 also includes register renaming logic 225 and scheduling logic 230, which generally allocate resources and queue operations corresponding to translation instructions for execution.

[0027] A processor core 200 is shown, which includes execution logic 250 having a set of execution units 255-1 to 255-N. Some embodiments may include multiple execution units dedicated to a particular function or set of functions. Other embodiments may include only one execution unit, or one execution unit capable of performing a particular function. The shown execution logic 250 performs operations specified by code instructions.

[0028] After the completion of the operation specified by the code instruction, the backend logic 260 causes the instruction of code 213 to be avoided. In one embodiment, the processor core 200 enables out-of-order execution but requires in-order retirement of the instruction. The retirement logic 265 can take various forms known to those skilled in the art (e.g., a reorder buffer or similar). In this way, the processor core 200 is transformed during the execution of code 213, at least in terms of the output generated by the decoder, the hardware registers and tables utilized by the register renaming logic 225, and any registers (not shown) modified by the execution logic 250.

[0029] Although not shown in Figure 9, the processing element may include other elements on the chip having the processor core 200. For example, the processing element may include memory control logic together with the processor core 200. The processing element may include I / O control logic and / or I / O control logic integrated with the memory control logic. The processing element may also include one or more caches.

[0030] Referring now to Figure 10, a block diagram of an embodiment of computing system 1000 according to the embodiment is shown. Shown in Figure 10 is a multiprocessor system 1000 including a first processing element 1070 and a second processing element 1080. Although two processing elements 1070 and 1080 are shown, it will be understood that embodiments of system 1000 may also include only one such processing element.

[0031] System 1000 is shown as a point-to-point interconnect system, where the first processing element 1070 and the second processing element 1080 may be connected via the point-to-point interconnect 1050. It should be understood that any or all interconnects shown in Figure 10 may be implemented as multidrop buses rather than point-to-point interconnects.

[0032] As shown in Figure 10, each of the processing elements 1070 and 1080 may be a multicore processor including first and second processor cores (i.e., processor cores 1074a and 1074b and processor cores 1084a and 1084b). Such cores 1074a, 1074b, 1084a, and 1084b may be configured to execute instruction code in a manner similar to that described above in relation to Figure 9.

[0033] Each processing element 1070, 1080 may include at least one shared cache 1896a, 1896b. The shared caches 1896a, 1896b may store data (e.g., instructions) used by one or more components of the processor, such as cores 1074a, 1074b and cores 1084a, 1084b, respectively. For example, the shared caches 1896a, 1896b may locally cache data stored in memories 1032, 1034 for faster access by components of the processor. In one or more embodiments, the shared caches 1896a, 1896b may include one or more intermediate-level caches, last-level caches (LLCs), and / or combinations thereof, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other level caches.

[0034] While only two processing elements 1070 and 1080 are shown, it will be understood that the scope of the embodiments is not limited thereto. In other embodiments, one or more additional processing elements may be present in a given processor. Alternatively, one or more of the processing elements 1070 and 1080 may be non-processor elements such as accelerators or field-programmable gate arrays. For example, the additional processing elements may include an additional processor identical to the first processor 1070, an additional processor that is heterogeneous or asymmetrical to the first processor 1070, an accelerator (e.g., a graphics accelerator or a digital signal processing (DSP) unit), a field-programmable gate array, or any other processing element. Various differences may exist between the processing elements 1070 and 1080 in terms of a wide variety of value criteria, including architectural characteristics, microarchitectural characteristics, thermal characteristics, power consumption characteristics, and so on. These differences may effectively represent themselves as asymmetries and heterogeneities between the processing elements 1070 and 1080. In at least one embodiment, various processing elements 1070, 1080 may be present in the same die package.

[0035] The first processing element 1070 may further include memory controller logic (MC) 1072 and point-to-point (P-P) interfaces 1076 and 1078. Similarly, the second processing element 1080 may include MC 1082, as well as PP interfaces 1086 and 1088. As shown in Figure 10, MCs 1072 and 1082 connect the processors to their respective memories, namely memory 1032 and memory 1034. These memories may be portions of the main memory locally attached to each processor. Although MCs 1072 and 1082 are shown as integrated into processing elements 1070 and 1080, in alternative embodiments, the MC logic may be separate logic outside of processing elements 1070 and 1080 rather than integrated into them.

[0036] The first processing element 1070 and the second processing element 1080 may be coupled to the I / O subsystem 1090 via PP interconnects 1076 and 1086, respectively. As shown in Figure 10, the I / O subsystem 1090 includes PP interfaces 1094 and 1098. Furthermore, the I / O subsystem 1090 includes interface 1092 which couples the I / O subsystem 1090 with the high-performance graphics engine 1038. In one embodiment, bus 1049 may be used to couple the graphics engine 1038 with the I / O subsystem 1090. Alternatively, a point-to-point interconnect may couple these components.

[0037] Similarly, the I / O subsystem 1090 may be coupled to the first bus 1016 via interface 1096. In one embodiment, the first bus 1016 may be a Peripheral Component Interconnect (PCI) bus, a PCI Express bus, or other third-generation I / O interconnect bus, but the scope of the embodiment is not limited to these.

[0038] As shown in Figure 10, various I / O devices 1014 (e.g., biometric scanners, speakers, cameras, sensors) can be coupled to the first bus 1016, along with a bus bridge 1018 that can couple the first bus 1016 to the second bus 1020. In one embodiment, the second bus 1020 may be a low-pin-count (LPC) bus. In one embodiment, various devices can be coupled to the second bus 1020, which includes a data storage unit 1019, such as a keyboard / mouse 1012, a communication device 1026, and other mass storage devices that may include a disk drive or code 1030. The shown code 1030 may implement method 40 (Figure 5) and / or method 50 (Figure 6), as already described, and may be similar to code 213 (Figure 9), as already described. Furthermore, the audio I / O 1024 may be coupled to the second bus 1020, and the battery 1010 may supply power to the computing system 1000.

[0039] It should be noted that other embodiments are contemplated. For example, instead of the point-to-point architecture of Figure 10, the system may implement a multidrop bus or other such communication topology. Also, the elements of Figure 10 may be divided using more or fewer integrated chips than those shown in Figure 10. [Additional notes and examples]

[0040] Example 1 includes an enhanced computing system comprising a display, a processor coupled to the display, and memory coupled to the processor, wherein the memory contains a set of executable program instructions, and when executed by the processor, the set of executable program instructions causes the computing system to detect the creation of a thread, dedicate a first memory region to an object associated with the thread, and in response to the cessation of the thread, the first memory region release Have them do it.

[0041] Example 2 includes the computing system described in Example 1, wherein the first memory region is a heap region, and the first release This bypasses the garbage collection process's pause and copy operations related to the heap area mentioned above.

[0042] Example 3 includes the computing system described in Example 1, wherein the executable program instruction, when executed, causes the computing system to activate thread-based allocation and map the thread to the first memory region so that the first memory region is dedicated to the object associated with the thread.

[0043] Example 4 includes the computing system described in Example 3, wherein, when the executable program instruction is executed, it causes the computing system to deactivate the thread-based allocation in response to the termination of the thread and to unmap the thread from the first memory region.

[0044] Example 5 includes the computing system described in Example 1, and when the executable program instruction is executed, the computing system, in response to determining that the first memory area is full, causes the second memory area to be dedicated to the object associated with the thread, and in response to the termination of the thread, the second memory area release Have them do it.

[0045] Example 6 includes a computing system described in any one of Examples 1 to 5, wherein the thread corresponds to user interface activity, and the display visually represents information associated with the user interface activity.

[0046] Example 7 includes a semiconductor device comprising one or more boards and logic coupled to the one or more boards, wherein the logic is at least partially implemented in one or more configurable logic or fixed-function hardware logic, and the logic coupled to the one or more boards detects the creation of a thread, dedicates a first memory region to an object associated with the thread, and in response to the cessation of the thread, the first memory region release To do so.

[0047] Example 8 includes the device described in Example 7, wherein the first memory area is a heap area, and the first release This bypasses the garbage collection process's pause and copy operations related to the heap area mentioned above.

[0048] Example 9 includes the apparatus described in Example 7, wherein the logic coupled to the one or more boards activates thread-based allocation and maps the thread to the first memory area so that the first memory area is dedicated to the object associated with the thread.

[0049] Example 10 includes the apparatus described in Example 9, wherein the logic coupled to the one or more boards deactivates the thread-based allocation and unmaps the thread from the first memory region in response to the termination of the thread.

[0050] Example 11 includes the apparatus described in Example 7, wherein the logic coupled to the one or more boards, in response to a determination that the first memory area is full, dedicates the second memory area to the object associated with the thread, and in response to the termination of the thread, the second memory area release Have them do it.

[0051] Example 12 includes the device described in any one of Examples 7 through 11, and the thread corresponds to user interface activity.

[0052] Example 13 includes at least one computer-readable storage medium comprising a set of executable program instructions, wherein, when executed by a computing system, the set of executable program instructions causes the computing system to detect the creation of a thread, to dedicate a first memory region to an object associated with the thread, and in response to the termination of the thread, the first memory region release Have them do it.

[0053] Example 14 includes at least one computer-readable storage medium as described in Example 13, wherein the first memory region is a heap region, and the first release This bypasses the garbage collection process's pause and copy operations related to the heap area mentioned above.

[0054] Example 15 includes at least one computer-readable storage medium as described in Example 13, and the executable program instruction, when executed, causes the computing system to activate thread-based allocation and map the thread to the first memory region so that the first memory region is dedicated to the object associated with the thread.

[0055] Example 16 includes at least one computer-readable storage medium as described in Example 15, wherein, when executed, the executable program instruction causes the computing system to deactivate the thread-based allocation in response to the termination of the thread and to unmap the thread from the first memory region.

[0056] Example 17 includes at least one computer-readable storage medium as described in Example 13, wherein, when the executable program instruction is executed, the computing system, in response to determining that the first memory area is full, causes the second memory area to be dedicated to the object associated with the thread, and in response to the termination of the thread, the second memory area release Have them do it.

[0057] Example 18 includes at least one computer-readable storage medium as described in any one of Examples 13 to 17, wherein the thread corresponds to user interface activity.

[0058] Example 19 includes the steps of detecting the creation of a thread, dedicating a first memory region to an object associated with the thread, and in response to the termination of the thread, the first memory region release This includes a step of performing and a method comprising

[0059] Example 20 includes the method described in Example 19, wherein the first memory region is a heap region, and the first releaseThis bypasses the garbage collection process's pause and copy operations related to the heap area mentioned above.

[0060] Example 21 includes the method described in Example 19, wherein the step of dedicating the first memory region to the object associated with the thread includes the steps of activating thread-based allocation and mapping the thread to the first memory region.

[0061] Example 22 includes the method described in Example 21, further comprising the steps of deactivating the thread-based allocation in response to the termination of the thread, and unmapping the thread from the first memory region.

[0062] Example 23 includes the method described in Example 19, the steps being: in response to a determination that the first memory area is full, the second memory area is dedicated to the object associated with the thread; and in response to the termination of the thread, the second memory area release This further includes the stage of having the action taken.

[0063] Example 24 includes the method described in any one of Examples 19 through 23, where the thread corresponds to user interface activity.

[0064] Accordingly, the technique described herein packs activities and objects created by such activities into a single bundle of objects and frees all memory consumed by those objects simultaneously (e.g., without calling a GC thread). The technique may be applied to any language and may focus on freeing all objects that share a similar lifespan. Furthermore, the technique does not impose any additional burden on application developers (e.g., all modifications may be done in a managed runtime framework layer). The technique is also transparent to the user (e.g., does not negatively impact the user experience) and supports the sharing of objects between functions without superfluous copying operations (e.g., initialization / RAII resolution in threaded memory allocation and / or resource allocation means).

[0065] The embodiments are suitable for use with all types of semiconductor integrated circuit ("IC") chips. Examples of these IC chips include, but are not limited to, processors, controllers, chipset components, programmable logic arrays (PLAs), memory chips, network chips, system-on-a-chip (SoCs), SSD / NAND controller ASICs, and similar devices. In addition, in some figures, signal lines are represented by lines. Some may differ to indicate more component signal paths, may have numbered labels to indicate multiple component signal paths, and / or may have arrows at one or more ends to indicate the direction of flow of primary information. However, this should not be interpreted restrictively. Rather, such additional details may be used in relation to one or more exemplary embodiments to facilitate a more easily understood circuit. Any signal line represented, whether or not it has additional information, may actually carry one or more signals that can propagate in multiple directions and may be implemented with any suitable type of signaling scheme, e.g., digital or analog lines implemented in differential pairs, optical fiber lines, and / or single-ended lines.

[0066] While exemplary sizes / models / values / ranges have been given, embodiments are not limited to those identical. It is anticipated that smaller devices may be manufactured as manufacturing technologies (e.g., photolithography) mature over time. In addition, for the sake of brevity in the examples and descriptions, and to avoid obscuring specific aspects of the embodiments, well-known power / ground connections to IC chips and other components may or may not be shown in the drawings. Furthermore, to avoid obscuring the embodiments, and considering the fact that details relating to the implementation of such block diagram configurations depend heavily on the platform on which the embodiments are implemented, i.e., such details should be well within the scope of those skilled in the art, the configurations may be shown in block diagram form. Where specific details (e.g., circuits) are described to illustrate exemplary embodiments, it should be apparent to those skilled in the art that the embodiments can be carried out without these specific details or using variations of these specific details. Therefore, the descriptions should be considered illustrative rather than restrictive.

[0067] The term “connected” may be used herein to refer to any type of relationship, direct or indirect, between the components in question, and may apply to electronic, mechanical, fluid, optical, electromagnetic, or other connections. In addition, terms such as “first,” “second,” etc., may be used herein solely for the sake of clarity and, unless otherwise stated, do not retain any particular temporal or chronological meaning.

[0068] When used in this application and claims, a list of items grouped by the term "one or more" may mean any combination of the terms listed. For example, items listed in the form "one or more of A, B, or C" may mean A, B, C, A and B, A and C, B and C, or A, B and C.

[0069] From the above description, those skilled in the art will understand that the broad range of technologies of the embodiments can be implemented in various forms. Therefore, while the embodiments have been described in relation to those specific examples, other modifications will become apparent to those skilled in the art by examining the drawings, specification, and the following claims, and the true scope of the embodiments should not be limited thereto. Other possible claims (Item 1) The display and The processor coupled to the above display, The memory connected to the above processor, A performance-enhanced computing system comprising: The above memory includes a set of executable program instructions, and when the above set of executable program instructions is executed by the above processor, it is transmitted to the above computing system. Detect the creation of a thread, The first memory region is dedicated to the object associated with the above thread. In response to the termination of the above thread, the first of the first memory region release To have them do it, Enhanced performance computing system. (Item 2) The above first memory region is the heap region, and the above first release The computing system described in item 1, which bypasses the pause and copy operations of the garbage collection process with respect to the heap area mentioned above. (Item 3) When the executable program instruction is executed, it causes the computing system to dedicate the above first memory region to the above object associated with the above thread. Activate thread-based allocation, Map the above thread to the above first memory region. The computing system described in item 1. (Item 4) When the above executable program instruction is executed, it will cause the computing system to: In response to the above termination of the above thread, the above thread-based allocation will be deactivated. Unmap the above thread from the above first memory region. The computing system described in item 3. (Item 5) When the above executable program instruction is executed, it will cause the computing system to: In response to the determination that the first memory region is full, the second memory region is made exclusive for the object associated with the thread. In response to the above termination of the above thread, the second memory region of the above second memory region release To have them do it, The computing system described in item 1. (Item 6) A computing system as described in any one of items 1 through 5, wherein the above thread corresponds to user interface activity, and the above display visually represents information associated with the above user interface activity. (Item 7) One or more substrates, A semiconductor device comprising logic coupled to one or more of the above-mentioned substrates, wherein the logic is at least partially implemented in one or more configurable logic or fixed-function hardware logic, and the logic coupled to the one or more of the above-mentioned substrates is Detect thread creation, The first memory region is dedicated to the object associated with the above thread, and in response to the termination of the above thread, the first memory region release To do Semiconductor equipment. (Item 8) The above first memory region is the heap region, and the above first release The device described in item 7 bypasses the pause and copy operations of the garbage collection process with respect to the heap area mentioned above. (Item 9) The logic coupled to the one or more boards so as to dedicate the above-mentioned first memory region to the above-mentioned object associated with the above-mentioned thread, This activates thread-based allocation and maps the aforementioned threads to the aforementioned first memory region. The device described in item 7. (Item 10) The apparatus according to item 9, wherein the logic coupled to one or more of the above-mentioned boards deactivates the thread-based allocation and unmaps the thread from the first memory region in response to the termination of the thread. (Item 11) The logic coupled to the one or more of the above-mentioned boards is In response to the determination that the first memory region is full, the second memory region is made exclusive for the object associated with the thread. In response to the above termination of the above thread, the second memory region of the above second memory region release To have them do it, The device described in item 7. (Item 12) The above thread corresponds to a user interface activity, and is a device as described in any one of items 7 through 11. (Item 13) A computer-readable storage medium comprising a set of executable program instructions, wherein, when the set of executable program instructions is executed by a computing system, the computing system receives the following information: Detect the creation of a thread, The first memory region is dedicated to the object associated with the above thread. In response to the termination of the above thread, the first of the first memory region release To have them do it, At least one computer-readable storage medium. (Item 14) The above first memory region is the heap region, and the above first releaseThis refers to at least one computer-readable storage medium as described in item 13, which bypasses the pause and copy operations of the garbage collection process with respect to the heap area mentioned above. (Item 15) When the executable program instruction is executed, it causes the computing system to dedicate the above first memory region to the above object associated with the above thread. Activate thread-based allocation, Map the above thread to the above first memory region. At least one computer-readable storage medium as described in item 13. (Item 16) When the above executable program instruction is executed, it will cause the computing system to: In response to the above termination of the above thread, the above thread-based allocation will be deactivated. Unmap the above thread from the above first memory region. At least one computer-readable storage medium as described in item 15. (Item 17) When the above executable program instruction is executed, it will cause the computing system to: In response to the determination that the first memory region is full, the second memory region is made exclusive for the object associated with the thread. In response to the above termination of the above thread, the second memory region of the above second memory region release To have them do it, At least one computer-readable storage medium as described in item 13. (Item 18) The above thread corresponds to user interface activity, and is a computer-readable storage medium as described in any one of items 13 through 17. (Item 19) The stage of detecting thread creation, The first memory region is dedicated to the object associated with the above thread, In response to the termination of the above thread, the first of the first memory region release The stage of carrying out the process, A method for providing this. (Item 20) The above first memory region is the heap region, and the above first release The method described in item 19, which bypasses the pause and copy operations of the garbage collection process with respect to the heap area mentioned above. (Item 21) The step of dedicating the above-mentioned first memory region to the above-mentioned object associated with the above-mentioned thread is: The stage of activating thread-based allocation, The step of mapping the above thread to the above first memory region, The method described in item 19, including the method described in item 19. (Item 22) The step of deactivating the above thread-based allocation in response to the above halt of the above thread, The step of unmapping the above thread from the above first memory region, The method described in item 21, further including the method described in item 21. (Item 23) In response to the determination that the first memory region is full, the second memory region is dedicated to the object associated with the thread; In response to the above termination of the above thread, the second memory region of the above second memory region release The stage of having them perform, The method described in item 19, further including the method described in item 19. (Item 24) The above thread corresponds to a user interface activity, as described in any one of items 19 through 23.

Claims

1. The display and A processor coupled to the aforementioned display, The memory coupled to the aforementioned processor, A performance-enhanced computing system comprising: The memory includes a set of executable program instructions, and when executed by the processor, the set of executable program instructions is transmitted to the enhanced computing system. Detect the creation of a thread, Upon detecting the creation of the aforementioned thread, the thread object managing the thread is instructed to set a flag to activate thread-based assignment. Based on the setting of the aforementioned flag, the first memory area is made dedicated to the object associated with the thread. In response to the termination of the aforementioned thread, the first memory region is released. The first memory region is a heap region, and during the first deallocation, the execution of the garbage collection process's pause operation and copy operation related to the heap region is avoided in this performance-enhanced computing system.

2. The display and A processor coupled to the aforementioned display, The memory coupled to the aforementioned processor, A performance-enhanced computing system comprising: The memory includes a set of executable program instructions, and when executed by the processor, the set of executable program instructions is transmitted to the enhanced computing system. Detect the creation of a thread, Upon detecting the creation of the aforementioned thread, the thread object managing the thread is instructed to set a flag to activate thread-based assignment. Based on the setting of the aforementioned flag, the first memory area is made dedicated to the object associated with the thread. In response to the determination that the first memory area is full, the second memory area is made exclusive for the object associated with the thread. A performance-enhanced computing system that, in response to the termination of the aforementioned thread, causes the first memory area to be freed and the second memory area to be freed.

3. When executed, the executable program instruction causes the enhanced computing system to dedicate the first memory region to the object associated with the thread. Based on the setting of the aforementioned flag, the thread is mapped to the first memory area. The performance-enhanced computing system according to claim 1.

4. When the aforementioned executable program instruction is executed, it will cause the enhanced computing system to: In response to the termination of the aforementioned thread, the flag is cleared, and based on the clearing of the flag, the thread-based allocation is deactivated. Unmapping the thread from the first memory area, The performance-enhanced computing system according to claim 3.

5. The performance-enhanced computing system according to any one of claims 1 to 4, wherein the thread corresponds to user interface activity, and the display visually represents information associated with the user interface activity.

6. One or more substrates, A semiconductor device comprising logic coupled to one or more substrates, wherein the logic is at least partially implemented as one or more configurable logic or fixed-function hardware logic, and the logic coupled to the one or more substrates is Detect thread creation, Upon detecting the creation of the aforementioned thread, the thread object managing the thread is instructed to set a flag to activate thread-based assignment. Based on the setting of the aforementioned flag, the first memory region is dedicated to the object associated with the thread, and the first memory region is released in response to the termination of the thread. A semiconductor device wherein the first memory region is a heap region, and when the first deallocation occurs, the execution of the garbage collection process and copy operations related to the heap region are avoided.

7. One or more substrates, A semiconductor device comprising logic coupled to one or more substrates, wherein the logic is at least partially implemented as one or more configurable logic or fixed-function hardware logic, and the logic coupled to the one or more substrates is Detect thread creation, Upon detecting the creation of the aforementioned thread, the thread object managing the thread is instructed to set a flag to activate thread-based assignment. Based on the setting of the aforementioned flag, the first memory area is dedicated to the object associated with the thread. In response to the determination that the first memory area is full, the second memory area is made exclusive for the object associated with the thread. In response to the termination of the aforementioned thread, the first memory area is freed and the second memory area is freed. Semiconductor equipment.

8. The logic coupled to the one or more boards so as to dedicate the first memory area to the object associated with the thread, Based on the setting of the aforementioned flag, the thread is mapped to the first memory area. The semiconductor device according to claim 6.

9. The semiconductor device according to claim 8, wherein the logic coupled to the one or more substrates clears the flag in response to the termination of the thread, deactivates the thread-based allocation and unmaps the thread from the first memory area based on the clearing of the flag.

10. The semiconductor device according to any one of claims 6 to 9, wherein the thread corresponds to user interface activity.

11. When executed by a computing system, the computing system Detect the creation of a thread, Upon detecting the creation of the aforementioned thread, the thread object managing the thread is instructed to set a flag to activate thread-based assignment. Based on the setting of the aforementioned flag, the first memory area is made dedicated to the object associated with the thread. In response to the termination of the aforementioned thread, the first memory region is released for the first time. A computer program in which the first memory region is a heap region, and when the first deallocation occurs, the execution of the garbage collection process's pause operation and copy operation related to the heap region is avoided.

12. When executed by a computing system, the computing system Detect the creation of a thread, Upon detecting the creation of the aforementioned thread, the thread object managing the thread is instructed to set a flag to activate thread-based assignment. Based on the setting of the aforementioned flag, the first memory area is made dedicated to the object associated with the thread. In response to the determination that the first memory area is full, the second memory area is made exclusive for the object associated with the thread. In response to the termination of the aforementioned thread, the first memory area is freed and the second memory area is freed. Computer program.

13. When the first memory region is executed to be dedicated to the object associated with the thread, the computing system, Based on the setting of the aforementioned flag, the thread is mapped to the first memory area. The computer program according to claim 11.

14. When executed, the computing system In response to the termination of the aforementioned thread, the flag is cleared, and based on the clearing of the flag, the thread-based allocation is deactivated. Unmapping the thread from the first memory area, The computer program according to claim 13.

15. The computer program according to any one of claims 11 to 14, wherein the thread corresponds to user interface activity.

16. The stage of detecting thread creation, Upon detecting the creation of the aforementioned thread, the step of setting a flag in the thread object that manages the thread to activate thread-based assignment, Based on the setting of the aforementioned flag, the first memory area is made dedicated to the object associated with the thread, A step of performing a first release of the first memory area in response to the termination of the thread, Equipped with, A method wherein the first memory region is a heap region, and when the first deallocation occurs, the execution of the garbage collection process's pause operation and copy operation related to the heap region is avoided.

17. The stage of detecting thread creation, Upon detecting the creation of the aforementioned thread, the step of setting a flag in the thread object that manages the thread to activate thread-based assignment, Based on the setting of the aforementioned flag, the first memory area is made dedicated to the object associated with the thread, In response to the determination that the first memory area is full, the second memory area is dedicated to the object associated with the thread, In response to the termination of the aforementioned thread, the first memory area is released and the second memory area is released. A method for providing this.

18. The step of dedicating the first memory area to the object associated with the thread is: Based on the setting of the aforementioned flag, the step of mapping the thread to the first memory area, The method according to claim 16, including the method described in claim 16.

19. In response to the termination of the aforementioned thread, the steps include clearing the flag and, based on the clearing of the flag, deactivating the thread-based allocation. The steps include unmapping the thread from the first memory area, The method according to claim 18, further comprising:

20. The method according to any one of claims 16 to 19, wherein the thread corresponds to user interface activity.

21. A computer-readable storage medium for storing a computer program according to any one of claims 11 to 15.

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