Magnetoresistive memory elements for spin-transfer torque and spin-orbit torque random access memories
Patent Information
- Application Number
- JP2022132440
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-02-18
- Filing Date
- 2022-08-23
- Publication Date
- 2025-08-21
AI Technical Summary
【0017】 本発明の他の実施形態によれば、スピン-軌道トルク磁気抵抗ランダムアクセスメモリ(SOT-MRAM)素子が提供され、これは、磁気基準層RL、磁気自由層FL、および磁気RLと磁気FLとの間に延びるトンネリングバリア層を含む。また、製造中の熱安定性を向上させるために磁気FLに拡散遮断層(DBL)が提供される。このDBLは、ビスマス(Bi)、アンチモン(Sb)、オスミウム(Os)、レニウム(Re)、スズ(Sn)、ロジウム(Rh)、インジウム(In)およびカドミウム(CD)からなるグループより選ばれた一つ以上の物質を含む。シャント電流減少酸化物(SRO)層がDBLの上に提供されてスピン軌道トルク書き込みラインがSRO層上に提供される。このようなSRO層は、酸化マグネシウム(Mg-O)、酸化カルシウム(Ca-O)、酸化スカンジウム(Sc-O)、酸化チタン(Ti-O)、酸化バナジウム(V-O)、酸化鉄(Fe-O)、酸化ニッケル(Ni-O)、酸化コバルト(Co-O)、酸化ジルコニウム(Zr-O)、酸化ニオビウム(Nb-O)、酸化タンタル(Ta-O)、タングステン酸化物(W-O)、およびオスミウム酸化物(Os-O)からなるグループより選ばれた少なくとも一つの物質を含むことができる。DBLはまた、1Å~10Å範囲の厚さを有することができ、SRO層と磁性FLとの間に延びることができる。
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Abstract
Description
[Technical field]
[0001] The present invention relates to integrated circuit memory devices, and more particularly to non-volatile integrated circuit memory devices and methods for fabricating the same. [Background technology]
[0002] Conventional magnetoresistive random access memory (MRAM) devices typically use magnetoresistive (a / k / a magnetic) tunnel junctions (MTJs) as non-volatile memory elements, which in simplified form can be defined as a vertical stack of three layers. The three layers include (i) a magnetic reference layer, referred to as the "pinned" or "fixed" magnetic layer, (ii) a tunneling barrier layer, referred to as the tunneling dielectric layer, and (iii) a magnetic free layer. As will be appreciated by those skilled in the art, the MTJs can be programmed to define "0" or "1" logic states by setting the "field" of the magnetic free layer to be parallel or anti-parallel to the field of the magnetic reference layer during a memory write operation.
[0003] Thus, as shown in FIG. 1a, the MTJ 10 is configured to have a “first” logic state by setting the magnetization of the magnetic free layer 12 to be parallel to the magnetization of the magnetic reference layer 16, so that a relatively low resistance state exists when a read current is established across the layers of the MTJ 10, including the tunneling barrier layer 14 that separates the magnetic free layer 12 from the reference layer 16.
[0004] Alternatively, the MTJ 10 can be configured to have a "second" logic state by setting the magnetization of the magnetic free layer 12 to be antiparallel to the magnetization of the magnetic reference layer 16, so that a relatively high resistance state exists when a read current is formed across the layers of the MTJ 10. Although not shown in the drawings, conventional MTJs can also be configured to support a "vertical" or "perpendicular" spin orientation rather than the "horizontal" spin orientation shown in FIG.
[0005] Also, as shown on the left side of FIG. 1b, a spin transfer torque (STT) MRAM 20a (having a single “read / write” select transistor T1) can be programmed during a write operation by conveying a “write” current through the layers of the MTJ 10 in a first direction to program a logic “0” and in a second direction opposite to the first direction to program a logic “1”.
[0006] Also, although shorter access times can be obtained using higher write currents as a result of faster programming, the higher currents cause progressive damage to the layers of the MTJ 10 in response to repeated programming, thereby reducing the long-term endurance and reliability of the STT-MRAM 20a.
[0007] Fortunately, as shown on the right side of FIG. 1b, a spin-orbit torque (SOT) MRAM 20b (with separate read and write select transistors T1, T2) can be programmed by transmitting a “write” current across a separate “strap” layer 18 that shares an interface with the magnetic free layer 12. As can be seen from the separate read and write current paths, the use of the strap layer 18 to support the write current operates to separate the write current path from the read current path, thereby avoiding potential endurance and reliability limitations associated with the STT-MRAM 20a, at the expense of a somewhat larger layout footprint per bit caused by the additional write select transistor T2 in each memory cell.
[0008] 2, a more representative MTJ 10′ according to the prior art is shown as including a seed layer 22 on which a stack of a lower magnetic reference layer 24a, a Ruderman-Kittel-Kasuya-Yosida (RKKY) spacer / coupling layer 24b, and an upper magnetic reference layer 24c are sequentially formed as a composite magnetic reference layer 24. A prior art device related to the MTJ 10′ is disclosed in D. Apalkov, B. Dieny, and J. M. Slaughter, “Magnetoresistive Random Access Memory,” IEEE Proceedings, vol. 104, no. 10, pp. 1796-1830, October 2016.
[0009] The MTJ 10' also includes a tunneling barrier layer 26 comprised of a magnesium oxide (Mg-O) layer, and a magnetic free layer 28 directly overlying the tunneling barrier layer 26. An oxide cap 30, which may also comprise a magnesium oxide (Mg-O) layer, is also provided over the magnetic free layer 28, as shown. Without wishing to be bound by any theory, oxide caps for high efficiency and / or optimal tunneling magnetoresistance (TMR) have poor post-annealing stability compared to other lower performance oxide caps. Thus, there is an emerging need for the development of MTJ-based non-volatile memory elements with high performance oxide caps and excellent post-annealing stability. Summary of the Invention [Problem to be solved by the invention]
[0010] The problem to be solved by the present invention is to provide a magnetoresistive tunnel junction (MTJ) memory element having improved thermal stability during fabrication and improved post-fabrication yield and durability.
[0011] The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned can be clearly understood by those skilled in the art from the following description. [Means for solving the problem]
[0012] Non-volatile memories according to embodiments of the present invention may employ magnetoresistive tunnel junction (MTJ) memory elements that have improved thermal stability during fabrication and improved post-fabrication yield and durability.
[0013] According to some of these embodiments, an MTJ memory element is provided that includes a magnetic reference layer RL, a magnetic free layer FL, and a tunneling barrier layer extending between the magnetic RL and the magnetic FL. A diffusion blocking layer (DBL) is also provided on the magnetic FL extending between the DBL and the tunneling barrier layer to improve thermal stability. The DBL is configured to have: (i) a relatively high thermal stability (e.g., annealing stability), (ii) a relatively high diffusion barrier energy (Eb) or a relatively high tendency to separate toward its layer interface(s), and (iii) a reduced lattice mismatch with adjacent layers, and can include at least one material selected from the group consisting of bismuth (Bi), antimony (Sb), osmium (Os), rhenium (Re), tin (Sn), rhodium (Rh), indium (In), and cadmium (Cd). In some embodiments, an oxide layer, such as an oxide capping layer, is provided on the DBL. Additionally, the DBL may have a thickness in the range of 1 Å to 10 Å (angstroms), while the oxide layer may have a thickness in the range of 2 Å to 20 Å. In some embodiments of the invention, the oxide layer comprises magnesium oxide (Mg-O); while in other embodiments, the oxide layer may comprise at least one of strontium oxide (Sr-O), tantalum oxide (Ta-O), scandium oxide (Sc-O), beryllium oxide (Be-O), calcium oxide (Ca-O), yttrium oxide (YO), zirconium oxide (Zr-O), and hafnium oxide (Hf-O).
[0014] According to another embodiment of the invention, the DBL comprises a laminated composite layer of a first DBL of a first material and a second DBL of a second material extending between the first DBL and the oxide layer. Such first material may be a material selected from the group consisting of magnesium (Mg), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V) and chromium (Cr). The oxide layer may be comprised of a composite layer of: (i) a first oxide layer including at least one oxide selected from the group consisting of scandium oxide (Sc-O), strontium oxide (Sr-O) and calcium oxide (Ca-O), and (ii) a second oxide layer including at least one oxide selected from the group consisting of tantalum oxide (Ta-O) and hafnium oxide (Hf-O). The first oxide layer extends between the DBL and the second oxide layer, which may be thicker than the first oxide layer.
[0015] According to additional embodiments of the invention, a spin-transfer torque magnetoresistive random access memory (STT-MRAM) element is provided that includes a magnetic reference layer RL, a magnetic free layer FL, a tunneling barrier layer extending between the magnetic RL and the magnetic FL, and a seed layer below the magnetic RL. In some of these embodiments, the magnetic RL can include stacked composite layers of first and second magnetic reference layers with a Ruderman-Kittel-Kasuya-Yosida (RKKY) coupling layer extending therebetween that is designed to facilitate antiferromagnetic coupling between the lower RL and the upper RL.
[0016] Also, a diffusion barrier layer (DBL) is provided on the magnetic FL, and an oxide "capping" layer is provided on the DBL. Preferably, the DBL operates, among other things, to inhibit out-diffusion from the magnetic FL (i.e., interdiffusion between the FL and the oxide capping layer) and to improve the annealing stability of the memory element during fabrication by inhibiting out-diffusion from the capping layer. In some of these embodiments, the DBL may have a thickness in the range of 1 Å to 10 Å and may include one or more materials selected from the group consisting of bismuth (Bi), antimony (Sb), osmium (Os), rhenium (Re), tin (Sn), rhodium (Rh), indium (In), and cadmium (Cd). The DBL may also be comprised of a stacked composite layer of a first DBL and a second DBL (of a different material) extending between the first DBL and the oxide capping layer. Such a first DBL may comprise a first material selected from the group consisting of magnesium (Mg), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V) and chromium (Cr) in contact with the magnetic FL. In yet another embodiment of the invention, the oxide capping layer may comprise a laminated composite of: (i) a scandium oxide (Sc-O) layer, a strontium oxide (Sr-O) layer and / or a calcium oxide (Ca-O) layer in contact with the DBL, and (ii) a tantalum oxide (Ta-O) layer and / or a hafnium oxide (Hf-O) layer thereon.
[0017] According to another embodiment of the present invention, a spin-orbit torque magnetoresistive random access memory (SOT-MRAM) device is provided, which includes a magnetic reference layer RL, a magnetic free layer FL, and a tunneling barrier layer extending between the magnetic RL and the magnetic FL. A diffusion barrier layer (DBL) is also provided in the magnetic FL to improve thermal stability during fabrication. The DBL includes one or more materials selected from the group consisting of bismuth (Bi), antimony (Sb), osmium (Os), rhenium (Re), tin (Sn), rhodium (Rh), indium (In), and cadmium (Cd). A shunt current reducing oxide (SRO) layer is provided on the DBL, and a spin orbit torque write line is provided on the SRO layer. Such an SRO layer can include at least one material selected from the group consisting of magnesium oxide (Mg-O), calcium oxide (Ca-O), scandium oxide (Sc-O), titanium oxide (Ti-O), vanadium oxide (VO), iron oxide (Fe-O), nickel oxide (Ni-O), cobalt oxide (Co-O), zirconium oxide (Zr-O), niobium oxide (Nb-O), tantalum oxide (Ta-O), tungsten oxide (WO), and osmium oxide (Os-O). The DBL can also have a thickness in the range of 1 Å to 10 Å and can extend between the SRO layer and the magnetic FL. [Brief description of the drawings]
[0018] [Figure 1a] 1 is a cross-sectional view of a conventional magnetoresistive tunnel junction (MTJ) that operates as a non-volatile memory element when programmed to a low-resistance programmed state and a high-resistance programmed state. [Figure 1b] FIG. 1 is a simplified schematic diagram of a spin-transfer torque (STT) MRAM unit cell and a spin-orbit torque (SOT) MRAM unit cell according to the prior art. [Diagram 2] 1 is a cross-sectional view of a conventional magnetoresistive tunnel junction (MTJ) that can operate as a non-volatile memory element. [Diagram 3] 1 is a cross-sectional view of a non-volatile magnetoresistive tunnel junction (MTJ) memory element according to one embodiment of the present invention. [Figure 4] 1 is a cross-sectional view of a non-volatile magnetoresistive tunnel junction (MTJ) memory element according to one embodiment of the present invention. [Diagram 5] 1 is a cross-sectional view of a non-volatile magnetoresistive tunnel junction (MTJ) memory element according to one embodiment of the present invention. [Figure 6] 1 is a cross-sectional view of a non-volatile magnetoresistive tunnel junction (MTJ) memory element according to one embodiment of the present invention. [Figure 7] 1 is a cross-sectional view of a non-volatile magnetoresistive tunnel junction (MTJ) memory element of a spin-orbit torque (SOT) MRAM device according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0019] The present invention will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, but the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
[0020] In the drawings, the thicknesses of layers and regions have been exaggerated for clarity. Also, when a layer is referred to as being "on" another layer or substrate, this can be understood as being immediately on top of the other layer or substrate, or intermediate layers may be present. Like reference numerals refer to like elements throughout. Also, each reference to a metal (M) oxide (O), identified herein as MO, refers to a metal oxide compound MxOy, where M represents the metal and O represents oxygen, with the stoichiometric subscripts varying: x≧1, y≧1.
[0021] Terms such as first, second, third, etc. may be used herein to describe various elements, components, regions, layers, and / or sections, but such elements, components, regions, layers, and / or sections are not limited to these terms. Such terms are merely used to distinguish one element, component, region, layer, or section from another region, layer, or section. Thus, a first component, component, region, layer, or section referred to below may be referred to as a second component, component, region, layer, or section without departing from the teachings of the present invention.
[0022] The terms used herein are merely used to describe certain embodiments and are not intended to limit the present invention. As used herein, the singular forms are intended to include the plural forms unless otherwise indicated by the context. Additionally, the terms "comprise", "comprise", "have" and variations thereof as used herein specify the presence of stated features, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups thereof. In contrast, the term "consisting of" as used herein specifies stated features, steps, operations, elements and / or components, but excludes additional features, steps, operations, elements and / or components.
[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention belongs. In addition, terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and unless otherwise defined in this specification, they should not be interpreted in an idealized or overly formal sense.
[0024] 3, a nonvolatile magnetoresistive tunnel junction (MTJ) memory element 100a according to an embodiment of the present invention is shown as including a vertical stack of: (i) a seed layer 122, (ii) a magnetic reference layer (RL, 124) on the seed layer 122, (iii) a tunneling barrier layer 126 on the magnetic RL 124, and (iv) a magnetic free layer (FL, 128) on the tunneling barrier layer 126. As shown, the magnetic RL 124 is composed of stacked composite layers of a lower magnetic RL 124a, a Ruderman-Kittel-Kasuya-Yosida (RKKY) coupling / spacer layer 124b, and an upper magnetic RL 124c on the spacer layer 124b.
[0025] According to some of these embodiments, the seed layer 122 can include a material selected from the group consisting of, for example, Ir, Ru, and Ta, and can have a thickness ranging from about 10 Å to about 2000 Å. Additionally, the lower magnetic RL 124a can include a material selected from the group consisting of Co / Pt multilayers or Co-Pt alloys, or other materials including multilayers of a non-magnetic material, such as Pt or Pd, and a magnetic material, such as Co or Fe, and can have a thickness ranging from about 10 Å to about 500 Å.
[0026] The Ruderman-Kittel-Kasuya-Yosida (RKKY) bonding layer 124b may include a material selected from the group consisting of Ru, Rh, Ir, and alloys thereof, and may have a thickness in the range of about 3 Å to about 18 Å.
[0027] The upper magnetic RL 124c may include a material selected from the group consisting of a Co / Pt multilayer or alloy with an optional non-magnetic or weakly magnetic insertion layer and CoFeB adjacent the tunneling barrier layer 126, and has a thickness in the range of about 5 Å to about 200 Å.
[0028] The tunneling barrier layer 126 may be composed of, for example, a magnesium oxide (Mg—O) layer and / or a Mg—Al—O layer, and may have a thickness of about 4 Å to about 20 Å.
[0029] The magnetic FL128 can include a material selected from the group consisting of Co, Fe, B, Nb, Ta, Mo, Si, Zr, Ge, and W, and can have a thickness in the range of about 4 Å to about 50 Å.
[0030] Preferably, to improve thermal stability, a diffusion blocking layer (DBL, 140) is provided extending between (and interfacing with) the magnetic FL 128 and the oxide capping layer 130 as shown.
[0031] In particular, to inhibit interdiffusion between the FL 128 and the oxide capping layer 130, the DBL 140 preferably has (i) a relatively high thermal stability (e.g., annealing stability), (ii) a relatively high diffusion barrier energy (Eb) or a relatively high segregation tendency toward its layer interface(s), and (iii) a reduced lattice mismatch with the adjacent magnetic FL 128 and oxide capping layer 130. In particular, as described in U.S. Provisional Application No. 63 / 285,672, filed December 3, 2021, and incorporated by reference herein above, the annealing stability of the oxide capping layer 130 can be improved by configuring the DBL 140 such that, in particular, an increased diffusion barrier energy (Eb) or a relatively high segregation tendency and a reduced lattice mismatch are achieved compared to a conventional interface between the magnetic FL and an oxide (e.g., Mg-O) capping layer (while maintaining sufficient perpendicular magnetic anisotropy (PMA) compared to a conventional interface).
[0032] Additionally, according to some embodiments of the present invention, DBL 140 may have a thickness of 1 Å to 10 Å and may include at least one material selected from the group consisting of bismuth (Bi), antimony (Sb), osmium (Os), rhenium (Re), tin (Sn), rhodium (Rh), indium (In), and cadmium (Cd).
[0033] Without wishing to be bound by any theory, it is believed that osmium (Os), rhenium (Re) and rhodium (Rh) have a lower tendency to segregate towards the interface of the free layer and the oxide layer, but have a relatively high diffusion barrier, suggesting that such elements may remain in the as-deposited state during post-annealing.
[0034] Alternatively, bismuth (Bi), indium (In) and cadmium (Cd) are believed to have lower diffusion barriers but a higher tendency to segregate towards the interface, so that diffusion during post-annealing is unlikely to move such elements out of the interface.
[0035] Additionally, in some embodiments, within the group of eight elements, a first subgroup of bismuth (Bi), antimony (Sb), osmium (Os), rhenium (Re) and tin (Sn) may be selected over a second subgroup of rhodium (Rh), indium (In) and cadmium (Cd) based on the likelihood of the stability (and other properties) of the subsequently formed oxide cap, as described in more detail below. Thickness uniformity of DBL140 may also be improved by cooling the intermediate stage substrate including magnetic FL128 to a temperature of about -250°C to about -100°C prior to deposition of DBL140.
[0036] The oxide capping layer 130 of FIG. 3 provided on the DBL 140 may have a thickness of 2 Å to 20 Å and may be made of magnesium oxide (Mg—O) or other oxides.
[0037] However, as illustrated by the magnetoresistive tunnel junction (MTJ) memory element 100b of FIG. 4, an alternative oxide capping layer 130′ can include at least one of strontium oxide (Sr—O), scandium oxide (Sc—O), beryllium oxide (Be—O), calcium oxide (Ca—O), tantalum oxide (Ta—O), yttrium oxide (YO), zirconium oxide (Zr—O) and hafnium oxide (Hf—O), which can provide low formation energy and high oxygen diffusion barrier.
[0038] Also, as shown by the magnetoresistive tunnel junction (MTJ) memory element 100c of Figure 5, the DBL 140 of Figures 3 and 4 can be modified to include a stacked composite layer of a first DBL 140a of a first material and a second DBL 140b of a second material, which extends between the first DBL 140a and the oxide capping layer 130'. Such first material can be a material selected from the group consisting of magnesium (Mg), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V) and chromium (Cr), and the second material can include at least one of bismuth (Bi), antimony (Sb), osmium (Os), rhenium (Re), tin (Sn), rhodium (Rh), indium (In) and cadmium (Cd).
[0039] Without wishing to be bound by any theory, the first DBL 140a may operate to suppress out-diffusion of atoms from the second DBL 140b into the magnetic FL 128 (e.g., during deposition and post-annealing of the second DBL 140b).
[0040] Referring now to the magnetoresistive tunnel junction (MTJ) memory element 100d of FIG. 6, the oxide capping layers 130, 130′ of FIGS. 3-5 may be modified to include a stacked composite layer of (i) a first oxide layer 130a having good annealing stability, comprising one oxide selected from the group consisting of scandium oxide (Sc-O), strontium oxide (Sr-O) and calcium oxide (Ca-O), and (ii) a second oxide layer 130b for good figure of merit (FOM), comprising at least one oxide selected from the group consisting of magnesium oxide (Mg-O), tantalum oxide (Ta-O) and hafnium oxide (Hf-O), and may be thicker than the first oxide layer 130a.
[0041] Finally, as shown in FIG. 7, a spin-orbit torque magnetoresistive random access memory (SOT-MRAM) device 100e according to another embodiment of the present invention includes: (i) a magnetic reference layer 224 (e.g., a nitride such as Ta-N, Ti-N) having a capping layer 250 thereon, (ii) a magnetic free layer 228, (iii) a tunneling barrier layer 226 extending between the magnetic reference layer 224 and the magnetic free layer 228, and (iv) a diffusion blocking layer 240 on the magnetic free layer 228. The magnetic reference layer 224 is shown to include a stacked composite layer of an upper reference layer 224a, a Ruderman-Kittel-Kasuya-Yosida (RKKY) coupling / spacer layer 224b, and a lower reference layer 224c. In some embodiments of the memory element 100e, layers (i)-(iv) can be configured as described above in connection with the memory elements 100a-100d of FIGS. 3-6.
[0042] The SOT-MRAM device 100e of FIG. 7 further includes a thin shunt current reducing oxide (SRO) layer 260 extending between the diffusion blocking layer 240 and the SOT write / read line 300, which has a relatively high resistance and can perform the same function as the strap layer 18 of the SOT-MRAM 20b of FIG. 1b during write and read operations. Advantageously, the SRO layer 260 is thin (to improve interface transparency) and provides a relatively high parallel resistance to the SOT write / read line 300, so as to block the lateral shunt current Jc from passing laterally through the relatively low resistance free layer 228 during a write operation. The diffusion blocking layer 240 also improves the annealing stability of the thin SRO layer 260.
[0043] According to some of these embodiments, the SRO layer comprises at least one material selected from the group consisting of magnesium oxide (Mg-O), calcium oxide (Ca-O), scandium oxide (Sc-O), titanium oxide (Ti-O), vanadium oxide (VO), iron oxide (Fe-O), nickel oxide (Ni-O), cobalt oxide (Co-O), zirconium oxide (Zr-O), niobium oxide (Nb-O), tantalum oxide (Ta-O), tungsten oxide (WO), and osmium oxide (Os-O), and has a thickness in the range of about 2 Å to about 10 Å.
[0044] In the drawings and specification there have been disclosed exemplary preferred embodiments of the invention, and although specific terms have been employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being as set forth in the following claims. [Explanation of symbols]
[0045] 100a-100d Magnetoresistive tunnel junction (MTJ) memory element 124 Magnetic Reference Layer 128 Magnetic free layer 126 Tunneling Barrier Layer 240 Diffusion barrier layer
Claims
1. In a magnetoresistive tunnel junction (MTJ) memory element, a magnetic reference layer; a magnetic free layer; a tunneling barrier layer extending between the magnetic reference layer and the magnetic free layer; a diffusion barrier layer on the magnetic free layer; an oxide layer overlying the diffusion barrier layer and extending between the oxide layer and the magnetic free layer, the oxide layer having a thickness of 2 Å to 20 Å; the diffusion barrier layer includes one or more materials selected from the group consisting of bismuth (Bi), antimony (Sb), osmium (Os), rhenium (Re), tin (Sn), rhodium (Rh), indium (In), and cadmium (Cd); The memory element, wherein the magnetic free layer extends between the diffusion blocking layer and the tunneling barrier layer, the diffusion blocking layer defining an interface with the magnetic free layer.
2. 10. The memory device of claim 1, wherein the diffusion barrier layer has a thickness in the range of 1 Å to 10 Å.
3. 2. The memory element of claim 1, wherein the oxide layer includes at least one of scandium oxide (Sc--O) and magnesium oxide (Mg--O).
4. 10. The memory element of claim 1, wherein the oxide layer comprises at least one of strontium oxide (Sr—O), tantalum oxide (Ta—O), beryllium oxide (Be—O), calcium oxide (Ca—O), yttrium oxide (Y—O), zirconium oxide (Zr—O), titanium oxide (Ti—O), and hafnium oxide (Hf—O).
5. The diffusion barrier layer is a first diffusion barrier layer comprising a first material; 10. The memory device of claim 1, comprising a laminated composite layer with a second diffusion barrier layer comprising a second material different from the first material and extending between the first diffusion barrier layer and the oxide layer.
6. 6. The memory device of claim 5, wherein the first diffusion barrier layer includes at least one material selected from the group consisting of magnesium (Mg), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), and chromium (Cr).
7. A magnetoresistive tunnel junction (MTJ) memory element, a magnetic reference layer; a magnetic free layer; a tunneling barrier layer extending between the magnetic reference layer and the magnetic free layer; a diffusion barrier layer on the magnetic free layer; an oxide layer on the diffusion barrier layer and extending between the oxide layer and the magnetic free layer; the diffusion barrier layer includes one or more materials selected from the group consisting of bismuth (Bi), antimony (Sb), osmium (Os), rhenium (Re), tin (Sn), rhodium (Rh), indium (In), and cadmium (Cd); the magnetic free layer extends between the diffusion barrier layer and the tunneling barrier layer, defining an interface with the magnetic free layer; The oxide layer is a first oxide layer containing at least one oxide selected from the group consisting of scandium oxide (Sc—O), strontium oxide (Sr—O), and calcium oxide (Ca—O); A memory element comprising a composite layer with a second oxide layer containing at least one oxide selected from the group consisting of tantalum oxide (Ta--O) and hafnium oxide (Hf--O).
8. The memory element of claim 7 , wherein the first oxide layer extends between the second oxide layer and the diffusion barrier layer.
9. The memory element of claim 8 , wherein the second oxide layer is thicker than the first oxide layer.
10. 2. The memory device of claim 1, wherein the oxide layer is a shunt-current reducing oxide (SRO) layer including at least one material selected from the group consisting of magnesium oxide (Mg—O), calcium oxide (Ca—O), scandium oxide (Sc—O), titanium oxide (Ti—O), vanadium oxide (V—O), iron oxide (Fe—O), nickel oxide (Ni—O), cobalt oxide (Co—O), zirconium oxide (Zr—O), niobium oxide (Nb—O), tantalum oxide (Ta—O), tungsten oxide (W—O), and osmium oxide (Os—O).
11. In a spin-transfer torque magnetoresistive random access memory (STT-MRAM) device, a magnetic reference layer (RL); a magnetic free layer (FL); a tunneling barrier layer extending between the magnetic reference layer and the magnetic free layer; a diffusion barrier layer (DBL) on the magnetic free layer, the diffusion barrier layer having a thickness in the range of 1 Å to 10 Å and including at least one material selected from the group consisting of bismuth (Bi), antimony (Sb), osmium (Os), rhenium (Re), tin (Sn), rhodium (Rh), indium (In), and cadmium (Cd); an oxide layer on the diffusion barrier layer; a seed layer on the magnetic reference layer.
12. 12. The memory element of claim 11, wherein the magnetic reference layer comprises a stacked composite layer of first and second magnetic reference layers having a Ruderman-Kittel-Kasuya-Yosida (RKKY) coupling layer extending therebetween.
13. The diffusion barrier layer is a first diffusion barrier layer in contact with the magnetic reference layer, the first diffusion barrier layer comprising a first material selected from the group consisting of magnesium (Mg), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), and chromium (Cr); 12. The memory device of claim 11, comprising a laminated composite layer with a second diffusion barrier layer comprising a second material different from the first material and extending between the first diffusion barrier layer and the oxide layer.
14. The oxide layer is a scandium oxide (Sc—O) layer, a strontium oxide (Sr—O) layer, and / or a calcium oxide (Ca—O) layer in contact with the diffusion barrier layer; 12. The memory element of claim 11, comprising a layered composite of a tantalum oxide (Ta-O) layer and / or a hafnium oxide (Hf-O) layer thereon.
15. 1. A spin-orbit torque magnetoresistive random access memory (SOT-MRAM) device comprising: a magnetic reference layer (RL); a magnetic free layer (FL); a tunneling barrier layer extending between the magnetic reference layer and the magnetic free layer; a diffusion barrier layer (DBL) on the magnetic free layer, the diffusion barrier layer including at least one material selected from the group consisting of bismuth (Bi), antimony (Sb), osmium (Os), rhenium (Re), tin (Sn), rhodium (Rh), indium (In), and cadmium (Cd); a shunt current reducing oxide (SRO) layer on the diffusion barrier layer; a spin-orbit torque write line on the shunt current reducing oxide layer; A memory element, wherein the shunt current reducing oxide layer includes at least one material selected from the group consisting of magnesium oxide (Mg—O), calcium oxide (Ca—O), scandium oxide (Sc—O), titanium oxide (Ti—O), vanadium oxide (V—O), iron oxide (Fe—O), nickel oxide (Ni—O), cobalt oxide (Co—O), zirconium oxide (Zr—O), niobium oxide (Nb—O), tantalum oxide (Ta—O), tungsten oxide (W—O), and osmium oxide (Os—O).
16. 16. The memory element of claim 15, wherein the diffusion barrier layer has a thickness in the range of 1 Å to 10 Å and extends between and contacts the shunt current reducing oxide layer and the magnetic free layer.