Mode switching in display device for driving display panel

Abstract

To provide various measures for mitigating display artifacts that could occur due to mode switching.SOLUTION: A display driver includes a GRAM, a data driver, and a control circuit. The data driver is configured to: update, in a first mode, display elements of a display panel based on a command provided to the display driver asynchronously with a display vertical sync signal; update, in a second mode, the display elements based on image data stored in the GRAM in synchronization with the display vertical sync signal; and update, in a third mode, the display elements in synchronization with an external vertical sync signal. The control circuit is configured to: switch the display drive from a first mode to a second mode in response to a first command; adjust, in the second mode, the display vertical sync signal based on an external vertical sync signal; and switch the display driver to the third mode after achieving synchronization of the display vertical sync signal with the external vertical sync signal.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The disclosed technology relates generally to display devices, and more particularly to a mode switching method for display devices.

Background Art

[0002] A display driver for driving a display panel may be configured to receive image data from an external source (e.g., a host, a controller, a processor, or other device configured to supply image data). The transfer of image data to the display driver may be asynchronous or synchronous with a vertical synchronization signal generated within the display driver. Some display drivers support both asynchronous and synchronous image data transfers. The display driver may be configured to receive image data asynchronously with the vertical synchronization signal in an asynchronous mode and update the display panel based on the received image data. The display driver may further be configured to receive image data and an external synchronization control input (e.g., a vertical synchronization packet and an external vertical synchronization signal) from an external source in a synchronous mode, generate a vertical synchronization signal based on the external synchronization control input, and update the display panel based on the received image data in synchronization with the generated vertical synchronization signal.

Summary of the Invention

[0003] This summary is provided to introduce, in a concise form, a selection of concepts that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0004] In one or more embodiments, a display driver is provided. The display driver comprises a graphics random access memory (GRAM), a data driver, and a control circuit. In a first mode, the data driver is configured to update a plurality of display elements of a display panel at least in part on a display vertical synchronization signal generated within the display driver and commands supplied to the display driver asynchronously. In a second mode, the data driver is further configured to update the display elements of the display panel at least in part on first image data stored in the GRAM, in synchronization with the display vertical synchronization signal. In a third mode, the data driver is further configured to update the display elements of the display panel in synchronization with an external vertical synchronization signal. The control circuit is configured to switch the display driver from the first mode to the second mode in response to a first command. In the second mode, the control circuit is further configured to adjust the display vertical synchronization signal at least in part on the external vertical synchronization signal. After achieving synchronization of the display vertical synchronization signal with the external vertical synchronization signal, the control circuit is further configured to switch the display driver to the third mode.

[0005] A display device is provided in one or more embodiments. The display device comprises a display panel and a display driver. The display panel comprises a plurality of display elements. The display driver comprises a GRAM, a data driver, and a control circuit. In a first mode, the data driver is configured to update the display elements at least in part on a display vertical synchronization signal generated within the display driver and commands supplied to the display driver asynchronously. In a second mode, the data driver is further configured to update the display elements of the display panel at least in part on first image data stored in the GRAM. In a third mode, the data driver is further configured to update the display elements of the display panel in synchronization with an external vertical synchronization signal. The control circuit is configured to switch the display driver from the first mode to the second mode in response to a first command. In a second mode, the control circuit is further configured to adjust the display vertical synchronization signal at least in part on an external vertical synchronization signal. After achieving synchronization of the display vertical synchronization signal with the external vertical synchronization signal, the control circuit is further configured to switch the display driver to the third mode.

[0006] In one or more embodiments, a method for driving a display panel is provided. The method includes generating emission pulses that control the emission of display elements of the display panel, at least partially based on a display vertical synchronization signal. The method further includes, in a first mode, updating the display elements, at least partially based on commands supplied to the display driver asynchronously with respect to the display vertical synchronization signal. The method further includes switching the display driver from a first mode to a second mode in response to a first command. The method further includes, in a second mode, updating the display elements of the display panel, at least partially based on first image data stored in the display driver's GRAM. The method further includes, after achieving synchronization of the display vertical synchronization signal with an external vertical synchronization signal, switching the display driver to a third mode. The method further includes, in a third mode, updating the display elements of the display panel in synchronization with the external vertical synchronization signal.

[0007] Other embodiments of the model will be apparent from the following description and the attached claims. [Brief explanation of the drawing]

[0008] To enable a detailed understanding of the features of this disclosure, a more specific description of this disclosure, which is briefly summarized above, may be given with reference to embodiments. Some of these embodiments are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only exemplary embodiments, and this disclosure recognizes other equally valid embodiments, and should not be considered to limit the scope of the invention.

[0009] [Figure 1] Figure 1 illustrates an exemplary configuration of a display device according to one or more embodiments.

[0010] [Figure 2A] Figure 2A illustrates exemplary control of the display brightness level of a display device according to one or more embodiments. [Figure 2B] Figure 2B illustrates exemplary control of the display brightness level of a display device according to one or more embodiments.

[0011] [Figure 2C] Figure 2C illustrates an exemplary display image artifact caused by a disturbance in the period of the display vertical synchronization signal resulting from mode switching.

[0012] [Figure 3] Figure 3 illustrates an exemplary configuration of a display driver according to one or more embodiments.

[0013] [Figure 4] Figure 4 illustrates exemplary operation of a display driver according to one or more embodiments.

[0014] [Figure 5A]FIG. 5A illustrates an exemplary operation of a display driver in command mode according to one or more embodiments.

[0015] [Figure 5B] FIG. 5B illustrates an exemplary operation of a display driver in video random access memory (RAM) mode according to one or more embodiments.

[0016] [Figure 5C] FIG. 5C illustrates an exemplary operation of a display driver in video through mode according to one or more embodiments.

[0017] [Figure 6A] FIG. 6A illustrates an exemplary operation of an external source configured to supply an image to a display driver according to one or more embodiments.

[0018] [Figure 6B] FIG. 6B illustrates an exemplary detailed operation of a display driver after receiving a mode switch command according to one or more embodiments.

[0019] [Figure 7] FIG. 7 illustrates an exemplary adjustment process of an internal horizontal synchronization (Hsync) signal according to one or more embodiments.

[0020] [Figure 8A] FIG. 8A illustrates an exemplary "long H dimming" process according to one or more embodiments.

[0021] [Figure 8B] FIG. 8B illustrates another exemplary "long H dimming" process according to one or more embodiments.

[0022] [Figure 9A] FIG. 9A illustrates an exemplary allocation of an extension amount to an extended frame period according to one or more embodiments. [Figure 9B] Figure 9C illustrates an exemplary allocation of the extension amount to the extended frame period according to one or more embodiments. [Figure 9C] Figure 9C illustrates an exemplary allocation of the extension amount to the extended frame period according to one or more embodiments.

[0023] [Figure 10A] Figure 10A illustrates an exemplary “long V dimming” process according to one or more embodiments.

[0024] [Figure 10B] Figure 10B illustrates another exemplary “long V dimming” process according to one or more embodiments.

[0025] [Figure 11] Figure 11 illustrates an exemplary configuration of a display device according to one or more embodiments.

[0026] [Figure 12] Figure 12 illustrates exemplary operation of a display device according to one or more embodiments.

[0027] [Figure 13] Figure 13 illustrates an exemplary method for driving a display panel according to one or more embodiments.

[0028] For ease of understanding, where possible, the same reference numerals are used to indicate identical elements common to the drawings. Elements disclosed in one embodiment are expected to be usefully used in other embodiments, even without specific mention. Reference numerals may be subscripted to distinguish identical elements from one another. Drawings referenced herein should not be understood to be dimensional unless otherwise noted. Also, for clarity of presentation and explanation, drawings are often simplified by omitting details or components. The drawings and discussions are intended to illustrate the principles discussed below, and similar numerals indicate similar elements. [Modes for carrying out the invention]

[0029] The embodiments for carrying out the invention described below are essentially illustrative and are not intended to limit the Disclosure or its uses and applications. Furthermore, they are not intended to be bound by any explicit or implicit theories presented in the preceding background, abstract, or the detailed description below. As used herein, the term “combined” means directly connected or connected via one or more intervening components or circuits.

[0030] The display driver that drives the display panel may be configured to receive image data from an external entity (e.g., a host, controller, processor, or other device configured to supply image data). The transfer of image data from the external entity to the display driver may be asynchronous or synchronous with the vertical synchronization signal generated within the display driver.

[0031] In asynchronous mode, an external entity may store image data in one or more commands and send these commands to the display driver at any time, asynchronously with the vertical synchronization signal generated within the display driver. In this case, the display driver may retrieve the image data from the commands and update the display panel based on the retrieved image data.

[0032] In synchronous mode, an external entity may transmit image data to the display driver along with external synchronous control inputs such as external synchronous packets (e.g., vertical synchronous packets and horizontal synchronous packets) or external synchronous signals (e.g., external vertical synchronous signals and external horizontal synchronous signals). In this case, the display driver may generate a vertical synchronous signal based on the external synchronous control inputs and update the display panel based on the image data in synchronization with the generated vertical synchronous signal.

[0033] Some display drivers support both asynchronous and synchronous image data transfer. Such display drivers may be configured in asynchronous mode to update the display panel based on image data stored in one or more commands received asynchronously in response to a vertical synchronization signal. The display driver may also be configured in synchronous mode to receive image data and external synchronization control inputs (e.g., vertical synchronization packets and external vertical synchronization signals) from an external source, generate a vertical synchronization signal based on the external synchronization control inputs, and update the display panel based on the received image data in synchronization with the generated vertical synchronization signal.

[0034] Switching from asynchronous to synchronous mode can disrupt the period of the vertical synchronization signal generated within the display driver, potentially causing display image artifacts. A disrupted vertical synchronization signal can lead to unsuccessful timing control when updating or controlling the display panel, resulting in display image artifacts. For example, in embodiments where the light emission of the display elements of the display panel is controlled in synchronization with the vertical synchronization signal, a disrupted period of the vertical synchronization signal can disrupt the order of the light emission control, resulting in uneven brightness of the display image.

[0035] This disclosure provides various measures to mitigate display artifacts that may occur due to mode switching. In one or more embodiments, a display driver comprises graphics random access memory (GRAM), a data driver, and a control circuit. In a first mode, the data driver is configured to update a plurality of display elements of a display panel based at least in part on a display vertical synchronization signal generated within the display driver and commands supplied to the display driver asynchronously. In a second mode, the data driver is further configured to update the display elements of the display panel in synchronization with the display vertical synchronization signal based at least in part on first image data stored in the GRAM. In a third mode, the data driver is further configured to update the display elements of the display panel in synchronization with an external vertical synchronization signal. The control circuit is configured to switch the display driver from the first mode to the second mode in response to a first command. In the second mode, the control circuit is further configured to adjust the display vertical synchronization signal based at least in part on the external vertical synchronization signal. The control circuit is further configured to switch the display driver to the third mode after achieving synchronization of the display vertical synchronization signal with the external vertical synchronization signal.

[0036] In such embodiments, the second mode uses GRAM while adjusting the display vertical synchronization signal based on an external vertical synchronization signal. Therefore, switching the display driver to the second mode may improve flexibility in achieving synchronization between the external vertical synchronization signal and the display vertical synchronization signal. In one embodiment, the use of the second mode mitigates display image artifacts that may be caused by periodic disturbances in the display vertical synchronization signal. A detailed description of various embodiments of this disclosure is given below.

[0037] Figure 1 illustrates an exemplary configuration of a display device 1000 according to one or more embodiments. In the illustrated embodiments, the display device 1000 comprises a display panel 100 and a display driver 200. The display panel 100 may be a self-emissive display panel such as an organic light-emitting diode (OLED) display panel or a micro-light-emitting diode (μLED) display panel. The display device 1000 is configured to display an image on the display panel 100 based on image data received from an external source 300. Examples of the external source 300 include a host, controller, processor, or other device suitable for supplying image data.

[0038] In the illustrated embodiment, the display panel 100 comprises a display area 110, a gate scan driver 120, and an emission scan driver 130. The display area 110 comprises display elements 112, gate lines 114, emission lines 116, and source lines 118. The gate lines 114 are coupled to the gate scan driver 120, and the emission lines 116 are coupled to the emission scan driver 130. The source lines 118 are coupled to the display driver 200. Each row of the display elements 112 is coupled to the corresponding gate line 114 and the corresponding emission line 116, and each column of the display elements is coupled to the corresponding source line 118. Each display element 112 is configured to be updated or programmed with a data voltage received from the display driver 200 and to emit light at a brightness level corresponding to the data voltage. In embodiments where the display panel 100 is an OLED display panel, each display element 112 may comprise an OLED element configured to emit light according to the data voltage. In one or more embodiments, programming of the display element 112 with a data voltage is achieved by asserting a gate line 114 coupled to the display element 112 while the display driver 200 generates the data voltage on a source line 118 coupled to the display element 112.

[0039] The gate scan driver 120 is configured to control the updating or programming of the display elements 112 of each "horizontal line". Here, "horizontal line" refers to a row of display elements 112 coupled to the same gate line 114 and the same emission line 116. In one implementation, the gate scan driver 120 is configured to sequentially assert the gate line 114 to allow the display elements 112 of each horizontal line to be programmed with the data voltage generated by the display driver 200. The operation of the gate scan driver 120 may be controlled by the gate scan start pulse signal GSTV and the gate scan clock GCK received from the display driver 200.

[0040] The emission scan driver 130 is configured to control the illumination of each horizontal line display element 112 using emission lines 116. The emission scan driver 130 may be configured to assert the emission line 116 coupled to a horizontal line display element 112 when allowing illumination of that horizontal line display element 112. The emission scan driver 130 may also be configured to deassert the emission line 116 coupled to a horizontal line display element 112 when prohibiting illumination of that horizontal line display element 112. The operation of the emission scan driver 130 may be controlled by the emission scan start pulse signal ESTV and the emission scan clock ECK received from the display driver 200.

[0041] The display driver 200 is configured to update the display elements 112 based at least partially on image data received from an external source 300. In one implementation, the image data includes the grayscale of each display element 112. The display driver 200 may also be configured to generate a data voltage corresponding to the grayscale of each display element 112 and to update or program the display elements 112 via the source line 118 using the generated data voltage.

[0042] The display driver 200 is further configured to control the gate scan driver 120 using a gate scan start pulse signal GSTV and a gate scan clock GCK. The gate scan driver 120 may be configured to scan the gate line 114 in synchronization with the gate scan clock GCK in response to the gate scan start pulse signal GSTV.

[0043] The display driver 200 is further configured to control the emission scan driver 130 using an emission scan start pulse signal ESTV and an emission scan clock ECK. The emission scan driver 130 may be configured to assert a selected emission line 116 in synchronization with the emission scan clock ECK in response to the emission scan start pulse signal ESTV. In one implementation, the emission scan start pulse signal ESTV transmits an emission pulse that controls the display brightness level of the display device 1000. The display brightness level may be the overall brightness level of the image displayed on the display panel 100. Details of controlling the display brightness level based on the emission pulse of the emission scan start pulse signal ESTV will be described in detail later.

[0044] The display driver 200 is configured to receive an external synchronization control input from an external source 300. The external synchronization control input may include vertical synchronization (Vsync) packets and horizontal synchronization (Hsync) packets. Vsync packets may indicate the start of each frame period and thereby define each frame period (or vertical synchronization period). Hsync packets may indicate the start of each line period (or horizontal synchronization period) and thereby define a line period. In other embodiments, the external synchronization control input may include an external vertical synchronization signal and an external horizontal synchronization signal. The display driver 200 may be configured to generate a display vertical synchronization signal and a display horizontal synchronization signal in response to the external synchronization control input and to use the display vertical synchronization signal and the display horizontal synchronization signal for timing control in the display device 1000. For example, the display driver 200 may be configured to generate a gate scan start pulse signal GSTV and an emission scan start pulse signal ESTV based at least partially on the display vertical synchronization signal and the display horizontal synchronization signal.

[0045] In one or more embodiments, the display device 1000 supports two image data transfer methods: command mode and video-through mode. In command mode, the external source 300 supplies one or more commands to the display driver 200 to store image data only when it wishes to update one or more display elements 112 of the display panel 100. Using command mode effectively reduces the power consumption of the display device 1000. In command mode, the external source 300 supplies one or more commands at any time without supplying an external synchronization control input to the display driver 200. The display driver 200 generates display vertical synchronization signals and display horizontal synchronization signals itself without using an external synchronization control input. Command mode can be considered a type of asynchronous mode as described above.

[0046] In video-through mode, the external source 300 continuously supplies video packets containing image data (for example, in the form of a video data stream) to the display driver 200, and the display driver 200 updates the display panel 100 based on the image data during each frame period (or each vertical synchronization period). In video-through mode, the external source 300 supplies an external synchronization control input along with the video packets, and the display driver 200 generates a display vertical synchronization signal and a display horizontal synchronization signal based on the external synchronization control input. Video-through mode can be considered a type of synchronization mode as described above.

[0047] Switching from command mode to video-through mode can disrupt the period of the display's vertical synchronization signal, potentially causing display image artifacts. Below, we will first describe display brightness control, and then discuss the potential for display image artifacts caused by mode switching.

[0048] Figures 2A and 2B illustrate exemplary control of the display brightness level of a display device 1000 based on emission pulses transmitted by an emission scan start pulse signal ESTV, according to one or more embodiments. The upper portions of Figures 2A and 2B illustrate exemplary waveforms of the emission scan start pulse signal ESTV and the emission scan clock ECK, while the lower portions illustrate exemplary images displayed on the display panel 100 at certain times (times t1 and t2 in Figure 2A, and time t3 and t4 in Figure 2B). In Figures 2A and 2B, reference numeral 201 indicates a non-emitting region where the display element 112 does not emit light. In one implementation, the emission line 116 in the non-emitting region is deasserted by the emission scan driver 130 to prevent light emission from the display element 112 coupled to the emission line 116. The display brightness level is controlled by the total area of ​​the non-emitting region in the displayed image.

[0049] The central portions of Figures 2A and 2B show exemplary changes over time in a horizontal line located in the non-emitting region. The vertical axis represents the horizontal line, and the horizontal axis represents time. The hatched region 202 shows the horizontal line located in the non-emitting region.

[0050] In one or more embodiments, emission pulses transmitted by the emission scan start pulse signal ESTV control the number and width of non-emitting regions 201 in the display panel 100. Each emission pulse instructs the emission scan driver 130 (shown in Figure 1) to introduce a non-emitting region 201 from the top edge of the display region 110. The width of the introduced non-emitting region 201 is based on the width of the emission pulse. In one implementation, the emission scan driver 130 introduces the non-emitting region 201 while the emission pulse appears in the emission scan start pulse signal ESTV. The introduced non-emitting region 201 is then scrolled or shifted downwards in the display panel 100 in synchronization with the emission scan clock ECK. The number of non-emitting regions 201 in the display region 110 is controlled by the number of emission pulses appearing in the emission scan start pulse signal ESTV per frame period (defined by the display Vsync signal), and the width of the non-emitting region 201 is controlled by the width of the emission pulse. In one implementation, the number of non-emitting regions 201 is equal to the number of emission pulses per frame period, and the width of the non-emitting regions is proportional to the width of the emission pulses. Figure 2A illustrates the case where one emission pulse appears in the emission scan start pulse signal ESTV during each frame period, and Figure 2B illustrates the case where four emission pulses appear in the emission scan start pulse signal ESTV during each frame period. The display brightness level decreases as the number and / or width of the non-emitting regions increases.

[0051] In ideal operation (as shown in Figures 2A and 2B), the emission scan start pulse signal ESTV is generated in synchronization with the display Vsync signal so that emission pulses appear at fixed time intervals with a fixed period. If emission pulses are not generated at fixed time intervals, this can cause irregularities in the arrangement of non-emitting regions 201, which can lead to display image artifacts.

[0052] Mode switching (for example, from command mode to video-through mode) can disrupt the period of the display Vsync signal used to generate the emission scan start pulse signal ESTV, thus causing irregularities in the emission pulses in the emission scan start pulse signal ESTV. Figure 2C illustrates an exemplary display artifact resulting from the disruption of the display Vsync signal period due to mode switching. In the illustrated operation, the timing of the second assertion of the display Vsync signal is delayed due to the mode switching. The delay in the assertion timing of the display Vsync signal causes irregularities in the emission pulses. In the illustrated operation, the pulse width of the emission pulse indicated by "1" in Figure 2C is incorrectly widened, and this widening of the pulse width undesirably widens the width of the corresponding non-emitting region indicated by code 203. Region 204 shows that an increased number of horizontal lines belong to the widened non-emitting region 203. Unwanted expansion of the width of non-emissive regions can lead to irregularities in the arrangement of non-emissive regions, potentially causing display image artifacts.

[0053] Figure 3 illustrates an exemplary configuration of a display driver 200 that addresses the mitigation of display image artifacts that may occur due to mode switching, according to one or more embodiments. In the illustrated embodiment, the display driver 200 comprises an interface (I / F) circuit 205, a drive circuit 210, a control circuit 230, a brightness controller 250, an emission pulse generator 260, and a gate-in-panel (GIP) pulse generator 270.

[0054] The interface circuit 205 is configured to receive image data from the external source 300 and send the received image data to the drive circuit 210. The image data may be transferred to the display driver 200 in the form of commands or video packets, as described in relation to Figure 1. The interface circuit 205 is further configured to receive various commands from the external source 300. Commands received from the external source 300 may include mode switching commands. The display driver 200 is configured to switch the operating mode in response to the mode switching commands, as will be described in detail below.

[0055] The interface circuit 205 is further configured to generate external vertical synchronization (Vsync) signals and external horizontal synchronization (Hsync) signals based at least partially on the external synchronization control input received from the external source 300. In embodiments where the external synchronization control input includes Vsync packets and Hsync packets, the interface circuit 205 may be configured to generate an external Vsync signal in synchronization with the Vsync packets and an external Vsync signal in synchronization with the Hsync packets. The external Vsync signals and external Hsync signals are supplied to the control circuit 230. In other embodiments, the external synchronization control input may include external Vsync signals and external Hsync signals. In this case, the interface circuit 205 sends the external Vsync signals and external Hsync signals to the control circuit 230.

[0056] The drive circuit unit 210 is configured to update or program the display elements 112 of the display panel 100 based at least partially on image data received from an external source 300 via the interface circuit 205. In the illustrated embodiment, the drive circuit unit 210 includes a selector 212, a line buffer 214, a graphics random access memory (GRAM) 216, a selector 218, an image processing circuit 220, a line latch 222, and a data driver 224. The selector 212 is configured to selectively send commands or video packets received from the external source 300 to the line buffer 214. The line buffer 214 is configured to store image data for one horizontal line of the display panel 100 and to send the stored image data to the GRAM 216. The GRAM 216 is configured to store image data for one frame of an image to be displayed on the display panel 100. The image data stored in the GRAM 216 is sequentially updated with image data received from the line buffer 214. The selector 218 is configured to selectively couple the output of the line buffer 214 or the output of the GRAM 216 to the image processing circuit 220, depending on the operating mode of the display driver 200. The image processing circuit 220 is configured to process the image data received from the line buffer 214 or the GRAM 216 and supply the processed image data to the line latch 222. The line latch 222 latches the processed image data from the image processing circuit 220 in units of horizontal lines and sends the processed image data to the data driver 224. The data driver 224 is configured to update or program the display elements 112 of the display panel 100 based at least partially on the processed image data. In one implementation, the processed image data may include the gradation of each display element 112, and the data driver 224 may be configured to update or program the display elements 112 with data voltages corresponding to the gradation of each display element 112.

[0057] The control circuit 230 is configured to generate a display vertical synchronization (Vsync) signal and a display horizontal synchronization (Hsync) signal used for timing control within the display driver 200. The display Vsync signal defines the frame period (or vertical synchronization period), and the display Hsync signal defines the line period (or horizontal synchronization period). In one or more embodiments, the control circuit 230 is configured to generate an internal Hsync signal based on an internal oscillator clock OSC_CLK generated by an internal oscillator (not shown) provided within the display driver 200, and to select a display Hsync signal from the internal Hsync signal and an external Hsync signal. The control circuit 230 is further configured to generate an internal Vsnc signal based on the display Hsync signal, and to select a display Vsync signal from the internal Vsync signal and an external Vsync signal. Details of the configuration and operation of the control circuit 230 will be described later.

[0058] The brightness controller 250 is configured to control the display brightness level of the display device 1000. As discussed in relation to Figures 2A and 2B, the display brightness level can be controlled using the width of the emission pulses transmitted by the emission scan start pulse signal ESTV and the number of emission pulses per frame period (or per vertical synchronization period). In one implementation, the brightness controller 250 is configured to determine the period and width of the emission pulses according to the target display brightness level.

[0059] The emission pulse generator 260 is configured to generate an emission scan start pulse signal ESTV that transmits emission pulses using the display Vsync signal and display Hsync signal received from the control circuit 230. The emission scan start pulse signal ESTV is generated so that the emission pulses have the period and pulse width as instructed by the brightness controller 250.

[0060] The GIP pulse generator 270 is configured to generate a gate scan start pulse signal GSTV using the indicator Vsync signal and the indicator Hsync signal. As described in relation to Figure 1, the gate scan start pulse signal GSTV is used to control the gate scan driver 120.

[0061] The control circuit 230 is described in detail below. In the illustrated embodiment, the control circuit 230 includes an internal Hsync generator 232, a selector 234, an internal Vsync generator 236, a selector 238, and a display mode controller 240. The internal Hsync generator 232 is configured to generate an internal Hsync signal using an internal oscillator clock OSC_CLK generated by an internal oscillator (not shown) provided in the display driver 200. In one implementation, the internal Hsync signal may be generated by counting the internal oscillator clock OSC_CLK. The selector 234 is configured to select a display Hsync signal from an internal Hsync signal and an external Hsync signal. The selection of the display Hsync signal is based on an Hsync mode signal received from the display mode controller 240. The internal Vsync generator 236 is configured to generate an internal Vsync signal using the display Hsync signal. In one implementation, the internal Vsync signal may be generated by counting the display Hsync signal. The selector 238 is configured to select a display Vsync signal from an internal Vsync signal and an external Vsync signal. The selection of the display Vsync signal is based on the Vsync mode signal received from the display mode controller 240.

[0062] In the illustrated embodiment, the control circuit 230 further comprises an emission synchronization (EMsync) generator 242, a delay measurement circuit 244, a long H dimming circuit 246, an external 1H measurement circuit 247, and a long V dimming circuit 248. The emission synchronization (EMsync) generator 242, the delay measurement circuit 244, the long H dimming circuit 246, the external 1H measurement circuit 247, and the long V dimming circuit 248 are configured to jointly control an internal Hsync generator 232 and an internal Vsync generator 236 to adjust the internal Hsync signal and the internal Vsync signal (and thereby adjust the display Hsync signal and the display Vsync signal).

[0063] The EMsync generator 242 is configured to generate an emission synchronization signal EMsync using an external Vsync signal and an external Hsync signal. In one implementation, the EMsync generator 242 is configured to generate an emission synchronization signal EMsync such that the emission synchronization signal is synchronized with an external vertical synchronization signal and has the same period as the period of the emission pulse determined by the brightness controller 250.

[0064] The delay measurement circuit 244 is configured to measure the delay between the assertion of the display Vsync signal and the assertion of the emission synchronization signal. In some embodiments, the delay measurement circuit 244 is configured to measure the delay from the assertion of the display Vsync signal to the next assertion of the emission synchronization signal. In other embodiments, the delay measurement circuit 244 is configured to measure the delay from the assertion of the emission synchronization signal to the next assertion of the display Vsync signal.

[0065] The long H dimming circuit 246 is configured to perform "long H dimming" based on the delay measured by the delay measurement circuit 244. "Long H dimming" here refers to the process of synchronizing the display Vsync signal with the emission synchronization signal EMsync by adjusting the internal Hsync signal (and thereby adjusting the display Hsync signal). The time interval between two consecutive assertions of the display Vsync signal corresponds to the length of the frame period (or vertical synchronization period) defined by these two consecutive assertions, while the frame period includes multiple line periods (or horizontal synchronization periods). Since the period of the display Hsync signal corresponds to the length of the line period (or horizontal synchronization period), the length of the frame period can be adjusted by adjusting the display Hsync signal. In one implementation, "long H dimming" synchronizes the display Vsync signal with the synchronization signal EMsync by extending a predetermined number of frame periods by adjusting the display Hsync signal.

[0066] The external 1H measurement circuit 247 is configured to measure the period of the external Hsync signal received from the interface circuit 205 (or the time interval between two consecutive assertions of the external Hsync signal). The internal Hsync generator 232 is configured to adjust the internal Hsync signal so that it has the same period as the external Hsync signal based on the measured period of the external Hsync signal.

[0067] The long V-dimming circuit 248 is configured to perform "long V-dimming" based on an external Vsync signal and an internal Vsync signal. "Long V-dimming" is the process of synchronizing the display Vsync signal with the external Vsync signal by adjusting the internal Vsync signal (and thereby adjusting the display Vsync signal). Synchronization of the display Vsync signal with the external Vsync signal is achieved by extending one or more frame periods in units of the emission pulse period.

[0068] Figure 4 illustrates the exemplary overall operation of the display driver 200 in Figure 3 during mode switching from command mode to video-through mode according to one or more embodiments. In the illustrated embodiments, the display driver 200 is initially in command mode. In command mode, one or more commands transmitting image data are transferred from the external source 300 to the display driver 200, as illustrated in Figure 5A. Note that in command mode, no external synchronization control input (e.g., Vsync packets and Hsync packets) is supplied to the display driver 200, and the display driver 200 generates the display Vsync signal and display Hsync signal without using the external synchronization control input (e.g., using the oscillator clock OSC_CLK generated within the display driver 200). In command mode, the internal Vsync signal and internal Hsync signal are selected as the display Vsync signal and display Hsync signal, respectively. The received command is sent to the GRAM 216 via the selector 212 and the line buffer 214, and the GRAM 216 stores the image data transferred by the command. Image data stored in GRAM216 is sent to the image processing circuit 220 via selector 218 and processed by the image processing circuit 220. The processed image data is sent to the data driver 224 via line latch 222, and the display elements 112 of the display panel 100 are updated (or programmed) by the data driver 224 based on the processed image data.

[0069] Returning to Figure 4, in step 1, the external source 300 sends a mode switching command to the display driver 200 instructing it to enter video-through mode. The external source 300 then begins supplying video packets and an external synchronization control input to the display driver 200 (also illustrated in Figure 6A). The video packets transmit image data for each frame period, and the display driver 200 updates the display elements 112 of the display panel 100 for each frame period based on the image data transmitted by the video packets. The external synchronization control input may include Vsync packets and Hsync packets, as discussed in relation to Figure 3.

[0070] As illustrated in Figure 4, the display driver 200 is configured to enter "video RAM mode" before entering video-through mode in response to the reception of a mode switching command. In "video RAM mode," the display driver 200 uses GRAM 216 to supply image data to the data driver 224 while adjusting the display Vsync signal to synchronize it with an external Vsync signal generated based on an external synchronization control input (which may include Vsync packets and / or Hsync packets). The display driver 200 is further configured to enter video-through mode once synchronization of the display Vsync signal to the external Vsync signal is achieved.

[0071] Figure 5B illustrates exemplary operation of the display driver 200 in video RAM mode according to one or more embodiments. In video RAM mode, the display driver 200 receives video packets from an external source 300. The video packets are sent to the GRAM 216 via the selector 212 and line buffer 214, and the GRAM 216 stores the image data transmitted by the video packets. The image data stored in the GRAM 216 is sent to the image processing circuit 220 via the selector 218 and processed by the image processing circuit 220. The processed image data is sent to the data driver 224 via the line latch 222, and the display elements 112 of the display panel 100 are updated (or programmed) by the data driver 224 based on the processed image data.

[0072] Returning to Figure 4, in one or more embodiments, the adjustment of the display Vsync signal in video RAM mode includes steps 2, 3, and 4, as discussed below. In step 2, the delay between the assertion of the display Vsync signal and the assertion of the emission synchronization signal EMsync is measured (for example, by the delay measurement circuit 244 shown in Figure 3). Note that in Figure 4 (and other figures), the display Vsync signal and the display Hsync signal are shown as asserted when pulled down to a low level, while the emission synchronization signal EMsync is shown as asserted when pulled up to a high level. As discussed in relation to Figure 3, the emission synchronization signal EMsync is synchronized with the external Vsync signal and has the same period as the emission pulse transmitted by the emission scan start pulse signal ESTV (shown by EM_PER in Figure 4). In the illustrated embodiments, the delay from the assertion of the display Vsync signal to the next assertion of the emission synchronization signal EMsync is measured.

[0073] In step 3, a “long H dimming” process is performed to compensate for the delay measured in step 2. As discussed in relation to Figure 3, the “long H dimming” process synchronizes the display Vsync signal to the emission synchronization signal EMsync by adjusting the internal Hsync signal (and thereby adjusting the display Hsync signal). Note that during the “long H dimming” process, the internal Vsync signal and the internal Hsync signal are selected as the display Vsync signal and the display Hsync signal, respectively. In one implementation, long H dimming extends one or more frame periods by reducing the frequency of the internal Hsync signal (or increasing the length of the line period defined by the internal Hsync signal). In embodiments where two or more frame periods are extended by long H dimming, the amount of extension allocated to the extended frame periods is determined based on the delay measured in step 2. In one implementation, the sum of the extension amounts is equal to the delay from the assertion of the display Vsync signal to the next assertion of the emission synchronization signal EMsync. When "long H dimming" is completed as desired, the timing skew between the display Vsync signal and the external Vsync signal will be equal to one period of the emission pulse or a multiple of the emission pulse period.

[0074] Step 4 involves the "long V-dimming" process. As discussed in relation to Figure 3, the "long V-dimming" process synchronizes the display Vsnc signal to the external Vsync signal by adjusting the internal Vsync signal to extend one or more frame periods in units of emission pulse periods. Note that in the "long V-dimming" process, the internal Vsync signal is selected as the display Vsync signal while the external Hsync signal is selected as the display Hsync signal. In some embodiments, the vertical front porch (VFP) period of one or more frame periods is extended during the "long V-dimming" process. In Figure 4, the extended portion of the vertical front porch period of the extended frame period is indicated by "VFP_EXT".

[0075] In step 5, following step 4, the display driver 200 enters video-through mode, completing the mode switch. In video-through mode, the external Vsync signal is selected as the display Vsync signal, and the emission scan start pulse signal ESTV, which transmits emission pulses, is generated in synchronization with the external Vsync signal.

[0076] Figure 5C illustrates exemplary operation of the display driver 200 in video-through mode according to one or more embodiments. In video-through mode, image data transmitted in video packets is transferred to the data driver 224, bypassing the GRAM 216, and the GRAM 216 is deactivated to reduce power consumption. More specifically, video packets received from an external source 300 are sent to the image processing circuit 220 via selector 212, line buffer 214, and selector 218. The image processing circuit 220 processes the image data transmitted in the video packets. The processed image data is sent to the data driver 224 via line latch 222, and the display elements 112 of the display panel 100 are updated (or programmed) by the data driver 224 based on the processed image data.

[0077] Figure 6B illustrates a detailed exemplary operation of the display driver 200 after receiving a mode switching command according to one or more embodiments. In the illustrated embodiments, the display driver 200 starts generating external Vsync signals and external Hsync signals in response to external synchronization control inputs (e.g., Vsync packets and Hsync packets), and further starts generating an emission synchronization signal EMsync. In embodiments where the display driver 200 is configured as shown in Figure 3, the external Vsync signals and external Hsync signals are generated by the interface circuit 205, and the emission synchronization signal EMsync is generated by the EMsync generator 242. However, it should be noted that immediately after receiving a mode switching command, the display driver 200 still selects the internal Vsync signal as the display Vsync signal and the internal Hsync signal as the display Hsync signal.

[0078] The display driver 200 further adjusts the internal Hsync signal so that it has the same period as the external Hsync signal. Figure 7 illustrates an exemplary adjustment process for the internal Hsync signal according to one or more embodiments. The adjustment of the internal Hsync signal is initiated by measuring the period of the external Hsync signal (shown as "external 1H" in Figure 7). In embodiments in which the display driver 200 is configured as shown in Figure 3, the external 1H measurement circuit 247 measures the period of the external Hsync signal.

[0079] Subsequently, the internal Hsync signal is adjusted to have the same period as the external Hsync signal based on the measured period of the external Hsync signal. In an embodiment where the display driver 200 is configured as shown in Figure 3, the internal Hsync generator 232 adjusts the internal Hsync signal based on the measured period of the external Hsync signal. In one implementation, the period of the internal Hsync signal is adjusted using a "dimming" technique. In this "dimming" technique, the period of the internal Hsync signal is gradually changed to the period of the external Hsync signal. This "dimming" technique avoids abrupt changes in the period of the internal Hsync signal and mitigates display image artifacts that may occur due to changes in the internal Hsync signal.

[0080] Returning to Figure 6B, after the internal Hsync signal adjustment is complete, the delay between the assertion of the display Vsync signal and the assertion of the emission synchronization signal EMsync is measured, as discussed in relation to Figure 4. In the illustrated embodiment, the delay from the assertion of the display Vsync signal to the next assertion of the emission synchronization signal EMsync is measured.

[0081] Subsequently, a "long H dimming" process is performed, in which the internal Hsync signal used to generate the display Hsync and display Vsync signals is adjusted to synchronize the display Vsync signal with the emission synchronization signal EMsync. As discussed in relation to Figure 4, the "long H dimming" process is based on a delay between the assertion of the display Vsync signal and the assertion of the emission synchronization signal EMsync. In one or more embodiments, "long H dimming" is performed by extending one or more frame periods by temporarily increasing the period of the internal Hsync signal (and the period of the display Hsync signal).

[0082] In some embodiments, two or more frame periods are extended during a “long H dimming” process to achieve synchronization of the display Vsync signal with the emission synchronization signal EMsync. In such embodiments, the amount of extension of these two or more frame periods is determined based on the delay between the assertion of the display Vsync signal and the next assertion of the emission synchronization signal EMsync. The extension amount is the amount of time the corresponding frame period is extended. In one implementation, the “long H dimming” process includes allocating the extension amounts to the extended frame periods such that the sum of the extension amounts of the two or more extended frame periods is equal to the delay between the assertion of the display Vsync signal and the next assertion of the emission synchronization signal EMsync. The extension amount allocated to a frame period is sometimes called the allocated extension amount.

[0083] Figure 8A illustrates an exemplary “long H dimming” process according to one or more embodiments. In the illustrated embodiments, four frame periods are extended after measuring the delay between the assertion of the indicator Vsync signal and the next assertion of the emission synchronization signal EMsync. In Figure 8A, “Tbase” represents the nominal length of the frame period, and “T” represents the delay between the assertion of the indicator Vsync signal and the next assertion of the emission synchronization signal EMsync. In the illustrated embodiments, the nominal length of the frame period “Tbase”, the delay “T”, and the amount of extension allocated to the extended frame period are measured as the number of clocks contained therein, as indicated by the notation "[clk]". For example, the nominal length of the frame period is measured as Tbase clocks, as indicated as Tbase [clk] in Figure 8A.

[0084] Figure 9A illustrates an exemplary allocation of extension amounts to the four extended frame periods according to one or more embodiments. The extension amounts are allocated to the four extended frame periods such that the length of the frame periods increases gradually first and then decreases gradually. More specifically, the extension amount allocated to the second of the four extended frame periods is longer than the extension amount allocated to the first of the four extended frame periods, and the extension amount allocated to the third of the four extended frame periods is shorter than the extension amount allocated to the second of the four extended frame periods. In the illustrated embodiments, the extension amount allocated to the first of the four extended frame periods is T × (1 / 4) (more precisely, an integer part of T × (1 / 4)) clocks, the extension amount allocated to the second frame period is T × (2 / 4) clocks, and the extension amount allocated to the third frame period is T × (1 / 4) clocks. The extension amount allocated to the fourth of the four extended frame periods is the remainder when T is divided by 4. The extension amount allocation, in which the frame period length initially increases gradually and then decreases gradually, suppresses the change in frame period length between two consecutive frame periods, thereby reducing the change in the period of the display Hsync signal during the "long H dimming" process. Reducing the change in the period of the display Hsync signal may mitigate display image artifacts that may be caused by the change in the period of the display Hsync signal.

[0085] The number of extended frame periods during the "long H dimming" process is not limited to four and can be varied. Figure 8B illustrates another exemplary "long H dimming" process according to one or more embodiments. In the illustrated embodiment, six frame periods are extended after measuring the delay between the assertion of the display Vsync signal and the next assertion of the emission synchronization signal EMsync. Figure 9B illustrates an exemplary allocation of extension amounts to the six extended frame periods according to one or more embodiments. The extension amounts are allocated to the six extended frame periods such that the length of the frame periods increases gradually at first, and then decreases gradually, as in Figure 9A. More specifically, the extension amounts allocated to the second, third, and fourth frame periods of the six extended frame periods are longer than those allocated to the first frame period of the six extended frame periods, and the extension amount allocated to the fifth frame period of the six extended frame periods is shorter than those allocated to the second, third, and fourth frame periods of the six extended frame periods. In the illustrated embodiment, the extension amount allocated to the first of the six extended frame periods is T × (1 / 8) (more precisely, the integer part of T × (1 / 8)) clocks, the extension amounts allocated to the second, third, and fourth frame periods are T × (2 / 8) clocks, and the extension amount allocated to the fifth frame period is T × (1 / 8) clocks. The extension amount allocated to the sixth of the six extended frame periods is the remainder when T is divided by 8. Furthermore, Figure 9C illustrates an exemplary allocation of extension amounts in an embodiment where the number of extended frame periods is eight. In the embodiment illustrated in Figure 9C, the extension amounts are also allocated to the eight extended frame periods such that the length of the frame periods increases gradually at first, and then decreases gradually.

[0086] Returning to Figure 6B, after the "long H dimming" process, a "long V dimming" process is performed to synchronize the display Vsync signal to the external Vsync signal by adjusting the internal Vsync signal used to generate the display Vsync signal at this stage. Note that when transitioning to the "long V dimming" process, the display Hsync signal is switched from the internal Hsync signal to the external Hsync signal. As discussed in relation to Figure 3, the "long V dimming" process synchronizes the display Vsync signal to the external Vsync signal by adjusting the internal Vsync signal to extend one or more frame periods in units of the emission pulse period. In some embodiments, the vertical front porch (VFP) period of the one or more frame periods is extended during the "long V dimming" process. In Figure 6B, the extended portion of the vertical front porch period of the extended frame period is indicated by "VFP_EXT".

[0087] Figure 10A illustrates an exemplary “long V-dimming” process according to one or more embodiments. After the “long H-dimming” process is completed as desired, the timing skew between the display Vsync signal and the external Vsync signal is the same as the period of the emission pulse or a multiple of the period of the emission pulse. Therefore, the display Vsync signal can be synchronized with the external Vsync signal by extending one or more frame periods in units of the period of the emission pulse. In the illustrated embodiment, the timing skew between the display Vsync signal and the external Vsync signal is twice the period of the emission pulse.

[0088] In one or more embodiments, the “long V-dimming” process is initiated by determining a timing skew between a display Vsync signal and an external Vsync signal. In one implementation, the timing skew between the display Vsync signal and the external Vsync signal may be determined based on the count value of an EMsync counter configured to count assertions of an emission synchronization signal EMsync and the count value of an emission counter configured to count emission pulses transmitted by an emission scan start pulse signal ESTV. The EMsync counter may be located in an EMsync generator 242 (illustrated in Figure 3) and configured to be reset by assertions of the external Vsync signal and then count up with each assertion of the emission synchronization signal EMsync. The emission counter may be located in an emission pulse generator 260 (illustrated in Figure 3) and configured to be reset by assertions of the external Vsync signal and then count up with the generation of each emission pulse in the emission scan start pulse signal ESTV. In one implementation, the timing skew between the display Vsync signal and the external Vsync signal is determined as the difference between the count value of the EMsync counter and the count value of the emission counter.

[0089] The "long V-dimming" process achieves synchronization of the display Vsync signal with the external Vsync signal in "long V-dimming" by extending one or more frame periods to compensate for the timing skew between the display Vsync signal and the external Vsync signal. When the timing skew is determined to be N times the period of the emission pulse, one or more frame periods are extended such that the total extension amount is N times the period of the emission pulse. In the embodiment illustrated in Figure 10A, the timing skew is determined to be twice the period of the emission pulse, and the vertical front porch (VFP) period of one frame period is extended by twice the period of the emission pulse. In Figure 10A, the extended portion of the VFP period is shown as "VFP_EXT".

[0090] Figure 10B illustrates another exemplary “long V-dimming” process according to one or more embodiments. In the illustrated embodiments, the timing skew between the display Vsync signal and the external Vsync signal is determined to be twice the period of the emission pulse, while two frame periods are each extended by the period of the emission pulse. Compensating for the timing skew by extending multiple frame periods during the “long V-dimming” process suppresses changes in frame period length and mitigates display image artifacts that may result from changes in frame period length.

[0091] Figure 11 illustrates an exemplary configuration of the display device 2000 according to another embodiment. In the illustrated embodiment, the display device 2000 comprises two display panels 100A and 100B and two display drivers 200A and 200B. The display device 2000 is configured so that the display panels 100A and 100B are connected by a hinge 140 and are foldable. Each of the display panels 100A and 100B may be configured similarly to the display panel 100 in Figure 1. In Figure 11, for simplicity, only the emission scan drivers 130A and 130B are illustrated. The display driver 200A is configured to drive the display panel 100A, and the display driver 200B is configured to drive the display panel 100B. Display drivers 200A and 200B are configured similarly to the display driver 200 shown in Figure 3, except that display driver 200A is configured to control the operating timing of display driver 200B by supplying a display Vsync signal and an emission synchronization signal EMsync to display driver 200B. Display driver 200B uses the display Vsync signal received from display driver 200A as an external Vsync signal. Since display driver 200A is configured to control display driver 200B, it may be referred to as the "master driver" below, and display driver 200B may be referred to as the "slave driver" below.

[0092] In one or more embodiments, the display device 2000 has two modes: individual mode and two-panel synchronized mode. In individual mode, display drivers 200A and 200B operate independently to display unrelated, independent images on display panels 100A and 100B. In two-panel synchronized mode, display driver 200A, operating as the master driver, supplies a display Vsync signal and an emission synchronization signal EMsync to display driver 200B, operating as the slave driver. Display driver 200B uses the display Vsync signal and emission synchronization signal EMsync received from display driver 200A as external synchronization control inputs and operates in synchronization with the display Vsync signal and emission synchronization signal EMsync received from display driver 200A to display synchronized images on display panels 100A and 100B. In individual mode, the display Vsync signal generated by display driver 200A may be asynchronous with the display Vsync signal generated by display driver 200B. Therefore, switching from individual mode to two-panel synchronous mode may disrupt the period of the display Vsync signal in display driver 200B, and this mode switching may cause display image artifacts. The following describes an embodiment that mitigates display image artifacts that may occur due to switching from individual mode to two-panel synchronous mode.

[0093] Figure 12 illustrates the exemplary operation of the display device 2000 of Figure 11 during mode switching from individual mode to two-panel synchronous mode according to one or more embodiments. In the illustrated embodiments, the display device 2000 is initially in individual mode, in which display drivers 200A and 200B operate independently. Display drivers 200A and 200B individually receive commands from an external source to store image data, and update display panels 100A and 100B based on the image data stored in the received commands.

[0094] In Step 1, an external source (e.g., a host, controller, processor, or other device configured to supply commands) sends a mode switching command to display drivers 200A and 200B, instructing them to enter 2-panel sync mode. Display driver 200B (acting as a slave driver) is configured to enter "transition mode" before entering 2-panel sync mode in response to receiving the mode switching command. During "transition mode," display driver 200B adjusts the display Vsync signal it generates based on the display Vsync signal and emission sync signal EMsync received from display driver 200A, so that the display Vsync signal it generates synchronizes with the display Vsync signal it receives from display driver 200A.

[0095] The adjustment of the display Vsync signal in the display driver 200B includes steps 2, 3, and 4, as discussed below. In step 2, the display driver 200B measures the delay between the assertion of the display Vsync signal generated by the display driver 200B and the assertion of the emission synchronization signal EMsync received from the display driver 200A. In the illustrated embodiment, the display driver 200B measures the delay from the assertion of the display Vsync signal generated by the display driver 200B to the next assertion of the emission synchronization signal EMsync.

[0096] In step 3, the display driver 200B performs a “long H dimming” process to compensate for the delay measured in step 2. The “long H dimming” process synchronizes the display Vsync signal generated by the display driver 200B with the emission synchronization signal EMsync received from the display driver 200A by adjusting the internal Hsync signal (and display Hsync signal) generated by the display driver 200B. In one implementation, the display driver 200B extends one or more frame periods during the long H dimming process by decreasing the frequency of the internal Hsync signal generated by the display driver 200B (or increasing the length of the line period defined by the internal Hsync signal). In embodiments where two or more frame periods are extended by long H dimming, the amount of extension allocated to the extended frame periods is based on the delay measured in step 2. In one implementation, the sum of the extension amounts is equal to the delay from the assertion of the display Vsync signal generated by the display driver 200B to the next assertion of the emission synchronization signal EMsync received from the display driver 200A. Once the "long H dimming" is completed as desired, the timing skew between the display Vsync signal generated by the display driver 200B and the display Vsync signal received from the display driver 200A will be the same as the period of the emission pulse or a multiple of the period of the emission pulse.

[0097] In step 4, the display driver 200B performs a “long V-dimming” process. The “long V-dimming” process synchronizes the display Vsync signal generated by the display driver 200B with the external Vsync signal received from the display driver 200A by adjusting the internal Vsync signal generated by the display driver 200B to extend one or more frame periods in units of the emission pulse period. In some embodiments, the display driver 200B extends the vertical front porch (VFP) period of one or more frame periods during the “long V-dimming” process. In Figure 12, the extended portion of the vertical front porch period of the extended frame period is shown as “VFP_EXT”.

[0098] In step 5, the display driver 200B enters two-panel synchronization mode, completing the mode transition. In two-panel synchronization mode, the display driver 200B updates the display panel 100B in synchronization with the display Vsync signal received from the display driver 200A.

[0099] Method 1300 in Figure 13 illustrates exemplary steps for driving a display panel (e.g., display panels 100, 100A, and 100B in Figures 1 and 11) according to one or more embodiments. Note that one or more of the steps illustrated in Figure 13 may be omitted, repeated, and / or performed in a different order. Furthermore, note that two or more steps may be performed simultaneously.

[0100] Method 1300 includes, in step 1302, generating emission pulses that control the illumination of display elements of a display panel (e.g., display panel 100 as shown in Figure 1) based at least in part on a display vertical synchronization (Vsync) signal. Method 1300 further includes, in step 1304, updating display elements in a first mode (e.g., command mode as shown in Figures 4 and 6B and individual mode as shown in Figure 12) based at least in part on commands supplied asynchronously to a display driver (e.g., display driver 200 as shown in Figure 1 and display driver 200B as shown in Figure 11) with respect to the display vertical synchronization signal. Method 1300 further includes, in step 1306, switching the display driver from the first mode to a second mode (e.g., command mode as shown in Figures 4 and 6B and individual mode as shown in Figure 12) in response to a first command (e.g., mode switching command as shown in Figures 4, 6A, 6B and 12). Method 1300 further includes, in step 1308, updating the display elements of the display panel based at least partially on first image data stored in the display driver's GRAM (e.g., GRAM 216 shown in Figure 3) in the second mode. Method 1300 further includes, in step 1310, adjusting the display vertical synchronization signal based at least partially on an external vertical synchronization signal in the second mode. Method 1300 further includes, in step 1312, switching the display driver to a third mode (e.g., video-through mode shown in Figures 4 and 6B and two-panel synchronization mode shown in Figure 12) after achieving synchronization of the display vertical synchronization signal with the external vertical synchronization signal. Method 1300 further includes, in step 1314, updating the display elements of the display panel in synchronization with the external vertical synchronization signal in the third mode.

[0101] Although many embodiments have been described, those skilled in the art who are interested in this disclosure will likely find that other embodiments can be devised without departing from the technical scope. Accordingly, the technical scope of the present invention should be limited only by the appended claims.

Claims

1. It is a display driver, Graphics Random Access Memory (GRAM), A data driver, In the first mode, a plurality of display elements of the display panel are updated at least partially based on a display vertical synchronization signal generated within the display driver and commands supplied to the display driver asynchronously. In the second mode, the display elements of the display panel are updated based at least partially on the first image data stored in the GRAM in synchronization with the display vertical synchronization signal. In the third mode, a data driver configured to update the display elements of the display panel in synchronization with an external vertical synchronization signal, A control circuit, In response to the first command, the display driver is switched from the first mode to the second mode. In the second mode, the display vertical synchronization signal is adjusted based at least partially on an external vertical synchronization signal. A control circuit configured to switch the display driver to the third mode after achieving synchronization of the display vertical synchronization signal with the external vertical synchronization signal, Equipped with Display driver.

2. The second mode is a video RAM mode configured such that the GRAM receives the first image data from the host, The third mode is a video-through mode in which the data driver is further configured to update the display elements of the display panel based at least partially on a second image data received from the host and bypassing the GRAM. The display driver according to claim 1.

3. The first mode is a command mode in which the GRAM is configured to store the third image data transmitted by the command, The display driver is configured to update the display elements of the display panel based at least partially on the third image data stored in the GRAM in the command mode. The display driver according to claim 1.

4. Furthermore, the system includes an emission pulse generator configured to generate emission pulses that control the light emission of the plurality of display elements of the display panel, based at least partially on the display vertical synchronization signal. The display driver according to claim 1.

5. Adjusting the display vertical synchronization signal in the second mode is Extending the first frame period by the first extension amount, The second frame period, which begins after the first frame period, is extended by a second extension amount that is longer than the first extension amount. The third frame period, which begins after the second frame period, is extended by a third extension amount that is shorter than the second extension amount. including The display driver according to claim 1.

6. A display panel equipped with multiple display elements, Display driver and, Equipped with, The aforementioned display driver GRAM and, A data driver, In the first mode, the display elements are updated at least partially based on a display vertical synchronization signal generated within the display driver and commands supplied to the display driver asynchronously. In the second mode, the display elements of the display panel are updated based at least partially on the first image data stored in the GRAM. In the third mode, a data driver configured to update the display elements of the display panel in synchronization with an external vertical synchronization signal, A control circuit, In response to the first command, the display driver is switched from the first mode to the second mode. In the second mode, the display vertical synchronization signal is adjusted based at least partially on an external vertical synchronization signal. A control circuit configured to switch the display driver to the third mode after achieving synchronization of the display vertical synchronization signal with the external vertical synchronization signal, Equipped with Display device.

7. The second mode is a video RAM mode configured such that the GRAM receives the first image data from the host, The third mode is a video-through mode in which the data driver is further configured to update the display elements of the display panel based at least partially on a second image data received from the host and bypassing the GRAM. The display device according to claim 6.

8. Furthermore, the system includes an emission pulse generator configured to generate emission pulses that control the light emission of the plurality of display elements of the display panel, based at least partially on the display vertical synchronization signal. The display device according to claim 6.

9. To generate emission pulses that control the light emission of the display elements of the display panel, at least partially based on the display vertical synchronization signal, In the first mode, the display element is updated at least partially based on commands supplied asynchronously to the display driver in response to the display vertical synchronization signal, Switching the display driver from the first mode to the second mode in response to the first command, In the second mode, the display elements of the display panel are updated based at least partially on the first image data stored in the GRAM of the display driver, In the second mode, the display vertical synchronization signal is adjusted based at least partially on an external vertical synchronization signal, After achieving synchronization of the display vertical synchronization signal with the external vertical synchronization signal, the display driver is switched to the third mode. In the third mode described above, the display elements of the display panel are updated in synchronization with the external vertical synchronization signal, including method.

10. In the second mode, adjusting the display vertical synchronization signal is at least partially based on an emission synchronization signal that is generated in synchronization with the external vertical synchronization signal and has the same period as the period of the emission pulse. The method according to claim 9.

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