Semiconductor device and power device

Abstract

To provide a semiconductor device that can reduce on-resistance.SOLUTION: A semiconductor device has: a first semiconductor part and a second semiconductor part that are of the same conductivity type as each other and arranged along a first direction; a third semiconductor part that is provided between the first semiconductor part and the second semiconductor part, and has a lower impurity concentration than the first semiconductor part and the second semiconductor part; a fourth semiconductor part that is provided between the second semiconductor part and the third semiconductor part, and has a lower impurity concentration than the first semiconductor part and the second semiconductor part; a gate insulating layer and a gate electrode that are provided side by side with the third semiconductor part in a second direction intersecting the first direction; and a dielectric part that is provided side by side with the fourth semiconductor part in the second direction. The dielectric part is formed of a material having a larger band gap and a larger dielectric constant than a material forming the fourth semiconductor part. When a predetermined voltage is applied to the gate electrode, a depletion layer is formed in the fourth semiconductor part.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a power device. [Background technology]

[0002] Semiconductor nanocolumns are attracting attention as a next-generation nanodevice component for application in various semiconductor devices such as transistors and light sources. For example, by adopting a GAA (Gate All Around) structure in which the semiconductor nanocolumn is completely surrounded in the circumferential direction by a gate electrode, the channel formation region of the semiconductor nanocolumn is completely surrounded by the gate electrode, resulting in complete depletion and improved current controllability. The GAA structure makes it possible to achieve both steep on / off switching characteristics over time and high density per unit area. For example, Patent Document 1 describes a transistor device including a nanowire, a gate dielectric surrounding the nanowire, and a gate conductor surrounding the gate dielectric. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2014-503998 Summary of the Invention [Problem to be solved by the invention]

[0004] In such transistor devices, it is desirable to reduce the on-resistance. [Means for solving the problem]

[0005] One aspect of the semiconductor device according to the present invention is a first semiconductor portion and a second semiconductor portion that are of the same conductivity type and are arranged along a first direction; a third semiconductor portion provided between the first semiconductor portion and the second semiconductor portion and having a lower impurity concentration than the first semiconductor portion and the second semiconductor portion; a fourth semiconductor portion provided between the second semiconductor portion and the third semiconductor portion and having an impurity concentration lower than that of the first semiconductor portion and the second semiconductor portion; a gate insulating layer and a gate electrode provided in a second direction intersecting the first direction of the third semiconductor portion; a dielectric portion provided in the second direction of the fourth semiconductor portion; and the dielectric portion is made of a material having a larger band gap and a larger relative dielectric constant than a material constituting the fourth semiconductor portion, When a predetermined voltage is applied to the gate electrode, a depletion layer is formed in the fourth semiconductor portion.

[0006] One aspect of the power device according to the present invention is a first semiconductor portion and a second semiconductor portion that are of the same conductivity type and are arranged along a first direction; a third semiconductor portion provided between the first semiconductor portion and the second semiconductor portion and having a lower impurity concentration than the first semiconductor portion and the second semiconductor portion; a fourth semiconductor portion provided between the second semiconductor portion and the third semiconductor portion and having an impurity concentration lower than that of the first semiconductor portion and the second semiconductor portion; a gate insulating layer and a gate electrode provided in a second direction intersecting the first direction of the third semiconductor portion; a dielectric portion provided in the second direction of the fourth semiconductor portion; and the dielectric portion is made of a material having a larger band gap and a larger relative dielectric constant than a material constituting the fourth semiconductor portion, When a predetermined voltage is applied to the gate electrode, a depletion layer is formed in the fourth semiconductor portion. [Brief explanation of the drawings]

[0007] [Figure 1]FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to an embodiment of the present invention. [Figure 2] FIG. 1 is a plan view schematically showing a semiconductor device according to an embodiment of the present invention. [Figure 3] 1A to 1C are cross-sectional views schematically showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 4] 1A to 1C are cross-sectional views schematically showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 5] 1A to 1C are cross-sectional views schematically showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 6] FIG. 10 is a cross-sectional view schematically showing a semiconductor device according to a modified example of the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Preferred embodiments of the present invention will be described in detail below with reference to the drawings. Note that the embodiments described below do not unduly limit the content of the present invention as defined in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0009] 1. Semiconductor Devices First, a semiconductor device according to this embodiment will be described with reference to the drawings. Fig. 1 is a cross-sectional view schematically showing a semiconductor device 100 according to this embodiment. Fig. 2 is a plan view schematically showing the semiconductor device 100 according to this embodiment. Fig. 1 is a cross-sectional view taken along line II in Fig. 2. Figs. 1 and 2 show an X-axis, a Y-axis, and a Z-axis as three mutually orthogonal axes.

[0010] As shown in FIGS. 1 and 2, the semiconductor device 100 includes a substrate 10, a buffer layer 20, a mask layer 22, a columnar section 30, an insulating layer 40, a gate insulating layer 50, a gate electrode 60, a dielectric layer 70, and a drain electrode 80. The semiconductor device 100 is, for example, a power device. The semiconductor device 100 is, for example, a vertical metal oxide semiconductor field effect transistor (MOSFET). For convenience, the drain electrode 80 is not shown in FIG. 2.

[0011] The substrate 10 is, for example, a Si substrate, a GaN substrate, a sapphire substrate, or a SiC substrate.

[0012] As shown in FIG. 1 , the buffer layer 20 is provided on the substrate 10. The buffer layer 20 is, for example, a Si-doped n-type GaN layer or an AlGaN layer. The buffer layer 20 functions, for example, as a source. The buffer layer 20 is electrically connected, for example, to a source pad (not shown). The source pad is electrically connected to the source region 32 of the columnar section 30 via the buffer layer 20.

[0013] In this specification, in the stacking direction of the channel formation region 34 and the drain region 38 of the columnar section 30, when the channel formation region 34 is used as a reference, the direction from the channel formation region 34 toward the drain region 38 is referred to as "up" and the direction from the channel formation region 34 toward the source region 32 is referred to as "down." In the illustrated example, the stacking direction of the channel formation region 34 and the drain region 38 is the Z-axis direction.

[0014] The mask layer 22 is provided on the buffer layer 20. The mask layer 22 is provided between the buffer layer 20 and the insulating layer 40. The mask layer 22 is, for example, a titanium layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, or the like. The mask layer 22 has a plurality of openings 24. In the illustrated example, the openings 24 penetrate the mask layer 22 in the Z-axis direction. The columnar portions 30 are located in the openings 24. The mask layer 22 functions as a mask for growing the columnar portions 30.

[0015] The columnar portion 30 is provided on the buffer layer 20. The columnar portion 30 is provided on the substrate 10 via the buffer layer 20. The columnar portion 30 has a columnar shape that protrudes upward from the buffer layer 20. In other words, the columnar portion 30 protrudes upward from the substrate 10 via the buffer layer 20. The columnar portion 30 is provided between the buffer layer 20 and the drain electrode 80. The columnar portion 30 is also called, for example, a nanocolumn, a nanowire, a nanorod, or a nanopillar. The planar shape of the columnar portion 30 is, for example, a polygon such as a hexagon, or a circle. In the example shown in FIG. 2, the planar shape of the columnar portion 30 is a regular hexagon.

[0016] The diameter of the columnar portion 30 is, for example, 50 nm or more and 500 nm or less, and preferably 100 nm or more and 300 nm or less. By making the diameter of the columnar portion 30 500 nm or less, it is possible to obtain a columnar portion 30 of high quality crystal.

[0017] It should be noted that the "diameter of the columnar portion 30" refers to the diameter when the planar shape of the columnar portion 30 is circular, and refers to the diameter of the smallest encompassing circle when the planar shape of the columnar portion 30 is not circular. For example, when the planar shape of the columnar portion 30 is polygonal, the diameter of the smallest circle that includes the polygon inside, and when the planar shape of the columnar portion 30 is elliptical, the diameter of the smallest circle that includes the ellipse inside.

[0018] For example, a plurality of columnar portions 30 are provided. By providing a plurality of columnar portions 30, the semiconductor device 100 can achieve a large current and is suitable for use as a power device. The plurality of columnar portions 30 are spaced apart from one another. The interval between adjacent columnar portions 30 is, for example, 10 nm to 1 μm, preferably 0.5 to 1.5 times the diameter of the columnar portion 30, i.e., 25 nm to 750 nm, and more preferably 400 nm to 600 nm. The plurality of columnar portions 30 are arranged, for example, at a predetermined pitch in a predetermined direction as viewed from the Z-axis direction. The plurality of columnar portions 30 are arranged, for example, in a triangular lattice or square lattice pattern. In the illustrated example, the plurality of columnar portions 30 are arranged, for example, in a regular triangular lattice pattern.

[0019] The "pitch of the columnar portions 30" refers to the distance between the centers of adjacent columnar portions 30 in a predetermined direction. When the planar shape of the columnar portions 30 is a circle, the "center of the columnar portion 30" refers to the center of the circle. When the planar shape of the columnar portions 30 is a shape other than a circle, the "center of the columnar portion 30" refers to the center of the smallest circle that contains the polygon. For example, when the planar shape of the columnar portions 30 is a polygon, the center of the smallest circle that contains the polygon. When the planar shape of the columnar portions 30 is an ellipse, the center of the smallest circle that contains the ellipse.

[0020] As shown in FIG. 1, the columnar section 30 has a source region 32, a channel formation region , a drift region 37, and a drain region .

[0021] The source region 32 is provided on the buffer layer 20. The source region 32 is provided between the buffer layer 20 and the channel formation region 34. The source region 32 is made of a semiconductor layer. The material of the source region 32 is, for example, n-type GaN or AlGaN doped with Si. The impurity concentration of the source region 32 may be the same as the impurity concentration of the buffer layer 20.

[0022] The channel formation region 34 is provided on the source region 32. The channel formation region 34 is provided between the source region 32 and the drift region 37. The channel formation region 34 is made of a semiconductor layer. The impurity concentration of the channel formation region 34 is lower than the impurity concentration of the source region 32 and the impurity concentration of the drain region 38. The impurity concentrations of the source region 32, the channel formation region 34, the drift region 37, and the drain region 38 are measured by, for example, atom probe analysis.

[0023] The material of the channel formation region 34 is, for example, UID (unintentionally doped) GaN or AlGaN, which is not intentionally doped with impurities. Because the diameter of the columnar portion 30 is small, the channel formation region 34 can be completely depleted even if the conductivity type of the channel formation region 34 is UID type. A channel is formed in the channel formation region 34 by applying a predetermined voltage to the gate electrode 60. For example, an N channel is formed in the channel formation region 34.

[0024] The drift region 37 is provided on the channel formation region 34. The drift region 37 is provided between the channel formation region 34 and the drain region 38. The drift region 37 is made of a semiconductor layer. The conductivity type of the drift region 37 is, for example, the same as that of the source region 32. The material of the drift region 37 is, for example, Si-doped n-type GaN or AlGaN.

[0025] The impurity concentration of the drift region 37 is lower than the impurity concentration of the source region 32 and the impurity concentration of the drain region 38. The impurity concentration of the drift region 37 may be the same as the impurity concentration of the channel formation region 34. Alternatively, the impurity concentration of the drift region 37 may be higher than the impurity concentration of the channel formation region 34. In other words, the impurity concentration of the drift region 37 may be between the impurity concentrations of the channel formation region 34 and the drain region 38. By providing the drift region 37, the breakdown voltage of the semiconductor device 100 in the off state can be improved.

[0026] The drain region 38 is provided on the drift region 37. The drain region 38 is provided between the drift region 37 and the drain electrode 80. The drain region 38 is made of a semiconductor layer. The conductivity type of the drain region 38 is the same as that of the source region 32. The material of the drain region 38 is, for example, Si-doped n-type GaN or AlGaN.

[0027] The impurity concentration of the drain region 38 is higher than the impurity concentration of the drift region 37. The impurity concentration of the drain region 38 may be the same as the impurity concentration of the source region 32. The source region 32, the channel formation region 34, the drift region 37, and the drain region 38 are arranged along a first direction. In the illustrated example, the first direction is the +Z-axis direction. The source region 32, the channel formation region 34, the drift region 37, and the drain region 38 are stacked, for example, in the +Z-axis direction to form the columnar section 30.

[0028] The insulating layer 40 is provided on the mask layer 22. The insulating layer 40 is provided between the substrate 10 and the gate electrode 60. The insulating layer 40 is provided between the source regions 32 of adjacent columnar sections 30. The insulating layer 40 surrounds the source regions 32 when viewed from the Z-axis direction. The insulating layer 40 is, for example, an SOG (spin on glass) layer.

[0029] The gate insulating layer 50 is provided on the side surface of the channel formation region 34 of the columnar section 30. The side surface of the channel formation region 34 is formed, for example, by the m-plane. The gate insulating layer 50 is provided in a second direction that intersects with the first direction of the channel formation region 34. In the example shown, the second direction is the +Y-axis direction, which is perpendicular to the first direction, which is the +Z-axis direction. The gate insulating layer 50 surrounds the channel formation region 34 when viewed from the Z-axis direction. The gate insulating layer 50 is provided between the channel formation region 34 and the gate electrode 60.

[0030] The gate insulating layer 50 is made of, for example, a material having a larger band gap than the material constituting the channel formation region 34. Furthermore, the gate insulating layer 50 is made of, for example, a material having a larger dielectric constant than the material constituting the channel formation region 34. The material of the gate insulating layer 50 is, for example, a transition metal oxide such as hafnium oxide (HfO2), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), or lanthanum oxide (La2O3), and is preferably hafnium oxide. The material of the gate insulating layer 50 may also be silicon oxide (SiO2).

[0031] The gate electrode 60 is provided in the gate insulating layer 50. The gate electrode 60 is provided in the +Y-axis direction of the channel formation region 34. In the illustrated example, the gate electrode 60 surrounds the gate insulating layer 50 when viewed from the Z-axis direction. The gate electrode 60 is provided in the insulating layer 40, for example, with an insulating layer 52 interposed therebetween. The material of the insulating layer 52 is the same as that of the gate insulating layer 50. The gate electrode 60 is provided between the insulating layer 40 and the dielectric layer 70. The gate electrode 60 is provided between the channel formation regions 34 of adjacent columnar sections 30.

[0032] The gate electrode 60 is made of a material such as polysilicon doped with impurities such as phosphorus or boron, or a metal. The semiconductor device 100 has a GAA structure. The gate electrode 60 is electrically connected to a gate pad (not shown).

[0033] The dielectric layer 70 is provided on the gate insulating layer 50 and the gate electrode 60. The dielectric layer 70 is provided between the gate insulating layer 50 and the gate electrode 60 and the drain electrode 80. The dielectric layer 70 is provided in the +Y-axis direction of the drift region 37. In the illustrated example, the dielectric layer 70 surrounds the drift region 37. The dielectric layer 70 is provided between the drift regions 37 of adjacent columnar sections 30.

[0034] The dielectric layer 70 is made of a material having a larger band gap than the material constituting the drift region 37. Furthermore, the dielectric layer 70 is made of a material having a larger dielectric constant than the material constituting the drift region 37. The material of the dielectric layer 70 is, for example, a transition metal oxide such as hafnium oxide, tantalum oxide, yttrium oxide, zirconium oxide, or lanthanum oxide, and preferably hafnium oxide.

[0035] Since the dielectric layer 70 is made of a material having a larger band gap and a larger dielectric constant than the material constituting the drift region 37, when a predetermined voltage is applied to the gate electrode 60, a dielectric RESURF (reduced surface field) effect is exerted, and a depletion layer is formed in the drift region 37 due to the electric field generated in the dielectric layer 70. The semiconductor device 100 can have a pseudo-superjunction structure due to the dielectric RESURF effect. The predetermined voltage is a voltage for turning the semiconductor device 100 into an off state.

[0036] The depletion layer formed by the electric field generated in the dielectric layer 70 spreads from the side surface of the drift region 37 of the columnar section 30 toward the center of the columnar section 30, as indicated by arrow A1 in Fig. 1. Furthermore, there is also a depletion layer that spreads from the channel formation region 34 toward the drift region 37, as indicated by arrow A2. In this way, in the semiconductor device 100, the depletion layer can be spread in both the vertical and horizontal directions, thereby exhibiting the dielectric RESURF effect.

[0037] The drain electrode 80 is provided on the drain region 38 and on the dielectric layer 70. The drain electrode 80 is provided in the +Z-axis direction of the drain region 38. The drain region 38 may be in ohmic contact with the drain electrode 80.

[0038] The drain electrode 80 is made of a material such as polysilicon doped with impurities such as phosphorus or boron, or a metal. The drain electrode 80 is electrically connected to a drain pad (not shown). The drain pad is electrically connected to the drain region 38 via the drain electrode 80.

[0039] The semiconductor device 100 is used, for example, as a power device, and is applied to inverters, chargers, step-up converters, step-down converters, DC (Direct Current) / DC converters, electric airplanes, electric vehicles, etc. The semiconductor device 100 may also be used as a logic device, a high-frequency device, etc., instead of a power device.

[0040] The semiconductor device 100 has the following advantages, for example.

[0041] The semiconductor device 100 includes a source region 32 as a first semiconductor portion and a drain region 38 as a second semiconductor portion, which are of the same conductivity type and arranged along the +Z-axis direction, a channel formation region 34 as a third semiconductor portion provided between the source region 32 and the drain region 38 and having a lower impurity concentration than the source region 32 and the drain region 38, a drift region 37 as a fourth semiconductor layer provided between the channel formation region 34 and the drain region 38 and having a lower impurity concentration than the source region 32 and the drain region 38, a gate insulating layer 50 and a gate electrode 60 provided in the +Y-axis direction of the channel formation region 34, and a dielectric layer 70 as a dielectric portion provided in the +Y-axis direction of the drift region 37. The dielectric layer 70 is made of a material having a larger band gap and a higher dielectric constant than the material constituting the drift region 37, and when a predetermined voltage is applied to the gate electrode 60, a depletion layer is formed in the drift region 37 by an electric field generated in the dielectric layer 70.

[0042] Therefore, in the semiconductor device 100, the dielectric resurf effect, in which a depletion layer expands from the side surface of the drift region 37 of the columnar section 30 toward the center of the columnar section 30, as indicated by the arrow A1, can be enhanced compared to when the dielectric constant of the dielectric layer is equal to or lower than that of the drift region. This improves the breakdown voltage. As a result, the impurity concentration of the drift region 37 can be increased, thereby reducing the on-resistance.

[0043] Furthermore, in the semiconductor device 100, the insulating properties of the dielectric layer 70 can be improved compared to when the band gap of the dielectric layer is equal to or smaller than the band gap of the drift region, for example. This can reduce leakage current.

[0044] Furthermore, in the semiconductor device 100, the impurity concentration of the channel formation region 34 is lower than the impurity concentrations of the source region 32 and the drain region 38, which increases the carrier mobility in the channel formation region 34. For example, when an N-channel is formed in the channel formation region 34, the electron mobility in the channel formation region 34 can be increased. This reduces the on-resistance.

[0045] Furthermore, the semiconductor device 100 can be manufactured more easily than when a p-type semiconductor layer having a conductivity type different from that of the source region 32 and the drain region 38 is provided instead of the dielectric layer 70. For example, when a superjunction structure is formed by providing a p-type semiconductor layer instead of the dielectric layer 70, it becomes necessary to control the impurity concentration of the p-type semiconductor layer with high precision, which complicates the manufacturing process.

[0046] Furthermore, in the semiconductor device 100, in the off state, the potential difference between the gate electrode 60 and the drain region 38 is larger than the potential difference between the gate electrode 60 and the source region 32. Therefore, the dielectric RESURF effect can be made larger than when a dielectric layer is provided in the +Y-axis direction of the source region.

[0047] In the semiconductor device 100, the source region 32, the channel formation region 34, and the drift region 37 are stacked in the +Z-axis direction to form the columnar portion 30. Therefore, in the semiconductor device 100, compared to when the source region, the channel formation region, and the drift region do not form a columnar portion, the possibility that crystal defects caused by the difference in lattice constant between the substrate 10 and the buffer layer 20 will bend at the side surface of the columnar portion 30 in the source region 32 and reach the channel formation region 34 and the drift region 37 can be reduced. This allows the channel formation region 34 and the drift region 37 to have high-quality crystallinity. In the illustrated example, the drain region 38 also forms the columnar portion 30, and therefore the drain region 38 can also have high-quality crystallinity.

[0048] In the semiconductor device 100, when viewed from the Z-axis direction, the gate insulating layer 50 surrounds the channel formation region 34, and the gate electrode 60 surrounds the gate insulating layer 50. Therefore, in the semiconductor device 100, the channel formation region 34 can be completely depleted.

[0049] In the semiconductor device 100, the material of the dielectric layer 70 is a transition metal oxide. Therefore, in the semiconductor device 100, it is easier to realize the dielectric layer 70 having a larger band gap and a larger relative dielectric constant than the drift region 37.

[0050] In the semiconductor device 100, the material of the dielectric layer 70 is hafnium oxide. Therefore, in the semiconductor device 100, the dielectric layer 70 can be formed by ALD (Atomic Layer Deposition). This allows the dielectric layer 70 to be formed without generating voids, even between adjacent columnar sections 30, for example.

[0051] In the semiconductor device 100, the gate insulating layer 50 is made of a material having a larger band gap and a larger dielectric constant than the material constituting the channel formation region 34. Therefore, in the semiconductor device 100, the controllability of the threshold voltage can be improved compared to, for example, a case where the dielectric constant of the gate insulating layer is equal to or lower than that of the channel formation region. Furthermore, the insulating properties of the gate insulating layer 50 can be improved compared to, for example, a case where the band gap of the gate insulating layer is equal to or lower than that of the channel formation region.

[0052] In the semiconductor device 100, the material of the gate insulating layer 50 is a transition metal oxide. Therefore, in the semiconductor device 100, it is easy to realize the gate insulating layer 50 having a larger band gap and a larger relative dielectric constant than the channel formation region 34.

[0053] In the semiconductor device 100, the material of the gate insulating layer 50 is hafnium oxide. Therefore, in the semiconductor device 100, the gate insulating layer 50 can be formed by the ALD method. This allows the gate insulating layer 50 to be formed without generating voids, even between adjacent columnar portions 30, for example.

[0054] 2. Manufacturing method of semiconductor device Next, a method for manufacturing the semiconductor device 100 according to this embodiment will be described with reference to the drawings. Figures 3 to 5 are cross-sectional views that schematically show the manufacturing process of the semiconductor device 100 according to this embodiment.

[0055] 3, a buffer layer 20 is epitaxially grown on a substrate 10. Examples of methods for epitaxial growth include MOCVD (Metal Organic Chemical Vapor Deposition) and MBE (Molecular Beam Epitaxy). The buffer layer 20 is grown while being doped with impurities.

[0056] Next, a mask layer 22 is formed on the buffer layer 20. The mask layer 22 is formed by, for example, electron beam evaporation or sputtering.

[0057] Next, the mask layer 22 is patterned to form a plurality of openings 24. The patterning is performed by, for example, electron beam lithography and dry etching.

[0058] As shown in FIG. 4, a source region 32, a channel formation region 34, a drift region 37, and a drain region 38 are epitaxially grown in this order on the buffer layer 20 using the mask layer 22 as a mask. Examples of epitaxial growth methods include MOCVD and MBE. The source region 32 and the drain region 38 are grown while doping with impurities. This process allows the formation of multiple columnar sections 30.

[0059] Next, an insulating layer 40 is formed on the mask layer 22 and between the source regions 32 of the adjacent columnar sections 30. The insulating layer 40 is formed by, for example, an ALD method, a CVD (Chemical Vapor Deposition) method, an SOG (spin on glass) method, or the like.

[0060] 5, an insulating layer 50a is formed on the insulating layer 40 so as to cover the columnar section 30. The insulating layer 50a is formed by, for example, an ALD method, a CVD method, or the like. In the illustrated example, the insulating layer 50a is formed on the side and top surfaces of the columnar section 30.

[0061] Next, the gate electrode 60 is formed on the insulating layer 50a. The gate electrode 60 is formed by, for example, a CVD method, a sputtering method, or a vacuum deposition method.

[0062] 1, a portion of the insulating layer 50a is removed by etching, thereby forming the gate insulating layer 50 between the channel formation region 34 and the gate electrode 60. The drain region 38 is exposed by this etching.

[0063] Next, the dielectric layer 70 is formed on the gate insulating layer 50 and the gate electrode 60. The dielectric layer 70 is formed by, for example, the ALD method, the CVD method, or the like.

[0064] Next, the drain electrode 80 is formed on the drain region 38 and the dielectric layer 70. The drain electrode 80 is formed by, for example, a CVD method, a sputtering method, or a vacuum deposition method.

[0065] Through the above steps, the semiconductor device 100 can be manufactured.

[0066] 3. Modifications of semiconductor devices Next, a semiconductor device according to a modification of this embodiment will be described with reference to the drawings. Fig. 6 is a cross-sectional view schematically showing a semiconductor device 200 according to a modification of this embodiment. Hereinafter, in the semiconductor device 200 according to the modification of this embodiment, components having the same functions as the components of the semiconductor device 100 according to this embodiment described above will be given the same reference numerals, and detailed description thereof will be omitted.

[0067] In the semiconductor device 100 described above, the drain region 38 constitutes the columnar section 30 as shown in FIG.

[0068] 6, in the semiconductor device 200, the drain region 38 does not constitute the columnar portion 30. The columnar portion 30 is constituted by a source region 32, a channel formation region 34, and a drift region 37.

[0069] The drain region 38 is further provided in the +Z-axis direction of the dielectric layer 70. The drain region 38 is provided on the drift region 37 and on the dielectric layer 70. The drain region 38 is provided between the drift region 37 and the dielectric layer 70 and the drain electrode 80. The drain region 38 is provided across multiple columnar portions 30. When viewed from the stacking direction, the drain region 38 overlaps with multiple columnar portions 30. When viewed from the stacking direction, the drain electrode 80 overlaps with multiple columnar portions 30.

[0070] The semiconductor device 200 has a drain electrode 80 provided in the +Z-axis direction of the drift region 37, and the drain region 38 is further provided in the +Z-axis direction of the dielectric layer 70. Therefore, in the semiconductor device 200, the contact area between the drain region 38 and the drain electrode 80 can be made larger than when the drain region is not provided in the +Z-axis direction of the dielectric layer. This makes it possible to reduce the contact resistance between the drain region 38 and the drain electrode 80. Since the contact resistance between a semiconductor layer and a metal electrode is generally high, it is important to increase the contact area.

[0071] The above-described embodiment and modifications are merely examples, and the present invention is not limited to these. For example, the embodiments and modifications can be combined as appropriate.

[0072] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects. The present invention also includes configurations that replace non-essential parts of the configurations described in the embodiments. The present invention also includes configurations that achieve the same effects or purposes as the configurations described in the embodiments. The present invention also includes configurations that add publicly known technology to the configurations described in the embodiments.

[0073] The following can be derived from the above-described embodiment and modifications.

[0074] One aspect of the semiconductor device is a first semiconductor portion and a second semiconductor portion that are of the same conductivity type and are arranged along a first direction; a third semiconductor portion provided between the first semiconductor portion and the second semiconductor portion and having a lower impurity concentration than the first semiconductor portion and the second semiconductor portion; a fourth semiconductor portion provided between the second semiconductor portion and the third semiconductor portion and having an impurity concentration lower than that of the first semiconductor portion and the second semiconductor portion; a gate insulating layer and a gate electrode provided in a second direction intersecting the first direction of the third semiconductor portion; a dielectric portion provided in the second direction of the fourth semiconductor portion; and the dielectric portion is made of a material having a larger band gap and a larger relative dielectric constant than a material constituting the fourth semiconductor portion, When a predetermined voltage is applied to the gate electrode, a depletion layer is formed in the fourth semiconductor portion.

[0075] Such a semiconductor layer can reduce the on-resistance.

[0076] In one aspect of the semiconductor device, The first semiconductor portion, the third semiconductor portion, and the fourth semiconductor portion may be stacked in the first direction to form a columnar portion.

[0077] Such a semiconductor layer can reduce the possibility that crystal defects will reach the third semiconductor portion and the fourth semiconductor portion.

[0078] In one aspect of the semiconductor device, When viewed from the first direction, the gate insulating layer surrounds the third semiconductor portion, The gate electrode may surround the gate insulating layer.

[0079] Such a semiconductor layer allows the third semiconductor portion to be completely depleted.

[0080] In one aspect of the semiconductor device, the first semiconductor portion constitutes a source region, The second semiconductor portion may constitute a drain region.

[0081] Such a semiconductor layer can enhance the dielectric RESURF effect.

[0082] In one aspect of the semiconductor device, The material of the dielectric portion may be a transition metal oxide.

[0083] With such a semiconductor layer, it is easy to realize a dielectric portion having a larger band gap and a larger relative dielectric constant than the second semiconductor portion.

[0084] In one aspect of the semiconductor device, The dielectric portion may be made of hafnium oxide.

[0085] With such a semiconductor layer, the dielectric portion can be formed by the ALD method.

[0086] In one aspect of the semiconductor device, The gate insulating layer may be made of a material having a larger band gap and a larger relative dielectric constant than a material making up the third semiconductor portion.

[0087] Such a semiconductor layer can improve the controllability of the threshold voltage.

[0088] In one aspect of the semiconductor device, The material of the gate insulating layer may be a transition metal oxide.

[0089] With such a semiconductor layer, it is easier to realize a gate insulating layer having a larger band gap and a larger relative dielectric constant than the third semiconductor portion.

[0090] In one aspect of the semiconductor device, The material of the gate insulating layer may be hafnium oxide.

[0091] With such a semiconductor layer, the gate insulating layer can be formed by the ALD method.

[0092] In one aspect of the semiconductor device, an electrode provided in the first direction of the second semiconductor portion; The second semiconductor portion may be further provided in the first direction of the dielectric portion.

[0093] Such a semiconductor layer can reduce the contact resistance between the second semiconductor portion and the electrode.

[0094] One aspect of the power device is a first semiconductor portion and a second semiconductor portion that are of the same conductivity type and are arranged along a first direction; a third semiconductor portion provided between the first semiconductor portion and the second semiconductor portion and having a lower impurity concentration than the first semiconductor portion and the second semiconductor portion; a gate insulating layer and a gate electrode provided in a second direction intersecting the first direction of the third semiconductor portion; a dielectric portion provided in the second direction of the second semiconductor portion; and the dielectric portion is made of a material having a larger band gap and a larger relative dielectric constant than a material constituting the second semiconductor portion, When a predetermined voltage is applied to the gate electrode, a depletion layer is formed in the second semiconductor portion due to an electric field generated in the dielectric portion.

[0095] Such a power device can reduce the on-resistance. [Explanation of symbols]

[0096] 10...substrate, 20...buffer layer, 22...mask layer, 24...opening, 30...columnar portion, 32...source region, 34...channel formation region, 37...drift region, 38...drain region, 40...insulating layer, 50...gate insulating layer, 50a, 52...insulating layers, 60...gate electrode, 70...dielectric layer, 80...drain electrode, 100, 200...semiconductor device

Claims

1. a first semiconductor portion and a second semiconductor portion that are of the same conductivity type and are arranged along a first direction; a third semiconductor portion provided between the first semiconductor portion and the second semiconductor portion and having a lower impurity concentration than the first semiconductor portion and the second semiconductor portion; a fourth semiconductor portion provided between the second semiconductor portion and the third semiconductor portion and having an impurity concentration lower than that of the first semiconductor portion and the second semiconductor portion; a gate insulating layer and a gate electrode provided in a second direction intersecting the first direction of the third semiconductor portion; a dielectric portion provided in the second direction of the fourth semiconductor portion; and the dielectric portion is made of a material having a larger band gap and a larger dielectric constant than a material constituting the fourth semiconductor portion, When a predetermined voltage is applied to the gate electrode, a depletion layer is formed in the fourth semiconductor portion.

2. In claim 1, The first semiconductor portion, the third semiconductor portion, and the fourth semiconductor portion are stacked in the first direction to form a columnar portion.

3. In claim 2, When viewed from the first direction, the gate insulating layer surrounds the third semiconductor portion, The gate electrode surrounds the gate insulating layer.

4. In any one of claims 1 to 3, the first semiconductor portion constitutes a source region, The second semiconductor portion constitutes a drain region.

5. In any one of claims 1 to 4, The semiconductor device, wherein the dielectric portion is made of a transition metal oxide.

6. In any one of claims 1 to 5, The semiconductor device, wherein the dielectric portion is made of hafnium oxide.

7. In any one of claims 1 to 6, The semiconductor device, wherein the gate insulating layer is made of a material having a larger band gap and a larger dielectric constant than a material making up the third semiconductor portion.

8. In any one of claims 1 to 7, The semiconductor device, wherein the gate insulating layer is made of a transition metal oxide.

9. In any one of claims 1 to 8, The semiconductor device, wherein the gate insulating layer is made of hafnium oxide.

10. In any one of claims 1 to 9, an electrode provided in the first direction of the second semiconductor portion; The second semiconductor portion is further provided in the first direction of the dielectric portion.

11. a first semiconductor portion and a second semiconductor portion that are of the same conductivity type and are arranged along a first direction; a third semiconductor portion provided between the first semiconductor portion and the second semiconductor portion and having a lower impurity concentration than the first semiconductor portion and the second semiconductor portion; a fourth semiconductor portion provided between the second semiconductor portion and the third semiconductor portion and having an impurity concentration lower than that of the first semiconductor portion and the second semiconductor portion; a gate insulating layer and a gate electrode provided in a second direction intersecting the first direction of the third semiconductor portion; a dielectric portion provided in the second direction of the fourth semiconductor portion; and the dielectric portion is made of a material having a larger band gap and a larger dielectric constant than a material constituting the fourth semiconductor portion, When a predetermined voltage is applied to the gate electrode, a depletion layer is formed in the fourth semiconductor portion.

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