Radio communication device, and radio communication system

Abstract

To synchronize a clock signal between devices performing radio communication even under an environment in which phase variation due to radio transmission path characteristic fluctuation occurs.SOLUTION: A radio communication device includes a transmission circuit part, a modulation part, a coding part, a reception circuit part, a phase adjustment part, and an antenna part. The transmission circuit part transmits a modulation signal, provided from the modulation part and coded by the coding part, from the antenna part to another radio communication device through a transmission path based on a first clock signal. The reception circuit part generates a second clock signal based on a signal received by the antenna part from the other radio communication device. The phase adjustment part detects phase variation due to the transmission path based on the second clock signal, and controls code of the modulation signal based on the phase variation.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a wireless communication device and a wireless communication system.

Background Art

[0002] In a device that transmits a signal synchronized with a reference clock signal wirelessly from a device having a reference clock signal source (hereinafter referred to as a clock source device) and receives the transmitted signal (hereinafter referred to as a clock reproduction device), a technique for reproducing a clock signal based on the received signal is known. Patent Document 1 discloses a technique in which control information obtained from the synchronization state of a clock signal reproduced by a clock reproduction device is fed back to the clock source device, and the clock source device adjusts the phase of the transmitted signal based on the control information.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In an environment where there are fluctuations in the position of an antenna for communication or movement of an object near a wireless transmission path, the phase of a signal changes due to Doppler shift or multipath effects caused by changes in the distance of the wireless transmission path. Hereinafter, this change in phase is referred to as a phase change due to fluctuations in wireless transmission path characteristics.

[0005] In the method described in Patent Document 1, the signal received by the clock regeneration device and the clock signal regenerated from that signal can be synchronized. Since the signal received by the clock regeneration device is synchronized with the reference clock signal, if no phase change occurs due to fluctuations in the wireless transmission path characteristics, the reference clock signal of the clock source device and the signal received and regenerated by the clock regeneration device will be synchronized. However, if a phase change occurs due to fluctuations in the wireless transmission path characteristics, there is a problem that the reference clock signal of the clock source device and the clock signal regenerated by the clock regeneration device will not be synchronized.

[0006] Therefore, the present invention aims to synchronize clock signals between wireless communication devices even in environments where phase changes occur due to fluctuations in wireless transmission path characteristics. [Means for solving the problem]

[0007] To solve the above problems, the wireless communication device according to the present invention comprises a transmitting circuit unit, a modulation unit, an encoding unit, a receiving circuit unit, a phase adjustment unit, and an antenna unit, wherein the transmitting circuit unit transmits a first modulated signal from the modulation unit encoded by the encoding unit as a first signal to another wireless communication device via a transmission line from the antenna unit, based on a first clock signal, the receiving circuit unit generates a second clock signal based on a second signal received by the antenna unit from the other wireless communication device, and the phase adjustment unit detects a phase change due to the transmission line based on the second clock signal and controls the code of the first modulated signal based on the phase change. [Effects of the Invention]

[0008] According to the present invention, clock signals between wireless communication devices can be synchronized even in environments where phase changes occur due to fluctuations in wireless transmission path characteristics. [Brief explanation of the drawing]

[0009] [Figure 1] Diagram showing the configuration of the wireless communication system in the first embodiment. [Figure 2] Diagram showing the configuration of the clock source device in the first embodiment. [Figure 3] This figure shows the configuration of the clock regeneration device in the first embodiment. [Figure 4] This figure shows the configuration of the phase adjustment unit in the first embodiment. [Figure 5] This figure shows the configuration of the transmission circuit in the first embodiment. [Figure 6] This figure shows the configuration of the receiving circuit in the first embodiment. [Figure 7] A diagram showing the phase relationship of each clock signal in the first embodiment. [Figure 8] Diagram showing the configuration of the clock source device in the second embodiment. [Figure 9] Flowchart showing the operation flow in the second embodiment [Figure 10] Time chart of each component block in the second embodiment [Modes for carrying out the invention]

[0010] Each embodiment will be described below with reference to the drawings. Note that the following embodiments do not necessarily limit the present invention. Furthermore, not all combinations of features described in each embodiment are essential to the solution of the present invention.

[0011] [First Embodiment] Hereinafter, the configuration of the entire wireless communication system in the present embodiment will be described. FIG. 1 shows the configuration of the wireless communication system in the present embodiment. The clock source device 100 is one of the two devices that synchronize clock signals, namely, the clock source device. The clock source device 100 includes a reference clock signal source 101 that generates a reference clock signal Sr, a processing unit 102 that performs various processes on the clock signal, and an antenna unit 103 that wirelessly transmits and receives signals. The clock reproduction device 104 represents the other of the two devices that synchronize clock signals, namely, the clock reproduction device. The clock reproduction device 104 includes an antenna unit 105 that wirelessly transmits and receives signals, and a processing unit 106 that reproduces the clock signal by processing the received signal.

[0012] The clock source device 100 generates the reference clock signal Sr with the reference clock signal source 101, performs processing with the processing unit 102, and then wirelessly transmits the signal with the antenna unit 103. The clock reproduction device 104 receives the signal transmitted by the antenna unit 103 with the antenna unit 105, performs processing with the processing unit 106 to reproduce the clock signal Srx, and feeds back the signal from the antenna unit 105 to the antenna unit 103. The clock source device 100 performs processing on the signal to be transmitted again with the processing unit 102 based on the phase of the signal received by the antenna unit 103, and transmits the processed signal from the antenna unit 103. In this way, the wireless communication system in the present embodiment repeatedly performs feedback by signal transmission between devices.

[0013] Finally, the clock signal Srx synchronizes with the reference clock signal Sr. Therefore, a system including the clock source device 100 that operates using the reference clock signal Sr and a system including the clock reproduction device 104 that operates using the clock signal Srx can operate at the same timing within the range where the clock signal can be wirelessly communicated.

[0014] Next, the more detailed configuration and functions of the clock source device 100 and the clock regeneration device 104 will be described. Figure 2 shows the configuration of the processing unit 102 and the antenna unit 103 connected to the processing unit 102. The processing unit 102 has a phase adjustment unit 201, a transmission circuit unit 202, a reception circuit unit 203, and a code data generation unit (encoding unit) 204, and the antenna unit 103 has a transmission antenna 103A and a reception antenna 103B. The code data generation unit 204 generates an encoded signal A. It is desirable that 0s and 1s are used randomly and at equal frequency in the encoded signal A. An example of a signal that satisfies this condition is PRBS (Pseudo-Random Binary Sequence). Furthermore, if it is desired to send a data signal together with a clock signal, Manchester coding or 6B10B may be combined with PRBS. In this embodiment, the encoded signal A is assumed to be PN9 encoded with 8B10B.

[0015] The phase adjustment unit 201 adjusts the phase of the encoded signal A input from the coded data generation unit 204 based on the phase of the clock signal Sf input from the receiving circuit unit 203 and the phase of the reference clock signal Sr input from the reference clock signal source 101 to generate encoded signal B. The transmitting circuit unit 202 upconverts encoded signal B with a carrier signal generated from the clock signal Sr and sends it as a wireless signal from the transmitting antenna 103A to the wireless transmission path. The receiving circuit unit 203 downconverts the wireless signal received by the receiving antenna 103B and inputs the downconverted signal as a clock signal Sf to the phase adjustment unit 201. In an environment where fluctuations in wireless transmission path characteristics occur, the phase adjustment unit 201 detects the phase change due to the fluctuations in wireless transmission path characteristics from the feedbacked wireless signal.

[0016] FIG. 3 shows the configuration of the processing unit 106 and the antenna unit 105 connected to the processing unit 106. The processing unit 106 has a reception circuit unit 301 and a transmission circuit unit 302, and the antenna unit 105 has a reception antenna 105A and a transmission antenna 105B. The reception circuit unit 301 down-converts the radio signal received by the reception antenna 105A, regenerates the clock signal Srx, and inputs the clock signal Srx to the transmission circuit unit 302. The transmission circuit unit 302 up-converts the clock signal Srx input from the reception circuit unit 301 and sends it out from the transmission antenna 105B to the radio transmission path. As described above, in the wireless communication system of this embodiment, the clock source device performs phase adjustment of the clock signal, the clock regeneration device regenerates the clock signal from the received signal without performing phase adjustment of the clock signal, and feeds back the received signal to the clock source device.

[0017] FIG. 4 shows the circuit configuration of the phase adjustment unit 201 shown in FIG. 2. The phase adjustment unit 201 has a phase comparator 401 and a bit compensation unit 402. The phase comparator 401 compares the phase of the reference clock signal Sr and the phase of the clock signal Sf obtained based on the radio signal fed back from the clock regeneration device 104 by using, for example, a mixer, and outputs a detection result (phase difference signal) corresponding to the phase difference. The bit compensation unit 402 generates a correction signal C with a phase corresponding to the output of the phase comparator 401, and outputs an encoded signal B by adding it to the encoded signal A. Specifically, the bit compensation unit 402 determines the compensation bits to be added and the addition period of the compensation bits according to the phase difference signal.

[0018] Figure 5 shows the configuration of the transmitting circuit 202 shown in Figure 2. Although only the transmitting circuit 202 is shown in Figure 5, the transmitting circuit 302 in Figure 3 has the same configuration. The transmitting circuit 202 has a PLL (Phase Locked Loop) 501, a modulation unit 502, and a mixer 503. The PLL 501 generates a carrier signal by upconverting the reference clock signal Sr to an arbitrary frequency using the frequency division ratio of its internal frequency divider. That is, the reference clock signal Sr and the carrier signal are synchronized. The modulation unit 502 generates an IQ modulated signal Stx based on the input encoded signal B. The clock used for IQ modulation may be the reference clock signal Sr, the output signal of the PLL 501, or a signal from an external clock source. The mixer 503 mixes the input carrier signal and the IQ modulated signal Stx and then outputs it to the transmitting antenna 103A.

[0019] The modulation scheme in this embodiment is CPFSK (Continuous Phase Frequency Shift Keying). In CPFSK, the average clock of the IQ modulation signal Stx varies depending on the total number of 0s and 1s in the encoded signal B. For example, if there are many 0s, the average clock becomes lower, and if there are many 1s, the average clock becomes higher. If the modulation is reversed, if there are many 0s, the average clock becomes higher, and if there are many 1s, the average clock becomes lower. Note that the modulation scheme is not limited to CPFSK, and other modulation schemes may be used.

[0020] Figure 6 shows the configuration of the receiving circuit 301 shown in Figure 2. Although only the receiving circuit 301 is shown in Figure 6, the receiving circuit 203 in Figure 2 has the same configuration. The receiving circuit 301 has a bandpass filter 601, an AGC (Automatic Gain Control) 602, and a frequency divider 603. The bandpass filter 601 allows only signals of a desired frequency to pass through the received signal. The AGC 602 adjusts the amplitude of the received signal to a constant value. The frequency divider 603 extracts the clock signal Srx by down-converting the received signal.

[0021] Next, we will explain how the feedbacked received signal is processed by the clock source device 100. Figure 7 shows the phase relationship for each clock signal compared in the phase adjustment unit 201 when the reference clock signal Sr and the clock signal Srx reproduced by the clock regeneration device 104 are synchronized. Here, the wireless transmission path characteristics are assumed to be symmetric, and the amount of phase change due to fluctuations in the wireless transmission path characteristics is denoted as Δθ. Since the transmitted wireless signal travels back and forth through the transmission path through feedback, the phase difference between the IQ modulated signal Stx and the clock signal Sf is 2Δθ. A This indicates the phase difference between the reference clock signal Sr and the clock signal Sf. Δθ B This shows the phase difference between the IQ modulated signal Stx and the clock signal Srx. The phase adjustment unit 201 detects the phase difference Δθ with the phase comparator 401, and Δθ A =Δθ B The phase of the encoded signal A is adjusted so that the following occurs. Specifically, the phase adjustment unit 201 assigns either 0 or 1 at a period of Δdθ / dt / 2π depending on whether the phase change is leading or lagging. A =Δθ B When (=Δθ), the phases of the reference clock signal Sr and the clock signal Srx become equal, and the clock signals between devices can be synchronized. In short, the phase adjustment unit 201 detects the amount of phase change due to fluctuations in the wireless transmission path characteristics based on the feedbacked wireless signal, and generates an IQ modulated signal Stx using an encoded signal B which is obtained by adding a correction signal C that causes a phase change in the opposite direction to that phase change to the encoded signal A. As a result, the clock signal Srx, which has the phase change due to fluctuations in the wireless transmission path characteristics added to the transmitted wireless signal, and the reference clock signal Sr are synchronized.

[0022] Furthermore, different frequencies may be used for communication between the transmitting antenna 103A and the receiving antenna 105A, and for communication between the receiving antenna 103B and the transmitting antenna 105B, in order to prevent interference. For example, a signal with frequency f1 may be used for communication between the transmitting antenna 103A and the receiving antenna 105A, and a signal with frequency f2 may be used for communication between the receiving antenna 103B and the transmitting antenna 105B. In this case, for communication between the transmitting antenna 103A and the receiving antenna 105A, the frequency of the output signal of the PLL 501 in the transmitting circuit 202 will be f1-Stx, and the bandpass filter 601 in the receiving circuit 301 will only allow frequency f1 to pass through. Also, for communication between the receiving antenna 103B and the transmitting antenna 105B, the two wireless transmission paths can be separated by using frequency f2 in the transmitting circuit 302 and the receiving circuit 203.

[0023] With the above circuit configuration, a system can be provided that allows for wireless synchronization of the clock signals of two devices, even in environments where phase changes occur due to fluctuations in wireless transmission path characteristics.

[0024] [Second Embodiment] The configuration of the wireless communication system in this embodiment will be described below. The configuration of the wireless communication system in this embodiment is the same as in the first embodiment, except that a switch (SW) for switching the encoded signal is added to the processing unit 102. Therefore, the configurations that differ from the first embodiment will be described in detail.

[0025] In the first embodiment, the PLL circuits in the transmitting circuit section 202 and transmitting circuit section 302 require a certain amount of time after startup before they can output a signal with a stable phase. This required time is called the pull-in time. Similarly, in the phase adjustment section 201, a pull-in time occurs until the clock signal achieves the phase relationship shown in Figure 7 and outputs a signal with a stable phase and frequency. During the pull-in time, the feedback clock signal Sf includes not only the phase change due to fluctuations in the wireless transmission line characteristics but also the phase change of the output of the PLL circuit. Therefore, in this embodiment, a configuration is described in which the phase adjustment section 201 detects only the phase change due to fluctuations in the wireless transmission line characteristics and can shorten the pull-in time until it outputs a clock signal with the phase relationship shown in Figure 7.

[0026] Figure 8 shows the configuration with the SW801 and control unit 802 added to the processing unit 102. SW801 is a switch for switching between encoded signal A and encoded signal B when the encoded signal input to the transmitting circuit unit 202. When encoded signal A is input to the transmitting circuit unit 202, SW801 connects the encoded data generation unit 204 to the transmitting circuit unit 202, and when encoded signal B is input to the transmitting circuit unit 202, SW801 connects the encoded data generation unit 204 to the phase adjustment unit 201. The control unit 802 controls the timing of switching the connection destination of SW801.

[0027] Next, using Figure 9, the operation flow from system startup to the startup of the phase adjustment unit 201 in this embodiment will be explained. First, immediately after system startup, the control unit 802 controls SW801 to connect the code data generation unit 204 and the transmission circuit unit 202 (S901). That is, the phase adjustment unit 201 does not operate, and a radio signal with the same phase as the reference clock signal Sr is transmitted. In this state, the system waits for a certain period of time until the phase of the output of the PLL circuit in the transmission circuit unit 202 and the transmission circuit unit 302 stabilizes (S902). The control unit 802 determines whether or not it has stabilized (S903), and waits until the phase fluctuation of the clock signal Sf obtained from the feedback radio signal stabilizes, that is, until the output voltage of the PLL circuit converges to within the set value. At this time, the clock signal Sf will only contain phase changes due to fluctuations in the radio transmission line characteristics.

[0028] When the control unit 802 determines that the signal phase has stabilized, the SW801 connects the code data generation unit 204 and the phase adjustment unit 201. The phase adjustment unit 201 operates and starts operating as a wireless clock synchronization system as described in the first embodiment (S904).

[0029] Figure 10 shows the time chart for each component block in this embodiment. The horizontal axis in Figure 10 represents time, and it represents the pull-in time until the phase of the output of each circuit section stabilizes. t0 is the startup time, t1 and t2 represent the pull-in time from the startup of each transmitting circuit section, respectively, and t3 represents the end of the pull-in time of the phase adjustment unit 201 in this embodiment. If SW801 is not provided and all circuit sections, including the phase adjustment unit 201, are started simultaneously, the pull-in time in each circuit section increases, and as a result, the pull-in time of the entire system increases.

[0030] By starting the operation of the phase adjustment unit 201 from t2 according to the flow shown in Figure 9, the operation of the entire system can be stabilized, and the total pull-in time from t0 to t3 can be shortened compared to the first embodiment.

[0031] Furthermore, PLL circuits may be provided in the receiving circuit section 301 and the receiving circuit section 203 as frequency dividers or for the purpose of jitter reduction. In this case, if the phase adjustment section 201 is operated after waiting for the pull-in time from the startup of each transmitting and receiving circuit section, the same effect as described above can be obtained. [Explanation of symbols]

[0032] 100 Clock source device 103 Antenna section 104 Clock Regeneration Device 105 Antenna section 201 Phase adjustment section 202 Transmitting Circuit Section 203 Receiving Circuit Section 301 Receiving circuit section 302 Transmitter Circuit Section

Claims

1. 1. A wireless communication device, comprising: The signal processing apparatus includes a transmission circuit unit, a modulation unit, an encoding unit, a reception circuit unit, a phase adjustment unit, and an antenna unit, the transmission circuit unit transmits, based on a first clock signal, the first modulated signal from the modulation unit, which has been coded by the coding unit, as a first signal from the antenna unit through a transmission path to another wireless communication device; the receiving circuit unit generates a second clock signal based on a second signal received by the antenna unit from the other wireless communication device; The wireless communication device, characterized in that the phase adjustment unit detects a phase change due to the transmission path based on the second clock signal, and controls a code of the first modulated signal based on the phase change.

2. The phase adjustment unit is a phase comparator that outputs a phase difference signal based on a phase difference between the first clock signal and the second clock signal; a bit compensation unit that determines a compensation bit to be provided and a period for providing the compensation bit in response to the phase difference signal; The encoding unit outputs the code to which the compensation bits are added to the modulation unit; The wireless communication device according to claim 1 , wherein the modulation section performs modulation based on the code.

3. 3. The wireless communication device according to claim 2, wherein the compensation bit is either 0 or 1.

4. a switch that switches so that the first clock signal is output to either the transmission circuit unit and the modulation unit or the phase adjustment unit; 4. The wireless communication device according to claim 3, further comprising a control unit that determines a state in which there is no output from the encoding unit as a stable state, and controls the switch based on a result of the determination.

5. The wireless communication device according to claim 1, wherein the receiving circuit section includes a bandpass filter, an AGC (Automatic Gain Control), and a frequency divider.

6. The wireless communication device according to claim 1, wherein the modulation method in the modulation section is CPFSK (Continuous Phase Frequency Shift Keying).

7. the other wireless communication device has a second transmitting circuit unit, a second modulating unit, a second encoding unit, a second receiving circuit unit, and a second antenna unit; the second receiving circuit unit generates a third clock signal based on the first signal received by the second antenna unit; The wireless communication device according to any one of claims 1 to 6, characterized in that the second transmitting circuit unit transmits a second modulated signal from the second modulation unit, which is encoded by the second encoding unit based on the third clock signal, as the second signal from the second antenna unit to the wireless communication device via a transmission path.

8. A wireless communication system having a first wireless communication device and a second wireless communication device, the first wireless communication device includes a first transmitting circuit unit, a first modulating unit, a first encoding unit, a first receiving circuit unit, a phase adjusting unit, and a first antenna unit; the second wireless communication device has a second transmitting circuit unit, a second modulating unit, a second encoding unit, a second receiving circuit unit, and a second antenna unit; the first transmission circuit unit transmits, based on a first clock signal, a first modulated signal from the first modulation unit, which has been encoded by the first encoding unit, as a first signal from the first antenna unit through a transmission path to the second wireless communication device; the second receiving circuit unit generates a second clock signal based on the first signal received by the second antenna unit; the second transmission circuit unit transmits, based on the second clock signal, a second modulated signal from the second modulation unit, which has been encoded by the second encoding unit, as a second signal from the second antenna unit through a transmission path to the first wireless communication device; the first receiving circuit unit generates a third clock signal based on the second signal received by the first antenna unit; The phase adjustment unit detects a phase change caused by the transmission path based on the third clock signal, and controls a code of the first modulated signal based on the phase change.

Images