Power storage device

Abstract

To suppress a failure of an FET due to heat generated by a parasitic diode.SOLUTION: A power storage device 50 includes: a cell 60; a relay 53 for cutting off current of the cell 60; a bypass circuit 120 connected to the relay 53 in parallel; and a management device 150. The bypass circuit 120 includes two FETs 121 and 123 which are back-to-back connected. When abnormality of the cell 60 is detected, the management device 150 OPENs the relay 53, CLOSEs one of the two FETs 121 and 123, OPENS the other, and allows discharge or charge of the cell 60 in a route passing a parasitic diode of the FET. If current of the FETs 121 and 123 and conduction time T reach a prescribed condition or a temperature of the FETs 121 and 123 reaches the prescribed condition during discharge or charge in the route passing the parasitic diode, the management device 150 CLOSEs the relay 53 and the other of the FETs 121 and 123 which is OPENed.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a technique for protecting a FET. [Background technology]

[0002] One of the protection devices for a battery is a relay. When an abnormality such as over-discharge or over-charge is detected, the relay opens to cut off the current, thereby protecting the battery. The following Patent Document 1 discloses providing a bypass circuit in parallel with the relay. The bypass circuit is composed of two FETs connected back-to-back. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-34297 Summary of the Invention [Problem to be solved by the invention]

[0004] It is possible to use a bypass circuit to control charging and discharging while the relay is open. Specifically, the first FET and second FET connected back-to-back have parasitic diodes oriented in opposite directions, with the parasitic diode of the first FET oriented in the charging direction and the parasitic diode of the second FET oriented in the discharging direction.

[0005] In this case, when the first FET is closed and the second FET is opened while the relay is open, only discharge is possible via the path that passes through the parasitic diode of the second FET.

[0006] Therefore, for example, when overcharging is detected, the relay is opened, the first FET is closed, and the second FET is opened, thereby restricting charging and allowing only discharging via the path that passes through the parasitic diode of the second FET.

[0007] However, since the parasitic diode generates heat when current is passed through it, if a current exceeding the allowable value flows through the parasitic diode for a certain period of time, the FET may break down.

[0008] In addition, in the case of over-discharge, the relay can be opened, the first FET can be opened, and the second FET can be closed to restrict discharge while only charging is performed via the path that passes through the parasitic diode of the first FET. In this case as well, the same problem occurred.

[0009] An object of the present invention is to suppress FET failure caused by heat generation from a parasitic diode. [Means for solving the problem]

[0010] The power storage device includes a cell, a relay for cutting off a current in the cell, a bypass circuit connected in parallel to the relay, and a management device. The bypass circuit includes two FETs connected back-to-back.

[0011] When the management device detects an abnormality in the cell, it opens the relay, closes one of the two FETs and opens the other, allowing the cell to be discharged or charged through a path that passes through the parasitic diode of the FET.

[0012] When discharging or charging through a path that passes through the parasitic diode, if the current I and current flow time T of the FET reach predetermined conditions or if the temperature of the FET reaches predetermined conditions, the management device CLOSEs the relay and the other FET that is open.

[0013] When discharging or charging through a path that passes through the parasitic diode, if the current I and current flow time T of the FET reach a predetermined condition or the temperature of the FET reaches a predetermined condition, the management device maintains the relay in the OPEN state and closes the other OPEN FET. Effect of the Invention

[0014] This technology can suppress FET failure caused by heat generation from parasitic diodes. [Brief description of the drawings]

[0015] [Figure 1] Car side view [Diagram 2] Exploded perspective view of the battery [Diagram 3] Cell top view [Figure 4] Cross section of line AA in Figure 3 [Diagram 5] Block diagram showing the electrical configuration of the battery [Figure 6] IT characteristics [Figure 7] Diagram showing the current path of the battery [Figure 8] Diagram showing the current path of the battery [Figure 9] IT characteristics [Figure 10] FET protection process flowchart [Figure 11] FET protection process flowchart [Figure 12] Diagram showing the current path of the battery [Figure 13] Diagram showing the current path of the battery [Figure 14] FET protection process flowchart [Figure 15] Block diagram showing the electrical configuration of the battery [Figure 16] Block diagram showing the electrical configuration of the battery DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] The outline of the power storage device will be described. (1) An energy storage device according to one embodiment of the present invention includes a cell, a relay for cutting off a current in the cell, a bypass circuit connected in parallel to the relay, and a management device. The bypass circuit includes two FETs connected back-to-back.

[0017] When the management device detects an abnormality in the cell, it opens the relay, closes one of the two FETs and opens the other, allowing the cell to be discharged or charged through a path that passes through the parasitic diode of the FET.

[0018] When discharging or charging through a path that passes through the parasitic diode, if the current I and current flow time T of the FET reach predetermined conditions or if the temperature of the FET reaches predetermined conditions, the management device CLOSEs the relay and the other FET that is open.

[0019] The above-mentioned energy storage device (1) has the following effects. While the relay is open, one of the FETs is open, and the cell is discharged or charged through a path that passes through the parasitic diode of the open FET. At this time, if there is a risk of FET failure due to heat generation from the parasitic diode, if the relay and the open FET are closed at the same time, the FET without contacts will close earlier than the relay with contacts. Closing the FET increases the current that can be passed through the bypass circuit compared to before it was closed, so that heat generation in the FET and failure of the FET can be suppressed. After the FET is closed, the relay contacts are closed with a delay, but after the relay contacts are closed, the current that can be passed further increases, and most of the current flows through the relay, so that failure of the FET can be further suppressed.

[0020] (2) An energy storage device according to one embodiment of the present invention includes a cell, a relay for cutting off a current in the cell, a bypass circuit connected in parallel to the relay, and a management device. The bypass circuit includes two FETs connected back-to-back.

[0021] When the management device detects an abnormality in the cell, it opens the relay, closes one of the two FETs and opens the other, allowing the cell to be discharged or charged through a path that passes through the parasitic diode of the FET.

[0022] When discharging or charging through a path that passes through the parasitic diode, if the current I and current flow time T of the FET reach a predetermined condition or the temperature of the FET reaches a predetermined condition, the management device maintains the relay in the OPEN state and closes the other OPEN FET.

[0023] The above-mentioned power storage device (2) has the following effects. While the relay is open, one of the FETs is open, and the cell is discharged or charged through a path that passes through the parasitic diode of the open FET. At this time, if there is a risk of the FET failing due to heat generation from the parasitic diode, the open FET is closed to increase the current that can be passed through the bypass circuit compared to before the FET was closed. The increase in the current that can be passed can suppress the heat generation of the FET and suppress FET failure. In addition, since the relay is maintained open, no clicking noises are generated when the contacts are opened and closed. Therefore, for example, by applying this technology to a power storage device mounted on an automobile, it is expected to be effective in reducing unpleasant noises while riding in the automobile.

[0024] (3) In the power storage device according to (1) or (2) above, the abnormality in the cell may be overcharging or over-discharging. With this configuration, it is possible to take measures against FET failure while protecting the cell from overcharging or over-discharging.

[0025] (4) In the power storage device according to any one of (1) to (3) above, the power storage device may be used for starting an engine. Since the power storage device for starting an engine discharges a large current, when cranking is performed with the relay controlled to OPEN, a large current flows through a parasitic diode in the bypass circuit, and the FET is highly likely to break down. In particular, when the battery is overcharged, the cell voltage is high and the cranking current is likely to be large, so that the FET is highly likely to break down. By applying the present technology to a power storage device for starting an engine that discharges a large current, it is possible to supply a cranking current while suppressing FET failure even when the battery is overcharged.

[0026] In the case of over-discharge, the cell voltage is low and the current is likely to be low. By turning on the two FETs, the resistance value of the bypass circuit can be lowered and the voltage drop of the storage device can be suppressed. This makes it possible to suppress cranking failures caused by voltage drops and current shortages.

[0027] <Embodiment 1> 1. Battery 50 Description As shown in Fig. 1, an automobile 10 is equipped with an engine 20 and a battery 50 used for starting the engine 20. The battery 50 is an example of an "electricity storage device." The automobile 10 may also be equipped with an electricity storage device for driving the vehicle or a fuel cell.

[0028] 2, the battery 50 includes a battery pack 60, a circuit board unit 65, and a housing 71. The housing 71 includes a main body 73 and a lid 74 made of a synthetic resin material. The main body 73 is cylindrical with a bottom, and includes a bottom portion 75 and four side portions 76. The four side portions 76 form an opening 77 at the upper end of the main body 73.

[0029] The container 71 houses the battery pack 60 and the circuit board unit 65. The circuit board unit 65 is a board unit having various components (such as the relay 53, the bypass circuit 120 shown in FIG. 5, and the management device 150) mounted on a circuit board 100, and is disposed adjacent to, for example, above, the battery pack 60 as shown in FIG. 2. Alternatively, the circuit board unit 65 may be disposed adjacent to, and to the side of, the battery pack 60.

[0030] The lid 74 closes the opening 77 of the main body 73. An outer peripheral wall 78 is provided around the lid 74. The lid 74 has a protruding portion 79 that is generally T-shaped in plan view. A positive external terminal 51 is fixed to one corner of the front part of the lid 74, and a negative external terminal 52 is fixed to the other corner. The circuit board unit 65 may be housed in the lid 74 (for example, in the protruding portion 79) instead of in the main body 73 of the container 71.

[0031] The battery pack 60 is composed of a plurality of cells 62. As shown in Fig. 4, each cell 62 has an electrode body 83 housed in a rectangular (prismatic) case 82 together with a non-aqueous electrolyte. The cell 62 is, for example, a lithium ion secondary battery cell. The case 82 has a case body 84 and a lid 85 that closes the upper opening.

[0032] Although not shown in detail, the electrode body 83 is a structure in which a separator made of a porous resin film is disposed between a negative electrode plate in which an active material is applied to a substrate made of copper foil and a positive electrode plate in which an active material is applied to a substrate made of aluminum foil. Both of these are in the form of a strip, and are wound flatly so as to be able to be housed in the case body 84, with the negative electrode plate and the positive electrode plate being shifted to opposite sides in the width direction relative to the separator. The electrode body 83 may be of a laminated type instead of a wound type.

[0033] A positive electrode terminal 87 is connected to the positive electrode plate via a positive electrode collector 86, and a negative electrode terminal 89 is connected to the negative electrode plate via a negative electrode collector 88. The positive electrode collector 86 and the negative electrode collector 88 each have a flat base portion 90 and a leg portion 91 extending from the base portion 90. A through hole is formed in the base portion 90. The leg portion 91 is connected to the positive electrode plate or the negative electrode plate.

[0034] The positive electrode terminal 87 and the negative electrode terminal 89 each comprise a terminal body 92 and a shaft 93 that protrudes downward from the center of the lower surface of the terminal body 92. The terminal body 92 and shaft 93 of the positive electrode terminal 87 are integrally formed from aluminum (a single material). In the negative electrode terminal 89, the terminal body 92 is made of aluminum, and the shaft 93 is made of copper, and these are assembled together. The terminal body 92 of the positive electrode terminal 87 and the negative electrode terminal 89 are disposed on both ends of the lid 85 via gaskets 94 made of an insulating material, and are exposed to the outside from the gaskets 94, as shown in FIG. 3.

[0035] The lid 85 has a pressure relief valve 95. The pressure relief valve 95 is located between the positive terminal 87 and the negative terminal 89. The pressure relief valve 95 is a safety valve. The pressure relief valve 95 opens to reduce the internal pressure of the case 82 when the internal pressure of the case 82 exceeds a limit.

[0036] 5 is a block diagram showing the electrical configuration of the battery 50. The battery 50 includes a battery pack 60, a relay 53, a voltage detection unit 54, a current sensor 55, a temperature sensor 58, a bypass circuit 120, and a management device 150.

[0037] The battery 50 is electrically connected to an engine starting device 160, an electric load 170 such as an auxiliary device, and a vehicle generator 180.

[0038] When the engine 20 is running, if the amount of power generated by the vehicle generator 180 is greater than the amount of power consumed by the electrical load 170, the battery 50 is charged by the vehicle generator 180. If the amount of power generated by the vehicle generator 180 is less than the amount of power consumed by the electrical load 170, the battery 50 discharges to make up for the shortfall.

[0039] When the engine 20 is stopped, the vehicle generator 180 stops generating power. When power generation is stopped, the battery 50 is not charged, and only discharges power to the electric load 170.

[0040] The battery pack 60 has, for example, 12 cells 62 (see FIG. 2), three connected in parallel and four in series. In FIG. 5, three cells 62 connected in parallel are represented by one battery symbol. The cells are not limited to prismatic cells, and may be cylindrical cells or pouch cells having a laminated film case.

[0041] The battery pack 60, the relay 53, and the current sensor 55 are connected in series via power lines 57P and 57N. The power lines 57P and 57N can be bus bars BSB (see FIG. 2), which are plate-shaped conductors made of a metal material such as copper.

[0042] 5, the power line 57P connects the positive external terminal 51 and the positive electrode of the battery pack 60. The power line 57N connects the negative external terminal 52 and the negative electrode of the battery pack 60.

[0043] The external terminals 51, 52 are terminals for connecting the battery 50 to the automobile 10 (the engine starting device 160, the electrical load 170, and the vehicle generator 180). The battery 50 can be electrically connected to the engine starting device 160, the electrical load 170, and the vehicle generator 180 via the external terminals 51, 52.

[0044] The current sensor 55 is provided on the negative power line 57N. The current sensor 55 may be a metal plate resistor (shunt resistor). The current sensor 55 measures the current I of the battery pack 60 based on the voltage Vr across the resistor. The current sensor 55 can distinguish between charging and discharging based on the polarity (positive or negative) of the voltage Vr across both ends.

[0045] The voltage detection unit 54 measures the cell voltage Vs of each cell 62 and the total voltage Vt of the battery pack 60. The temperature sensor 58 is attached to the battery pack 60 and detects the temperature of the battery pack 60 or its surroundings.

[0046] The relay 53 is provided on the positive power line 57P. The relay 53 is preferably a self-holding switch such as a latching relay. This embodiment uses a latching relay.

[0047] The relay 53 is of a normally closed type and is controlled to be closed under normal circumstances. If any abnormality occurs in the battery 50, the current I of the battery pack 60 can be cut off by switching the relay 53 from closed to open.

[0048] The bypass circuit 120 includes a first FET 121 and a second FET 123. In this embodiment, a P-channel FET is used for the first FET 121 and the second FET 123. The FETs are field effect transistors.

[0049] As shown in FIG. 5, the first FET 121 has a source S connected to one end (point A) of the relay 53, and the second FET 123 has a source S connected to the other end (point B) of the relay 53.

[0050] The first FET 121 and the second FET 123 have their drains connected to each other, forming a back-to-back connection. A back-to-back connection is a connection of the drains or sources of FETs to each other.

[0051] The first FET 121 has a parasitic diode D1, and the second FET 123 has a parasitic diode D2. The forward direction of the parasitic diode D1 is the charging direction, and the forward direction of the parasitic diode D2 is the discharging direction, so that they are opposite directions.

[0052] The gate G of the first FET 121 and the gate G of the second FET 123 are connected to the management device 150 via signal lines L1 and L2. The management device 150 can individually control the FETs 121 and 123 by sending control signals to the FETs 121 and 123 via the signal lines L1 and L2.

[0053] The bypass circuit 120 is connected in parallel with the relay 53. When the relay is open, the first FET 121 is closed and the second FET 123 is opened, so that the battery pack 60 can be discharged to the automobile 10 through a path that passes through the bypass circuit 120 (a path that passes through the source-drain of the first FET 121 and the parasitic diode D2 of the second FET 123: see FIG. 8). In this case, charging is prevented by the parasitic diode D2.

[0054] While the relay is open, the first FET 121 is open and the second FET 123 is closed, so that the battery pack 60 can be charged through a path passing through the bypass circuit 120 (a path passing through the source-drain of the second FET 123 and the parasitic diode D1 of the first FET: see FIG. 13). In this case, discharging is prevented by the parasitic diode D1.

[0055] The management device 150 is mounted on the circuit board 100 (see FIG. 2), and includes a CPU 151, a memory 153, and a timer unit 155, as shown in FIG.

[0056] The management device 150 monitors the state of the battery 50 based on the outputs of the voltage detection unit 54, the current sensor 55, and the temperature sensor 58. That is, the temperature, the current I, and the total voltage Vt of the battery pack 60 are monitored.

[0057] The memory 153 stores a program for monitoring the battery 50, a program for executing the FET protection process, and data required for executing these programs. The programs may be stored in a recording medium such as a CD-ROM and used, transferred, lent, etc. The programs may be distributed using an electric communication line.

[0058] The timer 155 is used to measure the time during which the first FET 121 and the second FET 123 are energized.

[0059] 2.IT characteristics of FET 6, F1 is the IT characteristic of the FET, with the horizontal axis representing the current flow time T and the vertical axis representing the current I. Specifically, this is the IT characteristic of the FET when the second FET 123 is open and a current flows through the parasitic diode D2.

[0060] The region below F1 is a safe operating region in which the second FET 123 operates safely. In the region above F1, the second FET 123 may fail due to heat generation by the parasitic diode D2.

[0061] For example, when the current value is 100 A, the second FET 123 is within the safe operating area and operates safely if the current is less than 30 ms, but if the current is more than 30 ms, the second FET 123 may be out of the safe operating area and may fail.

[0062] 3. Overcharge protection and heat generation from parasitic diodes 7, under normal circumstances, relay 53, first FET 121, and second FET 123 are all controlled to be CLOSE. The contact resistance of relay 53 is smaller than the on-resistance of first FET 121 and second FET 123, and most of current I passes through relay 53. The total voltage Vt of battery pack 60 increases with charging and decreases with discharging.

[0063] If the total voltage Vt of the battery pack 60 exceeds the upper limit during charging, the management device 150 determines that overcharging has occurred and switches the relay 53 from CLOSE to OPEN. Also, the first FET 121 is kept CLOSE, and the second FET 123 is switched from CLOSE to OPEN.

[0064] By closing the first FET 121 and opening the second FET 123, as shown in FIG. 8, even after overcharge is detected, discharge can be performed through a path passing through the source-drain of the first FET 121 and the parasitic diode D2 of the second FET 123.

[0065] If a large discharge current flows through the parasitic diode D2 and goes outside the safe operating area of ​​the IT characteristics, the second FET 123 may break down due to heat generation in the parasitic diode D2.

[0066] In order to prevent the failure of the second FET 123, it is conceivable to close the relay 53 to reduce the current of the second FET 123.

[0067] However, since relay 53 has mechanical contact 53A, it takes a long time to operate, and it takes time for contact 53A to switch after a command is sent from management device 150. Therefore, when a relatively large current is discharged to parasitic diode D2, there is a possibility that second FET 123 may break down before contact 53A closes.

[0068] In this embodiment, after an overcurrent is detected, if there is a possibility of failure of the second FET 123 during discharging via the path through the parasitic diode D2, a command is sent from the management device 150 to the relay 53 to switch from OPEN to CLOSE, and at the same time, a command is sent to the second FET 123 to switch from OPEN to CLOSE.

[0069] Since the second FET 123 is a semiconductor switch, its operating time is shorter than that of the mechanical switch, the relay 53. The operating time is the time from when a command is sent to a switch to when the state of the switch actually changes.

[0070] When a command is sent simultaneously to the relay 53 and the second FET 123, the second FET 123 closes in several tens of nanoseconds, and then, with a delay, the contacts of the relay close.

[0071] Since the allowable current between the drain and source of the second FET 123 is larger than the allowable current of the parasitic diode D2, it is possible to increase the allowable current of the bypass circuit 120 for a dozen or so milliseconds until the contact 53A of the relay 53 closes after the second FET 123 closes. Therefore, it is possible to suppress failure of the second FET 123 due to heat generation.

[0072] F0 to F3 shown in FIG. 9 are IT characteristics with the current flow time T on the horizontal axis and the current I on the vertical axis. Specifically, F1 is the IT characteristic when relay 53 is OPEN, first FET 121 is CLOSE, second FET 123 is OPEN, and current flows through parasitic diode D2. F2 is the IT characteristic when relay 53 is OPEN, first FET 121 and second FET 123 are CLOSE, and current flows between the source and drain of first FET 121 and second FET 123. F3 is the IT characteristic when relay 53 is CLOSE, first FET 121 and second FET 123 are CLOSE, and current flows between the contacts of relay 53.

[0073] The safe operating area becomes wider in the order of F3, F2, and F1, and the allowable current is largest in the order of relay 53, the source-drain of second FET 123, and the parasitic diode D2 of second FET 123. Specifically, when T=100 ms, the allowable current of relay 53 is approximately 2000 A, the allowable current of the drain-source of second FET 123 is 150 A, and the allowable current of the parasitic diode of second FET 123 is approximately 30 A.

[0074] F0 is an IT decision line that switches the relay 53 and the second FET 123 from OPEN to CLOSE in order to protect the FET.

[0075] Fig. 10 is a flowchart of the FET protection process. The FET protection process is executed when, after relay 53 is cut off due to overcharge detection, only discharging is allowed (charging is restricted) through the path passing through parasitic diode D2 of second FET 123, as shown in Fig. 8.

[0076] At the start of the FET protection process, the relay 53 is OPEN, the first FET 121 is CLOSE, and the second FET 123 is OPEN (see FIG. 8).

[0077] The FET protection process is made up of four steps, S10 to S40. In S10, management device 150 judges the IT condition of second FET 123. Specifically, management device 150 compares operating point P determined by current I and current flow time T of second FET 123 with IT judgment line F0 shown in Fig. 9, and judges whether operating point P of second FET 123 is below IT judgment line F0. The IT condition is an example of a predetermined condition of the present invention.

[0078] When the operating point P of the second FET 123 is below the IT determination line F0, the management device 150 keeps the first FET 121 CLOSE and the second FET 123 OPEN.

[0079] When the operating point P of the second FET 123 exceeds the IT decision line F0 and moves upward, the process proceeds to S20, and the management device 150 simultaneously sends a switching signal from OPEN to CLOSE to the relay 53 and the second FET 123.

[0080] Since the operating time of the FET is shorter than the operating time of the relay 53, the second FET 123 closes first (S30). The allowable current between the drain and source of the second FET 123 is greater than the allowable current of the parasitic diode D2. For example, when T=100 ms, the allowable current between the drain and source is approximately 150 A, and the allowable current of the parasitic diode D2 of the second FET 123 is approximately 30 A.

[0081] Therefore, it is possible to increase the current that can be passed through the bypass circuit 120 after the second FET 123 is closed, and therefore it is possible to prevent the second FET 123 from breaking down due to heat generation.

[0082] After the second FET 123 is closed, the relay 53 is closed with a delay (S40). After the relay 53 is closed, most of the discharge current flows through the relay 53, so that the current in the bypass circuit 120 is reduced and the heat generation in the second FET 123 is further suppressed.

[0083] <Embodiment 2> Fig. 11 is a flowchart of the FET protection process of embodiment 2. As in embodiment 1, the FET protection process is executed when, after relay 53 is cut off in response to overcharge detection, first FET 121 is controlled to be CLOSE and second FET 123 is controlled to be OPEN as shown in Fig. 8, and only discharging is possible (charging is restricted) through the path passing through parasitic diode D2 of second FET 123.

[0084] As in the first embodiment, after the management device 150 detects overcharge and opens the relay 53, it determines whether the operating point P of the bypass circuit 120 is below the IT determination line F0 (S10).

[0085] When the operating point P of the second FET 123 exceeds the IT determination line F0 (S10: YES), the management device 150 does not send a switching signal to the relay 53, but sends a switching signal from OPEN to CLOSE only to the second FET 123 (S23).

[0086] As shown in FIG. 12, the second FET 123 switches from OPEN to CLOSE in response to the switching signal (S33), and the relay 53 remains OPEN (S43).

[0087] The allowable drain-source current of the second FET 123 is larger than the allowable current of the parasitic diode D2. For example, when T=100 ms, the allowable drain-source current is about 150 A, and the allowable current of the parasitic diode D2 of the second FET 123 is about 30 A.

[0088] By closing the second FET 123 and increasing the allowable current, it is possible to suppress failure of the second FET 123 compared to the case where a current is allowed to continue to flow through the parasitic diode D2.

[0089] If the management device 150 detects charging after the second FET 123 is CLOSE (after S33), it can cut off the charging by switching the second FET 123 from CLOSE to OPEN.

[0090] In the second embodiment, the FET protection process is performed only by the second FET 123, and therefore the number of times the relay 53 operates can be reduced compared to the first embodiment in which the FET protection process is performed using the second FET 123 and the relay 53. Reducing the number of times the relay 53 operates can be expected to be effective in reducing unpleasant noise during riding.

[0091] <Embodiment 3> In the first embodiment, when overcharging is detected, the relay 53 is opened, the first FET 121 is closed, and the second FET 123 is opened, so that only discharging can occur through the path (parasitic diode D2) that passes through the bypass circuit 120, as shown in FIG.

[0092] When over-discharge is detected (when the total voltage Vt of the battery pack 60 falls below the lower limit voltage), the relay 53 may be opened, the first FET 121 may be opened, and the second FET 123 may be closed, so that charging can only be performed via the path that passes through the bypass circuit 120 (parasitic diode D1) as shown in FIG. 13.

[0093] If a large charging current flows through the parasitic diode D1 and goes outside the safe operating area of ​​the IT characteristic, the first FET 121 may break down due to heat generation by the parasitic diode D1.

[0094] Fig. 14 is a flowchart of the FET protection process. The FET protection process is executed when, after the relay 53 is cut off due to the detection of over-discharge, the relay 53 is opened, the first FET 121 is opened, the second FET 123 is closed, and only charging is possible (discharging is restricted) through the path passing through the parasitic diode D1 of the first FET 121 as shown in Fig. 13.

[0095] After detecting overcharge and opening relay 53, management device 150 determines whether operating point P of first FET 121 is below IT determination line F0 shown in FIG. 9 (S10).

[0096] When the operating point P of the first FET 121 exceeds the IT determination line F0, the management device 150 sends a switching signal to the relay 53 and the first FET 121 (S25).

[0097] Since the operating time of the FET is shorter than the operating time of the relay 53, the first FET 121 closes first (S35). The allowable current between the drain and source of the first FET 121 is greater than the allowable current of the parasitic diode D2. Therefore, after the first FET 121 closes, the allowable current of the bypass circuit 120 can be increased. Therefore, the failure of the first FET 121 due to heat generation can be suppressed.

[0098] After the first FET 121 is closed, the relay 53 is closed with a delay (S45). After the relay 53 is closed, most of the discharge current flows through the relay 53, so that the current in the bypass circuit 120 is reduced and the heat generation in the first FET 121 is further suppressed.

[0099] <Embodiment 4> The management device 150 may perform failure detection of the relay 53 by using the bypass circuit 120. The failure detection may be performed while the battery 50 is not in use, such as while the vehicle is parked.

[0100] The fault detection process will now be described. After the contact 53A of the relay 53 is switched from CLOSE to OPEN, the first FET 121 is CLOSE, the second FET 123 is OPEN, and the management device 150 detects the voltage at point B shown in FIG.

[0101] When the relay 53 is operating normally (when the contact 53A is open), the voltage at point B is lower than the voltage at the positive electrode of the battery pack 60 (the voltage at point A) by the voltage drop of the parasitic diode D2.

[0102] If there is an abnormality in relay 53 (if contact 53A is not open), the voltage at point B will be at the same potential as the voltage of the positive electrode of battery pack 60 (the voltage at point A). Therefore, a close failure of relay 53 (a failure in which it is stuck closed and does not open) can be detected based on the voltage at point B.

[0103] When it is confirmed that the relay 53 is normally opened, the relay 53 is CLOSE and the management device 150 detects the voltage at point B.

[0104] When the relay 53 is operating normally (when the contact 53A is closed), the voltage at point B has the same potential as the voltage at the positive electrode of the battery pack 60 (the voltage at point A).

[0105] If there is an abnormality in relay 53 (if contact 53A is not closed), the voltage at point B will be lower than the voltage of the positive electrode of battery pack 60 (the voltage at point A) by the voltage drop of parasitic diode D2. Therefore, an open fault (a fault in which relay 53 is stuck open and does not close) can be detected based on the voltage at point B.

[0106] In this way, it is possible to diagnose a fault in the relay 53 using the bypass circuit 120. Since the fault diagnosis of the relay 53 is performed using the bypass circuit 120, if the bypass circuit 120 is faulty or there is a possibility of a fault in the bypass circuit 120, the fault diagnosis may be avoided.

[0107] The bypass circuit 120 may have a failure when, for example, the FET protection operation is performed due to heat generation in the parasitic diodes D1 and D2.

[0108] <Embodiment 5> 15 is a block diagram of the battery 200. The battery 200 differs from the battery 50 of the first embodiment in that a current interruption device 210 is used instead of the relay 53.

[0109] The current interruption device 210 is composed of a first FET 211 and a second FET 213 that are connected back-to-back.

[0110] When the battery 200 is overcharged, the first FET 211 is closed and the second FET 123 is opened, so that the battery 200 can be discharged to the automobile 10 while the charging is limited by the parasitic diode D2.

[0111] When discharging through a path that passes through the parasitic diode D2, if the operating point P of the second FET 213 exceeds the IT judgment line F0, the management device 150 closes the second FET 213, thereby preventing failure of the second FET 213 due to heat generation by the parasitic diode D2.

[0112] Also, the first FET 211 may be the object to be protected. That is, when the battery 200 is charged via a path passing through the parasitic diode D1 by opening the first FET 211 and closing the second FET 123, if the operating point P of the first FET 211 exceeds the IT determination line F0, the first FET 211 is closed, thereby preventing the first FET 211 from failing due to heat generation by the parasitic diode D1.

[0113] <Other embodiments> The present invention is not limited to the embodiments described above and illustrated in the drawings, and the following embodiments, for example, are also included within the technical scope of the present invention.

[0114] (1) The cell (repeatedly chargeable and dischargeable storage cell) 62 is not limited to a lithium ion secondary battery cell, but may be another non-aqueous electrolyte secondary battery cell. The cells 62 are not limited to being connected in series and parallel, but may be connected in series or be a single cell. A capacitor may be used instead of the secondary battery cell. The secondary battery cell and the capacitor are examples of cells.

[0115] (2) In the above embodiment, the battery 50 is mounted on the automobile 10, but it may be mounted on a moving body other than a vehicle, such as a ship or an aircraft. In addition, the battery may be used for stationary purposes such as a power storage device for absorbing fluctuations in a distributed power generation system or a UPS (uninterruptible power supply).

[0116] (3) In the above embodiment, the relay 53 is disposed on the positive power line 57P, and the current sensor 55 is disposed on the negative power line 57N. The current sensor 55 may be disposed on the positive power line 57P, and the relay 53 may be disposed on the negative power line 57N. In addition, although a P-channel FET is used in the bypass circuit 120 in the above embodiment, an N-channel FET may be used.

[0117] (4) In the above-described first embodiment, when the operating point P of the second FET 123 exceeds the IT determination line F0, the process proceeds to S20, and the management device 150 simultaneously sends a switching signal from OPEN to CLOSE to the relay 53 and the second FET 123. If the second FET 123 can be closed before the contact 53A of the relay 53 is closed, it is not necessarily necessary to send the switching signal simultaneously. A switching signal may be sent to the relay 53, and then a switching signal may be sent to the second FET 123.

[0118] (5) In the above-described first embodiment, the IT condition of the second FET 123 is determined (S10), and the FET protection process (S20 to S40) is executed. The execution of the FET protection process (S20 to S40) may be determined based on another condition as long as it is based on the current I and the current flow time T of the second FET 123.

[0119] (6) In the above-described first embodiment, the IT condition of the second FET 123 is determined (S10), and the FET protection process (S20 to S40) is executed. The temperature condition of the second FET 123 may be determined (S10), and the FET protection process (S20 to S40) may be executed. In other words, the FET protection process (S20 to S40) may be executed when the temperature of the second FET 123 exceeds a threshold value. In this case, it is preferable to add a temperature sensor 125 to the bypass circuit 120 to measure the temperatures of the first FET 121 and the second FET 123 (FIG. 16). [Explanation of symbols]

[0120] 50 Battery (energy storage device) 53 Relay 55 Current Sensor 60 Battery pack 62 cells 120 Bypass Circuit 121 1st FET 123 2nd FET 150 Management device

Claims

1. A power storage device, comprising cells, a relay for interrupting the current of the cells, a bypass circuit connected in parallel with the relay, and a management device, wherein the bypass circuit includes two FETs connected back-to-back, and when the management device detects an abnormality in the cell, it opens the relay, closes one of the two FETs, opens the other, and enables discharging or charging of the cell through a path passing through the parasitic diode of the FET, and when discharging or charging through a path passing through the parasitic diode, if the current I and the energization time T of the FET reach predetermined conditions or if the temperature of the FET reaches predetermined conditions, the management device closes the relay and the other FET that is open, in the power storage device.

2. A power storage device, comprising cells, a relay for interrupting the current of the cells, a bypass circuit connected in parallel with the relay, and a management device, wherein the bypass circuit includes two FETs connected back-to-back, and when the management device detects an abnormality in the cell, it opens the relay, closes one of the two FETs, opens the other, and enables discharging or charging of the cell through a path passing through the parasitic diode of the FET, and when discharging or charging through a path passing through the parasitic diode, if the current I and the energization time T of the FET reach predetermined conditions or if the temperature of the FET reaches predetermined conditions, the relay remains open and the management device closes the other FET that is open, in the power storage device.

3. The power storage device according to claim 1 or claim 2, wherein the abnormality of the cell is overcharge or over-discharge, in the power storage device.

4. The power storage device for engine starting according to claim 1 or claim 2.

5. A power storage device, comprising cells, a current interruption device including a relay for interrupting the current of the cells and a bypass circuit connected in parallel with the relay, and a management device, wherein the bypass circuit included in the current interruption device includes two FETs connected back-to-back, and when the management device detects an abnormality in the cell, it opens the relay, closes one of the two FETs, opens the other, and enables discharging or charging of the cell through a path passing through the parasitic diode of the FET, When the management device discharges or charges through the path passing through the parasitic diode, when the current I and the energization time T of the FET reach predetermined conditions or when the temperature of the FET reaches predetermined conditions, the relay and the other FET that is open are closed, and the power storage device.

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