Electronic device and manufacturing method thereof

Abstract

To provide an electronic device using an oxide semiconductor as a wiring material.SOLUTION: An electronic device includes: a first lamination structure including a first oxide semiconductor layer having a polycrystalline structure, a first insulating layer and a first conducting layer overlapping the first oxide semiconductor layer via the first insulating layer; and a second lamination structure including a second oxide semiconductor layer consisting of the same layer as the first oxide semiconductor layer, the first insulating layer and a second conducting layer overlapping the second oxide semiconductor layer via the first insulating layer. The first oxide semiconductor layer includes a first portion, which is overlapping the first conducting layer, and a second portion which is not overlapping. The second oxide semiconductor layer includes a third portion, which is overlapping the second conducting layer, and a fourth portion which is not overlapping. An impurity element is contained in the second portion, and the impurity element is not contained in the first portion, the third portion and the fourth portion.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] One embodiment of the present invention relates to an electronic device and a manufacturing method thereof. In particular, one embodiment of the present invention relates to an electronic device including a semiconductor device using an oxide semiconductor and a manufacturing method thereof. [Background technology]

[0002] In recent years, development of semiconductor devices (e.g., thin film transistors) using oxide semiconductors containing metal oxides as active layers instead of inorganic semiconductors such as silicon has been progressing (e.g., Patent Documents 1 to 6). Semiconductor devices using oxide semiconductors can be formed with a simple structure and low-temperature process, similar to semiconductor devices using amorphous silicon as active layers. It is known that semiconductor devices using oxide semiconductors as active layers have higher field-effect mobility than semiconductor devices using amorphous silicon as active layers. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2021-141338 A [Patent Document 2] JP 2014-099601 A [Patent Document 3] Patent Publication No. 2021-153196 [Patent Document 4] JP 2018-006730 A [Patent Document 5] JP 2016-184771 A [Patent Document 6] Patent Publication No. 2021-108405 Summary of the Invention [Problem to be solved by the invention]

[0004] Since oxide semiconductors have light-transmitting properties, if they could be used as wiring materials by reducing their resistance, they would be extremely advantageous in improving the transmittance of array substrates (substrates on which multiple semiconductor devices are arranged in an array). However, it has been difficult to sufficiently reduce the resistivity of conventional oxide semiconductors, making them difficult to use as wiring materials.

[0005] An object of one embodiment of the present invention is to provide an electronic device using an oxide semiconductor as a wiring material. [Means for solving the problem]

[0006] An electronic device in one embodiment of the present invention includes a first stacked structure including a first oxide semiconductor layer having a polycrystalline structure, a first insulating layer on the first oxide semiconductor layer, and a first conductive layer overlapping with the first oxide semiconductor layer via the first insulating layer, and a second stacked structure including a second oxide semiconductor layer configured in the same layer as the first oxide semiconductor layer, the first insulating layer on the second oxide semiconductor layer, and a second conductive layer overlapping with the second oxide semiconductor layer via the first insulating layer and configured in the same layer as the first conductive layer, wherein the first oxide semiconductor layer includes a first portion overlapping with the first conductive layer and a second portion not overlapping with the first conductive layer, and the second oxide semiconductor layer includes a third portion overlapping with the second conductive layer and a fourth portion not overlapping with the second conductive layer, the second portion contains an impurity element, and the first portion, the third portion, and the fourth portion do not contain the impurity element.

[0007] An electronic device in one embodiment of the present invention includes a first stacked structure including a first oxide semiconductor layer having a polycrystalline structure, a first insulating layer on the first oxide semiconductor layer, and a first conductive layer overlapping with the first oxide semiconductor layer via the first insulating layer, and a second stacked structure including a second oxide semiconductor layer formed in the same layer as the first oxide semiconductor layer, the first insulating layer on the second oxide semiconductor layer, and a second conductive layer overlapping with the second oxide semiconductor layer via the first insulating layer and formed in the same layer as the first conductive layer, wherein the first oxide semiconductor layer includes a first portion overlapping with the first conductive layer and a second portion not overlapping with the first conductive layer, the second oxide semiconductor layer includes a third portion overlapping with the second conductive layer and a fourth portion not overlapping with the second conductive layer, the second portion, the third portion, and the fourth portion contain an impurity element, and the first portion does not contain the impurity element.

[0008] A method for manufacturing an electronic device in one embodiment of the present invention includes forming a first oxide semiconductor layer and a second oxide semiconductor layer having a polycrystalline structure on an insulating surface, forming a first insulating layer on the first oxide semiconductor layer and the second oxide semiconductor layer, forming a first conductive layer overlapping a portion of the first oxide semiconductor layer and a second conductive layer overlapping at least a portion of the second oxide semiconductor layer on the first insulating layer, forming a resist mask covering the second oxide semiconductor layer and the second conductive layer, performing ion implantation from above the first conductive layer and the resist mask, adding an impurity element to a portion of the first oxide semiconductor layer, removing the resist mask, and then forming an insulating layer containing hydrogen on the first conductive layer and the second conductive layer.

[0009] A method for manufacturing an electronic device in one embodiment of the present invention includes forming a first oxide semiconductor layer and a second oxide semiconductor layer having a polycrystalline structure on an insulating surface, forming a first insulating layer on the first oxide semiconductor layer and the second oxide semiconductor layer, forming a resist mask on the first insulating layer to overlap a portion of the first oxide semiconductor layer, performing ion implantation from above the resist mask to add an impurity element to the portion of the first oxide semiconductor layer and the second oxide semiconductor layer, removing the resist mask, forming a first conductive layer on the first insulating layer to overlap a portion of the first oxide semiconductor layer and a second conductive layer to overlap at least a portion of the second oxide semiconductor layer, and forming an insulating layer containing hydrogen on the first conductive layer and the second conductive layer.

[0010] A method for manufacturing an electronic device in one embodiment of the present invention includes forming a first oxide semiconductor layer and a second oxide semiconductor layer having a polycrystalline structure on an insulating surface, forming a first insulating layer on the first oxide semiconductor layer and the second oxide semiconductor layer, forming a resist mask on the first insulating layer to cover the first oxide semiconductor layer, performing ion implantation from above the resist mask to add an impurity element to the second oxide semiconductor layer, removing the resist mask, forming a first conductive layer overlapping a portion of the first oxide semiconductor layer and a second conductive layer overlapping at least a portion of the second oxide semiconductor layer on the first insulating layer, performing ion implantation from above the first conductive layer and the second conductive layer to add the impurity element to the portion of the first oxide semiconductor layer and the portion of the second oxide semiconductor layer, and forming an insulating layer containing hydrogen on the first conductive layer and the second conductive layer. [Brief description of the drawings]

[0011] [Figure 1] 1 is a plan view showing a configuration of a display device according to an embodiment of the present invention; [Diagram 2] 1 is a diagram showing a configuration of a pixel circuit in a display device according to an embodiment of the present invention; [Diagram 3] 1 is a plan view showing a pixel structure in a display device according to an embodiment of the present invention; [Figure 4] 1 is a cross-sectional view showing a structure of a pixel in a display device according to one embodiment of the present invention. [Diagram 5] 1 is a cross-sectional view showing a configuration of a semiconductor device used in a display device according to an embodiment of the present invention. [Figure 6] 1 is a plan view showing a configuration of a semiconductor device used in a display device according to an embodiment of the present invention; [Figure 7A] 1A and 1B are schematic diagrams illustrating a bonding state of Poly-OS included in a conductive portion of an oxide semiconductor layer. [Figure 7B] 1A and 1B are schematic diagrams illustrating a bonding state of Poly-OS included in a conductive portion of an oxide semiconductor layer. [Figure 7C] 1A and 1B are schematic diagrams illustrating a bonding state of Poly-OS included in a conductive portion of an oxide semiconductor layer. [Figure 8] 1 is a band diagram illustrating a band structure of a conductive portion of an oxide semiconductor layer. [Figure 9] 5 is a sequence diagram showing a manufacturing method of a semiconductor device used in the display device of the embodiment of the present invention. FIG. [Figure 10] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Figure 11] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Figure 12] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Figure 13] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Figure 14] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Figure 15] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Figure 16] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Figure 17]5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Figure 18] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Figure 19] 5A to 5C are cross-sectional views showing a manufacturing method of a display device according to one embodiment of the present invention. [Figure 20] 5A to 5C are cross-sectional views showing a manufacturing method of a display device according to one embodiment of the present invention. [Figure 21] 5A to 5C are cross-sectional views showing a manufacturing method of a display device according to one embodiment of the present invention. [Figure 22] 5A to 5C are cross-sectional views showing a manufacturing method of a display device according to one embodiment of the present invention. [Figure 23] 5A to 5C are cross-sectional views showing a manufacturing method of a display device according to one embodiment of the present invention. [Figure 24] 5A to 5C are cross-sectional views showing a manufacturing method of a display device according to one embodiment of the present invention. [Diagram 25] 5A to 5C are cross-sectional views showing a manufacturing method of a display device according to one embodiment of the present invention. [Figure 26] 5A to 5C are cross-sectional views showing a manufacturing method of a display device according to one embodiment of the present invention. [Figure 27] 5A to 5C are cross-sectional views showing a manufacturing method of a display device according to one embodiment of the present invention. [Figure 28] 5A to 5C are cross-sectional views showing a manufacturing method of a display device according to one embodiment of the present invention. [Figure 29] 5A to 5C are cross-sectional views showing a manufacturing method of a display device according to one embodiment of the present invention. [Diagram 30] 1 is a cross-sectional view showing a structure of a pixel in a display device according to one embodiment of the present invention. [Diagram 31] 1 is a cross-sectional view showing a configuration of a semiconductor device used in a display device according to an embodiment of the present invention. [Diagram 32] 5 is a sequence diagram showing a manufacturing method of a semiconductor device used in the display device of the embodiment of the present invention. FIG. [Diagram 33] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Diagram 34]5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Diagram 35] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Diagram 36] 5 is a sequence diagram showing a manufacturing method of a semiconductor device used in the display device of the embodiment of the present invention. FIG. [Figure 37] 5 is a sequence diagram showing a manufacturing method of a semiconductor device used in the display device of the embodiment of the present invention. FIG. [Figure 38] 1 is a diagram showing a configuration of a pixel circuit in a display device according to an embodiment of the present invention; [Figure 39] 1 is a cross-sectional view showing a structure of a pixel in a display device according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. A configuration that a person skilled in the art can easily come up with by appropriately modifying the configuration of the embodiment while maintaining the gist of the invention is naturally included in the scope of the present invention. In order to make the explanation clearer, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual form. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each figure, elements similar to those described above with respect to the previous figures may be given the same reference numerals, and detailed explanations may be omitted as appropriate.

[0013] In each embodiment, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "down". Thus, for convenience of explanation, the terms "up" or "down" are used in the explanation, but for example, the substrate and the oxide semiconductor layer may be arranged so that their vertical relationship is reversed from that shown in the figure. In the following explanation, for example, the expression "oxide semiconductor layer on a substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other members may be arranged between the substrate and the oxide semiconductor layer. The terms "up" or "down" refer to the order of stacking in a structure in which multiple layers are stacked, and when the expression "pixel electrode above a transistor" is used, the transistor and the pixel electrode may not overlap in a planar view. On the other hand, when the expression "pixel electrode vertically above a transistor" is used, the expression means that the transistor and the pixel electrode overlap in a planar view.

[0014] In each embodiment, multiple elements formed by processing a film such as etching may be described as elements having different functions or roles. These multiple elements are composed of the same layer structure and the same material, and are described as elements composed of the same layer.

[0015] In each embodiment, the terms "same" and "match" do not only refer to completely identical or completely matching, but also include a range that can be considered to be substantially identical or matching. For example, when certain numerical values ​​are identical, in addition to being completely identical, it also includes cases where the numerical values ​​differ within a range of ±5% (preferably ±3%).

[0016] In each embodiment, the expression "does not include impurity elements" includes not only cases where no impurity elements are included, but also cases where the concentration of the impurity elements is below the lower detection limit of an analysis device. Usually, impurity elements such as argon (Ar), phosphorus (P), or boron (B) are not included in an oxide semiconductor unless they are intentionally added. However, there may be cases where the above impurity elements are unintentionally mixed in during the formation of other films. Even in such cases, it may be considered that the impurity elements are not substantially included if the concentration is below the lower detection limit of the analysis device used.

[0017] In this specification, the term "electronic device" refers to a device that includes semiconductor elements such as transistors and performs electronic operations. For example, a display device and a semiconductor integrated device are included in the electronic device of this specification. A "display device" refers to a device that displays an image using an electro-optical layer. The "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. In addition, the term display device includes not only a display panel including an electro-optical layer, but also a device in which other optical members (e.g., a polarizing member or a backlight) are attached to the display panel. A "semiconductor integrated device" refers to a device that includes a circuit in which semiconductor elements are integrated. For example, a CPU (central processing unit), a storage device (memory), and an image sensor may be included in a semiconductor integrated device.

[0018] In each embodiment, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0019] (First embodiment) [Display device configuration] A display device 100 according to one embodiment of the present invention will be described. The display device 100 according to this embodiment is a liquid crystal display device having a liquid crystal layer as an electro-optical layer. The display device 100 is an example of an electronic device to which the present invention is applied.

[0020] Fig. 1 is a plan view showing a configuration of a display device 100 according to an embodiment of the present invention. As shown in Fig. 1, a display unit 110, a scanning side driving unit 120, and a terminal unit 130 are provided on the front side of a circuit board 100A of the display device 100.

[0021] The circuit board 100A is a substrate in which a plurality of semiconductor devices formed using oxide semiconductors are arranged on a light-transmitting support substrate. In this embodiment, an example in which thin film transistors are arranged as the semiconductor devices is shown, but the present invention is not limited to this example, and other semiconductor devices may be arranged as long as they function as switching elements. The circuit board 100A may also be called an active matrix substrate. A light-transmitting substrate may be used as the support substrate constituting the circuit board 100A. For example, it is preferable to use a glass substrate or a flexible resin substrate as the support substrate.

[0022] The display unit 110 is a part for controlling a plurality of pixels 112 that display an image. Specifically, the display unit 110 includes a plurality of scanning signal lines 114 extending in a D1 direction (row direction) and a plurality of video signal lines 116 extending in a D2 direction (column direction), and has pixels 112 including thin film transistors corresponding to each of the intersections of the plurality of scanning signal lines 114 and the plurality of video signal lines 116. In this embodiment, each pixel 112 is a sub-pixel corresponding to any one of the colors R (red), G (green), and B (blue). Therefore, in reality, the display unit 110 is configured to perform color display with one pixel (main pixel) including three pixels 112 corresponding to each of the colors RGB as a unit.

[0023] Here, a pixel circuit 200 for controlling the emission of each pixel 112 will be described with reference to Fig. 2. For convenience of explanation, a basic configuration using one semiconductor device (thin film transistor) and one storage capacitor will be described as an example, but the configuration of the pixel circuit 200 is not limited to this example.

[0024] Fig. 2 is a diagram showing a configuration of a pixel circuit 200 in a display device 100 according to one embodiment of the present invention. As shown in Fig. 2, the pixel circuit 200 includes a selection transistor 201, a capacitance element 202, and a liquid crystal element 203. As will be described later, the selection transistor 201 is a thin-film transistor including a channel portion formed of an oxide semiconductor layer.

[0025] The gate of the selection transistor 201 is connected to a scanning signal line 114, and the source of the selection transistor 201 is connected to a video signal line 116. A grayscale signal that determines the amount of light transmitted through the liquid crystal element 203 is supplied to the video signal line 116. A scanning signal for selecting a pixel to which a grayscale signal is to be written is supplied to the scanning signal line 114. The drain of the selection transistor 201 is connected to a capacitance element 202 and a liquid crystal element 203. Note that the source and drain of the selection transistor 201 may be switched depending on the magnitude relationship between the voltage applied to the video signal line 116 and the voltage accumulated in the capacitance element 202.

[0026] The capacitive element 202 is a capacitor that holds a voltage input from the video signal line 116 via the selection transistor 201. One electrode of the capacitive element 202 is connected to the drain of the selection transistor 201, and the other electrode is fixed to the ground potential. However, this is not limiting, and the other electrode may be fixed to another potential.

[0027] The liquid crystal element 203 is an electro-optical element having a structure in which a liquid crystal layer is provided between a pair of electrodes. Although the specific structure will be described later, the liquid crystal element 203 of this embodiment includes a pixel electrode connected to the drain of the selection transistor 201 and a common electrode connected to a common wiring 204, and the orientation of the liquid crystal molecules is controlled by an electric field formed between the pixel electrode and the common electrode.

[0028] The pixel circuit 200 described above is disposed in each pixel 112 of the display device 100. In other words, it can be said that the display unit 110 shown in FIG.

[0029] Returning to FIG. 1, the scanning side driving unit 120 is connected to the scanning signal line 114 and transmits a scanning signal to the scanning signal line 114. Specifically, the scanning signal is provided to the gate of the selection transistor 201 shown in FIG. 2 and is used for switching control of the selection transistor 201. In this embodiment, like the pixel circuits 200 included in the multiple pixels 112, the driving circuit constituting the scanning side driving unit 120 is also formed using thin film transistors, but it is also possible to substitute an IC chip or the like. Note that, in this embodiment, the circuit board 100A includes two scanning side driving units 120, but only one of them may be included.

[0030] The terminal section 130 is a portion for electrically connecting various wirings arranged on the circuit board 100A to the flexible printed circuit board 140. Specifically, the terminal section 130 is an assembly of a plurality of video signal lines 116, wirings (not shown) for supplying control signals to the scanning side driving section 120, and a plurality of terminals connected to the common wiring 204. The terminal section 130 is arranged outside the display section 110. Video signals and control signals supplied from the outside are supplied to the display section 110 and the scanning side driving section 120, respectively, via the terminal section 130.

[0031] A flexible printed circuit board 140 is connected to the terminal section 130. The flexible printed circuit board 140 is an interface board for connecting the circuit board 100A to an external control circuit (not shown). In this embodiment, a display control circuit 150 is mounted on the flexible printed circuit board 140. The display control circuit 150 is a signal processing circuit that performs signal processing of a video signal supplied to the display section 110 and various control signals supplied to the scanning side driving section 120. In this embodiment, the display control circuit 150 is mounted on the flexible printed circuit board 140 in the form of an IC chip.

[0032] The flexible printed circuit board 140 is a circuit board in which wiring is printed on a flexible substrate made of a resin material, and therefore can be bent. In this embodiment, the flexible printed circuit board 140 can be bent along the dashed dotted line 142 so that the flexible printed circuit board 140 and the back side of the circuit board 100A (the side on which the display unit 110 and the like are not formed) overlap with each other.

[0033] Fig. 3 is a plan view showing the structure of a pixel 112 in a display device 100 according to one embodiment of the present invention. Fig. 4 is a cross-sectional view showing the structure of a pixel 112 in a display device 100 according to one embodiment of the present invention. Specifically, Fig. 4 corresponds to a cross-sectional view of the pixel structure shown in Fig. 3 taken along line A-A'. For ease of explanation, the capacitive element 202 and the liquid crystal element 203 are omitted from Fig. 3.

[0034] 3 and 4, the scanning signal lines 114 and the video signal lines 116 are arranged to intersect with each other, and the selection transistors 201 are arranged corresponding to the intersections. In the selection transistors 201, the scanning signal lines 114 are arranged on an oxide semiconductor layer 544 functioning as an active layer via an insulating layer 550. A portion of the scanning signal line 114 that intersects with the oxide semiconductor layer 544 functions as a gate electrode. In other words, the selection transistors 201 include a stacked structure formed of the oxide semiconductor layer 544, the insulating layer 550, and the scanning signal line 114.

[0035] Furthermore, at the portion where the scanning signal line 114 and the video signal line 116 intersect, the scanning signal line 114 is disposed on a part of the video signal line 116 (hereinafter referred to as "intersection 116a") via the insulating layer 550. In other words, at the portion where the scanning signal line 114 and the video signal line 116 intersect, a laminated structure constituted by the intersection 116a, the insulating layer 550, and the scanning signal line 114 is formed.

[0036] In this embodiment, the video signal line 116 is formed in the same layer as the conductive portion 403b that functions as the source region or drain region of the selection transistor 201. Specifically, the video signal line 116 and the oxide semiconductor layer 544 that functions as the active layer of the selection transistor 201 are integrally formed. In other words, each of the multiple pixels 112 is connected by the video signal line 116 that is formed in the same layer as the active layer of the selection transistor 201.

[0037] In this embodiment, the resistivity of the oxide semiconductor layer that functions as the active layer (specifically, the conductive portion 403b) of the selection transistor 201 is lower than the resistivity of a conventional oxide semiconductor layer. Therefore, in this embodiment, the oxide semiconductor layer can be used as wiring (in this embodiment, the video signal line 116). The reason why the oxide semiconductor of this embodiment can be used as a wiring material will be described later.

[0038] In addition, in this embodiment, the configuration of the intersection 116a of the video signal line 116 is different from the configuration of the other parts. Specifically, the video signal line 116 basically has the same configuration as the conductive part 403b of the selection transistor 201, whereas the intersection 116a does not contain the impurity element contained in the conductive part 403b. This point will be described later.

[0039] Here, a specific structure of the pixel 112 will be described with reference to FIG. 4. As shown in FIG. 4, the selection transistor 201 is provided on a substrate 500. The substrate 500 is a light-transmitting substrate, and may be, for example, a glass substrate or a resin substrate. The insulating layer 520 is composed of a silicon oxide layer, a silicon nitride layer, or a stacked film of a silicon oxide layer and a silicon nitride layer. The insulating layer 520 serves to prevent impurities from entering from the substrate 500.

[0040] The selection transistor 201 of this embodiment includes an oxide semiconductor layer 544 made of an oxide semiconductor having a polycrystalline structure. As the oxide semiconductor, for example, a metal oxide containing two or more metals including indium (In) is used. In general, an oxide semiconductor has light-transmitting properties and is transparent to visible light. The oxide semiconductor layer 544 includes a channel portion 403a and a conductive portion 403b. The channel portion 403a functions as a channel of the selection transistor 201. The conductive portion 403b functions as a source or drain of the selection transistor 201.

[0041] In this embodiment, an example is shown in which a thin film transistor with a top gate structure is used as the selection transistor 201, but a thin film transistor with a dual gate structure having a gate electrode also below the oxide semiconductor layer 544 may be used. The gate electrode arranged below the oxide semiconductor layer 544 can block light from the substrate 500 side toward the channel portion 403a. Therefore, when the selection transistor 201 has a dual gate structure, there is an advantage that the leakage current due to light irradiation can be suppressed and the off current can be reduced. In addition, since gate voltages are applied to the channel portion 403a of the oxide semiconductor layer 544 from above and below, an increase in the on current is expected.

[0042] The intersection 116a shown in FIG. 3 is made of the same layer as the oxide semiconductor layer 544 constituting the selection transistor 201. That is, in this embodiment, the oxide semiconductor layer 544 and the intersection 116a are elements derived from the same oxide semiconductor layer. The intersection 116a is formed at the same time as the oxide semiconductor layer 544, but the method of reducing resistance is different from that of the conductive portion 403b. Specifically, the conductive portion 403b is made conductive in the process of adding an impurity element to the oxide semiconductor layer 544, whereas the intersection 116a is made conductive by a method such as hydrogenation without adding an impurity element. This point will be described later together with the manufacturing method of the selection transistor 201.

[0043] A planarization layer 610 made of a resin material is provided on the scanning signal line 114. The planarization layer 610 has a role of planarizing undulations on the substrate 500 caused by the formation of the selection transistor 201. A pixel electrode 620 is provided on the planarization layer 610. The pixel electrode 620 is made of a transparent conductive film containing a metal oxide such as ITO. The pixel electrode 620 is connected to the selection transistor 201 via a contact hole provided in the planarization layer 610.

[0044] An insulating layer 630 is provided on the pixel electrode 620. The insulating layer 630 is composed of a silicon oxide layer, a silicon nitride layer, or a laminated structure thereof. A common electrode 205 is provided on the insulating layer 630 so as to partially overlap the pixel electrode 620. The common electrode 205, like the pixel electrode 620, is composed of a transparent conductive film containing a metal oxide such as ITO.

[0045] In this embodiment, the common electrode 205 has a comb-like pattern. For example, the common electrode 205 has a pattern in which a linear electrode extending in the D1 direction in Fig. 1 is connected to a plurality of linear electrodes extending in the D2 direction. In the example shown in Fig. 4, three electrode patterns overlapping the pixel electrode 620 are shown, which correspond to cross sections of a plurality of linear electrodes extending in the D2 direction and are electrically connected to each other.

[0046] In this embodiment, a FFS (Fringe Field Switching) method is adopted in which a fringe field is formed between the pixel electrode 620 and the common electrode 205 to align the liquid crystal molecules of the liquid crystal layer 650. The FFS method is a well-known driving method for liquid crystal display devices, and therefore a description thereof will be omitted here. When forming the fringe field, a predetermined voltage (e.g., a ground voltage) is applied to the common electrode 205. In other words, the strength of the fringe field is controlled by the voltage applied to the pixel electrode 620. In this way, the common electrode 205 functions as an electrode for applying a voltage to the liquid crystal layer by being held at a constant voltage during the display period.

[0047] In this embodiment, an example of the FFS method of forming a fringe electric field between the pixel electrode 620 and the common electrode 205 has been described, but the present invention is not limited to this example, and for example, an IPS (In-Plane Switching) method may be adopted. In this case, both the pixel electrode and the common electrode are configured in a comb-like pattern, and the comb portions of the pixel electrode and the common electrode are arranged to face each other. In the case of the IPS method, a horizontal electric field is formed by the pixel electrode and the common electrode facing each other in the horizontal direction, and the orientation of the liquid crystal molecules is controlled by the horizontal electric field.

[0048] A substrate 700 and a color filter 710 are provided on the pixel electrode 620 and the common electrode 205 via a liquid crystal layer 650. In this embodiment, the substrate 700 and the color filter 710 are collectively referred to as a counter substrate 700A. The liquid crystal layer 650 is disposed between the circuit substrate 100A and the counter substrate 700A, which are bonded together by a sealant (not shown). Although not shown in FIG. 4, an alignment film is provided on the surfaces of the circuit substrate 100A and the counter substrate 700A that contact the liquid crystal layer 650. In this embodiment, only the color filter 710 is shown on the substrate 700, but a light-shielding film (so-called black matrix) may be provided as necessary.

[0049] As described above, in this embodiment, a semiconductor device (selection transistor 201) having an oxide semiconductor layer 544 as an active layer is disposed in each pixel 112, and the video signal line 116 (including the intersection 116a) is made of an oxide semiconductor layer that is the same layer as the active layer. In this case, the resistivity of the video signal line 116 in this embodiment at the portion overlapping with the scanning signal line 114 is low enough to function as a wiring. Therefore, when a signal is supplied to the video signal line 116, it is possible to suppress signal delays and the like caused by resistance components.

[0050] The oxide semiconductor layer 544 used in the selection transistor 201 of this embodiment has a polycrystalline structure and is extremely excellent in crystallinity. In addition, the conductive portion 403b of this embodiment, which is obtained by imparting conductivity to the oxide semiconductor layer 544, is characterized in that its resistance is significantly lower than that of conventional conductive portions. Specifically, the sheet resistance of the conductive portion 403b is 1000 Ω / sq. or less (preferably 500 Ω / sq. or less), which allows it to be used sufficiently as wiring. In the display device 100 of this embodiment, focusing on such physical properties of the oxide semiconductor layer 544, the video signal line 116 is formed of the same layer as the oxide semiconductor layer 544.

[0051] According to this embodiment, the video signal line 116 can be made of a light-transmitting material (specifically, the oxide semiconductor layer 544 made of a metal oxide). Moreover, since the video signal line 116 can be formed simultaneously with the oxide semiconductor layer 544 used in the selection transistor 201, it is possible to improve the aperture ratio of the display unit of the display device 100 with a simple structure.

[0052] The structure of the display unit 110 described above is realized by reducing the resistivity of the oxide semiconductor layer to a level at which it can be used as wiring. Specifically, it is realized by reducing the resistance of the conductive portion 403b of the selection transistor 201, which is a semiconductor device using an oxide semiconductor. Therefore, the configuration and manufacturing method of the semiconductor device (selection transistor 201 in FIG. 4) used in this embodiment will be described below.

[0053] [Configuration of semiconductor device] Fig. 5 is a cross-sectional view showing the configuration of a semiconductor device 10 used in a display device 100 according to one embodiment of the present invention. Fig. 6 is a plan view showing the configuration of a semiconductor device 10 used in a display device 100 according to one embodiment of the present invention. Fig. 5 corresponds to a cross-sectional view taken along the dashed dotted line shown in Fig. 6. Note that, although shown with slightly different dimensions for ease of explanation, the semiconductor device 10 shown in Fig. 5 and the selection transistor 201 shown in Fig. 4 have basically the same structure.

[0054] 5, the semiconductor device 10 is provided above a substrate 500. The semiconductor device 10 includes an insulating layer 520, an oxide semiconductor layer 544, an insulating layer 550, a gate electrode 564, an insulating layer 570, an insulating layer 580, a source electrode 591, and a drain electrode 593.

[0055] The insulating layer 520 is provided on the substrate 500. The oxide semiconductor layer 544 is provided on the insulating layer 520. The oxide semiconductor layer 544 is in contact with the insulating layer 520. Of the main surfaces of the oxide semiconductor layer 544, a surface in contact with the insulating layer 550 is referred to as an upper surface, and a surface in contact with the insulating layer 520 is referred to as a lower surface. A surface connecting the upper surface and the lower surface of the oxide semiconductor layer 544 is referred to as a side surface. The insulating layer 520 functions as a barrier layer that blocks impurities diffusing from the substrate 500 toward the oxide semiconductor layer 544.

[0056] The oxide semiconductor layer 544 has light transmitting properties. The oxide semiconductor layer 544 is divided into a source region 544S, a drain region 544D, and a channel region 544CH. The channel region 544CH is a region of the oxide semiconductor layer 544 vertically below the gate electrode 564 (i.e., a region overlapping with the gate electrode 564). The source region 544S is a region of the oxide semiconductor layer 544 that does not overlap with the gate electrode 564, and is closer to the source electrode 591 than the channel region 544CH. The drain region 544D is a region of the oxide semiconductor layer 544 that does not overlap with the gate electrode 564, and is closer to the drain electrode 593 than the channel region 544CH. The channel region 544CH corresponds to the channel portion 403a shown in FIG. 4, and the source region 544S and the drain region 544D correspond to the conductive portion 403b shown in FIG. 4.

[0057] The gate electrode 564 is made of a conductive layer and is arranged to overlap a part of the oxide semiconductor layer 544 via an insulating layer 550. The insulating layer 550 is made of, for example, a silicon oxide layer and is arranged in contact with the oxide semiconductor layer 544.

[0058] The insulating layer 570 and the insulating layer 580 are provided on the insulating layer 550 and the gate electrode 564, respectively. The insulating layer 570 and the insulating layer 580 are provided with contact holes 571 and 573 that reach the oxide semiconductor layer 544. The source electrode 591 contacts the source region 544S through the contact hole 571. The drain electrode 593 contacts the drain region 544D through the contact hole 573.

[0059] The oxide semiconductor layer 544 has a polycrystalline structure including a plurality of crystal grains. Although details will be described later, the oxide semiconductor layer 544 having a polycrystalline structure can be formed by using a polycrystalline oxide semiconductor (Poly-OS) technique. In the following description, an oxide semiconductor having a polycrystalline structure itself may be referred to as Poly-OS.

[0060] In this embodiment, the oxide semiconductor layer 544 contains two or more metals including indium, and the ratio of indium in the two or more metals is 50% or more. Metal elements other than indium include gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), and lanthanides. However, the present invention is not limited to this example, and the oxide semiconductor layer 544 may contain metal elements other than the above.

[0061] The source region 544S and the drain region 544D may contain elements other than the above metal elements. As will be described in detail later, the source region 544S and the drain region 544D have a lower resistivity than the channel region 544CH. Such a decrease in resistivity is achieved by adding an element such as argon (Ar), phosphorus (P), or boron (B) (hereinafter referred to as an "impurity element") to the oxide semiconductor layer 544.

[0062] The concentration of impurity elements contained in the source region 544S and the drain region 544D is 1×10 18 cm -3 More than 1×10 21 cm -3 The source region 544S and the drain region 544D are preferably 1×10 18 cm -3 More than 1×10 21 cm -3 When the impurity element is contained in the source region 544S and the drain region 544D, it is presumed that the impurity element is intentionally added by ion implantation or ion doping. 18 cm -3 Impurity elements other than argon (Ar), phosphorus (P), or boron (B) may be contained in the channel region 544CH at a concentration of less than 1×10. Note that if an impurity element is contained in the channel region 544CH, it will affect the characteristics of the semiconductor device 10. Therefore, the concentration of the impurity element contained in the channel region 544CH is set to 1×10 18 cm -3 Less than (more preferably 1 × 1016 cm -3 It is preferable that

[0063] The gate electrode 564 functions as a top gate of the semiconductor device 10. The insulating layer 550 functions as a gate insulating layer of the semiconductor device 10 and has a function of releasing oxygen by heat treatment in the manufacturing process. The insulating layers 570 and 580 insulate the gate electrode 564 from the source electrode 591 and the gate electrode 564 from the drain electrode 593, respectively. This makes it possible to reduce parasitic capacitances generated between the gate electrode 564 and the source electrode 591 and between the gate electrode 564 and the drain electrode 593.

[0064] As shown in FIG. 6, the gate wiring 565 extends in a first direction (D1 direction). A part of the gate wiring 565 branches out toward a second direction (D2 direction) and overlaps with the oxide semiconductor layer 544. The part of the gate wiring 565 that overlaps with the oxide semiconductor layer 544 functions as a gate electrode 564. The length of a region where the oxide semiconductor layer 544 and the gate electrode 564 overlap (i.e., a channel region 544CH) in the first direction (D1 direction) is a channel length (L), and the length of the region in the second direction (D2 direction) is a channel width (W). The gate wiring 565 shown in FIG. 6 corresponds to the scanning signal line 114 shown in FIG. 3 and FIG. 4. The gate electrode 564 shown in FIG. 5 corresponds to a part of the scanning signal line 114 shown in FIG. 3 and FIG. 4 that overlaps with the oxide semiconductor layer 544.

[0065] [Crystal structure of oxide semiconductor layer] The oxide semiconductor layer 544 of the present embodiment includes Poly-OS. In the following description, the oxide semiconductor layer 544 will be taken as an example, but the same description can be applied to the video signal line 116 (including the intersection 116a) which is made of the same layer as the oxide semiconductor layer 544.

[0066] The crystal grains contained in the Poly-OS observed from the top surface of the oxide semiconductor layer 544 (or from the thickness direction of the oxide semiconductor layer 544) have a crystal grain size of 0.1 μm or more, preferably 0.3 μm or more, and more preferably 0.5 μm or more. The crystal grain size of the crystal grains can be obtained by, for example, cross-sectional SEM observation, cross-sectional TEM observation, or an electron backscattered diffraction (EBSD) method.

[0067] In the Poly-OS, a plurality of crystal grains may have one type of crystal structure or a plurality of types of crystal structures. The crystal structure of the Poly-OS can be identified by electron beam diffraction, XRD, or the like. That is, the crystal structure of the oxide semiconductor layer 544 can be identified by electron beam diffraction, XRD, or the like.

[0068] The crystal structure of the oxide semiconductor layer 544 is preferably a cubic crystal. A cubic crystal has a high symmetry, and even if oxygen defects are generated in the oxide semiconductor layer 544, structural relaxation is unlikely to occur and the crystal structure is stable. As described above, the oxide semiconductor layer 544 contains two or more metals including indium, and the ratio of indium in the two or more metals is 50% or more. By increasing the ratio of indium element, the crystal structure of each of the multiple crystal grains is controlled, and the oxide semiconductor layer 544 having a cubic crystal structure can be formed.

[0069] As shown in FIG. 5, the oxide semiconductor layer 544 includes a channel portion 403a corresponding to the channel region 544CH, and a conductive portion 403b corresponding to the source region 544S and the drain region 544D. In the oxide semiconductor layer 544, the channel portion 403a has a first crystal structure, and the conductive portion 403b has a second crystal structure. The conductive portion 403b has a higher electrical conductivity than the channel portion 403a, but the second crystal structure is the same as the first crystal structure. Here, the two crystal structures being the same means that the crystal systems are the same. For example, when the crystal structure of the oxide semiconductor layer 544 is a cubic crystal, the first crystal structure of the channel portion 403a and the second crystal structure of the conductive portion 403b are both cubic crystals and are the same. The first crystal structure and the second crystal structure can be identified, for example, by using a microelectron beam diffraction method or the like.

[0070] In addition, in a given crystal orientation, the d-spacing value of the first crystal structure is substantially the same as the d-spacing value of the second crystal structure. Here, "substantially the same" refers to one d-spacing value being 0.95 to 1.05 times the other d-spacing value. Alternatively, this refers to two diffraction patterns that are almost identical in a microelectron beam diffraction method.

[0071] There may be no crystal grain boundary between the channel portion 403a and the conductive portion 403b. Also, the channel portion 403a and the conductive portion 403b may be included in one crystal grain. In other words, the change from the channel portion 403a to the conductive portion 403b may be a continuous change in crystal structure.

[0072] 7A to 7C are schematic diagrams illustrating a bonding state of Poly-OS included in the conductive portion 403b of the oxide semiconductor layer 544. 7A to 7C show Poly-OS including indium atoms (In atoms) and metal atoms (M atoms) different from In atoms.

[0073] In the Poly-OS shown in FIG. 7A, each of the In atom and the metal atom M is bonded to an oxygen atom (O atom). In the crystal structure of the Poly-OS shown in FIG. 7A, in the conductive portion 403b, in order to increase the electrical conductivity compared to the channel portion 403a, the bond between the In atom and the O atom (or the metal atom M and the O atom) is cut, and oxygen defects resulting from the removal of the O atom are generated (see FIG. 7B). Since the Poly-OS contains crystal grains with a large crystal grain size, the long-range order is easily maintained. Therefore, even if oxygen defects are generated, structural relaxation is unlikely to occur, and the positions of the In atom and the metal atom M are hardly changed. In the state shown in FIG. 7B, if hydrogen is present, the dangling bond of the In atom in the oxygen defect and the dangling bond of the metal atom M are bonded to the hydrogen atom (H atom) and stabilized (see FIG. 7C). Since the H atom in the oxygen defect functions as a donor, the carrier concentration of the conductive portion 403b increases.

[0074] 7C, in Poly-OS, even if an H atom is bonded in an oxygen defect, the positions of the In atom and the metal atom M hardly change. Therefore, the second crystal structure of the conductive portion 403b does not change from the crystal structure of Poly-OS without oxygen defects. That is, the second crystal structure of the conductive portion 403b is the same as the first crystal structure of the channel portion 403a.

[0075] FIG. 8 is a band diagram illustrating the band structure of the conductive portion 403b of the oxide semiconductor layer 544. In FIG.

[0076] As shown in FIG. 8, the poly-OS of the conductive portion 403b has a band gap E g The energy level includes a first energy level 1010 and a second energy level 1020. In addition, the energy level E C The first energy level 1010 includes a tail level 1030 adjacent to each of the first and second energy levels. gThe first energy level 1010 is a deep trap level present in the conduction band and is due to oxygen vacancies. The second energy level 1020 is a donor level present near the bottom of the conduction band and is due to hydrogen atoms bonded in the oxygen vacancies. The tail level 1030 is due to a disorder of the long-range order.

[0077] Although the Poly-OS in the conductive portion 403b contains oxygen defects, it has a crystalline structure and maintains long-range order. In addition, in the Poly-OS in the conductive portion 403b, hydrogen atoms can be bonded within the oxygen defects without causing structural disorder. Therefore, the DOS of the second energy level 1020 can be increased while suppressing the DOS of the tail level 1030. Therefore, the DOS of the second energy level 1020 is larger than the DOS of the tail level 1030 near the bottom of the conduction band, and the DOS of the second energy level 1020 is larger than the DOS of the energy level E C That is, the Fermi level E F is the energy level E at the bottom of the conduction band C , and the Poly-OS in the conductive portion 403b has metallic properties.

[0078] As described above, the Poly-OS in the conductive portion 403b has metallic properties, unlike conventional oxide semiconductors. Therefore, the conductive portion 403b can have a sufficiently low resistance by generating oxygen defects. The sheet resistance of the conductive portion 403b is 1000 Ω / sq. or less, preferably 500 Ω / sq. or less, and more preferably 250 Ω / sq.

[0079] In this manner, in this embodiment, since it is possible to sufficiently reduce the resistance of the source region 544S and the drain region 544D (i.e., the conductive portion 403b) of the oxide semiconductor layer 544, the conductive portion 403b can be used as wiring. The video signal line 116 shown in FIGS. 3 and 4 utilizes such a feature of the oxide semiconductor layer 544.

[0080] In this embodiment, a light-shielding layer may be provided between the substrate 500 and the oxide semiconductor layer 544. By providing the light-shielding layer in a region overlapping with the channel region 544CH, it is possible to suppress a characteristic change of the semiconductor device 10 caused by irradiation of the channel region 544CH with light. In this case, the light-shielding layer may be used as a gate electrode to give the semiconductor device 10 a dual-gate structure.

[0081] [Method of manufacturing semiconductor device] A method for manufacturing the semiconductor device 10 used in the display device 100 of one embodiment of the present invention will be described with reference to Fig. 9 to Fig. 18. Fig. 9 is a sequence diagram showing a method for manufacturing the semiconductor device 10 used in the display device 100 of one embodiment of the present invention. Figs. 10 to 18 are cross-sectional views showing a method for manufacturing the semiconductor device 10 used in the display device 100 of one embodiment of the present invention.

[0082] First, as shown in FIGS. 9 and 10, an insulating layer 520 is formed on a substrate 500 (step S1001).

[0083] A rigid substrate having light-transmitting properties, such as a glass substrate, a quartz substrate, or a sapphire substrate, is used as the substrate 500. When the substrate 500 needs to be flexible, a substrate containing a resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, is used as the substrate 500. When a substrate containing a resin is used as the substrate 500, an impurity element may be introduced into the resin in order to improve the heat resistance of the substrate 500.

[0084] The insulating layer 520 is formed by a chemical vapor deposition (CVD) method or a sputtering method. A general insulating material is used as the insulating layer 520. For example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum oxide (AlOx ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), and aluminum nitride (AlN x ) and other inorganic insulating materials are used.

[0085] The above SiO x N y and AlO x N y is a silicon and aluminum compound that contains a smaller proportion (x>y) of nitrogen (N) than oxygen (O). SiN x O y and AlN x O y are silicon and aluminum compounds that contain a smaller proportion of oxygen than nitrogen (x>y).

[0086] The insulating layer 520 is formed in a single layer structure or a laminated structure. When the insulating layer 520 has a laminated structure, it is preferable to provide an insulating material containing nitrogen near the substrate 500 and then form an insulating material containing oxygen. By using an insulating material containing nitrogen, for example, impurities diffusing from the substrate 500 side toward the oxide semiconductor layer 544 can be blocked. In addition, by using an insulating material containing oxygen, oxygen can be released by heat treatment. The temperature of the heat treatment at which the insulating material containing oxygen releases oxygen is, for example, 600° C. or less, 500° C. or less, 450° C. or less, or 400° C. or less. That is, the insulating material containing oxygen releases oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 10 when a glass substrate is used as the substrate 500. In this embodiment, for example, silicon nitride is used as the insulating material containing nitrogen. For example, silicon oxide is used as the insulating material containing oxygen.

[0087] 9 and 11, an oxide semiconductor layer 540 is formed on the insulating layer 520 (step S1002). The oxide semiconductor layer 540 is formed by sputtering or atomic layer deposition (ALD). The thickness of the oxide semiconductor layer 540 is, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 20 nm to 40 nm.

[0088] A metal oxide having semiconductor properties can be used as the oxide semiconductor layer 540. For example, an oxide semiconductor containing two or more metals including indium (In) is used as the oxide semiconductor layer 540. The ratio of indium in the two or more metals is 50% or more. In addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), or lanthanoids is used as the oxide semiconductor layer 540. Elements other than the above may be used as the oxide semiconductor layer 540. In this embodiment, a metal oxide (IGO-based oxide semiconductor) containing indium (In) and gallium (Ga) is used as the oxide semiconductor layer 540.

[0089] When the oxide semiconductor layer 540 is crystallized by OS annealing (step S1004) described later, the oxide semiconductor layer 540 after deposition and before OS annealing is preferably amorphous (a state in which the oxide semiconductor has few crystalline components). In other words, the oxide semiconductor layer 540 is preferably formed under conditions that prevent the oxide semiconductor layer 540 immediately after deposition from crystallizing as much as possible. For example, when the oxide semiconductor layer 540 is formed by a sputtering method, conditions that prevent the oxide semiconductor layer 540 from crystallizing can be realized by controlling the temperature of the object on which the oxide semiconductor layer 540 is to be formed (the substrate 500 and a structure formed thereon).

[0090] When a film is formed on a target object by sputtering, ions generated in the plasma and atoms recoiled from the sputtering target collide with the target object, and the temperature of the target object increases with the film formation process. If the temperature of the target object increases during the film formation process, the oxide semiconductor layer 540 contains microcrystals immediately after the film formation, and crystallization by the subsequent OS annealing is inhibited. In order to control the temperature of the target object as described above, for example, the target object can be cooled while the film is formed. For example, the target object can be cooled from the surface opposite to the surface to be formed so that the temperature of the surface to be formed of the target object (hereinafter referred to as the "film formation temperature") becomes 100°C or less, 70°C or less, 50°C or less, or 30°C or less. As described above, by forming the oxide semiconductor layer 540 while cooling the target object, the oxide semiconductor layer 540 having a small amount of crystalline components immediately after the film formation can be formed.

[0091] 9 and 12, a pattern of the oxide semiconductor layer 540 is formed by photolithography (step S1003). Although not shown in the drawings, a resist mask is formed on the oxide semiconductor layer 540, and the oxide semiconductor layer 540 is etched using the resist mask. Although not shown in the drawings, when the pattern of the oxide semiconductor layer 540 is formed, a pattern to be used as the video signal line 116 is also formed at the same time.

[0092] Either wet etching or dry etching may be used for etching the oxide semiconductor layer 540. In the case of wet etching, etching can be performed using an acidic etchant. As the etchant, for example, oxalic acid or hydrofluoric acid can be used.

[0093] The oxide semiconductor layer 540 is preferably patterned before the OS annealing performed in step S1004. If the oxide semiconductor layer 540 is crystallized by the OS annealing, it tends to be difficult to etch. Even if the oxide semiconductor layer 540 is damaged by etching, the damage can be repaired by the OS annealing.

[0094] After the oxide semiconductor layer 540 is patterned, a heat treatment (OS annealing) is performed on the oxide semiconductor layer 540 (step S1004). In the OS annealing, the oxide semiconductor layer 540 is held at a predetermined temperature for a predetermined time. The predetermined temperature is 300° C. or more and 500° C. or less, and preferably 350° C. or more and 450° C. or less. The holding time at the temperature is 15 minutes or more and 120 minutes or less, and preferably 30 minutes or more and 60 minutes or less. By performing the OS annealing, the oxide semiconductor layer 540 is crystallized, and an oxide semiconductor layer 544 having a polycrystalline structure is formed.

[0095] In manufacturing the display device 100 of this embodiment, a wiring pattern made of an oxide semiconductor layer to be used as the video signal line 116 is formed at the same time as forming the oxide semiconductor layer 544 of the selection transistor 201. Therefore, the wiring pattern formed in this process has the same crystal structure as the oxide semiconductor layer 544.

[0096] Next, as shown in FIGS. 9 and 13, an insulating layer 550 is formed on the oxide semiconductor layer 544 (Step S1005).

[0097] The description of the insulating layer 520 may be referred to for the method of forming the insulating layer 550 and the insulating material. In this embodiment, the thickness of the insulating layer 550 is, for example, not less than 50 nm and not more than 150 nm, but is not limited to this example.

[0098] It is preferable to use an insulating material containing oxygen for the insulating layer 550. It is also preferable to use an insulating layer with few defects for the insulating layer 550. For example, when the oxygen composition ratio in the insulating layer 550 is compared with the oxygen composition ratio in an insulating layer having the same composition as the insulating layer 550 (hereinafter referred to as "another insulating layer"), the oxygen composition ratio in the insulating layer 550 is closer to the stoichiometric ratio for the insulating layer than the oxygen composition ratio in the other insulating layer. For example, when silicon oxide (SiO x), the composition ratio of oxygen in the silicon oxide used as the insulating layer 550 is closer to the stoichiometric ratio of silicon oxide than the composition ratio of oxygen in the silicon oxide used as the insulating layer 580. For example, the insulating layer 550 may be a layer in which no defects are observed when evaluated by electron spin resonance (ESR).

[0099] In order to form an insulating layer with few defects as the insulating layer 550, the insulating layer 550 may be formed at a film formation temperature of 350° C. or higher. In addition, after forming the insulating layer 550, a process of implanting oxygen into a part of the insulating layer 550 may be performed. In this embodiment, in order to form an insulating layer with few defects as the insulating layer 550, a silicon oxide layer is formed at a film formation temperature of 350° C. or higher.

[0100] Next, as shown in FIGS. 9 and 13, a metal oxide layer 555 containing aluminum as a main component is formed on the insulating layer 550 (step S1006).

[0101] The metal oxide layer 555 is formed by a sputtering method. By forming the metal oxide layer 555, oxygen is implanted into the insulating layer 550. The metal oxide layer mainly composed of aluminum is, for example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), Aluminum Nitride (AlN x ) is used. "Aluminum-based metal oxide layer" means that the ratio of aluminum contained in metal oxide layer 555 is 1% or more of the entire metal oxide layer 555. The ratio of aluminum contained in metal oxide layer 555 may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide layer 555. The above ratio may be a mass ratio or a weight ratio.

[0102] The thickness of the metal oxide layer 555 is, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 555. Aluminum oxide has high barrier properties against gas. In this embodiment, aluminum oxide used as the metal oxide layer 555 suppresses outward diffusion of oxygen implanted into the insulating layer 550 during deposition of the metal oxide layer 555.

[0103] For example, when the metal oxide layer 555 is formed by a sputtering method, the process gas used in the sputtering remains in the film of the metal oxide layer 555. For example, when Ar is used as the process gas for the sputtering, Ar may remain in the film of the metal oxide layer 555. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the metal oxide layer 555.

[0104] The insulating layer 550 is formed on the oxide semiconductor layer 544, and the metal oxide layer 555 is formed on the insulating layer 550. In this state, a heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer 544 (step S1007).

[0105] During the process from when the oxide semiconductor layer 544 is formed until when the insulating layer 550 is formed on the oxide semiconductor layer 544, many oxygen defects are generated on the upper surface and side surfaces of the oxide semiconductor layer 544. By the above-mentioned oxidation annealing, oxygen released from the insulating layer 550 is supplied to the upper surface and side surfaces of the oxide semiconductor layer 544, and the oxygen defects inside the oxide semiconductor layer 544 are repaired.

[0106] In the above-described oxidation annealing, oxygen implanted into the insulating layer 550 is blocked by the metal oxide layer 555, and thus is prevented from being released into the atmosphere. Therefore, oxygen is efficiently supplied to the oxide semiconductor layer 544 by the oxidation annealing performed in step S1007, and oxygen defects in the oxide semiconductor layer 544 are repaired.

[0107] Next, as shown in FIG. 9 and FIG. 14, after the oxidation annealing, the metal oxide layer 555 is etched (removed) (step S1008). Either wet etching or dry etching may be used for etching the metal oxide layer 555. As an etchant for the wet etching, for example, diluted hydrofluoric acid (DHF) is used. By this etching, the metal oxide layer 555 formed on the entire surface of the insulating layer 550 is removed. In other words, the removal of the metal oxide layer 555 is performed without using a mask. In further other words, by the etching performed in step S1008, all of the metal oxide layer 555 in the region overlapping with the oxide semiconductor layer 544 formed in a certain pattern is removed at least in a plan view.

[0108] 9 and 15, a gate electrode 564 is formed on the insulating layer 550 (step S1009). The gate electrode 564 is formed by patterning a metal layer formed by sputtering or atomic layer deposition. As described above, the gate electrode 564 is formed so as to be in contact with the insulating layer 550 exposed by removing the metal oxide layer 555.

[0109] As described above, the gate electrode 564 corresponds to the scanning signal line 114 shown in Figures 3 and 4. Therefore, although not shown, when forming the gate electrode 564, a wiring pattern that functions as the scanning signal line 114 is also formed.

[0110] A common metal material is used as the material of the gate electrode 564. Examples of the metal material that can be used include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof. The gate electrode 564 may be made of the above materials in a single layer structure or a multilayer structure.

[0111] 9 and 16, with the gate electrode 564 formed, a source region 544S and a drain region 544D of the oxide semiconductor layer 544 are formed (step S1010). Specifically, an impurity element is implanted into the oxide semiconductor layer 544 through the insulating layer 550 by ion implantation or ion doping using the gate electrode 564 as a mask. In step S1010, an impurity element such as argon (Ar), phosphorus (P), or boron (B) is implanted into a part of the oxide semiconductor layer 544 that is not covered with the gate electrode 564.

[0112] In the region of the oxide semiconductor layer 544 into which the impurity element is implanted, oxygen vacancies are formed. Then, a donor level in which hydrogen is bonded to the oxygen vacancies is formed, and the resistance is reduced to such an extent that the oxide semiconductor layer 544 can function as a conductive layer. That is, as a result of implanting the impurity element into the oxide semiconductor layer 544 in step S1010, a conductive portion 403b (a source region 544S and a drain region 544D) is formed in the region not covered by the gate electrode 564. On the other hand, in the region of the oxide semiconductor layer 544 covered by the gate electrode 564, a channel portion 403a (a channel region 544CH) is formed. Since the gate electrode 564 functions as a mask, the impurity element is not implanted into the channel portion 403a. The resistivity of the conductive portion 403b is lower than that of the channel portion 403a.

[0113] In manufacturing the display device 100 of this embodiment, impurities are injected into the oxide semiconductor layer 544 and at the same time, impurities are also injected into the wiring pattern (the wiring pattern that functions as the video signal line 116) made of the oxide semiconductor layer. This impurity injection makes the wiring pattern into an oxide semiconductor layer having the same sheet resistance or electrical conductivity as the conductive portion 403b. That is, the video signal line 116 made of the oxide semiconductor layer is formed by the process shown in FIG.

[0114] However, if the above ion implantation is performed in a state where the scanning signal lines 114 are disposed on the wiring patterns that function as the video signal lines 116, the impurity element is not added to the wiring patterns that overlap with the scanning signal lines 114, and the resistance of the wiring patterns cannot be reduced. Therefore, in this embodiment, a part of the video signal lines 116 (the intersections 116a shown in FIGS. 3 and 4) is formed by a method different from the process for manufacturing the semiconductor device 10. This point will be described later.

[0115] In this embodiment, since the impurity element is implanted into the oxide semiconductor layer 544 through the insulating layer 550, the impurity element such as argon (Ar), phosphorus (P), boron (B) is contained not only in the source region 544S and the drain region 544D but also in the insulating layer 550. Furthermore, the insulating layer 520 located below the oxide semiconductor layer 544 or the insulating layer 550 also contains the impurity element such as argon (Ar), phosphorus (P), boron (B), etc.

[0116] Next, as shown in FIGS. 9 and 17, insulating layers 570 and 580 are formed on the insulating layer 550 and the gate electrode 564 (step S1011).

[0117] The description of the insulating layer 520 may be referred to for the method of forming the insulating layers 570 and 580 and the insulating material. The insulating layer 570 has a thickness of 50 nm or more and 500 nm or less. The insulating layer 580 has a thickness of 50 nm or more and 500 nm or less. In this embodiment, for example, a silicon nitride layer is formed as the insulating layer 570, and a silicon oxide layer is formed as the insulating layer 580. In this embodiment, the insulating layers 570 and 580 are formed by a plasma CVD method at a film formation temperature of 350° C. or more and 400° C. or less.

[0118] 9 and 18, contact holes 571 and 573 are formed in insulating layer 550, insulating layers 570 and 580 (step S1012). Source region 544S is exposed through contact hole 571, and drain region 544D is exposed through contact hole 573. After source region 544S and drain region 544D are exposed through contact holes 571 and 573, source electrode 591 and drain electrode 593 shown in FIG. 5 are formed (step S1013). Through the above processes, semiconductor device 10 shown in FIG. 5 is completed.

[0119] The source electrode 591 and the drain electrode 593 are formed by, for example, a sputtering method. The source electrode 591 and the drain electrode 593 can be formed by using a general metal material. As the metal material, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof can be used. The source electrode 591 and the drain electrode 593 may have a single-layer structure or a multilayer structure.

[0120] In the semiconductor device 10 manufactured by the above manufacturing method, when the channel length L of the channel region 544CH is in the range of 2 μm to 4 μm and the channel width of the channel region 544CH is in the range of 2 μm to 25 μm, the mobility is 30 cm 2 / Vs or more, 35cm 2 / Vs or more, or 40cm 2 In this embodiment, the field effect mobility means the field effect mobility in the saturation region of the semiconductor device 10, and refers to the maximum value of the field effect mobility in a region where the potential difference (Vd) between the source electrode and the drain electrode is greater than the voltage (Vg) supplied to the gate electrode minus the threshold voltage (Vth) of the semiconductor device 10 (Vg-Vth).

[0121] In the semiconductor device 10 of this embodiment, the resistivity of the conductive portion 403b constituting the source region 544S and the drain region 544D is sufficiently low. Therefore, it is possible to use an oxide semiconductor layer formed of the same layer as the conductive portion 403b as wiring (specifically, the video signal line 116). Since the oxide semiconductor has light transmissivity, if it is possible to use the oxide semiconductor as a wiring material as in this embodiment, it is very advantageous in improving the aperture ratio of the display unit 110 in the display device 100.

[0122] [Manufacturing method of pixel structure] As described above, if ion implantation of an impurity element is performed with the scanning signal lines 114 intersecting a wiring pattern made of an oxide semiconductor layer, the scanning signal lines 114 act as a mask and the impurity element is not added to the wiring pattern, so that it is not possible to reduce the resistance in a part (intersection) of the wiring pattern. Therefore, in this embodiment, the resistance of the intersection 116a of the video signal lines 116 is reduced by a method different from that for other parts. A method for manufacturing the pixel structure will be described below.

[0123] Figures 19 to 22 are cross-sectional views showing a manufacturing method of the display device 100 of one embodiment of the present invention. Specifically, all of Figures 19 to 22 correspond to cross-sectional views taken along line A-A' of the pixel structure shown in Figure 3. For ease of explanation, Figures 21 and 22 also show enlarged views of each layered structure.

[0124] First, the process is advanced to the state shown in FIG. 15 according to the sequence diagram shown in FIG. 9. As shown in FIG. 19, oxide semiconductor layers 544 and 544a are formed on an insulating layer 520. The oxide semiconductor layer 544 functions as an active layer of the semiconductor device 10. The oxide semiconductor layer 544a is formed in the same layer as the oxide semiconductor layer 544, and is a wiring pattern for use as the video signal line 116.

[0125] The scanning signal line 114 is formed on each of the oxide semiconductor layers 544 and 544a via an insulating layer 550. The scanning signal line 114 overlapping the oxide semiconductor layer 544 functions as a gate electrode of the semiconductor device 10. As shown in FIG. 3, the scanning signal line 114 overlapping the oxide semiconductor layer 544a simply intersects with the oxide semiconductor layer 544a.

[0126] Next, as shown in FIG. 20, a resist mask 566 is formed so as to cover the oxide semiconductor layer 544a. The resist mask 566 is arranged so as to prevent impurity elements from being added to the oxide semiconductor layer 544a in an ion implantation process described later. For this reason, it is desirable to form the resist mask 566 with a size that ensures a sufficient margin with respect to the size of the oxide semiconductor layer 544a. For example, as shown in FIG. 20, the resist mask 566 is arranged so as to cover an area that is a predetermined distance L away from an end (edge) of the oxide semiconductor layer 544a toward the outside.

[0127] 21, an impurity element is added to a part of the oxide semiconductor layer 544 by ion implantation. This process corresponds to S1010 in FIG. 9, and the conditions for ion implantation are the same as those of the process shown in FIG. 16. As described above, a channel portion 403a and a conductive portion 403b are formed in the oxide semiconductor layer 544 during the process of adding the impurity element. At this time, the impurity element is added to the oxide semiconductor layer 544 using the scanning signal line 114 (gate electrode) as a mask, so that the channel portion 403a and the conductive portion 403b are formed in a self-aligned manner.

[0128] Note that it is considered that in the insulating layer 550, the bond between silicon and hydrogen is broken during the process of adding the impurity element, and hydrogen is generated. The hydrogen generated in the insulating layer 550 is combined with oxygen vacancies in the oxide semiconductor layer 544 to form a shallow donor level. Therefore, it is considered that the resistance of the conductive portion 403b is reduced when the process illustrated in FIG. 21 is performed.

[0129] In the enlarged view shown in FIG. 21, the symbol "x" typically indicates a defect formed inside the film by the ion implantation process. As shown in FIG. 21, the defect is formed in a part of the insulating layer 520, a part of the oxide semiconductor layer 544 (conductive portion 403b), and a part of the insulating layer 550. Specifically, the defect is not formed in the part of the insulating layer 520, the oxide semiconductor layer 544, and the insulating layer 550 that overlaps with the scanning signal line 114, but is formed in the part that does not overlap with the scanning signal line 114. The defect is formed by the addition of an impurity element. In other words, it can be said that, in the laminated structure formed by the insulating layer 520, the oxide semiconductor layer 544, and the insulating layer 550, the impurity element is contained in each layer in the region that does not overlap with the scanning signal line 114 (i.e., the region where the defect exists), and the impurity element is not contained in each layer in the region that overlaps with the scanning signal line 114.

[0130] On the other hand, since the resist mask 566 is provided over the oxide semiconductor layer 544a, the oxide semiconductor layer 544a is not doped with an impurity element. Thus, the oxide semiconductor layer 544a is generally maintained in the same state as the channel portion 403a (having a higher resistivity than the conductive portion 403b) and does not contain an impurity element. In other words, it can be said that the stacked structure including the insulating layer 520, the oxide semiconductor layer 544a, and the insulating layer 550 does not contain an impurity element in any of the layers in the region overlapping with the scan signal line 114 and the region not overlapping with the scan signal line 114.

[0131] 21 is performed, the insulating layer 520 and the insulating layer 550 located within a predetermined range from the end of the oxide semiconductor layer 544a toward the outside do not contain impurity elements, whereas the insulating layer 520 and the insulating layer 550 located within a predetermined range from the end of the oxide semiconductor layer 544a toward the outside (inside the range separated by a predetermined distance L) contain impurity elements, which is a difference between the configurations of the two.

[0132] Next, as shown in FIG. 22, an insulating layer 570 is formed on the scanning signal line 114. As described above, in this embodiment, a silicon nitride layer is formed as the insulating layer 570. The insulating layer 570 is formed by a plasma CVD method at a film formation temperature of 350° C. or more and 400° C. or less. Usually, a silicon nitride layer formed by a plasma CVD method contains a large amount of hydrogen. In this embodiment, the hydrogen contained in the insulating layer 570 is used in a process for reducing the resistance of the oxide semiconductor layer 544a.

[0133] In the case of this embodiment, since the temperature during film formation is 350° C. or higher, hydrogen contained in the silicon nitride layer diffuses through insulating layer 520 and insulating layer 550. In the enlarged view shown in Fig. 22, the symbol "o" indicates hydrogen diffused from insulating layer 570, or hydrogen generated inside insulating layer 520 or insulating layer 550 by the ion implantation process and diffused.

[0134] 22, many defects (mainly silicon dangling bonds) indicated by "x" are formed in the insulating layers 520 and 550 around the oxide semiconductor layer 544, and the diffused hydrogen is trapped by combining with the defects. Therefore, most of the hydrogen diffused around the oxide semiconductor layer 544 does not reach the channel portion 403a, and the resistance of the channel portion 403a is not reduced due to hydrogenation.

[0135] On the other hand, since no defects are formed in the insulating layers 520 and 550 around the oxide semiconductor layer 544a, the diffused hydrogen reaches the entire oxide semiconductor layer 544a. As a result, oxygen vacancies inside the oxide semiconductor layer 544a are combined with the diffused hydrogen to form a shallow donor level. That is, the oxide semiconductor layer 544a is almost entirely hydrogenated and reduced in resistance. The oxide semiconductor layer 544a reduced in resistance in this process functions as the intersection 116a shown in FIG. 3. As described above, since the oxide semiconductor layer 544a is almost entirely hydrogenated, it can be said that the oxide semiconductor layer 544a (i.e., the intersection 116a) has the same resistivity in both the portion overlapping the scanning signal line 114 and the portion not overlapping the scanning signal line 114.

[0136] As described above, in this embodiment, when performing an ion implantation process for forming the conductive portion 403b, a resist mask is placed at the portion (corresponding to the intersection 116a) where the scanning signal line 114 and the video signal line 116 intersect. This makes it possible to sufficiently hydrogenate the portion of the wiring pattern (oxide semiconductor layer 544a) used as the video signal line 116 that overlaps with the scanning signal line 114, thereby realizing a reduction in resistance at the intersection 116a.

[0137] In this embodiment, the video signal line 116 is formed in the same layer as the oxide semiconductor layer 544 that functions as the active layer of the semiconductor device 10. Therefore, most of the video signal line 116 has the same resistivity as the conductive portion 403b that functions as the source region or drain region of the semiconductor device 10. However, in this embodiment, an intersection portion 116a is formed as a part of the video signal line 116 at a portion where the scanning signal line 114 and the video signal line 116 intersect. The intersection portion 116a is a portion where the oxide semiconductor layer is made to have a low resistance by hydrogenation, unlike the conductive portion 403b where the oxide semiconductor layer is made to have a low resistance by ion implantation. Therefore, the resistivity of the intersection portion 116a is lower than that of the channel portion 403a.

[0138] Second Embodiment In this embodiment, an example will be described in which the resistance of the portion of the video signal line 116 that intersects with the scanning signal line 114 is reduced by a method different from that of the first embodiment. In the following description, the same components as those in the first embodiment will be denoted by the same reference numerals in the drawings and will not be described again, and differences from the first embodiment will be described.

[0139] 23 to 25 are cross-sectional views showing a manufacturing method of the display device 100 of one embodiment of the present invention. In Fig. 23 to 25, the stacked structure on the left side corresponds to the stacked structure included in the selection transistor 201, and the stacked structure on the right side corresponds to the stacked structure included in the intersection of the scanning signal line 114 and the video signal line 116. For convenience of explanation, Fig. 24 and Fig. 25 also show enlarged views of each stacked structure.

[0140] First, the process is advanced to the state shown in FIG. 14 according to the sequence diagram shown in FIG. 9 of the first embodiment. As shown in FIG. 23, oxide semiconductor layers 544 and 544a are formed on an insulating layer 520. The oxide semiconductor layer 544 functions as an active layer of the selection transistor 201. The oxide semiconductor layer 544a is formed in the same layer as the oxide semiconductor layer 544, and is a wiring pattern for use as the video signal line 116.

[0141] Then, a resist mask 552 overlapping with the oxide semiconductor layer 544 is formed over the insulating layer 550. In this embodiment, the resist mask 552 is aligned and positioned so as to be located directly above a portion of the oxide semiconductor layer 544 that is to eventually function as the channel portion 403a.

[0142] Next, as shown in FIG. 24, an impurity element is added to a part of the oxide semiconductor layer 544 and the entire oxide semiconductor layer 544a by ion implantation. The conditions of the ion implantation are the same as those of the process shown in FIG. 16 described in the first embodiment. As described above, a channel portion 403a and a conductive portion 403b are formed in the oxide semiconductor layer 544 during the process of adding the impurity element. In the enlarged view of FIG. 24, the symbol "x" typically indicates a defect formed inside the film by the ion implantation process, as in the first embodiment.

[0143] On the other hand, since the resist mask 552 is not disposed on the oxide semiconductor layer 544a, the impurity element is added to the entire oxide semiconductor layer 544a. Therefore, the resistance of the oxide semiconductor layer 544a is reduced in the process of adding the impurity element. That is, in this embodiment, the entire video signal line 116 is made of an oxide semiconductor layer having the same configuration (for example, the same resistivity) as the conductive portion 403b. In addition, since the impurity element is added to the entire oxide semiconductor layer 544a, the impurity element is also contained in the insulating layers 520 and 550 around the oxide semiconductor layer 544a.

[0144] 25, the scanning signal line 114 is formed so as to overlap with the oxide semiconductor layers 544 and 544a. The scanning signal line 114 overlapping with the oxide semiconductor layer 544 is arranged to match the channel portion 403a. That is, the width of the scanning signal line 114 in the channel length direction is set to be equal to or slightly wider than the width of the channel portion 403a. By arranging the scanning signal line 114 in this manner, the scanning signal line 114 overlapping with the oxide semiconductor layer 544 can function as a gate electrode of the semiconductor device 10.

[0145] Thereafter, the insulating layer 570 is formed on the scanning signal line 114. As described above, in this embodiment, a silicon nitride layer is formed as the insulating layer 570. As in the first embodiment, hydrogen diffuses through the insulating layers 520 and 550 in the process of forming the insulating layer 570, but since many defects are formed in the insulating layers 520 and 550 around the oxide semiconductor layer 544, the diffused hydrogen is trapped. Therefore, most of the hydrogen diffused around the oxide semiconductor layer 544 does not reach the channel portion 403a, and the resistance of the channel portion 403a is not reduced due to hydrogenation.

[0146] As described above, in this embodiment, the resist mask 552 is used when forming the channel portion 403a and the conductive portion 403b in the oxide semiconductor layer 544 that is to be the active layer of the selection transistor 201. At that time, since the resist mask 552 is not disposed above the oxide semiconductor layer 544a that is the wiring pattern, the resistance of the entire oxide semiconductor layer 544a can be reduced by the ion implantation process.

[0147] 25, it can be said that in the stacked structure including the insulating layer 520, the oxide semiconductor layer 544, and the insulating layer 550, each layer in a region not overlapping with the scanning signal line 114 (i.e., a region where a defect exists) contains an impurity element, and each layer in a region overlapping with the scanning signal line 114 does not contain an impurity element. It can also be said that in the stacked structure including the insulating layer 520, the oxide semiconductor layer 544a, and the insulating layer 550, each layer in both a region overlapping with the scanning signal line 114 and a region not overlapping with the scanning signal line 114 contains an impurity element.

[0148] Third embodiment In this embodiment, an example will be described in which the resistance of the portion of the video signal line 116 that intersects with the scanning signal line 114 is reduced by a method different from that of the first embodiment. In the following description, the same components as those in the first embodiment will be denoted by the same reference numerals in the drawings and will not be described again, and differences from the first embodiment will be described.

[0149] 26 to 29 are cross-sectional views showing a manufacturing method of a display device 100 according to one embodiment of the present invention. In Fig. 26 to 29, the stacked structure on the left side corresponds to the stacked structure included in the selection transistor 201, and the stacked structure on the right side corresponds to the stacked structure included in the intersection of the scanning signal line 114 and the video signal line 116. For ease of explanation, Fig. 28 to 29 also show enlarged views of each stacked structure.

[0150] First, the process is advanced to the state shown in FIG. 14 according to the sequence diagram shown in FIG. 9 of the first embodiment. As shown in FIG. 26, oxide semiconductor layers 544 and 544a are formed on an insulating layer 520. The oxide semiconductor layer 544 functions as an active layer of the selection transistor 201. The oxide semiconductor layer 544a is formed in the same layer as the oxide semiconductor layer 544, and is a wiring pattern for use as the video signal line 116.

[0151] Then, a resist mask 553 overlapping with the oxide semiconductor layer 544 is formed on the insulating layer 550. In this embodiment, the resist mask 553 is arranged so as to cover the entire oxide semiconductor layer 544. However, this is not the only example, and the resist mask 553 may be arranged so as to cover a part of the oxide semiconductor layer 544. However, the width of the resist mask 553 in the channel length direction is set wider than the width of the portion that will eventually function as the channel portion 403a (i.e., the width of the scanning signal line 114).

[0152] Next, as shown in FIG. 27, an impurity element is added to the entire oxide semiconductor layer 544a by ion implantation. The conditions of the ion implantation are the same as those of the process shown in FIG. 16 described in the first embodiment. In the enlarged view of FIG. 27, the symbol "x" typically indicates a defect formed inside the film by the ion implantation process, as in the first embodiment. In the process shown in FIG. 27, the oxide semiconductor layer 544 is entirely covered with the resist mask 553, and therefore the impurity element is not added. That is, the oxide semiconductor layer 544 maintains a high resistivity state.

[0153] On the other hand, since the resist mask 552 is not disposed on the oxide semiconductor layer 544a, the impurity element is added to the entire oxide semiconductor layer 544a. Therefore, the resistance of the oxide semiconductor layer 544a is reduced in the process of adding the impurity element. That is, in this embodiment, the entire video signal line 116 is made of an oxide semiconductor layer having the same configuration (for example, the same resistivity) as the conductive portion 403b. In addition, since the impurity element is added to the entire oxide semiconductor layer 544a, the impurity element is also contained in the insulating layers 520 and 550 around the oxide semiconductor layer 544a.

[0154] Next, as shown in FIG. 28, the scanning signal line 114 is formed so as to overlap the oxide semiconductor layers 544 and 544a, and then the impurity element is added again by ion implantation. In this case, the conditions of the ion implantation may be the same as or different from those of the process shown in FIG. 27. By the process shown in FIG. 28, the channel portion 403a and the conductive portion 403b are formed in the oxide semiconductor layer 544. Since the impurity element is added to the oxide semiconductor layer 544 using the scanning signal line 114 (gate electrode) as a mask, the channel portion 403a and the conductive portion 403b are formed in a self-aligned manner. Note that the impurity element is also added to the oxide semiconductor layer 544a again, but since a sufficient amount of the impurity element has already been added during the first ion implantation, the resistivity of the oxide semiconductor layer 544a does not change significantly.

[0155] Next, as shown in FIG. 29, an insulating layer 570 is formed on the scanning signal line 114. In this embodiment, a silicon nitride layer is formed as the insulating layer 570. As in the first embodiment, hydrogen diffuses through the insulating layers 520 and 550 in the process of forming the insulating layer 570. However, since many defects are formed in the insulating layers 520 and 550 around the oxide semiconductor layer 544, the diffused hydrogen is trapped. Therefore, most of the hydrogen diffused around the oxide semiconductor layer 544 does not reach the channel portion 403a, and the resistance of the channel portion 403a is not reduced due to hydrogenation.

[0156] As described above, in this embodiment, an impurity element is added to the entire oxide semiconductor layer 544a, which is a wiring pattern, by ion implantation in advance to reduce the resistance of the entire oxide semiconductor layer 544a. Then, the channel portion 403a and the conductive portion 403b are formed in the oxide semiconductor layer 544, which is to be the active layer of the selection transistor 201, by using the scanning signal line 114 as a mask. According to this embodiment, the active layer of the selection transistor 201 can be formed in a self-aligned manner while the entire oxide semiconductor layer 544a is constituted by the conductive portion 403b.

[0157] Furthermore, according to this embodiment, the distribution of impurity elements in the stacked structure including the insulating layer 520, the oxide semiconductor layer 544, and the insulating layer 550, and the distribution of impurity elements in the stacked structure including the insulating layer 520, the oxide semiconductor layer 544a, and the insulating layer 550 are the same as those in the second embodiment.

[0158] Fourth embodiment In the first to third embodiments, an example has been described in which the resistance of the video signal line 116 overlapping the scanning signal line 114 is reduced in a laminated structure in which the scanning signal line 114 and the video signal line 116 cross each other. However, the configurations described in the first to third embodiments can be applied to any laminated structure in which a conductive layer made of an oxide semiconductor overlaps with another conductive layer. For example, the configurations described in the first to third embodiments can also be applied to the case of forming a capacitive element.

[0159] Fig. 30 is a cross-sectional view showing a structure of a pixel 112 in a display device 100 according to one embodiment of the present invention. Specifically, Fig. 30 shows a selection transistor 201 and a capacitance element 202 arranged in the pixel 112. Note that the same components as those in Fig. 4 of the first embodiment are denoted by the same reference numerals and will not be described.

[0160] In this embodiment, the lower electrode 202a of the capacitance element 202 can be formed, for example, using an oxide semiconductor layer configured as the same layer as the active layer (oxide semiconductor layer 544) of the selection transistor 201. In the example shown in FIG. 30, similarly to the first embodiment, an oxide semiconductor layer with low resistance due to hydrogenation is used as the lower electrode 202a. As the insulator of the capacitance element 202, for example, an insulating layer 550 can be used. The upper electrode 202b of the capacitance element 202 can be formed, for example, using a metal layer configured as the same layer as the gate electrode (scanning signal line 114) of the selection transistor 201.

[0161] In this embodiment, since the resistance of the oxide semiconductor layer located directly below the upper electrode 202b of the capacitance element 202 can be sufficiently reduced, it is possible to use the oxide semiconductor layer as the lower electrode 202a of the capacitance element 202. In this case, since the conductive portion 403b connecting the selection transistor 201 and the capacitance element 202 is transparent to visible light, there is an advantage that there is no need to worry about a decrease in the aperture ratio regardless of how the conductive portion 403b is arranged in the pixel 112.

[0162] Fifth embodiment In this embodiment, a semiconductor device 10a having a different configuration from the semiconductor device 10 shown in the first embodiment will be described.

[0163] The configuration of the semiconductor device 10a according to this embodiment is similar to that of the semiconductor device 10 of the first embodiment, but differs from the semiconductor device 10 of the first embodiment in that a metal oxide layer 530 is provided between an underlying insulating layer 520 and an oxide semiconductor layer 544. In the following description, the description of the same configuration as in the first embodiment will be omitted, and differences from the first embodiment will be mainly described.

[0164] 31 is a cross-sectional view showing a configuration of a semiconductor device 10a used in a display device 100 of one embodiment of the present invention. As shown in FIG. 31, the semiconductor device 10a includes an insulating layer 520, a metal oxide layer 530, an oxide semiconductor layer 544, an insulating layer 550, a gate electrode 564, an insulating layer 570, an insulating layer 580, a source electrode 591, and a drain electrode 593.

[0165] The metal oxide layer 530 is provided on the insulating layer 520. The metal oxide layer 530 is in contact with the insulating layer 520. The oxide semiconductor layer 544 is provided on the metal oxide layer 530. The lower surface of the oxide semiconductor layer 544 is in contact with the metal oxide layer 530. In this embodiment, an end of the metal oxide layer 530 and an end of the oxide semiconductor layer 544 are approximately aligned.

[0166] The metal oxide layer 530 is a layer containing a metal oxide mainly composed of aluminum, similar to the metal oxide layer 555 (see FIG. 13), and has a function as a gas barrier film that blocks gases such as oxygen and hydrogen. The metal oxide layer 530 can be made of the same material as the metal oxide layer 555, but may also be made of a different material.

[0167] 6, and therefore is not shown. However, in plan view, the planar pattern of the metal oxide layer 530 is substantially the same as the planar pattern of the oxide semiconductor layer 544. With reference to FIG. 31, the lower surface of the oxide semiconductor layer 544 is covered with the metal oxide layer 530. In particular, in this embodiment, the entire lower surface of the oxide semiconductor layer 544 is covered with the metal oxide layer 530.

[0168] A high-mobility semiconductor device 10a can be realized by setting the ratio of indium to 50% or more in the oxide semiconductor layer 544. On the other hand, in such an oxide semiconductor layer 544, oxygen contained in the oxide semiconductor layer 544 is easily reduced, and oxygen defects are easily formed in the oxide semiconductor layer 544.

[0169] In a top-gate structure such as the semiconductor device 10a, hydrogen is released from a layer (e.g., the insulating layer 520) provided on the substrate 500 side of the oxide semiconductor layer 544 during a heat treatment process in the manufacturing process. When hydrogen released from a lower layer reaches the oxide semiconductor layer 544, oxygen defects may occur in the oxide semiconductor layer 544. The occurrence of oxygen defects is more prominent as the pattern size of the oxide semiconductor layer 544 becomes larger. In order to suppress the occurrence of such oxygen defects, it is preferable to suppress the arrival of hydrogen at the lower surface of the oxide semiconductor layer 544.

[0170] The upper surface of the oxide semiconductor layer 544 is affected by a process (for example, a patterning process or an etching process) performed after the oxide semiconductor layer 544 is formed. On the other hand, the lower surface of the oxide semiconductor layer 544 is not affected as described above. Therefore, the number of oxygen defects formed on the upper surface of the oxide semiconductor layer 544 is greater than the number of oxygen defects formed on the lower surface of the oxide semiconductor layer 544. That is, the oxygen defects in the oxide semiconductor layer 544 are not uniformly distributed in the film thickness direction of the oxide semiconductor layer 544 but are non-uniformly distributed in the film thickness direction of the oxide semiconductor layer 544. Specifically, the number of oxygen defects in the oxide semiconductor layer 544 is smaller on the lower surface side of the oxide semiconductor layer 544 and is more on the upper surface side of the oxide semiconductor layer 544.

[0171] When an amount of oxygen necessary to repair the oxygen defects formed on the upper surface side of the oxide semiconductor layer 544 in which oxygen defects are distributed as described above is uniformly supplied to the oxide semiconductor layer 544, an excess of oxygen is supplied to the lower surface side of the oxide semiconductor layer 544. As a result, a defect level different from the oxygen defects is formed on the lower surface side due to the excess oxygen, which may cause a phenomenon such as a characteristic fluctuation in a reliability test or a decrease in field-effect mobility. Therefore, in order to suppress such a phenomenon, it is desirable to supply oxygen to the upper surface side of the oxide semiconductor layer 544 while suppressing the supply of oxygen to the lower surface side of the oxide semiconductor layer 544.

[0172] As described above, in the configuration and manufacturing method of the first embodiment, even if the initial characteristics of the semiconductor device are improved by the oxygen supply process to the oxide semiconductor layer, there is a risk that the characteristics may vary due to the reliability test. In other words, it can be said that there is a trade-off between the initial characteristics and the reliability test. However, according to the present embodiment, by disposing the metal oxide layer 530 on the lower surface of the oxide semiconductor layer 544, it is possible to obtain good initial characteristics and reliability tests for the semiconductor device 10a.

[0173] A method for manufacturing the semiconductor device 10a used in the display device 100 of one embodiment of the present invention will be described with reference to Fig. 32 to Fig. 35. Fig. 32 is a sequence diagram showing a method for manufacturing the semiconductor device 10a used in the display device 100 of one embodiment of the present invention. Figs. 33 to 35 are cross-sectional views showing a method for manufacturing the semiconductor device 10a used in the display device 100 of one embodiment of the present invention.

[0174] 32, an insulating layer 520 is formed on a substrate 500 (step S2001). For step S2001, refer to the description of step S1001 shown in FIGS. 9 and 10. In this embodiment, silicon nitride and silicon oxide are used as materials for the insulating layer 520. Silicon oxide is preferable in terms of reducing oxygen defects in the oxide semiconductor layer 544 because it releases oxygen by heat treatment.

[0175] 32 and 33, a metal oxide layer 530 and an oxide semiconductor layer 540 are formed on an insulating layer 520 (step S2002). The metal oxide layer 530 and the oxide semiconductor layer 540 are formed by a sputtering method or an atomic layer deposition method (ALD).

[0176] For the material of the metal oxide layer 530, the description of the material of the metal oxide layer 555 shown in FIG. 13 may be referred to. The film thickness of the metal oxide layer 530 is, for example, 1 nm to 100 nm, 1 nm to 50 nm, 1 nm to 30 nm, or 1 nm to 10 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 530. Aluminum oxide has high barrier properties against gas. In this embodiment, aluminum oxide used as the metal oxide layer 530 blocks hydrogen and oxygen released from the insulating layer 520 and prevents the released hydrogen and oxygen from reaching the oxide semiconductor layer 540.

[0177] The oxide semiconductor layer 540 has a thickness of, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 20 nm to 40 nm. In this embodiment, an oxide containing indium (In) and gallium (Ga) is used as the oxide semiconductor layer 540. The oxide semiconductor layer 540 is amorphous before OS annealing performed in step S2004 described later.

[0178] When the oxide semiconductor layer 540 is crystallized by OS annealing described later, the oxide semiconductor layer 540 is preferably amorphous (having a small amount of crystalline components in the oxide semiconductor) after deposition and before OS annealing. For a deposition method for making the oxide semiconductor layer 540 amorphous after deposition, the description of step S1002 in FIG. 9 may be referred to.

[0179] Next, as shown in FIG. 32 and FIG. 34, a pattern of the oxide semiconductor layer 540 is formed (step S2003). Although not shown, a resist mask is formed on the oxide semiconductor layer 540, and the oxide semiconductor layer 540 is etched using the resist mask. The oxide semiconductor layer 540 may be etched by either wet etching or dry etching. The wet etching can be performed using an acidic etchant. As the acidic etchant, for example, oxalic acid or hydrofluoric acid can be used.

[0180] 32, after the oxide semiconductor layer 540 is patterned, a heat treatment (OS annealing) is performed on the oxide semiconductor layer 540 (step S2004). In this embodiment, the oxide semiconductor layer 540 is crystallized by the OS annealing. The crystallized oxide semiconductor layer is referred to as an oxide semiconductor layer 544.

[0181] Next, as shown in FIG. 32 and FIG. 35, a pattern of the metal oxide layer 530 is formed (step S2005). The metal oxide layer 530 is etched using the crystallized oxide semiconductor layer 544 as a mask. Either wet etching or dry etching may be used for etching the metal oxide layer 530. As an etchant for wet etching, for example, diluted hydrofluoric acid (DHF) is used. The crystallized oxide semiconductor layer 544 has etching resistance to diluted hydrofluoric acid compared to the amorphous oxide semiconductor layer 540. Therefore, the metal oxide layer 530 can be etched in a self-aligned manner using the oxide semiconductor layer 544 as a mask. This makes it possible to omit a photolithography process.

[0182] The process shown in steps S2006 to S2014 in Fig. 32 is similar to steps S1005 to S1013 in Fig. 9, and therefore the following description will be omitted. By going through steps S2006 to S2014, the semiconductor device 10a shown in Fig. 31 can be formed.

[0183] In the semiconductor device 10a manufactured by the above manufacturing method, when the channel length L of the channel region 544CH is in the range of 2 μm to 4 μm and the channel width of the channel region 544CH is in the range of 2 μm to 25 μm, the mobility is 50 cm 2 / Vs or more, 55cm 2 / Vs or more, or 60cm 2 In this embodiment, the field effect mobility is defined in the same manner as in the first embodiment.

[0184] Sixth embodiment In this embodiment, a semiconductor device manufactured by a method different from that of the fifth embodiment will be described. The structure of the semiconductor device of this embodiment is the same as the semiconductor device 10a described in the second embodiment in appearance, and will therefore be referred to as the semiconductor device 10a in the following description. In this embodiment, the differences from the fifth embodiment will be described.

[0185] Fig. 36 is a sequence diagram showing a method for manufacturing a semiconductor device 10a used in a display device 100 according to an embodiment of the present invention. As shown in Fig. 36, in this embodiment, two steps, step S2007 and step S2009 shown in Fig. 32, are omitted. That is, in this embodiment, after the insulating layer 550 is formed, oxidation annealing (step S2008) is performed in this state. By the oxidation annealing, oxygen released from the insulating layer 550 is supplied to the oxide semiconductor layer 540, and oxygen defects contained in the oxide semiconductor layer 540 are repaired. The role of the metal oxide layer 530 in this case is the same as in the fifth embodiment, and therefore a description thereof will be omitted here.

[0186] In the semiconductor device 10a manufactured by the manufacturing method of this embodiment, when the channel length L of the channel region 544CH is in the range of 2 μm to 4 μm and the channel width of the channel region 544CH is in the range of 2 μm to 25 μm, the mobility is 30 cm 2 / Vs or more, 35cm 2 / Vs or more, or 40cm 2 In this embodiment, the field effect mobility is defined in the same manner as in the first embodiment.

[0187] Seventh embodiment In this embodiment, a semiconductor device manufactured by a method different from that of the first embodiment will be described. Since the structure of the semiconductor device of this embodiment is identical in appearance to the semiconductor device 10 described in the first embodiment, the semiconductor device will be referred to as the semiconductor device 10 in the following description. In this embodiment, the description will focus on the differences from the first embodiment.

[0188] Fig. 37 is a sequence diagram showing a manufacturing method of the semiconductor device 10 used in the display device 100 of one embodiment of the present invention. As shown in Fig. 37, in this embodiment, two processes, step S1006 and step S1008 shown in Fig. 9, are omitted. That is, in this embodiment, after the insulating layer 550 is formed, oxidation annealing (step S1007) is performed in this state. By the oxidation annealing, oxygen released from the insulating layer 550 is supplied to the oxide semiconductor layer 544, and oxygen defects contained in the oxide semiconductor layer 544 are repaired.

[0189] Eighth embodiment In the first embodiment, a liquid crystal display device is taken as an example of the display device 100, but in this embodiment, an example in which the present invention is applied to an organic EL display device is described. In this embodiment, configurations different from those in the first embodiment are described, and the same configurations are illustrated with the same reference numerals, and description thereof will be omitted.

[0190] Fig. 38 is a diagram showing a configuration of a pixel circuit 300 in a display device of one embodiment of the present invention. The pixel circuit 300 is a circuit for controlling light emission of each pixel 112 (see Fig. 1). In the example shown in Fig. 38, for convenience of explanation, a basic configuration using two semiconductor devices is illustrated, but the present invention is not limited to this example.

[0191] 38, a pixel circuit 300 of the present embodiment includes a driving transistor 301, a selection transistor 302, a storage capacitor 303, and a light-emitting element 304. The driving transistor 301 and the selection transistor 302 are configured of a semiconductor device using an oxide semiconductor layer (specifically, a thin film transistor).

[0192] The source of the driving transistor 301 is connected to an anode power line 311, and the drain of the driving transistor 301 is connected to one end (anode) of the light-emitting element 304. The other end (cathode) of the light-emitting element 304 is connected to a common wiring 312. That is, during the display period, the common wiring 312 functions as a cathode power line. A power supply voltage higher than that of the common wiring 312 is applied to the anode power line 311.

[0193] The gate of the selection transistor 302 is connected to the scanning signal line 114, and the source of the selection transistor 302 is connected to the video signal line 116. The drain of the selection transistor 302 is connected to the gate of the drive transistor 301. Note that the source and drain of the selection transistor 302 may be switched depending on the relationship between the voltage applied to the video signal line 116 and the voltage stored in the storage capacitor 303.

[0194] The storage capacitor 303 is connected to the gate and drain of the drive transistor 301 and the drain of the selection transistor 302. A gradation signal that determines the light emission intensity of the light emitting element 304 is supplied to the video signal line 116. A scanning signal for selecting a pixel to which the gradation signal is to be written is supplied to the scanning signal line 114.

[0195] In the pixel circuit 300 described above, a gray scale signal (gray scale voltage) input from the video signal line 116 via the selection transistor 302 is held in the holding capacitance 303. During a display period (light emitting period), a current according to the voltage held in the holding capacitance 303 flows from the anode power line 311 to the light emitting element 304 via the drive transistor 301. In this embodiment, the light emitting element 304 is an organic EL element. The light emitting element 304 emits light with a luminance according to the amount of current flowing between the anode electrode and the cathode electrode.

[0196] Fig. 39 is a cross-sectional view showing the structure of a pixel 112 in a display device of one embodiment of the present invention. As shown in Fig. 39, a driving transistor 301 is disposed on a substrate 500 on which an insulating layer 520 is provided. The driving transistor 301 of this embodiment includes an oxide semiconductor layer 544 having a polycrystalline structure. The basic structure of the driving transistor 301 is similar to the structure of the selection transistor 201 of the first embodiment, and therefore a detailed description thereof will be omitted.

[0197] On the insulating layer 520, there is provided a video signal line 116 (specifically, an intersection 116a) made of the same layer as the oxide semiconductor layer 544 of the driving transistor 301. The video signal line 116 of this embodiment is a wiring whose resistance is reduced by hydrogenating an oxide semiconductor layer in the same process as in the first embodiment.

[0198] The driving transistor 301 is provided with a pixel electrode 620 that functions as an anode electrode of the light-emitting element 304. In this embodiment, the pixel electrode 620 has a structure in which a transparent conductive film such as ITO and a metal layer such as silver are laminated. The end of the pixel electrode 620 is covered with a resin layer 810 called a bank or rib. An opening 815 provided in the resin layer 810 exposes a part of the surface of the pixel electrode 620. The outer shape of the surface of the pixel electrode 620 exposed by the opening 815 defines the light-emitting region of the light-emitting element 304.

[0199] A light-emitting layer 820 and a common electrode 830 are provided inside the opening 815. The common electrode 830 functions as a cathode electrode of the light-emitting element 304, and is disposed across a plurality of pixels 112. On the other hand, the pixel electrode 620 and the light-emitting layer 820 are provided individually for each pixel 112. Different materials are used for the light-emitting layer 820 depending on the display color of the pixel. Although only the light-emitting layer 820 is illustrated in FIG. 39, in addition to the light-emitting layer 820, functional layers such as a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer may be provided.

[0200] A sealing layer 840 is provided on the light emitting element 304. The sealing layer 840 may be made of a resin material, or may be made of a combination of a resin material and an inorganic material. The sealing layer 840 of this embodiment has a three-layer structure in which a resin layer is sandwiched between silicon nitride layers. A protective substrate 850 is provided on the sealing layer 840. As the protective substrate 850, a light-transmitting substrate such as a glass substrate can be used.

[0201] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Furthermore, those in which a person skilled in the art appropriately adds or removes components or modifies designs, or adds or omits steps or modifies conditions, based on the embodiments, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0202] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0203] 10, 10a...semiconductor device, 100...display device, 100A...circuit board, 110...display section, 112...pixel, 114...scanning signal line, 116...video signal line, 120...scanning side driving section, 130...terminal section, 140...flexible printed circuit board, 150...display control circuit, 200...pixel circuit, 201...selection transistor, 202...capacitance element, 203...liquid crystal element, 204...common wiring, 205...common electrode, 300...pixel circuit, 301...driving transistor, 302...selection transistor, 303...storage capacitance, 304...light emitting element, 311...anode power line, 312...common wiring (cathode power line), 403a...channel section, 403b...conductive section, 500...substrate, 520...insulating layer, 53 0...metal oxide layer, 540, 544, 544a...oxide semiconductor layer, 544CH...channel region, 544D...drain region, 544S...source region, 550...insulating layer, 555...metal oxide layer, 570...insulating layer, 571, 573...contact hole, 580...insulating layer, 591...source electrode, 593...drain electrode, 610...planarization layer, 620...pixel electrode, 630...insulating layer, 650...liquid crystal layer, 700...substrate, 700A...opposite substrate, 710...color filter, 810...resin layer, 815...opening, 820...light-emitting layer, 830...common electrode, 840...sealing layer, 850...protective substrate, 1010...first energy level, 1020...second energy level, 1030...tail level

Claims

1. A first stacked structure including a first oxide semiconductor layer, a first insulating layer on the first oxide semiconductor layer, and a first conductive layer overlapping the first oxide semiconductor layer via the first insulating layer; a second stacked structure including a second oxide semiconductor layer formed of the same layer as the first oxide semiconductor layer, the first insulating layer on the second oxide semiconductor layer, and a second conductive layer overlapping the second oxide semiconductor layer via the first insulating layer and formed of the same layer as the first conductive layer; Including, the first oxide semiconductor layer includes a first portion overlapping with the first conductive layer and a second portion not overlapping with the first conductive layer; the second oxide semiconductor layer includes a third portion overlapping with the second conductive layer and a fourth portion not overlapping with the second conductive layer; the second portion includes an impurity element; the first portion, the third portion, and the fourth portion do not contain the impurity element.

2. the first insulating layer located within a predetermined range extending outward from an end of the first oxide semiconductor layer in a plan view contains the impurity element; The electronic device according to claim 1 , wherein the first insulating layer located within the predetermined range extending outward from an end of the second oxide semiconductor layer in a plan view does not contain the impurity element.

3. the resistivity of the second portion is lower than the resistivity of the first portion; The electronic device of claim 1 , wherein the resistivity of the third portion is lower than the resistivity of the first portion.

4. The electronic device of claim 3 , wherein the resistivity of the third portion is the same as the resistivity of the fourth portion.

5. the first insulating layer includes a fifth portion overlapping the first conductive layer, a sixth portion overlapping the first oxide semiconductor layer without overlapping the first conductive layer, and a seventh portion overlapping the second oxide semiconductor layer; the sixth portion includes an impurity element, The electronic device according to claim 1 , wherein the fifth portion and the seventh portion do not contain the impurity element.

6. the first oxide semiconductor layer and the second oxide semiconductor layer are provided on a second insulating layer; 2. The electronic device according to claim 1, wherein in the second insulating layer, an eighth portion overlapping with the first conductive layer and the first oxide semiconductor layer does not contain the impurity element, a ninth portion overlapping with the first oxide semiconductor layer but not with the first conductive layer contains the impurity element, and a tenth portion overlapping with the second oxide semiconductor layer does not contain the impurity element.

7. A first stacked structure including a first oxide semiconductor layer, a first insulating layer on the first oxide semiconductor layer, and a first conductive layer overlapping the first oxide semiconductor layer via the first insulating layer; a second stacked structure including a second oxide semiconductor layer formed of the same layer as the first oxide semiconductor layer, the first insulating layer on the second oxide semiconductor layer, and a second conductive layer overlapping the second oxide semiconductor layer via the first insulating layer and formed of the same layer as the first conductive layer; Including, the first oxide semiconductor layer includes a first portion overlapping with the first conductive layer and a second portion not overlapping with the first conductive layer; the second oxide semiconductor layer includes a third portion overlapping with the second conductive layer and a fourth portion not overlapping with the second conductive layer; the second portion, the third portion, and the fourth portion contain an impurity element; The first portion does not contain the impurity element.

8. the resistivity of the second portion is lower than the resistivity of the first portion; The electronic device of claim 7 , wherein the resistivity of the third portion and the fourth portion is the same as the resistivity of the second portion.

9. the first insulating layer includes a fifth portion overlapping the first conductive layer, a sixth portion overlapping the first oxide semiconductor layer without overlapping the first conductive layer, and a seventh portion overlapping the second oxide semiconductor layer; the sixth portion and the seventh portion contain an impurity element, The electronic device according to claim 7 , wherein the fifth portion does not contain the impurity element.

10. the first oxide semiconductor layer and the second oxide semiconductor layer are provided on a second insulating layer; 8. The electronic device according to claim 7, wherein in the second insulating layer, an eighth portion overlapping with the first conductive layer and the first oxide semiconductor layer does not contain the impurity element, a ninth portion overlapping with the first oxide semiconductor layer but not with the first conductive layer contains the impurity element, and a tenth portion overlapping with the second oxide semiconductor layer contains the impurity element.

11. 11. The electronic device according to claim 1, wherein the second portion has a sheet resistance of 500 Ω / sq. or less.

12. the first stacked structure is a thin film transistor, The electronic device according to claim 1 , wherein the second stacked structure is an intersection of wirings or a capacitor element.

13. forming a first oxide semiconductor layer and a second oxide semiconductor layer on an insulating surface; forming a first insulating layer on the first oxide semiconductor layer and the second oxide semiconductor layer; forming a first conductive layer overlapping a portion of the first oxide semiconductor layer and a second conductive layer overlapping at least a portion of the second oxide semiconductor layer on the first insulating layer; forming a resist mask covering the second oxide semiconductor layer and the second conductive layer; performing ion implantation from above the first conductive layer and the resist mask to add an impurity element to a part of the first oxide semiconductor layer; a step of forming an insulating layer containing hydrogen on the first conductive layer and the second conductive layer after removing the resist mask;

14. The method for manufacturing an electronic device according to claim 13 , wherein the second oxide semiconductor layer is not doped with the impurity element.

15. The method for manufacturing an electronic device according to claim 13 , wherein the insulating layer is formed at a temperature of 350° C. or higher and 400° C. or lower.

16. forming a first oxide semiconductor layer and a second oxide semiconductor layer on an insulating surface; forming a first insulating layer on the first oxide semiconductor layer and the second oxide semiconductor layer; forming a resist mask on the first insulating layer so as to overlap a portion of the first oxide semiconductor layer; ion implantation is performed from above the resist mask to add an impurity element to a part of the first oxide semiconductor layer and the second oxide semiconductor layer; After removing the resist mask, a first conductive layer overlapping a portion of the first oxide semiconductor layer and a second conductive layer overlapping at least a portion of the second oxide semiconductor layer are formed on the first insulating layer; forming an insulating layer containing hydrogen on the first conductive layer and the second conductive layer.

17. The method for manufacturing an electronic device according to claim 16 , wherein the first conductive layer is formed in the same position as the position where the resist mask is formed.

18. forming a first oxide semiconductor layer and a second oxide semiconductor layer on an insulating surface; forming a first insulating layer on the first oxide semiconductor layer and the second oxide semiconductor layer; forming a resist mask on the first insulating layer to cover the first oxide semiconductor layer; an ion implantation from above the resist mask to add an impurity element to the second oxide semiconductor layer; After removing the resist mask, a first conductive layer overlapping a portion of the first oxide semiconductor layer and a second conductive layer overlapping at least a portion of the second oxide semiconductor layer are formed on the first insulating layer; performing ion implantation from above the first conductive layer and the second conductive layer to add the impurity element to a part of the first oxide semiconductor layer and a part of the second oxide semiconductor layer; forming an insulating layer containing hydrogen on the first conductive layer and the second conductive layer.

19. The method for manufacturing an electronic device according to claim 18 , wherein, in a cross-sectional view, the width of the resist mask in the channel length direction is wider than the width of the first conductive layer.

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