Memory system

Abstract

To provide a memory system which improves a processing performance.SOLUTION: In a data processing device, a memory system includes: a plurality of memory chips CP each including a first memory region PU0 and a second memory region PU1; and a memory controller which independently controls a first group including the plurality of first memory regions included in each of the plurality of memory chips, and a second group including the plurality of second memory regions included in each of the plurality of memory chips with each other, configures a data group which includes write data of a plurality of pages, and first data including an erasure correction code corresponding to the write data of the plurality of pages, distributes the write data of the plurality of pages of the data group and the first data, to the plurality of first memory regions of the first group, and writes the distributed write data and first data at different timings.SELECTED DRAWING: Figure 13

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present invention generally relate to memory systems. [Background technology]

[0002] 2. Description of the Related Art Memory systems such as solid state drives (SSDs) incorporating NAND flash memories are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6753746 [Patent Document 2] JP 2023-42992 A Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment of the present invention provides a memory system that allows for increased processing power. [Means for solving the problem]

[0005] The memory system according to the embodiment includes a memory controller configured to independently control a plurality of memory chips, each including a first memory area and a second memory area, a first group including a plurality of first memory areas included in each of the plurality of memory chips, and a second group including a plurality of second memory areas included in each of the plurality of memory chips, to configure a data group including a plurality of pages of write data and first data including an erasure correction code corresponding to the plurality of pages of write data, and to distribute the plurality of pages of write data and the first data of the data group to a plurality of first memory areas of the first group and write them at different timings. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram showing the overall configuration of a data processing device including a memory system according to a first embodiment. [Diagram 2] 1 is a block diagram showing a basic configuration of a memory chip included in a memory system according to a first embodiment. [Diagram 3] 1 is a circuit diagram of a memory cell array included in a memory system according to a first embodiment. [Figure 4] 2 is a diagram showing the configuration of a memory area of ​​a memory chip included in the memory system according to the first embodiment. [Diagram 5] 4 is a diagram showing a specific example of the operation of a memory chip included in the memory system according to the first embodiment. [Figure 6] 2 is a diagram showing the configuration of a memory area of ​​a memory unit included in the memory system according to the first embodiment. [Figure 7] 4 is a diagram showing a specific example of the operation of a memory unit included in the memory system according to the first embodiment. [Figure 8] FIG. 2 is a block diagram showing the configuration of a write control unit included in the memory system according to the first embodiment. [Figure 9] 2 is a block diagram showing the configuration of a read control unit included in the memory system according to the first embodiment. [Figure 10] 2 is a block diagram showing the configuration of a write buffer included in the memory system according to the first embodiment. [Figure 11] 5 is a flowchart of a write operation in the memory system according to the first embodiment. [Figure 12] 5 is a flowchart of a write operation in the memory system according to the first embodiment. [Figure 13] 4A and 4B are diagrams showing a specific example of a write operation in the memory system according to the first embodiment. [Figure 14] 5 is a flowchart of a read operation in the memory system according to the first embodiment. [Figure 15] 4 is a diagram showing a specific example of a read operation in the memory system according to the first embodiment. [Figure 16]10A and 10B are diagrams showing a specific example of a read operation in the memory system according to the first modification of the first embodiment; [Figure 17] FIG. 11 is a diagram showing a specific example of a read operation in the memory system according to the second modification of the first embodiment. [Figure 18] 13 is a flowchart of a write operation in a memory system according to a third modification of the first embodiment. [Figure 19] 13 is a flowchart of a write operation in a memory system according to a third modification of the first embodiment. [Figure 20] 13A to 13C are diagrams showing specific examples of write and read operations in a memory system according to a third modification of the first embodiment. [Figure 21] 13 is a flowchart of a read operation in a memory system according to a first example of the second embodiment. [Figure 22] 13 is a diagram showing a specific example of a read operation in the memory system according to the first example of the second embodiment; [Figure 23] 13 is a flowchart of a read operation in a memory system according to a second example of the second embodiment. [Figure 24] 13 is a flowchart of a read operation in a memory system according to a third example of the second embodiment. [Diagram 25] 13 is a flowchart of a read operation in a memory system according to a fourth example of the second embodiment. [Figure 26] FIG. 13 is a block diagram showing a configuration of a read control unit in a memory system according to a fifth example of the second embodiment. [Figure 27] 13 is a flowchart of a read operation in a memory system according to a fifth example of the second embodiment. [Figure 28] 13 is a flowchart of a read operation in a memory system according to a sixth example of the second embodiment. [Figure 29] 13 is a flowchart of a read operation in a memory system according to a sixth example of the second embodiment. [Diagram 30] 13 is a flowchart of a garbage collection read operation in a memory system according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment will be described with reference to the drawings. The drawings are schematic. In the following description, components having substantially the same functions and configurations are given the same reference numerals. Numbers following the letters constituting the reference numerals are used to distinguish between elements having similar configurations.

[0008] A memory system according to an embodiment will be described below.

[0009] 1. First embodiment 1.1 Configuration 1.1.1 Data Processing Device Configuration First, an example of the configuration of a data processing device 1 having a memory system will be described with reference to Fig. 1. Fig. 1 is a block diagram showing an example of the overall configuration of the data processing device 1.

[0010] 1, a data processing device 1 includes a host device 2 and a memory system 3. Note that the host device 2 may be connected to a plurality of memory systems 3.

[0011] The host device 2 is an information processing device (computing device) that accesses the memory system 3. The host device 2 controls the memory system 3. More specifically, for example, the host device 2 requests (commands) the memory system 3 to perform a data write operation or a data read operation. That is, the host device 2 transmits a write request or a read request to the memory system 3. For example, a write request includes a command, an address, and user data. A read request includes a command and an address.

[0012] The memory system 3 is, for example, a solid state drive (SSD) equipped with a non-volatile memory. The memory system 3 is connected to the host device 2 via a host bus HB. CXL (Compute Express Link) (registered trademark) may be applied as a connection standard for interconnecting the memory system 3 and the host device 2. The connection standard is not limited to CXL. For example, the connection standard may be PCIe (Peripheral Component Interconnect-Express) (registered trademark). The memory system 3 may be connected to the host device 2 via a network or wireless communication.

[0013] 1.1.2 Memory System Configuration Continuing with reference to FIG. 1, an example of the configuration of the memory system 3 will be described.

[0014] As shown in FIG. 1, the memory system 3 includes a non-volatile memory 10 and a memory controller 20.

[0015] The nonvolatile memory 10 is a nonvolatile memory. The nonvolatile memory 10 includes a plurality of memory chips CP (also simply referred to as "chips"). The number of memory chips CP included in the nonvolatile memory 10 is arbitrary.

[0016] The memory chip CP is, for example, a NAND type flash memory. The memory chip CP can store data in a non-volatile manner. The memory chips CP can operate independently of each other. The memory chips CP are connected to the memory controller 20 via a NAND bus NB. The number of NAND buses NB and the number of memory chips CP connected to one NAND bus NB are arbitrary. In the example of FIG. 1, four NAND buses NB0 to NB3 are provided. Four memory chips CP are connected to each NAND bus NB. More specifically, the memory chips CP0_0, CP0_1, CP0_2, and CP0_3 are connected to the memory controller 20 via a NAND bus NB0. The memory chips CP1_0, CP1_1, CP1_2, and CP1_3 are connected to the memory controller 20 via a NAND bus NB1. The memory chips CP2_0, CP2_1, CP2_2, and CP2_3 are connected to the memory controller 20 via a NAND bus NB2. The memory chips CP3_0, CP3_1, CP3_2, and CP3_3 are connected to the memory controller 20 via a NAND bus NB3. Hereinafter, when any of the memory chips CP0_0, CP0_1, CP0_2, and CP0_3 is not limited, it is simply written as "memory chip CP0". When any of the memory chips CP1_0, CP1_1, CP1_2, and CP1_3 is not limited, it is simply written as "memory chip CP1". When any of the memory chips CP2_0, CP2_1, CP2_2, and CP2_3 is not limited, it is simply written as "memory chip CP2". When any of the memory chips CP3_0, CP3_1, CP3_2, and CP3_3 is not limited, it is simply written as "memory chip CP3".

[0017] In this embodiment, a memory unit MU is configured by one memory chip CP connected to each NAND bus NB. For example, the memory unit MU is a unit of multiple memory chips CP corresponding to erasure correction decoding processing. The erasure correction decoding processing is a process of decoding data of a memory chip CP that cannot be read out based on data read out from other memory chips CP and erasure correction code when there is a memory chip CP from which data cannot be read out. In the example of FIG. 1, the memory unit MU0 includes memory chips CP0_0, CP1_0, CP2_0, and CP3_0. The memory unit MU1 includes memory chips CP0_1, CP1_1, CP2_1, and CP3_1. The memory unit MU2 includes memory chips CP0_2, CP1_2, CP2_2, and CP3_2. The memory unit MU3 includes memory chips CP0_3, CP1_3, CP2_3, and CP3_3.

[0018] The configuration of the memory unit MU is arbitrary. For example, the memory unit MU may be configured by a plurality of memory chips CP connected to one NAND bus NB. More specifically, for example, one memory unit MU may be configured by memory chips CP0_0, CP0_1, CP0_2, and CP0_3. The memory unit MU may also be configured by a plurality of memory areas of one memory chip CP. In this case, the plurality of memory areas of the memory chip CP may operate independently of each other. In the following, in this embodiment, a case will be described in which the plurality of memory chips CP constituting the memory unit MU are connected to the memory controller 20 via different NAND buses NB. In this case, no collision of data transmission occurs when the read data of each memory chip CP is simultaneously transmitted to the memory controller 20, so that an increase in tail latency can be suppressed.

[0019] The memory controller 20 is, for example, a SoC (System On a Chip). The memory controller 20 controls the nonvolatile memory 10 based on a request (command) from a host device. More specifically, the memory controller 20 commands the nonvolatile memory 10 to perform data read operations, write operations, erase operations, and the like.

[0020] The memory controller 20 includes a host interface circuit 21, a write control unit 22, a read control unit 23, an error correction circuit 24, a buffer memory 25, and a NAND interface circuit 26. The host interface circuit 21, the write control unit 22, the read control unit 23, the error correction circuit 24, the buffer memory 25, and the NAND interface circuit 26 are connected to each other via a memory bus MB so as to be able to transmit and receive data to and from each other. Note that the functions of the write control unit 22, the read control unit 23, and the error correction circuit 24 may be realized by a dedicated circuit, or may be realized by a processor (not shown) included in the memory controller 20 executing firmware.

[0021] The host interface circuit 21 is a hardware interface that manages communication with the host device 2. For example, when the host interface circuit 21 receives a write request from the host device 2, it transfers the command and address of the write request to the write control unit 22. Then, the host interface circuit 21 transfers user data to the buffer memory 25. When the host interface circuit 21 receives a read request from the host device 2, it transfers the command and address of the read request to the read control unit 23. Then, the host interface circuit 21 transfers the user data in the buffer memory 25 to the host device 2 based on the control of the read control unit 23.

[0022] The write control unit 22 controls the write operation in the nonvolatile memory 10. A plurality of write control units 22 may be provided corresponding to the number of memory units MU.

[0023] The write control unit 22 controls the error correction circuit 24 to generate write data using the user data. The write data includes the user data and an error correction code for the user data. The error correction code is used for ECC (Error Checking and Correcting) processing of the user data. The write control unit 22 stores the write data in the write buffer 27.

[0024] The write control unit 22 controls the error correction circuit 24 to generate one page of parity data corresponding to the write data of multiple pages. In the following description, in a write operation, a unit of data written collectively in one write operation is defined as a "page". The parity data includes an erasure correction code and an error correction code of the erasure correction code. The erasure correction code is used in erasure correction decoding processing. The write control unit 22 stores the parity data in the write buffer 27. In the following description, a data group consisting of the write data of multiple pages and the parity data corresponding thereto is referred to as an "erasure correction data group".

[0025] The write control unit 22 controls to distribute and write the write data of multiple pages and the parity data of one page included in the erasure correction data group to multiple memory chips CP in the memory unit MU. More specifically, for example, when the erasure correction data group is composed of the write data of three pages and the parity data of one page, the write control unit 22 distributes and writes the write data of three pages and the parity data of one page to four memory chips CP in the memory unit MU.

[0026] The write control unit 22 controls the schedule of write operations executed in the memory unit MU. The write control unit 22 controls the number of write operations that can be executed in parallel in the memory unit MU. The write control unit 22 may control the number of erase operations that can be executed in parallel in the memory unit MU. Note that "executed in parallel" includes a state in which operations are executed overlapping with each other at any timing. The start or end timings of multiple operations executed in parallel, or the duration of the execution periods of the operations, may be different.

[0027] The read control unit 23 controls the read operation in the non-volatile memory 10. A plurality of read control units 23 may be provided corresponding to the number of memory units MU. The read data (including parity data) is stored in a read buffer 28.

[0028] The read control unit 23 controls to execute either a normal read operation or a parity read operation based on the operating status of the read target memory chip CP in which the read target data is stored. The normal read operation is an operation of reading the read target data from the read target memory chip CP. The parity read operation is an operation of reading data (other data of the erasure correction data group) used for the erasure correction decoding process of the read target data from a memory chip CP other than the read target memory chip CP in the memory unit MU. For example, if the read target memory chip CP is performing a write operation and therefore cannot immediately read the read target data, the tail latency of the normal read operation increases. In such a case, the read control unit 23 selects the parity read operation.

[0029] The read control unit 23 controls the error correction circuit 24 to execute ECC processing on data (write data or parity data) read from the memory chip CP. The read control unit 23 causes the buffer memory 25 to store the user data or erasure correction code after the ECC processing.

[0030] The read control unit 23 controls the error correction circuit 24 to execute erasure correction decoding process. More specifically, the read control unit 23 executes ECC processing of other data (including parity data) of erasure correction data group that executes parity reading operation and reads out. Then, executes erasure correction decoding process by using the user data and erasure correction code after ECC processing. For example, in erasure correction decoding process, executes XOR operation by using other user data and erasure correction code of erasure correction data group, thereby decodes the data to be read out.

[0031] The error correction circuit 24 generates write data and parity data under the control of the write control unit 22. More specifically, the error correction circuit 24 generates an error correction code of user data. The error correction circuit 24 generates write data by adding an error correction code to the user data. The error correction circuit 24 also generates erasure correction code using a plurality of user data. The error correction circuit 24 generates parity data by adding an error correction code corresponding to the erasure correction code.

[0032] Moreover, the error correction circuit 24 executes ECC processing and erasure correction decoding processing based on the control of the read control unit 23.

[0033] The buffer memory 25 is a volatile semiconductor memory that temporarily stores data. The buffer memory 25 includes a write buffer 27 and a read buffer .

[0034] The write buffer 27 temporarily stores write data, parity data, etc. A plurality of write buffers 27 may be provided according to the number of write control units 22.

[0035] The read buffer 28 temporarily stores data read from the non-volatile memory 10. A plurality of read buffers 28 may be provided according to the number of read control units 23.

[0036] The NAND interface circuit 26 is a hardware interface that manages communication between the memory controller 20 and the nonvolatile memory 10. In the example of FIG. 1, the NAND interface circuit 26 has four channels CH0, CH1, CH2, and CH3. NAND buses NB0, NB1, NB2, and NB3 are connected to the channels CH0, CH1, CH2, and CH3, respectively. For example, the NAND interface circuit 26 receives a write command for the nonvolatile memory 10 from the write control unit 22. The NAND interface circuit 26 transfers a control signal for a write operation, a command, an address, and write data (or parity data) to the nonvolatile memory 10 via the selected channel CH. In addition, for example, the NAND interface circuit 26 receives a read command for the nonvolatile memory 10 from the read control unit 23. The NAND interface circuit 26 transmits a control signal for a read operation, a command, and an address to the nonvolatile memory 10 via the selected channel CH. Then, the NAND interface circuit 26 transfers the data read from the non-volatile memory 10 to the read buffer 28 .

[0037] 1.1.3 Memory chip configuration Next, an example of the configuration of the memory chip CP will be described with reference to Fig. 2. Fig. 2 is a block diagram showing the basic configuration of the memory chip CP. In the example of Fig. 2, some of the connections between the blocks are indicated by arrows. However, the connections between the blocks are not limited to this.

[0038] The memory chip CP includes a sequencer 101 and one or more domains DM. In the example of Fig. 2, the memory chip CP includes four domains DM0 to DM3. The number of domains DM may be one or more.

[0039] The domain DM is a management unit in which execution of a write operation, an erase operation, and a read operation is managed. Each domain DM can operate independently of the others. Also, each domain DM can operate in parallel. For example, each domain DM may be connected to a different driver (power supply).

[0040] The domain DM includes a plurality of planes PLN. In the example of FIG. 2, the domain DM includes two planes PLN0 and PLN1. The number of planes PLN is not limited to two. The number of planes PLN may be three or more. The planes PLN are units that perform write operations, read operations, and erase operations. The planes PLN0 and PLN1 can operate independently of each other. The planes PLN0 and PLN1 can perform write operations or erase operations and read operations in parallel. However, the planes PLN0 and PLN1 cannot perform read operations in parallel. In addition, the planes PLN0 and PLN1 cannot perform write operations or erase operations in parallel.

[0041] More specifically, for example, during a period when a write operation or an erase operation is being performed in the plane PLN0, a read operation can be performed in parallel in the plane PLN1. However, for example, during a period when a read operation is being performed in the plane PLN0, a read operation cannot be performed in the plane PLN1. Also, for example, during a period when a write operation or an erase operation is being performed in the plane PLN0, a write operation or an erase operation cannot be performed in the plane PLN1.

[0042] The sequencer 101 controls the operation of the entire memory chip CP. More specifically, the sequencer 101 controls the write operation, read operation, and erase operation in each domain DM.

[0043] Next, the internal configuration of the planes PLN0 and PLN1 will be described. In the following, the case where the planes PLN0 and PLN1 have the same configuration will be described. Note that the configurations of each plane PLN may be different.

[0044] The plane PLN0 includes a memory cell array 102a, a row decoder 103a, and a sense amplifier 104a. Similarly, the plane PLN1 includes a memory cell array 102b, a row decoder 103b, and a sense amplifier 104b. Note that the planes PLN0 and PLN1 do not simultaneously execute read, write, and erase operations, and therefore may share some of the circuits used for these operations. Hereinafter, when either the memory cell arrays 102a or 102b is not specified, it is simply referred to as the "memory cell array 102". When either the row decoders 103a or 103b is not specified, it is simply referred to as the "row decoder 103". When either the sense amplifiers 104a or 104b is not specified, it is simply referred to as the "sense amplifier 104".

[0045] The memory cell array 102 is a set of multiple memory cell transistors arranged in a row. The memory cell array 102 includes multiple blocks BLK (BLK0, BLK1, ...). The number of blocks BLK in the memory cell array 102 is arbitrary. The block BLK is, for example, a set of multiple memory cell transistors from which data is erased collectively. In other words, the block BLK is a unit for erasing data. The configuration of the block BLK will be described in detail later.

[0046] The row decoder 103 is a row address decoding circuit. The row address is address information received from the memory controller 20. The row decoder 103 selects one of the blocks BLK in the memory cell array 102 based on the decoded result. The row decoder 103 applies a voltage to the row direction wiring (word lines and select gate lines described later) of the selected block BLK.

[0047] The sense amplifier 104 is a read and write circuit. During a read operation, the sense amplifier 104 reads data from the memory cell array 102. During a write operation, the sense amplifier 104 applies a voltage to the memory cell array 102 according to write data.

[0048] 1.1.4 Memory cell array circuit configuration Next, an example of a circuit configuration of the memory cell array 102 will be described with reference to Fig. 3. Fig. 3 is a circuit diagram of the memory cell array 102. Note that the example of Fig. 3 shows the circuit configuration of one block BLK.

[0049] The block BLK includes, for example, four string units SU0 to SU3. The number of string units SU included in the block BLK is arbitrary. The string unit SU is, for example, a set of multiple NAND strings NS that are collectively selected in a write operation or a read operation.

[0050] The string unit SU includes a plurality of NAND strings NS. The NAND string NS is a collection of a plurality of memory cell transistors connected in series. The plurality of NAND strings NS in the string unit SU are connected to any one of bit lines BL0 to BLn (n is an integer equal to or greater than 1).

[0051] Each NAND string NS includes a plurality of memory cell transistors MC and select transistors ST1 and ST2. In the example of Fig. 3, the NAND string NS includes eight memory cell transistors MC0 to MC.

[0052] The memory cell transistor MC is a memory element that stores data in a non-volatile manner. The memory cell transistor MC includes a control gate and a charge storage layer. The memory cell transistor MC may be of a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type or a FG (Floating Gate) type. The MONOS type uses an insulating layer for the charge storage layer. The FG type uses a conductive layer for the charge storage layer.

[0053] The selection transistors ST1 and ST2 are switching elements and are used to select the string units SU during various operations.

[0054] The current paths of the select transistor ST2, the memory cell transistors MC0 to MC7, and the select transistor ST1 in the NAND string NS are connected in series. The drain of the select transistor ST1 is connected to a bit line BL. The source of the select transistor ST2 is connected to a source line SL.

[0055] The control gates of the memory cell transistors MC0 to MC7 in the same block BLK are commonly connected to the word lines WL0 to WL7, respectively. More specifically, for example, the block BLK includes four string units SU0 to SU3. Each string unit SU includes a plurality of memory cell transistors MC0. The control gates of the plurality of memory cell transistors MC0 in the block BLK are commonly connected to one word line WL0. The same is true for the memory cell transistors MC1 to MC7.

[0056] The gates of the multiple selection transistors ST1 in the string unit SU are commonly connected to one selection gate line SGD. More specifically, the gates of the multiple selection transistors ST1 in the string unit SU0 are commonly connected to a selection gate line SGD0. The gates of the multiple selection transistors ST1 in the string unit SU1 are commonly connected to a selection gate line SGD1. The gates of the multiple selection transistors ST1 in the string unit SU2 are commonly connected to a selection gate line SGD2. The gates of the multiple selection transistors ST1 in the string unit SU3 are commonly connected to a selection gate line SGD3.

[0057] The gates of the select transistors ST2 in the block BLK are commonly connected to a select gate line SGS. Similar to the select gate line SGD, a different select gate line SGS may be provided for each string unit SU.

[0058] The word lines WL0 to WL7, the select gate lines SGD0 to SGD3, and the select gate line SGS are each connected to a row decoder 103 in the plane PLN.

[0059] The bit line BL is commonly connected to one NAND string NS in each string unit SU of each block BLK. The same column address is assigned to the multiple NAND strings NS connected to one bit line BL. Each bit line BL is connected to a sense amplifier 104 in the plane PLN.

[0060] The source line SL is shared among, for example, a plurality of blocks BLK.

[0061] A set of multiple memory cell transistors MC connected to a common word line WL in one string unit SU is denoted as, for example, a "cell unit CU." For example, when a memory cell transistor MC stores one bit of data, the storage capacity of the cell unit CU is defined as "one page." The cell unit CU may have a storage capacity of two or more pages based on the number of bits of data stored in the memory cell transistor MC.

[0062] 1.1.5 Configuration of memory area of ​​memory chip CP Next, an example of the configuration of the memory area of ​​the memory chip CP will be described with reference to FIG. 4. FIG. 4 is a diagram showing the configuration of the memory area of ​​the memory chip CP. In the following description, when the planes PLN0 and PLN1 and the memory cell arrays 102a and 102b of the domain DM0 are limited, they are written as planes PLN0_0 and PLN1_0 and memory cell arrays 102a_0 and 102b_0. When the planes PLN0 and PLN1 and the memory cell arrays 102a and 102b of the domain DM1 are limited, they are written as planes PLN0_1 and PLN1_1 and memory cell arrays 102a_1 and 102b_1. When the planes PLN0 and PLN1 and the memory cell arrays 102a and 102b of the domain DM2 are limited, they are written as planes PLN0_2 and PLN1_2 and memory cell arrays 102a_2 and 102b_2. When limiting the planes PLN0 and PLN1 and the memory cell arrays 102a and 102b of the domain DM3, they are expressed as planes PLN0_3 and PLN1_3 and memory cell arrays 102a_3 and 102b_3.

[0063] As shown in FIG. 4, the memory area of ​​the memory chip CP includes a plurality of plane units PU each composed of a memory cell array 102 of one plane PLN of each domain DM. The plane units PU are memory areas controlled independently. The number of plane units PU is arbitrary. The number of plane units PU corresponds to the number of plane PLNs included in each domain DM. In the example of FIG. 4, the memory chip CP includes two plane units PU0 and PU1. The plane unit PU0 includes a memory cell array 102a of the plane PLN0 of each domain DM. More specifically, the plane unit PU0 includes memory cell arrays 102a_0, 102a_1, 102a_2, and 102a_3. Similarly, the plane unit PU1 includes a memory cell array 102b of the plane PLN1 of each domain DM. More specifically, the plane unit PU1 includes memory cell arrays 102b_0, 102b_1, 102b_2, and 102b_3.

[0064] 1.1.6 Example of memory chip operation Next, a specific example of the operation in the memory chip CP will be described with reference to Fig. 5. Fig. 5 is a diagram showing a specific example of the operation in the memory chip CP.

[0065] As shown in FIG. 5, the sequencer 101 can execute a write operation or an erase operation in parallel in any one of the planes PLN of each of the multiple domains DM. In the example of FIG. 5, the write operation or the erase operation is executed in parallel in the planes PLN0_0, PLN1_1, and PLN0_2. During this time, the write operation and the erase operation cannot be executed in the plane PLN1_0 in the same domain DM0 as the plane PLN0_0, the plane PLN0_1 in the same domain DM1 as the plane PLN1_1, and the plane PLN1_2 in the same domain DM2 as the plane PLN0_2. Note that the read operation can be executed in the planes PLN1_0, PLN0_1, and PLN1_2. The latency of the read operation is shorter than the latency of the write operation and the erase operation. For this reason, for example, two read operations are executed in the plane PLN1_0. Also, for example, three read operations are executed in the planes PLN0_1 and PLN1_2.

[0066] In the domain DM3, no write operation or erase operation is being performed. In this case, a read operation can be performed in either the plane PLN0_3 or PLN1_3. For example, three read operations are being performed in the plane PLN1_3. Since read operations cannot be performed in parallel in the domain DM, one read operation is being performed in the plane PLN0_3 while no read operation is being performed in the plane PLN1_3.

[0067] 1.1.7 Configuration of memory area of ​​memory unit Next, an example of the configuration of the memory area of ​​memory unit MU will be described with reference to Fig. 6. Fig. 6 is a diagram showing the configuration of the memory area of ​​memory unit MU. Note that the example of Fig. 6 shows the configuration of the memory area of ​​memory unit MU0.

[0068] As shown in FIG. 6, a stream STM0 is configured by the plane units PU0 of each of the memory chips CP0_0, CP1_0, CP2_0, and CP3_0. A stream STM1 is configured by the plane units PU1 of each of the memory chips CP0_0, CP1_0, CP2_0, and CP3_0. The number of streams STM included in the memory unit MU is arbitrary. For example, the number of streams STM corresponds to the number of plane units PU of each memory chip CP. The stream STM is not limited to this. For example, one stream STM may be configured by one plane PLN of one domain DM of one plane unit PU of each memory chip CP. For example, a stream STM0 may be configured by the plane PLN0 of the domain DM0 of the plane units PU0 of each of the memory chips CP0_0, CP1_0, CP2_0, and CP3_0.

[0069] For example, the stream STM is a set of a plurality of plane units PU corresponding to the erasure correction data group. For example, three pages of write data and one page of parity data included in the erasure correction data group are distributed and written to four plane units PU of the stream STM0. For example, when a write operation or an erase operation is being performed in one plane unit PU in the stream STM, the write operation and the erase operation in the other plane units PU are restricted so that the erasure correction decoding process of the data in the plane unit PU can be performed. Therefore, in the stream STM, the number of plane units PU that can perform a write operation or an erase operation is limited to, for example, one. In other words, in one stream STM, a write operation or an erase operation cannot be performed in parallel in a plurality of plane units PU. Note that a read operation can be performed in parallel in a plurality of plane units PU in the stream STM.

[0070] 1.1.8 Example of operation of memory unit Next, a specific example of the operation in the memory unit MU will be described with reference to Fig. 7. Fig. 7 is a diagram showing a specific example of the operation in the memory unit MU.

[0071] As shown in Fig. 7, for example, a write operation or an erase operation is being performed in the plane unit PU0 of the memory chip CP0_0 included in the stream STM0. More specifically, a write operation or an erase operation is being performed in the plane PLN0 of at least one domain DM of the memory chip CP0_0. For example, when the plane unit PU0 includes four domains DM0 to DM3, four write operations corresponding to four erasure correction data groups may be performed in parallel in each plane PLN0 (PLN0_0, PLN0_1, PLN0_2, and PLN0_3).

[0072] In this situation, in the plane unit PU0 of the other memory chips CP1_0, CP2_0, and CP3_0 included in the stream STM0, read operations can be executed but write operations and erase operations cannot be executed.

[0073] Also, in the plane unit PU1 of the memory chip CP0_0 included in the stream STM1, a read operation can be executed. Furthermore, in a domain DM other than the domain DM in which a write operation or erase operation corresponding to the stream STM0 is executed, a write operation or erase operation corresponding to the stream STM1 can be executed. More specifically, for example, when a write operation or erase operation is executed in the plane PLN0 of the domain DM0 of the memory chip CP1_0, a write operation or erase operation cannot be executed in the plane PLN1 of the domain DM0. In contrast, a write operation or erase operation can be executed in each of the planes PLN1 of the domains DM1 to DM3. Note that, for example, when write operations corresponding to four erasure correction data groups are executed in parallel in each of the planes PLN0 of the domains DM0 to DM3 of the memory chip CP1_0, a write operation or erase operation cannot be executed in the plane unit PU1 of the memory chip CP1_0.

[0074] Furthermore, the plane units PU1 of the other memory chips CP1_0, CP2_0, and CP3_0 included in the stream STM1 can perform read, write, and erase operations.

[0075] Therefore, in one memory unit MU corresponding to the erasure correction data group, two write operations in different memory chips CP can be executed in parallel.

[0076] 1.1.9 Write control section configuration Next, an example of the configuration of the write control unit 22 will be described with reference to Fig. 8. Fig. 8 is a block diagram showing the configuration of the write control unit 22.

[0077] As shown in Fig. 8, the write control unit 22 includes a plurality of stream control units 221 and a write monitoring unit 222. In the example of Fig. 8, the write control unit 22 includes a stream 0 control unit 221a corresponding to stream STM0 and a stream 1 control unit 221b corresponding to stream STM1. Note that the number of stream control units 221 included in the write control unit 22 is arbitrary. The number of stream control units 221 corresponds to the number of streams STM included in the memory unit MU.

[0078] The stream 0 control unit 221a is a control circuit that controls the write operation in the stream STM0. The stream 0 control unit 221a controls the schedule of the write operation in each plane unit PU0 in the stream STM0 based on a signal received from the write monitoring unit 222.

[0079] The stream 1 control unit 221b is a control circuit that controls the write operation in the stream STM1. Based on a signal received from the write monitoring unit 222, the stream 1 control unit 221b controls the schedule of the write operation in each plane unit PU1 in the stream STM1.

[0080] The write monitor 222 monitors a write operation or an erase operation being performed in the memory unit MU. The write monitor 222 estimates the time when the write operation or the erase operation being performed will be completed, and transmits the result to the stream 0 control unit 221a and the stream 1 control unit 221b.

[0081] 1.1.10 Configuration of read control unit Next, an example of the configuration of the read control unit 23 will be described with reference to Fig. 9. Fig. 9 is a block diagram showing the configuration of the read control unit 23.

[0082] As shown in FIG. 9, the read control unit 23 includes a parity decoding determination circuit 231.

[0083] The parity decoding determination circuit 231 judges whether to execute erasure correction decoding process for the data to be read. When the parity decoding determination circuit 231 receives a read request from the host device 2, it checks the operation status of the target memory unit MU and judges whether to execute parity read operation. When the parity decoding determination circuit 231 judges that erasure correction decoding process is not executed, the read control unit 23 commands the memory chip CP having the data to be read to execute normal read operation. Also, when the parity decoding determination circuit 231 judges that erasure correction decoding process is executed, the read control unit 23 commands the other memory chip CP of the memory unit MU to execute the read operation of other data of the erasure correction data group including the data to be read.

[0084] 1.1.11 Write Buffer Configuration Next, an example of the configuration of the write buffer 27 will be described with reference to Fig. 10. Fig. 10 is a block diagram showing the configuration of the write buffer 27.

[0085] As shown in FIG. 10, the write buffer 27 includes a plurality of stream buffers 271. In the example of FIG. 10, the write buffer 27 includes a stream 0 buffer 271a corresponding to the stream STM0 and a stream 1 buffer 271b corresponding to the stream STM1. The number of stream buffers 271 included in the write buffer 27 is arbitrary. The number of stream buffers 271 may correspond to the number of stream control units 221 included in the write control unit 22. For example, a stream buffer 271 is not released until the write operation of the corresponding stream STM is completed. For this reason, the write buffer 27 may include a surplus buffer for temporarily storing new write data while each stream buffer 271 is not released.

[0086] The stream 0 buffer 271a includes a data buffer 272a and a parity buffer 273a. The data buffer 272a temporarily stores write data corresponding to the stream STM0. The parity buffer 273a temporarily stores parity data corresponding to the write data stored in the data buffer 272a.

[0087] The stream 1 buffer 271b includes a data buffer 272b and a parity buffer 273b. The data buffer 272b temporarily stores write data corresponding to the stream STM1. The parity buffer 273b temporarily stores parity data corresponding to the write data stored in the data buffer 272b.

[0088] Hereinafter, when either the data buffers 272a or 272b is not specified, it will simply be referred to as the "data buffer 272." Furthermore, when either the parity buffers 273a or 273b is not specified, it will simply be referred to as the "parity buffer 273."

[0089] 1.2 Write Operation 1.2.1 Write operation flow Next, referring to Fig. 11 and Fig. 12, an example of the flow of write operation will be described. Fig. 11 and Fig. 12 are flowcharts of write operation. In the following description, the case of selecting the stream STM0 of memory unit MU0 and executing write operation will be described. Note that, the same applies to the write operation when selecting other memory unit MU or other stream STM. In addition, in the following, in order to simplify the description, the case of executing the write operation corresponding to one erasure correction data group will be described.

[0090] 11, first, the memory controller 20 receives a write request from the host device 2 (S101). Upon receiving the write request (user data), the write control unit 22 controls the error correction circuit 24 to generate write data.

[0091] The write control unit 22 refers to the data buffer 272 of each stream buffer 271 to check whether or not unwritten write data is stored in the non-volatile memory 10 (S102). More specifically, the write control unit 22 refers to the data buffer 272a of the stream 0 buffer 271a and the data buffer 272b of the stream 1 buffer 271b to check whether or not unwritten write data is stored.

[0092] If there is no unwritten write data (S102_No), the write control unit 22 selects one of the streams STM. For example, if the write control unit 22 selects the stream STM0, the stream 0 control unit 221a initializes the parity buffer 273a (S103).

[0093] Furthermore, if there is unwritten write data (S102_Yes), the write control unit 22 selects the stream STM corresponding to the data buffer 272 in which the unwritten write data is stored. For example, if unwritten write data is stored in the data buffer 272a of the stream 0 buffer 271a, the write control unit 22 selects the stream STM0.

[0094] After the initialization of the parity buffer 273a in step S103 is completed, or if there is unwritten write data in the data buffer 272a (S102_Yes), the stream 0 control unit 221a stores (temporarily stores) the generated write data in the data buffer 272a (S104).

[0095] The stream 0 control unit 221a controls the error correction circuit 24 to generate parity data using the write data stored in the data buffer 272a (S105). The parity data is stored in the parity buffer 273a.

[0096] The stream 0 control unit 221a checks whether the number of pages of the write data stored in the data buffer 272a has reached the set value (S106). For example, when the erasure correction data group is composed of three pages of write data and one page of parity data, the set value is set to 3. In this case, the stream 0 control unit 221a checks whether three pages of write data are stored in the data buffer 272a. Note that, in this embodiment, the case where the number of pages of the write data stored in the data buffer 272a has reached the set value has been described, but is not limited to this. For example, the write data may be written to the target memory chip CP at any timing after being used to generate the parity data. In this case, the write data that has been written to the memory chip CP may not be stored in the data buffer 272a. The stream 0 control unit 221a checks whether the number of pages of the write data used to generate the parity data has reached the set value.

[0097] If the page number of the write data has not reached the set value (S106_No), the stream 0 control unit 221a repeats the loop of steps S101 to S106 until the page number of the write data reaches the set value.

[0098] If the page number of the write data has reached the set value (S106_Yes), the stream 0 control unit 221a checks whether or not there is a write operation or an erase operation being executed in the stream STM0 (S107).

[0099] If there is a write operation or erase operation being performed in stream STM0 (S107_Yes), the write monitor 222 monitors the ongoing write operation or erase operation (S108). The write monitor 222 estimates the time when the ongoing write operation or erase operation will be completed, and notifies the stream 0 control unit 221a. The stream 0 control unit 221a puts the write operation of the data (write data and parity data) in the stream 0 buffer 271a into a standby state until the completion time is reached.

[0100] The ongoing write or erase operation is terminated (S109).

[0101] 12, after the ongoing write or erase operation of step S109 is completed, or if there is no ongoing write or erase operation in the stream STM0 (S107_No), the stream 0 control unit 221a selects a memory chip CP and a domain DM to which data is to be written (S110). More specifically, for example, the stream 0 control unit 221a selects a plane PLN0 of the domain DM0 of each of the memory chips CP0_0, CP1_0, CP2_0, and CP3_0.

[0102] The stream 0 control unit 221a checks whether there is a write operation or erase operation in progress corresponding to another stream STM1 in the selected domain DM (S111). That is, the stream 0 control unit 221a checks whether a collision (overlap) of a write operation or erase operation has occurred in the same domain DM. For example, when the stream 0 control unit 221a selects the plane PLN0 of the domain DM0 of the memory chip CP0_0, it checks whether a write operation or erase operation in progress corresponding to the stream STM1 is in progress in the plane PLN1 of the same domain DM0.

[0103] If there is a write operation or erase operation being executed in the same domain DM (S111_Yes), the stream 0 control unit 221a waits until it is time to execute the write operation (S112). For example, the write monitoring unit 222 estimates the time when the write operation or erase operation being executed will be completed, and notifies the stream 0 control unit 221a. The stream 0 control unit 221a remains in a standby state until the completion time of the write operation or erase operation being executed is reached.

[0104] After the wait in step S112 ends, or if there is no write operation or erase operation being executed (S111_No), the stream 0 control unit 221a executes a write operation. For example, the stream 0 control unit 221a executes four write operations corresponding to three pages of write data and one page of parity data at different timings so that multiple write operations are not executed in parallel (overlapping) in each plane unit PU of the stream STM0.

[0105] 1.2.2 Example of a write operation Next, a specific example of a write operation will be described with reference to Fig. 13. Fig. 13 is a diagram showing a specific example of a write operation. The following description focuses on the write operation corresponding to the stream STM0.

[0106] 13, for example, a write operation or an erase operation is being executed in the plane unit PU0 of the memory chip CP0 and the plane unit PU1 of the memory chip CP1. The plane unit PU0 of the memory chip CP0 and the plane unit PU1 of the memory chip CP1 are different streams STM of different memory chips CP, so that the write operation or the erase operation can be executed in parallel.

[0107] In this state, for example, the stream 0 control unit 221a receives the write data D0, D1, and D2, and the parity data P 012 Write the parity data P 012 corresponds to the erasure correction decoding process of the write data D0, D1, and D2. That is, the write data D0, D1, and D2 and the parity data P 012 An erasure correction data group is formed by the above.

[0108] First, after the write operation or erase operation of the plane unit PU0 of the memory chip CP0 is completed, the stream 0 control unit 221a executes the write operation of the write data D0 in the plane unit PU0 of the memory chip CP0. During this time, for example, the write operation or erase operation may be executed in the plane unit PU1 of any of the memory chips CP1 to CP3 corresponding to the stream STM1. In the example of FIG. 13, the write operation or erase operation is executed in the plane unit PU1 of the memory chip CP2.

[0109] Next, after the write operation of the write data D0 is completed in the plane unit PU0 of the memory chip CP0, the stream 0 control unit 221a executes the write operation of the write data D1 in the plane unit PU0 of the memory chip CP1. During this time, for example, a write operation or an erase operation may be executed in the plane unit PU1 of any of the memory chips CP0, CP2, and CP3 corresponding to the stream STM1. In the example of FIG. 13, a write operation or an erase operation is executed in the plane unit PU1 of the memory chip CP3.

[0110] Next, after the write operation of the write data D1 is completed in the plane unit PU0 of the memory chip CP1, the stream 0 control unit 221a executes the write operation of the write data D2 in the plane unit PU0 of the memory chip CP2. During this time, for example, a write operation or an erase operation may be executed in the plane unit PU1 of any of the memory chips CP0, CP1, and CP3 corresponding to the stream STM1.

[0111] Next, after the write operation of the write data D2 is completed in the plane unit PU0 of the memory chip CP2, the stream 0 control unit 221a writes the parity data P 012During this time, for example, a write operation or an erase operation may be performed in the plane unit PU1 of any of the memory chips CP0 to CP2 corresponding to the stream STM1. In the example of FIG. 13, a write operation or an erase operation is performed in the plane unit PU1 of the memory chip CP0. Note that the data D0, D1, and D2, and the parity data P 012 The order in which the write operations are performed can be set arbitrarily.

[0112] 1.3 Read Operation 1.3.1 Read operation flow Next, referring to Fig. 14, an example of the flow of read operation will be described. Fig. 14 is a flow chart of read operation. In the following, in order to simplify the description, the read operation corresponding to one erasure correction data group is described.

[0113] As shown in FIG. 14, first, the memory controller 20 receives a read request from the host device 2 (S201).

[0114] The read control unit 23 checks whether there is a write operation or an erase operation being executed in the target plane PLN of the target memory chip CP in which the read target data is stored (S202).

[0115] If a write operation or erase operation is being executed (S202_Yes), the read control unit 23 checks whether or not there is parity data corresponding to the data to be read in the read buffer 28 or in another memory chip CP (S203).

[0116] If there is parity data (S203_Yes), the read control unit 23 executes a parity read operation (S204). The read control unit 23 can execute the read operation of other data (including parity data) of the erasure correction data group including the data to be read in parallel.

[0117] The read control unit 23 controls the error correction circuit 24 to execute erasure correction decoding processing using the read data, and decodes the data to be read (S205).

[0118] Moreover, if there is no write operation or erase operation being executed (S202_No), or if there is no parity data (S203_No), the read control unit 23 executes a normal read operation of the read target data in the target plane PLN (S206).

[0119] 1.3.2 Example of a read operation Next, a specific example of a write operation will be described with reference to Fig. 15. Fig. 15 is a diagram showing a specific example of a read operation. The example in Fig. 15 shows a case where a parity read operation is executed.

[0120] As shown in FIG. 15, for example, a write operation or an erase operation is being executed in the plane unit PU0 of the memory chip CP0 and in the plane unit PU1 of the memory chip CP1.

[0121] In this state, for example, when the read control unit 23 receives a read request for data D0 of the plane unit PU0 of the memory chip CP0, the read control unit 23 selects a parity read operation. For example, the read control unit 23 selects a read operation for data D1 of the plane unit PU0 of the memory chip CP1, a read operation for data D2 of the plane unit PU0 of the memory chip CP2, and a read operation for parity data P of the plane unit PU0 of the memory chip CP3. 012 The read control unit 23 then controls the error correction circuit 24 to read the data D1 and D2 and the parity data P 012 Then, the erasure correction decoding process is performed using the above-mentioned. As a result, the data D0 is decoded.

[0122] 1.4 Effects of this embodiment The configuration according to this embodiment can improve the processing capacity of the memory system 3. This effect will be described in detail.

[0123] For example, a write request and a read request to the same memory area of ​​a memory chip may collide (overlap). If a write operation is already being performed in the memory area, the read operation is put into a waiting state, and the tail latency of the read operation increases. One method for suppressing the increase in the tail latency of a read operation is to decode the read target data using an erasure correction decoding process. For example, if the read target data cannot be read due to an operation being performed, the read target data can be decoded using data (including erasure correction code) read from another memory chip, thereby suppressing the increase in the tail latency of the read operation. However, for multiple memory chips corresponding to an erasure correction data group, the number of memory chips that can perform a write operation in parallel is limited to, for example, one. This reduces the write performance.

[0124] In contrast, in the configuration according to this embodiment, a memory chip CP can be provided with a plurality of plane units PU. For example, even when a write operation or an erase operation is being performed in one plane unit PU, a read operation can be performed in the other plane units PU. Then, a stream STM corresponding to an erasure correction data group can be configured by one plane unit PU of each of a plurality of memory chips CP. Therefore, for example, a plurality of write operations can be performed in parallel for a plurality of memory chips CP corresponding to an erasure correction data group according to the number of streams STM. Therefore, the memory system 3 can improve the write performance. Therefore, the memory system 3 can improve the processing capacity.

[0125] 1.5 Modification of the first embodiment Next, three modifications of the first embodiment will be described, focusing on the differences from the first embodiment.

[0126] 1.5.1 First modification of the first embodiment First, a first modified example of the first embodiment will be described. In the first modified example, a case where erase operations are executed in parallel in a plurality of plane units PU in the same stream STM will be described. Fig. 16 is a diagram showing a specific example of a write operation.

[0127] As shown in FIG. 16, erase operations may be executed in parallel in multiple plane units PU in the same stream STM. The latency of an erase operation is shorter than the latency of a write operation. Also, the execution frequency of an erase operation is lower than that of a write operation. Therefore, the collision frequency between a read operation and an erase operation is lower than that between a read operation and a write operation. By executing erase operations in parallel, the processing time of the erase operation can be reduced.

[0128] 1.5.2 Second modification of the first embodiment Next, a second modification of the first embodiment will be described. In the second modification, a case where an erase operation is suspended and a read operation is executed will be described. Fig. 17 is a diagram showing a specific example of the read operation.

[0129] 17, when a read request is received during an erase operation, the read control unit 23 may suspend (interrupt) the erase operation being executed and execute the read operation. After the read operation is completed, the read control unit 23 controls the erase operation to resume (restart). By suspending the erase operation, an increase in the tail latency of the read operation can be suppressed.

[0130] 1.5.3 Third modification of the first embodiment Next, a third modified example of the first embodiment will be described. In the third modified example, a case will be described in which the write or erase operations of two memory chips CP are executed in the same stream STM with some of the processing times overlapping each other.

[0131] 1.5.3.1 Write Operation Flow First, an example of the flow of a write operation will be described with reference to Fig. 18 and Fig. 19. Fig. 18 and Fig. 19 are flowcharts of the write operation. The description will focus on the differences from Fig. 11 and Fig. 12 of the first embodiment.

[0132] As shown in FIG. 18, the operations from step S101 to step S108 are similar to those in FIG. 11 of the first embodiment.

[0133] The write monitoring unit 222 monitors the ongoing write or erase operation (S108), and notifies the stream 0 control unit 221a of the time when the ongoing write or erase operation will be completed.

[0134] The stream 0 control unit 221a calculates the allowable overlap time of the ongoing write or erase operation from the completion time. When the allowable overlap time is reached (S121), the stream 0 control unit 221a releases the standby state for the next write or erase operation.

[0135] 19, after the overlap permitted time in step S121 is reached or if there is no write or erase operation being performed in stream STM0 (S107_No), the stream 0 control unit 221a selects a memory chip CP and a domain DM to which one page of data in the stream 0 buffer 271a is to be written (S110). More specifically, for example, the stream 0 control unit 221a selects a plane PLN0 of the domain DM0 of each of the memory chips CP0_0, CP1_0, CP2_0, and CP3_0.

[0136] The operations after step S110 are similar to those in FIG. 12 of the first embodiment.

[0137] 1.5.3.2 Examples of overlapping Next, a specific example of overlap will be described with reference to Fig. 20. Fig. 20 is a diagram showing specific examples of write and read operations. The following description focuses on the write and read operations corresponding to the stream STM0.

[0138] As shown in FIG. 20, for example, a write operation or an erase operation is being executed in the plane unit PU0 of the memory chip CP0 and in the plane unit PU1 of the memory chip CP2.

[0139] In this state, when the write operation or erase operation being executed in the plane unit PU0 of the memory chip CP0 reaches the overlap allowable time, the stream 0 control unit 221a starts the write operation or erase operation in the plane unit PU0 of the memory chip CP1, for example.

[0140] Next, a read operation corresponding to the overlap will be described. For example, a write operation or an erase operation is being performed in the plane unit PU0 of the memory chip CP0. In this state, the read control unit 23 receives a read request for data D0 of the plane unit PU0 of the memory chip CP0. For example, if the parity read operation does not collide with the next write operation or erase operation performed in an overlapping manner, the read control unit 23 executes the parity read operation to decode the data D0. More specifically, for example, if the read operation of data D1 does not collide with the next write operation or erase operation performed in an overlapping manner in the plane unit PU0 of the memory chip CP1, the read control unit 23 executes the parity read operation.

[0141] Also, for example, the read control unit 23 receives a read request for data D3 in the plane unit PU0 of the memory chip CP0. When a parity read operation corresponding to the data D3 is executed, it collides with the next write operation or erase operation executed in an overlapping manner in the plane unit PU0 of the memory chip CP1. In this case, the read control unit 23 does not select the parity read operation, and executes a normal read operation of the data D3 after the write operation or erase operation of the plane unit PU0 of the memory chip CP0 is completed.

[0142] 1.5.4 Effects of the Modification of the First Embodiment With the configurations according to the first to third modified examples of the first embodiment, the same effects as those of the first embodiment can be obtained.

[0143] Furthermore, with the configuration according to the first modification of the first embodiment, erase operations can be executed in parallel in a plurality of plane units PU in the same stream STM, thereby improving the processing capacity of the erase operation.

[0144] Furthermore, with the configuration according to the second modification of the first embodiment, the erase operation can be suspended to execute the read operation, thereby making it possible to suppress an increase in the tail latency of the read operation.

[0145] Furthermore, with the configuration according to the third modification of the first embodiment, two write or erase operations can be executed in the same stream STM with some of the processing time overlapped, thereby improving the processing capacity of the write or erase operations.

[0146] The first to third modified examples may be combined with each other. For example, the first modified example may be combined with the second modified example. For example, when erase operations are performed in parallel in a plurality of plane units PU in the same stream STM, the erase operation may be suspended in the memory chip CP that is the read target, and a normal read operation may be performed.

[0147] 2. Second embodiment Next, a second embodiment will be described. In the second embodiment, six examples of read operations different from those in the first embodiment will be described. The following description will focus on the differences from the first embodiment.

[0148] 2.1 First Example First, a first example of the second embodiment will be described.

[0149] 2.1.1 Read operation flow An example of the flow of a read operation will be described with reference to Fig. 21. Fig. 21 is a flowchart of the read operation.

[0150] As shown in FIG. 21, the operations from step S201 to step S203 are similar to those in FIG. 14 of the first embodiment.

[0151] If parity data is present (S203_Yes), the read control unit 23 checks whether the length of time until the ongoing write or erase operation is completed is longer than a preset threshold value (S211).

[0152] If the length of time until the ongoing write or erase operation is completed is longer than a preset threshold (S211_Yes), the read control unit 23 executes a parity read operation (S204).

[0153] The read control unit 23 controls the error correction circuit 24 to execute erasure correction decoding processing using the read data, and decodes the data to be read (S205).

[0154] Moreover, if the length of time until the ongoing write operation or erase operation is completed is equal to or less than a preset threshold (S211_No), the read control unit 23 waits until the ongoing write operation or erase operation is completed (S212).

[0155] If there is no write or erase operation in progress (S202_No), if there is no parity data (S203_No), or after the standby state of step S212 is released, the read control unit 23 executes a normal read operation of the data to be read (S206).

[0156] 2.1.2 Example of a read operation Next, a specific example of a read operation will be described with reference to Fig. 22. Fig. 22 is a diagram showing a specific example of a read operation.

[0157] As shown in FIG. 22, for example, a write operation or an erase operation is being executed in the plane unit PU0 of the memory chip CP0 and the plane unit PU1 of the memory chip CP1.

[0158] In this state, for example, the read control unit 23 receives a read request for data D0 of the plane unit PU0 of the memory chip CP0. For example, if the length of time from when the read request for data D0 is received until the ongoing write or erase operation is completed is longer than a threshold, the read control unit 23 executes a parity read operation. For example, the read control unit 23 reads data D1 and D2 and parity data P 012 and decodes the data D0.

[0159] Also, for example, the read control unit 23 receives a read request for data D3 from the plane unit PU0 of the memory chip CP0. For example, if the length of time from when the read request for data D3 is received until the ongoing write operation or erase operation is completed is equal to or less than a threshold, the read control unit 23 executes a normal read operation for data D3 after the write operation or erase operation of the plane unit PU0 of the memory chip CP0 is completed.

[0160] 2.2 Second Example Next, a second example of the second embodiment will be described with reference to Fig. 23, which is a flowchart of a read operation.

[0161] As shown in FIG. 23, first, the memory controller 20 receives a read request from the host device 2 (S201).

[0162] The read control unit 23 checks whether the read target data can be read immediately in the target plane PLN of the target memory chip CP in which the read target data is stored (S221). In other words, it checks whether a waiting period is required before a normal read operation can be performed. For example, if there is an operation (write operation, erase operation, or read operation) being performed in the target plane PLN, or if multiple commands are stacked in the command queue corresponding to the target plane PLN (i.e., multiple operations are reserved), the read control unit 23 determines that the read target data cannot be read immediately.

[0163] If immediate reading is not possible (S221_No), the read control unit 23 checks whether or not there is parity data corresponding to the data to be read in the read buffer 28 or in another memory chip CP (S203).

[0164] If parity data is present (S203_Yes), the read control unit 23 estimates the completion time of the normal read operation of the data to be read and the completion time of the parity read operation. Then, the read control unit 23 checks whether the completion time of the parity read operation is earlier than the completion time of the normal read operation by a certain time or more. In other words, the read control unit 23 checks whether the difference between the completion time of the normal read operation and the completion time of the parity read operation is longer than a preset threshold value (S222).

[0165] When the difference between the normal read completion time and the parity read operation completion time is longer than a preset threshold value (S222_Yes), the read control unit 23 executes the parity read operation (S204).

[0166] The read control unit 23 controls the error correction circuit 24 to execute erasure correction decoding processing using the read data, and decodes the data to be read (S205).

[0167] Also, if the difference between the completion time of the normal read operation and the completion time of the parity read operation is less than or equal to a preset threshold (S222_No), the read control unit 23 waits until the operation of the command stacked in the command queue corresponding to the target plane PLN of the target memory chip CP is completed and the normal read operation becomes possible (S223).

[0168] If immediate reading is possible (S221_Yes), if there is no parity data (S203_No), or after the standby state of step S223 is released, the read control unit 23 executes a normal read operation of the data to be read (S206).

[0169] 2.3 Third Example Next, a third example of the second embodiment will be described with reference to Fig. 24, which is a flowchart of a read operation.

[0170] As shown in FIG. 24, first, the memory controller 20 receives a read request from the host device 2 (S201).

[0171] The read control unit 23, like step S221 in the second example of the second embodiment, checks whether real-time reading of the read target data is executable in the target plane PLN of the target memory chip CP in which the read target data is stored (S231).

[0172] If immediate reading is not possible (S231_No), the read control unit 23 checks whether or not there is parity data corresponding to the data to be read in the read buffer 28 or in another memory chip CP (S203).

[0173] If parity data is present (S203_Yes), the read control unit 23 checks whether the congestion level of the target memory chip CP is greater than a preset threshold (S232). For example, the read control unit 23 checks the congestion level based on the type and number of commands stacked in the command queue corresponding to the target memory chip CP.

[0174] If the congestion degree of the target memory chip CP is greater than a preset threshold value (S232_Yes), the read control unit 23 executes a parity read operation (S204).

[0175] The read control unit 23 controls the error correction circuit 24 to execute erasure correction decoding processing using the read data, and decodes the data to be read (S205).

[0176] Also, if the congestion level of the target memory chip CP is equal to or lower than a preset threshold value (S232_No), the read control unit 23 waits until the operation of the command stacked in the command queue is completed and normal read operation becomes possible (S233).

[0177] If immediate reading is possible (S231_Yes), if there is no parity data (S203_No), or after the standby state of step S233 is released, the read control unit 23 executes a normal read operation of the data to be read (S206).

[0178] 2.4 Fourth Example Next, a fourth example of the second embodiment will be described with reference to Fig. 25, which is a flowchart of a read operation.

[0179] As shown in FIG. 25, first, the memory controller 20 receives a read request from the host device 2 (S201).

[0180] The read control unit 23, like step S221 in the second example of the second embodiment, checks whether real-time reading of the read target data is executable in the target plane PLN of the target memory chip CP in which the read target data is stored (S241).

[0181] If immediate reading is not possible (S241_No), the read control unit 23 checks whether or not there is parity data corresponding to the data to be read in the read buffer 28 or in another memory chip CP (S203).

[0182] If there is parity data (S203_Yes), the read control unit 23 checks whether the power consumption in the memory system 3 is smaller than a preset threshold value (S232).

[0183] If the power consumption is less than the preset threshold (S242_Yes), the read control unit 23 executes a parity read operation (S204).

[0184] The read control unit 23 controls the error correction circuit 24 to execute erasure correction decoding processing using the read data, and decodes the data to be read (S205).

[0185] Moreover, if the power consumption is equal to or greater than the preset threshold (S242_No), the read control unit 23 waits until the operation of the command stacked in the command queue is completed and a normal read operation becomes possible (S243).

[0186] If immediate reading is possible (S241_Yes), if there is no parity data (S203_No), or after the standby state of step S243 is released, the read control unit 23 executes a normal read operation of the data to be read (S206).

[0187] 2.5 Fifth Example Next, a fifth example of the second embodiment will be described.

[0188] 2.5.1 Configuration of the read control unit First, an example of the configuration of the read control unit 23 will be described with reference to Fig. 26. Fig. 26 is a block diagram showing the configuration of the read control unit 23.

[0189] As shown in FIG. 26, the parity decoding decision circuit 231 of this example includes a decider 232 .

[0190] The determiner 232 outputs true as a determination result when all the determinations based on a plurality of determination conditions are true. For example, the determiner 232 determines true or false based on three determination conditions. For example, the first determination condition is determined to be true when the difference between the normal read operation completion time and the parity read operation completion time is longer than a preset threshold. The second determination condition is determined to be true when the congestion degree of the target memory chip CP is greater than a preset threshold. The third determination condition is determined to be true when the power consumption is less than a preset threshold. Note that the determination conditions are not limited to these.

[0191] If the determination result of the determiner 232 is true, the parity decoding determination circuit 231 determines to execute a parity read operation.

[0192] 2.5.1 Read operation flow Next, an example of the flow of a read operation will be described with reference to Fig. 27. Fig. 27 is a flowchart of the read operation.

[0193] As shown in FIG. 27, first, the memory controller 20 receives a read request from the host device 2 (S201).

[0194] The read control unit 23, like step S221 in the second example of the second embodiment, checks whether real-time reading of the read target data is executable in the target plane PLN of the target memory chip CP in which the read target data is stored (S251).

[0195] If immediate reading is not possible (S251_No), the read control unit 23 checks whether or not there is parity data corresponding to the data to be read in the read buffer 28 or in another memory chip CP (S203).

[0196] If parity data is present (S203_Yes), the read control unit 23 checks whether the determination result of the determiner 232 is true (S252).

[0197] If the determination result is true (S252_Yes), the read control unit 23 executes a parity read operation (S204).

[0198] The read control unit 23 controls the error correction circuit 24 to execute erasure correction decoding processing using the read data, and decodes the data to be read (S205).

[0199] If the determination result is not true, that is, false (S252_No), the read control unit 23 waits until the operation of the command stacked in the command queue is completed and a normal read operation becomes possible (S253).

[0200] If immediate reading is possible (S251_Yes), if there is no parity data (S203_No), or after the standby state of step S253 is released, the read control unit 23 executes a normal read operation of the data to be read (S206).

[0201] 2.6 Example 6 Next, a sixth example of the second embodiment will be described below. Figures 28 and 29 are flowcharts of a read operation.

[0202] As shown in FIG. 28, first, the memory controller 20 receives a read request from the host device 2 (S201).

[0203] The read control unit 23, like step S221 in the second example of the second embodiment, checks whether real-time reading of the read target data is executable in the target plane PLN of the target memory chip CP in which the read target data is stored (S261).

[0204] If immediate reading is not possible (S261_No), the read control unit 23 checks whether or not there is parity data corresponding to the data to be read in the read buffer 28 or in another memory chip CP (S203).

[0205] If there is parity data (S203_Yes), the read control unit 23 checks the power consumption in the memory system 3 (S262), similarly to step S242 in the fourth example of the second embodiment.

[0206] As shown in FIG. 29, when the power consumption is smaller than the preset first threshold (S262_Yes), the read control unit 23 executes the parity read operation (S204).

[0207] The read control unit 23 controls the error correction circuit 24 to execute erasure correction decoding processing using the read data, and decodes the data to be read (S205).

[0208] Furthermore, if the power consumption is greater than or equal to a preset first threshold (S262_No), the read control unit 23 checks whether the length of time remaining until the ongoing write or erase operation is completed is longer than a preset second threshold (S263), similar to step S211 in the first example of the second embodiment.

[0209] If the length of time until the ongoing write operation or erase operation is completed is longer than a preset second threshold (S263_Yes), the read control unit 23 executes a suspend process of the ongoing write operation or erase operation (S264). After the suspension, the read control unit 23 executes a normal read operation of the data to be read (S265). When the normal read operation is completed, the read control unit 23 executes a resume process of the suspended write operation or erase operation (S266).

[0210] Furthermore, if the length of time until the ongoing write or erase operation is completed is equal to or less than a preset second threshold (S263_No), the read control unit 23 waits until the operation of the command stacked in the command queue is completed and a normal read operation becomes possible (S267).

[0211] If immediate reading is possible (S261_Yes), if there is no parity data (S203_No), or after the standby state of step S267 is released, the read control unit 23 executes a normal read operation of the data to be read (S268).

[0212] 2.7 Effects of this embodiment With the configuration according to this embodiment, the same effects as those of the first embodiment can be obtained.

[0213] Furthermore, in the configuration according to the first example of the present embodiment, if the time until the ongoing write operation or erase operation is completed is equal to or less than a threshold value, the read control unit 23 can select a normal read operation without executing a parity read operation. This can reduce the collision probability between the parity read operation and the next write operation or erase operation. Therefore, the memory system 3 can improve the write performance. Furthermore, by selecting a normal read operation, the total number of executions of the read operation can be reduced compared to the parity read operation. This can also reduce the collision probability of the read operation of each plane PLN in the domain DM. Therefore, it is possible to suppress an increase in the tail latency of the read operation due to congestion of the read operation.

[0214] Furthermore, in the configuration according to the second example of the present embodiment, when the difference between the normal read operation completion time and the parity read operation completion time is equal to or less than a preset threshold, that is, when the difference between the normal read operation completion time and the parity read operation completion time is relatively small, the read control unit 23 can select the normal read operation without executing the parity read operation. This can reduce the collision probability between the parity read operation and the next write operation. Therefore, the memory system 3 can improve the write performance.

[0215] Furthermore, in the configuration according to the third example of the present embodiment, when the degree of congestion of the memory chip CP to be read is equal to or lower than the threshold, the read control unit 23 can select the normal read operation without executing the parity read operation. This makes it possible to suppress an increase in the degree of congestion of the memory chip CP to be the target of the parity read operation.

[0216] Furthermore, in the configuration according to the fourth example of the present embodiment, when the power consumption of the memory system 3 is equal to or greater than the threshold, the read control unit 23 can select a normal read operation without executing a parity read operation. This allows the memory system 3 to suppress an increase in power consumption.

[0217] Furthermore, with the configuration according to the fifth example of this embodiment, the same effects as those of the second to fourth examples of this embodiment can be obtained.

[0218] Furthermore, in the configuration according to the sixth example of this embodiment, when the power consumption of the memory system 3 is equal to or greater than the first threshold and the length of time until the ongoing write or erase operation is completed is longer than the second threshold, the read control unit 23 can suspend the ongoing operation. After the suspension, the read control unit 23 can execute a normal read operation. Then, after the normal read operation, the read control unit 23 can resume the suspended operation. This allows the memory system 3 to suppress an increase in the tail latency of the read operation. Therefore, the memory system 3 can improve the processing capacity.

[0219] 3. Third embodiment Next, a third embodiment will be described. In the third embodiment, a data read operation in garbage collection will be described. Below, the differences from the first and second embodiments will be mainly described.

[0220] Garbage collection is also called compaction. Garbage collection is a process of reading (collecting) valid data from multiple blocks BLK and rewriting (copying) it to another block BLK. The block BLK from which data has been read by garbage collection is made erasable. When data is rewritten in the non-volatile memory 10, the new data is written to another memory cell transistor (cell unit CU). For this reason, as data rewriting progresses, the amount of invalid data increases in the block BLK. If even one valid data remains in the block BLK even if the amount of invalid data increases, the erase operation of the block BLK cannot be executed. For example, garbage collection is executed when the number of erasable blocks BLK decreases.

[0221] 3.1 Read Behavior in Garbage Collection Next, referring to FIG. 30, an example of the flow of the read operation in the garbage collection will be described. FIG. 30 is a flow chart of the read operation in the garbage collection. In the read operation in the garbage collection of this embodiment, the data of a plurality of blocks BLK corresponding to the erasure correction data group is read at once. In the following description, the erasure correction data group is composed of N pieces of write data (N is any integer) and one piece of parity data. Note that the read operation of this embodiment can be used when reading the erasure correction data group at once, such as a sequential read operation. The sequential read operation is a read operation that reads the data of a plurality of pages stored in the cell unit CU at once.

[0222] As shown in Fig. 30, the read control unit 23 extracts (N+1) blocks BLK that contain (N+1) pieces of data that correspond to the erasure correction data group (S301). The extracted (N+1) blocks BLK are each included in the plane unit PU of the different memory chips CP in the stream STM.

[0223] The read control unit 23 checks whether there is a memory chip CP that is currently executing a write operation or an erase operation (S302).

[0224] If there is a memory chip CP currently executing a write operation or an erase operation (S302_Yes), the read control unit 23 reads data of the target block BLK of the N memory chips CP excluding the memory chip CP currently executing a write operation or an erase operation (S303).

[0225] Moreover, if there is no memory chip CP currently executing a write operation or an erase operation (S302_No), the read control unit 23 checks the congestion degree of each memory chip CP (S305).

[0226] If there is a congested memory chip CP (S305_Yes), the read control unit 23 reads data of the target blocks BLK of the N memory chips CP with the least congestion degree (S306). More specifically, for example, if the congestion degree of the most congested memory chip CP is equal to a preset threshold value, the read control unit 23 determines that the memory chip is congested. Then, the read control unit 23 reads data of the target blocks BLK of the N memory chips CP excluding the memory chip CP with the most congested degree.

[0227] After reading data of the target blocks BLK of the N memory chips CP in step S303 or step S306, the read control unit 23 uses the read data to decode data of the target blocks BLK of the memory chips CP from which data has not been read (S304).

[0228] Furthermore, if there is no congested memory chip CP (S305_No), the read control unit 23 reads the write data from the target blocks BLK of the N memory chips CP corresponding to the write data (S307).

[0229] 3.2 Effects of this embodiment With the configuration according to this embodiment, the same effects as those of the first and second embodiments can be obtained.

[0230] 4. Modifications, etc. The memory system according to the above embodiment includes a memory controller (20) configured to independently control a plurality of memory chips (CP) each including a first memory area (PU0) and a second memory area (PU1), a first group (STM0) including a plurality of first memory areas included in each of the plurality of memory chips, and a second group (STM1) including a plurality of second memory areas included in each of the plurality of memory chips, configure a data group (erasure correction data group) including a plurality of pages of write data and first data including erasure correction codes corresponding to the plurality of pages of write data, and distribute the plurality of pages of write data and the first data of the data group to a plurality of first memory areas of the first group and write them at different timings.

[0231] According to the above embodiment, a memory system with improved processing power can be provided.

[0232] The above embodiments can be combined as much as possible.

[0233] In the above embodiment, "connected" includes a state in which something else, such as a transistor or a resistor, is interposed between them and indirectly connected.

[0234] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0235] 1...data processing device, 2...host device, 3...memory system, 10...non-volatile memory, 20...memory controller, 21...host interface circuit, 22...write control unit, 23...read control unit, 24...error correction circuit, 25...buffer memory, 26...NAND interface circuit, 27...write buffer, 28...read buffer, 101...sequencer, 102, 102a, 102a_0 to 102a_3, 102b, 102b_0 to 102b_3...memory cell array, 103, 103a, 103b...row decoder, 104, 104a, 104b...sense amplifier, 221...stream control unit, 221a...stream 0 control unit, 221b...stream 1 control unit, 222...write monitoring unit, 231...parity decoding decision circuit, 232...decision unit, 271...stream buffer, 271a...stream stream 0 buffer, 271b...stream 1 buffer, 272, 272a, 272b...data buffer, 273, 273a, 273b...parity buffer, BL, BL0 to BLn...bit line, CP, CP0, CP0_0 to CP0_3, CP1_0 to CP1_3, CP2_0 to CP2_3, CP3_0 to CP3_3...memory chip, DM, DM0 to DM3...domain, MC, MC0 to MC7...memory cell transistor, MU, MU0 to MU3...memory unit, NB, NB0 to NB3...NAND bus, PLN, PLN0, PLN1...plane, PU, ​​PU0, PU1...plane unit, SGD, SGD0 to SGD3, SGS...select gate line, ST1, ST2...select transistor, STM, STM0, STM1...stream, SU, SU0 to SU3...string unit, WL, WL0 to WL7...word line

Claims

1. Each of the first to n (where n is an integer of 2 or more) memory chips includes a first memory area and a second memory area, A memory controller configured to independently control a first group including a plurality of first memory areas contained in each of the first to nth memory chips, and a second group including a plurality of second memory areas contained in each of the first to nth memory chips. Equipped with, The aforementioned memory controller A data group is formed that includes data written on multiple pages and first data including an erasure correction code corresponding to the data written on multiple pages. The write data of the multiple pages of the data group and the first data are written in a distributed manner to the multiple first memory areas included in the first group. While a write or erase operation is being performed in the first memory area of ​​the first memory chip, a read operation can be performed in the second memory area of ​​the first memory chip. When the first memory chip is performing a write or erase operation, in response to a request to read first write data, which is data written to the first memory chip from among the multiple pages of write data included in the data group, the first write data is obtained by reading data from the first memory area of ​​each of the second to n memory chips and performing a decoding process on the read data. It is further constructed in such a way. Memory system.

2. The memory controller is configured to be able to perform a read operation in the first memory area of ​​the second memory chip while performing a write operation or erase operation in the first memory area of ​​the first memory chip, and to be able to perform a write operation, erase operation, or read operation in the second memory area of ​​the second memory chip. The memory system according to claim 1.

3. Each of the first memory area and the second memory area includes a plurality of memory cell arrays, Each of the aforementioned multiple memory cell arrays is connected to a different sense amplifier and a row decoder. The memory system according to claim 1.

4. The plurality of memory cell arrays in the first memory area include a first memory cell array included in the first management unit, The plurality of memory cell arrays in the second memory area include the second memory cell array included in the first management unit. The memory controller is configured to manage the second memory cell array so that it does not perform a write or erase operation while a write or erase operation is being performed in the first memory cell array. The memory system according to claim 3.

5. The memory controller is configured to manage the second memory cell array so as not to perform a read operation while a read operation is being performed in the first memory cell array. The memory system according to claim 4.

6. The plurality of memory cell arrays in the first memory area further include a third memory cell array included in the second management unit, The memory controller is configured to perform write operations or erase operations in parallel in the first memory cell array and the third memory cell array. The memory system according to claim 4.

7. The memory controller includes a first buffer capable of storing the write data for the plurality of pages, and a second buffer capable of storing the first data, The memory controller is configured to repeatedly store the data to be written for multiple pages in the first buffer and generate the first data in the data group writing operation until the data to be written for multiple pages reaches a predetermined number of pages. The memory system according to claim 1.

8. The memory controller is configured to monitor the write operation or erase operation being performed on the first group if it is performing a write operation or erase operation on data different from that of the data group, and to perform the write operation on the data group after the write operation or erase operation being performed has finished. The memory system according to claim 7.

9. The memory controller is configured to execute the first group write operation and the second group write operation in parallel. The memory system according to claim 1.

10. The memory controller is configured to execute multiple write operations corresponding to each of the multiple pages of write data and the first data without duplication. The memory system according to claim 1.

11. The memory controller is configured to perform erase operations in parallel in each of the plurality of first memory regions. The memory system according to claim 1.

12. The memory controller is configured to interrupt the erase operation and perform a read operation when an erase operation is being performed in the first group, The memory system according to claim 1.

13. The memory controller is configured such that, in a plurality of write operations corresponding to each of the plurality of page write data and the first data, one of the plurality of write operations and another of the plurality of write operations are executed such that a portion of their durations overlap with each other. The memory system according to claim 1.

14. The memory controller is configured such that when reading the first write data from the first memory chip, if the first memory chip is performing a write operation or erase operation, it checks the length of time until the write operation or erase operation is completed, and if the length of time is longer than a preset threshold, it reads other data from the data group from other memory chips and decodes the first write data, and if the length of time is less than or equal to the threshold, it reads the first write data from the first memory chip. The memory system according to claim 1.

15. The memory controller is configured such that, when a waiting period occurs when executing a first read operation to read the first write data from the first memory chip, it checks the length of a first time until the first read operation is completed and the length of a second time until a second read operation to read other data in the data group contained in another memory chip is completed, and if the difference between the length of the first time and the length of the second time is greater than a preset threshold, it executes the second read operation, and if the difference is less than or equal to the threshold, it executes the first read operation. The memory system according to claim 1.

16. The memory controller is configured such that, when a waiting period occurs when executing a first read operation to read the first write data from the first memory chip, it checks the congestion level of the first memory chip, and if the congestion level is greater than a preset threshold, it executes a second read operation to read other data of the data group contained in another memory chip, and if the congestion level is less than or equal to the threshold, it executes the first read operation. The memory system according to claim 1.

17. The memory controller is configured such that, when a waiting period occurs when executing a first read operation to read the first write data from the first memory chip, it checks the power consumption, and if the power consumption is less than a preset first threshold, it executes a second read operation to read other data in the data group contained in another memory chip, and if the power consumption is equal to or greater than the first threshold, it executes the first read operation. The memory system according to claim 1.

18. The memory controller is configured to suspend the write operation or erase operation and then execute the first read operation if the power consumption is equal to or greater than the first threshold and the time required for the write operation or erase operation being performed on the first memory chip to be completed is longer than a preset second threshold. The memory system according to claim 17.

19. The memory controller is configured to distribute the write data of the multiple pages of the data group and the first data to the multiple first memory areas included in the first group and write them at different timings. The memory system according to claim 1.

20. The first memory chip includes a plurality of first memory cells corresponding to the write operation or erase operation being performed, and a plurality of second memory cells that differ from the first memory cells and on which the first write data has been written. The memory system according to claim 1.

Images