Method for manufacturing laminate and laminate

Abstract

To provide a method for manufacturing a laminate with improved adhesive strength between organic insulating layers while keeping production costs low.SOLUTION: A method for manufacturing a laminate comprises the steps of: forming a first organic insulating layer including a first thermosetting resin and first inorganic oxide particles on a first support substrate; polishing and planarizing the first surface of the first organic insulating layer; and attaching the polished first surface to the second surface of a second organic insulating layer containing a second thermosetting resin and second inorganic oxide particles.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present disclosure relates to a method for producing a stack and a stack, for example, to a method for producing a stack (semiconductor device) including a semiconductor chip, and a stack including a semiconductor chip. [Background technology]

[0002] In recent years, various direct bonding techniques for directly bonding metal connection terminals have been proposed as a method for connecting vertically stacked semiconductor chips together or connecting a semiconductor chip to a semiconductor package such as a silicon interposer (see, for example, Patent Documents 1 to 3). In connection methods using direct bonding techniques, not only are the connection terminals bonded together, but also the insulating layers disposed around the connection terminals are bonded together. An inorganic insulating material such as silicon oxide is used as the insulating layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2020 / 0135636 [Patent Document 2] US Patent Application Publication No. 2020 / 0135683 [Patent Document 3] US Patent Application Publication No. 2020 / 0135684 Summary of the Invention [Problem to be solved by the invention]

[0004] In the direct bonding technique using an inorganic insulating material as an insulating layer, defects may occur in the adhesion between the insulating layers due to the influence of cutting waste (debris) generated in processes such as dicing or surface irregularities. In addition, in order to use an inorganic insulating material as an insulating layer, it is necessary to apply expensive semiconductor processing processes such as wiring formation and via formation, which tends to increase the manufacturing cost of the semiconductor device. Therefore, it has been considered to embed debris and the like in the organic resin material or suppress surface irregularities during heat molding by using a direct bonding technique using an organic insulating material such as a resin material that is softer and cheaper than inorganic materials as an insulating layer. On the other hand, the adhesive strength between organic insulating resin materials may be lower than the adhesive strength between inorganic insulating materials, and it is desired to increase the adhesive strength between organic insulating layers while suppressing manufacturing costs. [Means for solving the problem]

[0005] As one aspect, the present disclosure provides a method for producing a laminate, comprising the steps of forming a first organic insulating layer containing a first thermosetting resin and first inorganic oxide particles on a first support substrate, polishing and planarizing a first surface of the first organic insulating layer, and bonding the polished first surface to a second surface of a second organic insulating layer containing a second thermosetting resin and second inorganic oxide particles.

[0006] In this method for producing a laminate, the first and second organic insulating layers contain a thermosetting resin and inorganic oxide particles, and such first and second organic insulating layers are bonded together. In this case, the thermosetting resins contained in the first and second organic insulating layers are bonded together, and the inorganic oxide particles contained in the first and second organic insulating layers are bonded together. This makes it possible to further increase the adhesive strength between the first organic insulating layer and the second organic insulating layer while suppressing manufacturing costs. Note that when inorganic oxide particles are contained in each organic insulating layer, the surface roughness may become rough, but in this production method, at least one of the organic insulating layers is polished before bonding. This ensures sufficient accuracy and adhesive strength when bonding.

[0007] In the above-mentioned method for producing a laminate, in the step of polishing the first organic insulating layer, the first organic insulating layer may be polished so that the arithmetic mean roughness of the first surface is 50 nm or less. In this case, it is possible to more reliably improve the accuracy and adhesive strength when bonding the first organic insulating layer to the second organic insulating layer. The arithmetic mean roughness used here is the arithmetic mean roughness (Ra) specified in JIS B 0601 2001.

[0008] In the method for producing the laminate, the content of the first inorganic oxide particles may be 15 to 70 volume % relative to the total volume of the first organic insulating layer, which can further increase the adhesive strength between the first and second organic insulating layers.

[0009] The method for producing the laminate may further include a step of grinding the first organic insulating layer, and the step of polishing the first organic insulating layer may include polishing the ground first surface of the first organic insulating layer. When inorganic oxide particles are contained in each organic insulating layer, grinding the insulating layer to a predetermined thickness may result in a rough surface. However, in the present production method, at least one of the ground surfaces is polished before bonding. This ensures sufficient accuracy and adhesive strength when bonding.

[0010] The method for producing the laminate may further include a step of forming a second organic insulating layer containing a second thermosetting resin and second inorganic oxide particles on a second support substrate, and a step of polishing and planarizing a second surface of the second organic insulating layer. In this production method, the laminating step includes laminating the planarized first surface to the planarized second surface. In this case, it is possible to further increase the adhesive strength between the first organic insulating layer and the second organic insulating layer.

[0011] In the above-mentioned method for producing a laminate, in the step of polishing the second organic insulating layer, the second organic insulating layer may be polished so that the arithmetic mean roughness of the second surface is 50 nm or less. In this case, it is possible to more reliably improve the accuracy and adhesive strength when bonding the second organic insulating layer to the first organic insulating layer. The arithmetic mean roughness used here is the arithmetic mean roughness (Ra) specified in JIS B 0601 2001.

[0012] In the method for producing the laminate, the content of the second inorganic oxide particles may be 15% by volume to 70% by volume of the total volume of the second organic insulating layer, which can further increase the adhesive strength between the first organic insulating layer and the second organic insulating layer.

[0013] The method for producing the laminate may further include a step of grinding the second organic insulating layer, and the step of polishing the second organic insulating layer may include polishing the ground second surface of the second organic insulating layer. When inorganic oxide particles are contained in each organic insulating layer, grinding the insulating layer to a predetermined thickness may result in a rough surface. However, in the present production method, the ground surface is polished before bonding. This ensures sufficient accuracy and adhesive strength when bonding.

[0014] The method for producing the laminate may further include a step of forming a first wiring electrode on a first support substrate. In the step of forming the first organic insulating layer in this method, the first wiring electrode may be sealed with a first organic insulating material containing a first thermosetting resin and first inorganic oxide particles. This allows the first wiring electrode to be protected by the first organic insulating material.

[0015] In the above-mentioned method for producing a laminate, before the step of polishing the first organic insulating layer, the first organic insulating layer may be ground so that the connection terminal of the first wiring electrode is exposed from the first surface of the first organic insulating layer, thereby making it possible to more reliably connect the first wiring electrode to other wiring electrodes, etc.

[0016] The method for producing the laminate may further include a step of forming a second wiring electrode on a second support substrate, and a step of forming a second organic insulating layer containing a second thermosetting resin and a second inorganic oxide on the second support substrate so as to seal the second wiring electrode with a second organic insulating material containing a second thermosetting resin and a second inorganic oxide particle. In this production method, in the bonding step, when bonding the first surface of the first organic insulating layer to the second surface of the second organic insulating layer, the connection terminal of the first wiring electrode may be bonded to the connection terminal of the second wiring electrode. In this case, the first connection terminal and the second connection terminal can be bonded more reliably.

[0017] The method for producing the laminate may further include a step of arranging a first semiconductor chip on a first support substrate. In the method, in the step of forming the first organic insulating layer, the first semiconductor chip may be sealed with a first organic insulating material containing a first thermosetting resin and first inorganic oxide particles. This allows the first semiconductor chip to be protected by the first organic insulating material.

[0018] In the above-mentioned method for producing a laminate, before the step of polishing the first organic insulating layer, the first organic insulating layer may be ground so that the connection terminals of the first semiconductor chip are exposed from the first surface of the first organic insulating layer, thereby enabling the first semiconductor chip to be more reliably connected to other semiconductor chips, etc.

[0019] The method for producing the laminate may further include a step of disposing a second semiconductor chip on a second support substrate, and a step of forming a second organic insulating layer containing a second thermosetting resin and a second inorganic oxide on the second support substrate so as to seal the second semiconductor chip with a second organic insulating material containing a second thermosetting resin and a second inorganic oxide particle. In this production method, in the bonding step, when bonding the first surface of the first organic insulating layer to the second surface of the second organic insulating layer, the connection terminals of the first semiconductor chip may be bonded to the connection terminals of the second semiconductor chip. In this case, the first semiconductor chip and the second semiconductor chip can be bonded more reliably.

[0020] In another aspect, the present disclosure provides a laminate including a first support substrate, a first organic insulating layer including a cured product of a first thermosetting resin and first inorganic oxide particles and formed on the first support substrate, and a second organic insulating layer including a cured product of a second thermosetting resin and second inorganic oxide particles and bonded to the first organic insulating layer.

[0021] In this laminate, the first and second organic insulating layers contain a thermosetting resin and inorganic oxide particles, and the first and second organic insulating layers are bonded together. In this case, the thermosetting resins contained in the first and second organic insulating layers are bonded together, and the inorganic oxide particles contained in the first and second organic insulating layers are bonded together. This makes it possible to produce a laminate with increased adhesive strength between the first and second organic insulating layers while reducing manufacturing costs.

[0022] The stack may further include a semiconductor chip disposed on or within the first supporting substrate.

[0023] The laminate may further include a first wiring electrode, at least a part of which is disposed in the first organic insulating layer, a connection terminal of which is exposed from a first surface of the first organic insulating layer that is bonded to the second organic insulating layer, the first wiring electrode being connected to the semiconductor chip, and a second wiring electrode, at least a part of which is disposed in the second organic insulating layer, a connection terminal of which is exposed from a second surface of the second organic insulating layer that is bonded to the first organic insulating layer. In this laminate, the connection terminal of the first wiring electrode and the connection terminal of the second wiring electrode may be joined. This makes it possible to obtain a laminate in which the connection terminals protected by the organic insulating layer are connected to each other.

[0024] In the above laminate, the semiconductor chip may be on a first supporting substrate, at least a portion of which is disposed in the first organic insulating layer, and the connection terminals of the semiconductor chip may be exposed from a first surface of the first organic insulating layer which is bonded to the second organic insulating layer.

[0025] In the laminate, the content of the first inorganic oxide particles relative to the total volume of the first organic insulating layer may be 15% by volume to 70% by volume. In this case, the laminate can have a further increased adhesive strength between the first organic insulating layer and the second organic insulating layer. In this laminate, the content of the second inorganic oxide particles relative to the total volume of the second organic insulating layer may be 15% by volume to 70% by volume.

[0026] In the laminate, the first inorganic oxide particles and the second inorganic oxide particles may be bonded to each other on the surface where the first organic insulating layer and the second organic insulating layer are bonded to each other, thereby making it possible to obtain a laminate having a more reliably increased bonding strength between the first organic insulating layer and the second organic insulating layer. Effect of the Invention

[0027] According to the present disclosure, it is possible to provide a laminate in which the adhesive strength between organic insulating layers is increased while keeping production costs down. [Brief description of the drawings]

[0028] [Figure 1] FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present disclosure. [Diagram 2] 2(a) to 2(c) are diagrams illustrating a method for manufacturing the semiconductor device shown in FIG. [Diagram 3] 3(a) to 3(c) are diagrams showing a method for manufacturing the semiconductor device shown in FIG. 1, illustrating steps subsequent to those shown in FIG. [Figure 4] 4(a) to 4(c) are diagrams showing a method for manufacturing the semiconductor device shown in FIG. 1, illustrating steps subsequent to those shown in FIG. [Diagram 5] FIG. 5 is a plan view showing the surface of the organic insulating layer after it has been polished in the step shown in FIG. 4(c). [Figure 6] FIG. 6(a) is a cross-sectional view showing the organic insulating layer formed in the step shown in FIG. 4(a), and FIG. 6(b) is a cross-sectional view showing the organic insulating layer after being polished in the step shown in FIG. 4(c). [Figure 7] FIG. 7 is a diagram showing a method of manufacturing the semiconductor device shown in FIG. 1, illustrating a step subsequent to that shown in FIG. [Figure 8] FIG. 8 is a cross-sectional view showing a cross section of a semiconductor device in which organic insulating layers are connected to each other in the step shown in FIG. [Figure 9] 9(a) to 9(c) are diagrams showing a method for manufacturing a semiconductor device according to a second embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram showing the method for manufacturing a semiconductor device according to the second embodiment, showing a step subsequent to that shown in FIG. [Figure 11] FIG. 11 is a cross-sectional view showing the semiconductor device according to the second embodiment. [Figure 12] 12(a) to 12(c) are diagrams showing a method for manufacturing a semiconductor device according to a third embodiment of the present disclosure. [Figure 13] FIG. 13 is a cross-sectional view showing the semiconductor device according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the same or equivalent parts are given the same reference numerals, and duplicated descriptions are omitted. Furthermore, positional relationships such as up, down, left, right, etc. are based on the positional relationships shown in the drawings unless otherwise specified. When terms such as "left", "right", "front", "back", "up", "down", "upper", and "lower" are used in the description and claims of this specification, these are intended for explanation purposes only, and do not necessarily mean that the relative positions are always the same. Furthermore, the dimensional ratios of the drawings are not limited to those shown in the drawings.

[0030] In this specification, the term "layer" includes a structure having a shape formed over the entire surface as well as a structure having a shape formed on a portion of the surface when observed in a plan view. In addition, in this specification, the term "process" includes not only an independent process, but also a process that cannot be clearly distinguished from other processes as long as the intended effect of the process is achieved. In addition, a numerical range indicated using "~" indicates a range including the numerical values ​​before and after "~" as the minimum and maximum values, respectively.

[0031] (Configuration of Semiconductor Device) Fig. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present disclosure. As shown in Fig. 1, the semiconductor device 1 (laminate) includes a support substrate 2 (first support substrate), a wiring electrode 3, an organic insulating layer 4 (first organic insulating layer), a support substrate 5 (second support substrate), a wiring electrode 6, and an organic insulating layer 7 (second organic insulating layer).

[0032] The supporting substrate 2 and the supporting substrate 5 are not particularly limited, and are highly rigid substrates, such as silicon plates, glass plates, SUS plates, substrates containing glass cloth, sealing resin substrates containing semiconductor chips, etc. At least one of the supporting substrate 2 and the supporting substrate 5 may be a substrate having a built-in semiconductor chip, or both the supporting substrate 2 and the supporting substrate 5 may be substrates having a built-in semiconductor chip.

[0033] The thickness of the support substrate 2 and the support substrate 5 is not particularly limited, but may be, for example, 0.2 to 2.0 mm. When the support substrate 2 and the support substrate 5 are 0.2 mm or more, the handleability of the substrate can be improved. Furthermore, when the support substrate 2 and the support substrate 5 are 2.0 mm or less, the material cost can be reduced. The support substrate 2 and the support substrate 5 may be in a wafer shape or a panel shape. The size of the support substrate 2 and the support substrate 5 is not particularly limited, but may be, for example, a wafer with a diameter of 200 mm, 300 mm, or 450 mm, or a rectangular panel with one side of 300 to 700 mm.

[0034] The wiring electrode 3 is a minute electrode formed on the support substrate 2. When the wiring electrode 3 is formed by plating or the like, it may be configured to include a seed layer portion 3a and a plated portion 3b. The wiring electrode 3 is formed of a conductive material such as copper (Cu). The wiring electrode 3 may be an electrode pin, and although only two electrode pins are shown in FIG. 1, the number of electrode pins may be 500 or more, and in a finer case, the number of electrode pins may be 1000 to 10000 or more. In this case, the gap between the electrode pins may be 100 μm or less, and in a finer case, the gap between the electrode pins may be 20 to 100 μm.

[0035] The organic insulating layer 4 is an insulating layer formed on the support substrate 2, including a cured product 4a of a thermosetting resin (a cured product of a first thermosetting resin) and inorganic oxide particles 4b (first inorganic oxide particles) (see FIG. 8). The thickness of the organic insulating layer 4 may be, for example, 10 to 300 μm. When the thickness of the organic insulating layer 4 is 10 μm or more, it is possible to ensure the insulation of the wiring electrode 3 and to ensure the adhesive force when the organic insulating layer 4 is bonded to the organic insulating layer 7. When the thickness of the organic insulating layer 4 is 300 μm or less, the thickness of the entire semiconductor device 1 can be reduced. The wiring electrode 3 described above is protected by being embedded in the organic insulating layer 4 so that the connection terminal 3c is exposed from a surface 4c (first surface) of the organic insulating layer 4 that is bonded to the organic insulating layer 7.

[0036] The thermosetting resin used in the organic insulating layer 4 is not particularly limited and may be a known thermosetting resin, such as an epoxy resin, an acrylic resin, a methacrylic resin, a maleimide resin, a phenolic resin, an unsaturated imide resin, a cyanate resin, an isocyanate resin, a benzoxazine resin, an oxetane resin, an amino resin, an unsaturated polyester resin, an allyl resin, a dicyclopentadiene resin, a silicone resin, a triazine resin, a melamine resin, etc. Among these, the thermosetting resin used in the organic insulating layer 4 is preferably an epoxy resin.

[0037] The inorganic oxide particles contained in the organic insulating layer 4 are not particularly limited, and known inorganic oxide particles can be used, such as silica (SiO2), alumina (Al2O3), titania (TiO2), tantalum oxide (Ta2O5), zirconia (ZrO2), zinc oxide (ZnO), etc. The inorganic oxide particles may be used alone or in combination of two or more types. As an example, the inorganic oxide particles contained in the organic insulating layer 4 are silica.

[0038] The content of the inorganic oxide particles contained in the organic insulating layer 4 is, for example, 15 volume % to 70 volume % with respect to the total volume of the organic insulating layer 4. When the content of the inorganic oxide particles is 15 volume % or more of the total volume, the ratio of the cured thermosetting resin contained in the organic insulating layer 4 is reduced, thereby suppressing the coefficient of thermal expansion (CTE) of the organic insulating layer 4, and it becomes possible to reduce warping when heat is applied to the semiconductor device 1. Furthermore, when the content of the inorganic oxide particles is 70 volume % or less of the total volume, it becomes possible to secure a sufficient adhesion area between the thermosetting resins and increase the adhesive strength between the organic insulating layer 4 and the organic insulating layer 7.

[0039] The wiring electrode 6 is a minute electrode formed on the support substrate 5. When the wiring electrode 6 is formed by plating or the like, it may be configured to include a seed layer portion 6a and a plating portion 6b. The wiring electrode 6 is formed of a conductive material such as copper, similar to the wiring electrode 3. The wiring electrode 6 is an electrode provided corresponding to the wiring electrode 3, and may be an electrode pin, similar to the wiring electrode 3. In FIG. 1, only two electrodes are shown as the wiring electrode 6, but the number of electrode pins may be 500 or more, and in a finer case, the number of electrode pins may be 1000 to 10000 or more. In this case, the gap between the electrode pins may be 100 μm or less, and in a finer case, the gap between the electrode pins may be 20 to 100 μm.

[0040] The organic insulating layer 7 includes a cured product 7a of a thermosetting resin (a cured product of a second thermosetting resin) and inorganic oxide particles 7b (second inorganic oxide particles), and is an insulating layer formed on the support substrate 5 (see FIG. 8). The thickness of the organic insulating layer 7 may be, for example, 10 to 300 μm, similar to the organic insulating layer 4. The wiring electrodes 6 described above are protected by being embedded in the organic insulating layer 7 such that the connection terminals 6c are exposed from a surface 7c (second surface) of the organic insulating layer 7 that is bonded to the organic insulating layer 4.

[0041] In such a semiconductor device 1, the wiring electrodes 3 and 6 are provided in the organic insulating layers 4 and 7 so as to correspond to each other, and the connection terminals 3c and 6c are bonded to each other. In addition, the cured products 4a and 7a of the thermosetting resin contained in the organic insulating layers 4 and 7 are also bonded to each other, and the inorganic oxide particles 4b and 7b contained in the organic insulating layers 4 and 7 are also bonded to each other. In particular, the inorganic oxide particles 4b and 7b are bonded to each other firmly because they are bonded to each other by inorganic oxides, which makes the connection between the organic insulating layers 4 and 7 in the semiconductor device 1 more reliable.

[0042] (Method of manufacturing a semiconductor device) Next, the manufacturing method of the semiconductor device 1 (the method of manufacturing the laminate) will be described in order with reference to FIG. 2 to FIG. 8. (a) to (c) of FIG. 2 are diagrams showing the manufacturing method of the semiconductor device shown in FIG. 1. (a) to (c) of FIG. 3 are diagrams showing the manufacturing method of the semiconductor device shown in FIG. 1, showing the steps following FIG. 2. (a) to (c) of FIG. 4 are diagrams showing the manufacturing method of the semiconductor device shown in FIG. 1, showing the steps following FIG. 3. FIG. 5 is a plan view showing the surface of the organic insulating layer after polishing in the step shown in FIG. 4(c). (a) of FIG. 6 is a cross-sectional view showing the organic insulating layer formed in the step shown in FIG. 4(a), and (b) of FIG. 6 is a cross-sectional view showing the organic insulating layer after polishing in the step shown in FIG. 4(c). FIG. 7 is a diagram showing the manufacturing method of the semiconductor device shown in FIG. 1, showing the steps following FIG. 4. FIG. 8 is a cross-sectional view showing the cross section of the semiconductor device in which the organic insulating layers are connected to each other in the step shown in FIG. 7. For ease of explanation, the wiring electrodes are omitted in FIG. 5, FIG. 6, and FIG. 8.

[0043] First, as shown in FIG. 2(a), a seed layer 21 is formed on a support substrate 20 (first support substrate, second support substrate). The seed layer 21 is a portion that serves as a seed when forming electrolytic copper plating, which will be described later, and is formed of, for example, nickel or the like. The support substrate 20 is a highly rigid substrate, and is not particularly limited, but may be, for example, a silicon plate, a glass plate, a SUS plate, a substrate containing glass cloth, or a sealing resin substrate containing a semiconductor chip. The thickness of the support substrate 20 is not particularly limited, but may be, for example, 0.2 to 2.0 mm. When the support substrate 20 is 0.2 mm or more, the handleability of the support substrate 20 can be improved. When the support substrate 20 is 2.0 mm or less, the material cost can be suppressed and the cost can be reduced. The support substrate 20 may be in a wafer shape or a panel shape. The size of the support substrate 20 is not particularly limited, but may be, for example, a wafer with a diameter of 200 mm, 300 mm, or 450 mm, or a rectangular panel with one side of 300 to 700 mm.

[0044] Next, as shown in (b) of Fig. 2, a photosensitive resist is applied onto the seed layer 21 to form a resist layer 22. Any known material may be used as the photosensitive resist. After that, as shown in (c) of Fig. 2, exposure is performed to form a via 23 in an area corresponding to the wiring electrode. As a result, the via 23 in which the seed layer 21 is exposed is formed.

[0045] Next, as shown in (a) of FIG. 3, wiring electrodes 24 (first wiring electrode, second wiring electrode) are formed on the seed layer 21 in the via 23 by electrolytic copper plating. Thereafter, as shown in (b) and (c) of FIG. 3, the resist layer 22 is peeled off and removed, and the seed layer 21 other than the wiring electrodes 24 is removed by etching. In this manner, the wiring electrodes 24 are formed on the support substrate 20. Note that the method for forming the wiring electrodes 24 is not limited to this, and the wiring electrodes 24 may be formed by other methods. The wiring electrodes 24 formed in this manner can function as wiring pads, electrode pads, connection bumps, pillars, or the like.

[0046] Next, as shown in (a) of FIG. 4, an organic insulating layer 25 is formed on the support substrate 20 so that the wiring electrodes 24 are sealed with an organic insulating material (first organic insulating material, second organic insulating material) containing a thermosetting resin (first thermosetting resin, second thermosetting resin) and inorganic oxide particles (first inorganic oxide particles, second inorganic oxide particles). At this time, the wiring electrodes 24 may be completely covered with the organic insulating material. At this time, the organic insulating layer 25 containing the thermosetting resin and inorganic oxide particles may be sealed by forming it in a mold using a compression type or transfer type molding machine. Alternatively, the organic insulating layer 25 containing the thermosetting resin and inorganic oxide particles molded into a film shape may be sealed using a roll type or pressure type lamination molding machine. The sealed support substrate 20 is heated using an oven, a hot plate, or the like. As a result, the organic insulating layer 25 containing the thermosetting resin and inorganic oxide particles is formed on the support substrate 20. By this heating, the thermosetting resin of the organic insulating layer 25 may be in a completely cured state, or may be in an incompletely cured state (eg, semi-cured, B stage).

[0047] The materials of the thermosetting resin and inorganic oxide particles constituting the organic insulating layer 25 are not particularly limited, but from the viewpoint of high rigidity and embeddability, for example, they are sealing materials that can be formed in a mold by a compression type or transfer type molding machine. Alternatively, the material constituting the organic insulating layer 25 may be a sealing material, a build-up material, or a solder resist material molded into a film. In that case, from the viewpoint of preventing the entrapment of air bubbles, the film-like material may be laminated on the support substrate 20 under reduced pressure.

[0048] The thermosetting resin constituting the organic insulating layer 25 is not particularly limited, and any known thermosetting resin can be used, such as epoxy resin, acrylic resin, methacrylic resin, maleimide resin, phenol resin, unsaturated imide resin, cyanate resin, isocyanate resin, benzoxazine resin, oxetane resin, amino resin, unsaturated polyester resin, allyl resin, dicyclopentadiene resin, silicone resin, triazine resin, melamine resin, etc. Of the above thermosetting resins, the thermosetting resin used in the organic insulating layer 25 is preferably an epoxy resin.

[0049] The thermosetting resin may contain a crosslinking agent that crosslinks by heat. Although not particularly limited, known crosslinking agents may be used, such as epoxy compounds, isocyanate compounds, phenolic resins, phenoxy resins, unsaturated polyester resins, alkyd resins, urethane resins, melamine resins, urea resins, guanamine resins, polyimide resins, polyamide resins, vinyl ester resins, and diallyl phthalate resins, and two or more of these may be used in combination.

[0050] The inorganic oxide particles constituting the organic insulating layer 25 are not particularly limited, and known inorganic oxide particles can be used, such as silica (SiO2), alumina (Al2O3), titania (TiO2), tantalum oxide (Ta2O5), zirconia (ZrO2), zinc oxide (ZnO), etc. The inorganic oxide particles may be used alone or in combination of two or more kinds. As an example, the inorganic oxide particles contained in the organic insulating layer 4 are silica.

[0051] The content of inorganic oxide particles contained in the organic insulating layer 25 is, for example, 15 volume % to 70 volume % of the total volume of the organic insulating layer 25. When the content of inorganic oxide particles is 15 volume % or more of the total volume, it is possible to suppress an increase in the coefficient of thermal expansion (CTE) of the entire organic insulating layer 25, and to reduce warpage after the sealing process and lamination process. Furthermore, when the content of inorganic oxide particles is 70 volume % or less of the total volume, it is possible to ensure an adhesive area between the thermosetting resins and obtain sufficient adhesive strength when the surfaces of the polished substrates are pressure-bonded while being heated in the bonding process described later.

[0052] Furthermore, the materials of the thermosetting resin and inorganic oxide particles constituting the organic insulating layer 25 are not particularly limited, and may be selected depending on the semiconductor package structure to be applied. For example, in the case of a semiconductor package in which a memory is stacked on an interposer substrate to which a sealing material is applied, when the sealing material constituting the interposer and the sealing material formed so as to cover the memory chip are stacked, the sealing materials are stacked on each other by applying the manufacturing method described above.

[0053] The thickness of such an organic insulating layer 25 is, for example, 10 to 400 μm. When the thickness of the organic insulating layer 25 is 10 μm or more, the adhesive strength when the organic insulating layer 25 is bonded to another organic insulating layer can be ensured. When the thickness of the organic insulating layer 25 is 400 μm or less, the warping of the entire substrate can be reduced, and the substrate can be easily attached to a device in a subsequent grinding process.

[0054] Next, as shown in FIG. 4B, the surface 25c of the organic insulating layer 25 formed on the support substrate 20 is ground to make the organic insulating layer 25 have a predetermined thickness. In this grinding process, the surface 25c of the organic insulating layer 25 containing the thermosetting resin 25a and the inorganic oxide particles 25b is exposed by grinding (see FIG. 5 and FIG. 6). This grinding is performed, for example, by a grinding technique using a grindstone rotating at high speed. By this grinding process, the surface 24a of the wiring electrode 24 is exposed from the surface 25d of the organic insulating layer 25A. The surface roughness of the organic insulating layer 25A containing the thermosetting resin 25a and the inorganic oxide particles 25b that has been subjected to this grinding process is 0.5 μm or less in arithmetic mean roughness Ra when measured at a magnification of 20 times using a laser microscope, from the viewpoint of grinding variation in the subsequent polishing process. In FIG. 4B, the state in which the surface 25d has a certain degree of roughness is emphasized. The arithmetic mean roughness Ra used here is the arithmetic mean roughness (Ra) specified in JIS B 0601 2001.

[0055] Subsequently, as shown in FIG. 4(c), the surface 25d of the organic insulating layer 25A containing the thermosetting resin 25a and the inorganic oxide particles 25b is polished and planarized by chemical mechanical polishing (CMP). In this polishing step, the surface 25d of the organic insulating layer 25A containing the thermosetting resin 25a and the inorganic oxide particles 25b is planarized. This polishing step is performed, for example, by polishing the polished portion (organic insulating layer 25A) on the support substrate 20 while supplying a polishing liquid between the polishing pad (polishing cloth) and the polished portion. Various polishing liquids can be used for CMP. Polishing liquids for CMP are classified according to the type of abrasive grains (polishing particles) contained therein, and examples of the abrasive grains include cerium oxide (ceria) particles, silicon oxide (silica) particles, aluminum oxide (alumina) particles, and organic resin particles. From the viewpoint of polishing speed, for example, ceria-based particles are applied as the abrasive grains.

[0056] By such polishing, the surface of the surface 25d of the organic insulating layer 25A may be polished so that the arithmetic mean roughness Ra of the surface 25e becomes 50 nm or less. By making the arithmetic mean roughness Ra of the surface 25e of the organic insulating layer 25A 50 nm or less, it is possible to suppress the shedding of the filler in the organic insulating layer 25A and the insufficient grinding of the filler surface. In addition, it is possible to prevent the occurrence of voids at the adhesive interface between the organic insulating layers due to wear of the surface 25e of the organic insulating layer 25A, and to make the adhesiveness between the organic insulating layers described later more reliable. The arithmetic mean roughness Ra of the organic insulating layer 25A that has been subjected to the polishing process may be 50 nm or less, and the polishing or grinding may be performed by a method other than CMP. For example, grinding by a flycut method is applicable. In addition, the flycut method may be combined with etching, etc.

[0057] The thickness of the organic insulating layer 25A after the grinding and polishing steps is, for example, 1 to 300 μm. When the thickness of the organic insulating layer 25A is 1 μm or more, the buried wiring and electrodes are not excessively ground, and the yield can be increased. When the thickness of the organic insulating layer 25A is 300 μm or less, the warping of the entire substrate can be suppressed, and it is possible to prevent voids from occurring at the contact interface in the compression bonding step described below, which makes it impossible to perform compression bonding.

[0058] FIG. 5 shows an example of a plan view of the surface 25e of the organic insulating layer 25A after the above-mentioned polishing step. As shown in FIG. 5, the organic insulating layer 25A contains a thermosetting resin 25a and inorganic oxide particles 25b. In the polishing step, the ratio of the area occupied by the inorganic oxide particles 25b on the surface of the organic insulating layer 25A that has been polished is, for example, 15% to 75% of the total area. When the ratio of the area occupied by the inorganic oxide particles 25b is 15% or more of the total area, it is possible to suppress the increase in the coefficient of thermal expansion (CTE) of the organic insulating layer 25A, and to suppress warping after the sealing configuration and lamination step. In addition, when the ratio of the area occupied by the inorganic oxide particles 25b is 70% or less of the total area of ​​the organic insulating layer 25A, it is possible to secure the adhesion area between the thermosetting resins and obtain sufficient adhesive strength when the surfaces of the polished organic insulating layers are heated and pressure-bonded in the bonding step described later.

[0059] FIG. 6(a) is a cross-sectional view showing the organic insulating layer 25 when the organic insulating material is formed on the support substrate 20, and FIG. 6(b) is a cross-sectional view showing the organic insulating layer 25A after grinding and polishing. As shown in FIG. 6(a) and (b), the surface 25c of the organic insulating layer 25 is ground and polished by the grinding and polishing process, and the desired thickness can be obtained. In addition, the inorganic oxide particles in the organic insulating layer 25 are also appropriately ground and polished. The above steps form an organic substrate 26 with a polished surface. For example, a pair of organic substrates 26 having such a configuration are formed and bonded together as shown in the following steps.

[0060] Next, when a pair of organic substrates 26 whose surfaces have been planarized in the polishing process are prepared, the surfaces 26a of the organic substrates 26 are bonded together by pressure bonding, as shown in Fig. 7. This bonding may be performed under a nitrogen atmosphere. By setting the oxygen concentration during this bonding to 1000 ppm or less, it is possible to prevent the wiring electrodes, thermosetting resin, and inorganic oxide particles on the surface 26a of the organic substrate 26 exposed by the polishing process from being oxidized, thereby making it possible to reduce adhesion failure.

[0061] In this bonding step, the heating temperature when the planarized organic insulating layers 25A are pressure-bonded together is, for example, 200°C to 400°C. By setting the heating temperature during pressure bonding to 200°C or higher, insufficient melting of the resin and poor adhesion between the wiring layers can be prevented, and the adhesive strength between the organic insulating layers 25A can be increased. Furthermore, by setting the heating temperature during pressure bonding to 400°C or lower, decomposition of the thermosetting resin in the organic insulating layer 25A can be prevented, and the adhesion between the thermosetting resins can be more reliably achieved.

[0062] In this bonding step, the applied pressure when bonding the organic insulating layers 25A planarized in the polishing step together is, for example, 5.0 to 100 MPa. By applying a pressure of 5.0 MPa or more, the organic insulating layers 25A planarized by CMP can be sufficiently contacted with each other even if there is an influence of warping, etc., and sufficient adhesive strength can be obtained. Furthermore, by applying a pressure of 100 MPa or less, it is possible to prevent the substrate planarized by CMP from being damaged.

[0063] In this bonding step, additional heating may be performed under a nitrogen atmosphere after the pressure bonding, if necessary. The heating temperature after the pressure bonding is, for example, 250 to 400°C, and the heating time after the pressure bonding is, for example, 30 to 180 minutes. By heating at a temperature of 250°C or higher, the embedded wiring electrodes 24 can be firmly bonded to each other by metal bonding. By setting the heating temperature to 400°C or lower, it is possible to prevent the resin component of the organic insulating layer 25A from being decomposed by heat. Note that the thermosetting resin in the organic insulating layer 25A is completely cured by this additional heating or heating during the pressure bonding. In this manner, the semiconductor device 1 having the configuration shown in FIG. 1 is formed.

[0064] The materials constituting the thermosetting resin and inorganic oxide particles of the pair of organic insulating layers 25A to be bonded in the above-mentioned bonding process may be the same, and in that case, the adhesive strength when bonding the organic insulating layers 25A together can be easily increased. On the other hand, the materials constituting the thermosetting resin and inorganic oxide particles of the organic insulating layer 25A to be bonded in the above-mentioned bonding process may be different. When bonding the surfaces of the organic insulating layer 25A flattened by CMP, which contains the organic insulating layer containing the thermosetting resin and inorganic oxide particles, in the two substrates to be bonded, the combination of materials constituting the organic insulating layer containing the thermosetting resin and inorganic oxide particles is not particularly limited, but may be selected depending on the semiconductor package structure to be applied. For example, when applying to a semiconductor package assuming a 2.1D package structure in which a fine wiring layer is formed on the organic insulating layer 25A, or a structure in which semiconductor chips mounted on a substrate can be connected to each other at high density using a bridge chip embedded in a cavity formed in the organic insulating layer 25A, the solder resist material or build-up material on the organic substrate side and the sealing material covering the semiconductor chip are laminated by applying the above-mentioned manufacturing method.

[0065] As described above, according to the manufacturing method of the semiconductor device of this embodiment, each organic insulating layer 25A to be bonded together contains a thermosetting resin 25a and inorganic oxide particles 25b, and such organic insulating layers 25A are bonded together. In this case, in addition to bonding the thermosetting resins 25a contained in each organic insulating layer 25A together, the inorganic oxide particles 25b contained in each organic insulating layer 25A are bonded together (see FIG. 8). This makes it possible to further increase the adhesive strength between the organic insulating layers 25A while suppressing manufacturing costs. Note that when each organic insulating layer 25A contains inorganic oxide particles 25b, grinding the insulating layer to a predetermined thickness may result in rough surface roughness. However, in this manufacturing method, at least one of the organic insulating layers 25, 25A is polished before bonding. This ensures sufficient accuracy and adhesive strength when bonding.

[0066] In the method for manufacturing a semiconductor device according to this embodiment, in the step of polishing the organic insulating layer 25A, the organic insulating layer 25A may be polished so that the arithmetic mean roughness Ra of the surface 25e of the organic insulating layer 25A becomes 50 nm or less. In this case, it is possible to more reliably improve the accuracy and adhesive strength when bonding the organic insulating layer 25A to another corresponding organic insulating layer 25A.

[0067] In the method for manufacturing a semiconductor device according to this embodiment, the content of the inorganic oxide particles 25b with respect to the total volume of the organic insulating layer 25A may be 15 volume % to 70 volume %, which can further increase the adhesive strength between the organic insulating layers 25A.

[0068] In the method for manufacturing a semiconductor device according to this embodiment, in the step of forming the organic insulating layer 25A, the wiring electrodes 24 are sealed with an organic insulating material containing the thermosetting resin 25a and the inorganic oxide particles 25b, so that the wiring electrodes 24 are protected by the organic insulating material.

[0069] In the method for manufacturing a semiconductor device according to this embodiment, in the step of grinding the organic insulating layer 25A, the organic insulating layer 25A is ground so that the connection terminal 24c of the wiring electrode 24 is exposed from the surface 25d of the organic insulating layer 25A. This allows the wiring electrode 24 to be connected to other wiring electrodes 24, etc. more reliably.

[0070] Second embodiment Next, a method for manufacturing a semiconductor device (a method for fabricating a stack) according to a second embodiment of the present disclosure and a semiconductor device (a stack) will be described with reference to Figs. 9 to 11. In the following description, differences from the first embodiment will be mainly described, and descriptions similar to or overlapping with those of the first embodiment may be omitted. Fig. 9 (a) to (c) are diagrams showing a method for manufacturing a semiconductor device according to a second embodiment of the present disclosure. Fig. 10 is a diagram showing the method for manufacturing a semiconductor device according to the second embodiment, showing a process subsequent to Fig. 9. Fig. 11 is a cross-sectional view showing the semiconductor device according to the second embodiment.

[0071] 9(a), in the method for manufacturing a semiconductor device according to the second embodiment, in a member having wiring electrodes 24 provided on a support substrate 20, a semiconductor chip 30 (first semiconductor chip, second semiconductor chip) is placed at a predetermined location on the support substrate 20 (between the wiring electrodes 24 in the illustrated example). More specifically, the semiconductor chip 30 is placed on the support substrate 20 by an adhesive 32 so that the connection terminals 31 of the semiconductor chip 30 face upward, that is, so that they face the opposite side to the support substrate 20. At this time, the connection terminals 31 of the semiconductor chip 30 and the connection terminals 24c of the wiring electrodes 24 may be placed so that their heights are approximately the same.

[0072] 9(b), an organic insulating layer 25 is formed on the support substrate 20 so that the wiring electrodes 24 and the semiconductor chip 30 are sealed with an organic insulating material containing a thermosetting resin 25a and inorganic oxide particles 25b. At this time, the wiring electrodes 24 and the semiconductor chip 30 may be completely covered with the organic insulating material. The organic insulating layer 25 preferably has a thickness sufficient to place the main body and wiring of the semiconductor chip 30 within the organic insulating layer 25.

[0073] Subsequently, as shown in FIG. 9(c), the grinding step and the polishing step of the first embodiment are performed. The grinding step and the polishing step may be performed under the same conditions as those of the first embodiment. However, in the second embodiment, during the grinding step, not only the connection terminals 24c of the wiring electrodes 24 but also the connection terminals 31 of the semiconductor chip 30 are exposed to the outside from the organic insulating layer 25A. The arithmetic mean roughness Ra of the organic insulating layer 25A at this time may be 50 nm or less, as in the first embodiment. Moreover, the content of the inorganic oxide particles 25b contained in the organic insulating layers 25, 25A subjected to the grinding step and the polishing treatment is, for example, 15% to 70% by volume of the total volume of the organic insulating layers 25, 25A, as in the first embodiment. Moreover, the ratio of the area occupied by the inorganic oxide particles 25b on the surface 25e of the organic insulating layer 25A is, for example, 15% to 75% of the total area, as in the first embodiment. In this manner, an organic substrate 27 in which the semiconductor chip 30 is arranged on the support substrate 20 can be obtained.

[0074] Next, when a pair of organic substrates 27 whose surfaces have been planarized in a polishing process are prepared, the surfaces 27a of the organic substrates 27 are bonded together by pressure bonding, as shown in Fig. 10. The bonding conditions can be the same as those in the first embodiment. During this bonding, the organic insulating layers 25A are connected together, and the connection terminals 24c of the wiring electrodes 24 are bonded together, as in the first embodiment. In addition, in the manufacturing method according to the second embodiment, the connection terminals 31 of the semiconductor chips 30 are further bonded together.

[0075] As a result of the above, a semiconductor device 1A incorporating a semiconductor chip 30 is manufactured, as shown in Fig. 11. The semiconductor device 1A includes a supporting substrate 2A, a wiring electrode 3A, an organic insulating layer 4A, a supporting substrate 5A, a wiring electrode 6A, an organic insulating layer 7A, and a semiconductor chip 30, as shown in Fig. 11.

[0076] As described above, in the method for manufacturing a semiconductor device according to this embodiment, similarly to the first embodiment, each of the organic insulating layers 25A to be bonded together contains a thermosetting resin 25a and inorganic oxide particles 25b, and such organic insulating layers 25A are bonded together. In this case, in addition to bonding the thermosetting resins 25a contained in the organic insulating layers 25A together, the inorganic oxide particles 25b contained in the organic insulating layers 25A together are bonded together (see FIG. 8). This makes it possible to further increase the adhesive strength between the organic insulating layers 25A while suppressing manufacturing costs. Other effects are also similar to those of the first embodiment.

[0077] Third embodiment Next, a method for manufacturing a semiconductor device (a method for fabricating a stack) according to a third embodiment of the present disclosure and a semiconductor device (a stack) will be described with reference to Fig. 12 and Fig. 13. In the following description, differences from the first embodiment will be mainly described, and descriptions similar to or overlapping with the first embodiment may be omitted. Fig. 12 (a) to (c) are diagrams showing a method for manufacturing a semiconductor device according to a third embodiment of the present disclosure. Fig. 13 is a cross-sectional view showing the semiconductor device according to the third embodiment.

[0078] As shown in FIG. 12(a), in the method for manufacturing a semiconductor device according to the third embodiment, an organic insulating layer 25 is formed on a support substrate 20 using an organic insulating material containing a thermosetting resin 25a and inorganic oxide particles 25b.

[0079] Subsequently, as shown in FIG. 12(b), the grinding step and polishing step of the first embodiment are performed. The grinding step and polishing step may be performed under the same conditions as those of the first embodiment. The arithmetic mean roughness Ra of the organic insulating layer 25A may be 50 nm or less, as in the first embodiment. The content of the inorganic oxide particles 25b contained in the organic insulating layer 25, 25A subjected to the grinding step and polishing treatment is, for example, 15% to 70% by volume of the total volume of the organic insulating layer 25, 25A, as in the first embodiment. The proportion of the area occupied by the inorganic oxide particles 25b on the surface 25e of the organic insulating layer 25A is, for example, 15% to 75% of the total area, as in the first embodiment. As a result of the above, an organic substrate 28 in which the organic insulating layer 25A containing inorganic oxide particles is disposed on the support substrate 20 can be obtained.

[0080] Next, when a pair of organic substrates 28 whose surfaces have been planarized in a polishing process are prepared, the surfaces 28a of the organic substrates 28 are bonded together by pressure bonding, as shown in (c) of Fig. 12. The bonding conditions can be the same as those in the first embodiment.

[0081] In this manner, a semiconductor device 1B is fabricated as shown in Fig. 13. As shown in Fig. 13, the semiconductor device 1B includes a support substrate 2B, an organic insulating layer 4B, a support substrate 5B, and an organic insulating layer 7B. In the semiconductor device 1B, a semiconductor chip may be embedded inside at least one of the support substrates 2B and 5B, or a semiconductor chip may be mounted on the outside of at least one of the support substrates 2B and 5B.

[0082] As described above, in the method for manufacturing a semiconductor device according to this embodiment, similarly to the first embodiment, each of the organic insulating layers 25A to be bonded together contains a thermosetting resin 25a and inorganic oxide particles 25b, and such organic insulating layers 25A are bonded together. In this case, in addition to bonding the thermosetting resins 25a contained in the organic insulating layers 25A together, the inorganic oxide particles 25b contained in the organic insulating layers 25A together are bonded together (see FIG. 8). This makes it possible to further increase the adhesive strength between the organic insulating layers 25A while suppressing manufacturing costs. Other effects are also similar to those of the first embodiment.

[0083] Although the embodiments of the present disclosure have been described above, the present invention is not limited to the above-mentioned embodiments, and appropriate modifications may be made without departing from the spirit of the present disclosure. For example, in the second embodiment, both organic substrates 27 are provided with the semiconductor chip 30, but one organic substrate 27 may be provided with the semiconductor chip 30 and the other organic substrate 27 may not be provided with the semiconductor chip 30. In addition, the configurations of the first to third embodiments may be combined as appropriate. [Explanation of symbols]

[0084] 1, 1A, 1B... semiconductor device (laminate), 2, 2A, 2B... supporting substrate (first supporting substrate), 3, 3A... wiring electrode (first wiring electrode), 3c... connection terminal, 4, 4A, 4B... organic insulating layer (first organic insulating layer), 4c... surface (first surface), 5, 5A, 5B... supporting substrate (second supporting substrate), 6, 6A... wiring electrode (second wiring electrode), 6c... connection terminal, 7, 7A, 7B... organic insulating layer (second organic insulating layer), 7c... surface (second surface surface), 20...support substrate (first support substrate, second support substrate), 24...wiring electrodes (first wiring electrode, second wiring electrode), 24c...connection terminal, 25, 25A...organic insulating layer, 25a...thermosetting resin (first thermosetting resin, second thermosetting resin), 25b...inorganic oxide particles (first inorganic oxide particles, second inorganic oxide particles), 25c, 25d, 25e...surface (first surface, second surface), 30...semiconductor chip, 31...connection terminal.

Claims

1. A method for manufacturing a semiconductor device comprising the steps of: forming a first insulating layer on a first support substrate, the first insulating layer including first inorganic oxide particles; polishing and planarizing a first surface of the first insulating layer; and bonding the polished first surface to a second surface of a second insulating layer containing second inorganic oxide particles; At least one of the first insulating layer and the second insulating layer is an organic insulating layer containing a thermosetting resin.

2. In the step of polishing the first insulating layer, the first insulating layer is polished so that the arithmetic mean roughness of the first surface is 50 nm or less. A method for producing the laminate according to claim 1 .

3. The content of the first inorganic oxide particles relative to the total volume of the first insulating layer is 15 vol% to 70 vol%. A method for producing the laminate according to claim 1 or 2.

4. The method further includes a step of grinding the first insulating layer, In the step of polishing the first insulating layer, the ground first surface of the first insulating layer is polished. A method for producing the laminate according to any one of claims 1 to 3.

5. A method for manufacturing a semiconductor device comprising the steps of: forming the second insulating layer on a second support substrate; and polishing the second surface of the second insulating layer to be planar. In the bonding step, the planarized first surface is bonded to the planarized second surface. A method for producing the laminate according to any one of claims 1 to 4.

6. In the step of polishing the second insulating layer, the second insulating layer is polished so that the arithmetic mean roughness of the second surface is 50 nm or less. A method for producing the laminate according to claim 5 .

7. The content of the second inorganic oxide particles relative to the total volume of the second insulating layer is 15 vol% to 70 vol%. A method for producing the laminate according to claim 5 or 6.

8. The method further includes a step of grinding the second insulating layer, In the step of polishing the second insulating layer, the ground second surface of the second insulating layer is polished. A method for producing the laminate according to any one of claims 5 to 7.

9. The method further includes forming a first wiring electrode on the first support substrate, In the step of forming the first insulating layer, the first wiring electrode is sealed with a first insulating material containing the first inorganic oxide particles. A method for producing the laminate according to any one of claims 1 to 8.

10. prior to the step of polishing the first insulating layer, grinding the first insulating layer so that a connection terminal of the first wiring electrode is exposed from the first surface of the first insulating layer; A method for producing the laminate according to claim 9 .

11. forming a second wiring electrode on a second support substrate; forming the second insulating layer containing the second inorganic oxide particles on the second support substrate so as to seal the second wiring electrode with the second insulating material containing the second inorganic oxide particles; in the bonding step, when bonding the first surface of the first insulating layer to the second surface of the second insulating layer, a connection terminal of the first wiring electrode is joined to a connection terminal of the second wiring electrode; A method for producing the laminate according to claim 9 or 10.

12. The method further includes the step of disposing a first semiconductor chip on the first support substrate; In the step of forming the first insulating layer, the first semiconductor chip is sealed with a first insulating material containing the first inorganic oxide particles. A method for producing a laminate according to any one of claims 1 to 11.

13. prior to the step of polishing the first insulating layer, grinding the first insulating layer so that connection terminals of the first semiconductor chip are exposed from the first surface of the first insulating layer; A method for producing the laminate according to claim 12.

14. disposing a second semiconductor chip on a second support substrate; forming the second insulating layer containing the second inorganic oxide particles on the second support substrate so as to seal the second semiconductor chip with the second insulating material containing the second inorganic oxide particles; In the bonding step, when the first surface of the first insulating layer is bonded to the second surface of the second insulating layer, a connection terminal of the first semiconductor chip is joined to a connection terminal of the second semiconductor chip. A method for producing the laminate according to claim 12 or 13.

15. A first support substrate; a first insulating layer formed on the first support substrate, the first insulating layer including first inorganic oxide particles; a second insulating layer including second inorganic oxide particles and bonded to the first insulating layer; Equipped with At least one of the first insulating layer and the second insulating layer is an organic insulating layer containing a cured product of a thermosetting resin, a laminate, wherein the first inorganic oxide particles and the second inorganic oxide particles are bonded to each other on a surface where the first insulating layer and the second insulating layer are bonded to each other.

16. Further comprising a semiconductor chip disposed on or within the first support substrate. The laminate according to claim 15.

17. a first wiring electrode, at least a portion of which is disposed in the first insulating layer, and a connection terminal of which is exposed from a first surface of the first insulating layer that is bonded to the second insulating layer, the first wiring electrode being connected to the semiconductor chip; a second wiring electrode at least a part of which is disposed in the second insulating layer, and a connection terminal is exposed from a second surface of the second insulating layer which is bonded to the first insulating layer; a connection terminal of the first wiring electrode and a connection terminal of the second wiring electrode are joined together; The laminate of claim 16.

18. the semiconductor chip is disposed on the first support substrate, at least a portion of the semiconductor chip is disposed in the first insulating layer, and a connection terminal of the semiconductor chip is exposed from a first surface of the first insulating layer that is bonded to the second insulating layer; 18. The laminate according to claim 16 or 17.

19. The content of the first inorganic oxide particles relative to the total volume of the first insulating layer is 15 vol% to 70 vol%. The laminate according to any one of claims 15 to 18.

20. A first support substrate; a first insulating layer formed on the first support substrate, the first insulating layer including first inorganic oxide particles; a second insulating layer including second inorganic oxide particles and bonded to the first insulating layer; a semiconductor chip disposed on or within the first support substrate; Equipped with At least one of the first insulating layer and the second insulating layer is an organic insulating layer containing a cured product of a thermosetting resin, A laminate, wherein the semiconductor chip is on the first support substrate, at least a portion of the semiconductor chip is disposed in the first insulating layer, and a connection terminal of the semiconductor chip is exposed from a first surface of the first insulating layer that is bonded to the second insulating layer.

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