Gate drive circuit
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-04-28
- Publication Date
- 2026-03-12
AI Technical Summary
Conventional gate drive circuits can effectively remove common mode noise superimposed on the output side but fail to address noise on the input side, leading to potential interference and noise propagation.
A gate drive circuit design that utilizes a first ground potential as a reference, converts single-ended signals into differential signals, employs pulse transformers with insulated neutral points, and includes differential amplification circuits to cancel common mode noise on both input and output sides.
The circuit effectively removes common mode noise from both input and output sides, protecting the control device from noise generated by switching elements and improving noise immunity.
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Abstract
Description
[Technical field]
[0001] The present invention relates to a gate drive circuit. [Background technology]
[0002] Conventionally, it is known that in a gate drive circuit that drives a switching element that operates in a floating state, the input side and the output side are insulated. In such a case, common mode noise may occur due to switching of the switching element. Various proposals have been made as a countermeasure against this common mode noise. For example, in the gate drive circuit of Patent Document 1, the input side and the output side are insulated by a pulse transformer, the input side is grounded to a first ground potential point, and the output side is grounded to a second ground potential point. A primary side gate drive signal is input to the primary winding of the pulse transformer, and the output of the secondary side of the pulse transformer is differentially amplified by a comparator and output as a secondary side gate drive signal. Furthermore, an electrostatic shield plate grounded to the second ground potential point is arranged between the primary winding and the secondary winding of the pulse transformer. [Prior art documents] [Patent documents]
[0003] [Patent Document 1] JP2013-074079A Summary of the Invention [Problem to be solved by the invention]
[0004] The gate drive circuit of Patent Document 1 can remove common mode noise superimposed on the output side, but cannot remove common mode noise superimposed on the input side.
[0005] The present invention has been made to solve such problems, and has an object to provide a gate drive circuit capable of removing common mode noise superimposed on the output side and input side. [Means for solving the problem]
[0006] In order to achieve the above object, a gate drive circuit according to an aspect of the present disclosure includes a signal conversion circuit that operates using the potential of a first ground as a reference potential and converts a gate control signal, which is a single-ended signal, into a differential signal consisting of a positive signal and a negative signal whose signal level difference corresponds to the gate control signal; a first pulse transformer that has a primary winding and a secondary winding that are electrically insulated from each other and each having a neutral point, the neutral point of the primary winding is set to the potential of the first ground and a positive signal and a negative signal of the differential signal are input to both ends of the primary winding, respectively; and a pair of resistance elements connected in series with each other, the neutral point is connected to both ends of the secondary winding of the first pulse transformer directly or via a transmission cable and a second pulse transformer, respectively, and generates a pair of input differential voltages across the pair of resistance elements based on the potential of the connection points; a differential amplifier circuit electrically connected to the input differential voltage generation circuit and configured to differentially amplify the pair of input differential voltages to output a pair of output differential voltages; and a gate drive signal generation circuit electrically connected to the differential amplifier circuit and configured to generate a gate drive signal which is a single-ended signal based on a predetermined potential based on the pair of output differential voltages, and output the gate drive signal to a switching element which operates based on the potential of a second ground. Effect of the Invention
[0007] The present invention has an effect of providing a gate drive circuit capable of removing common mode noise superimposed on the output side and the input side. [Brief description of the drawings]
[0008] [Figure 1] FIG. 1 is a circuit diagram showing the configuration of a push-pull amplifier circuit in which a gate drive circuit according to the present disclosure is used. [Figure 2A]FIG. 2A is a block diagram showing a first configuration example of the gate drive circuit of FIG. [Figure 2B] FIG. 2B is a block diagram showing a second configuration example of the gate drive circuit of FIG. [Diagram 3] FIG. 3 is a circuit diagram showing an example of a specific circuit configuration of the first configuration example of the gate drive circuit of FIG. 2A. [Figure 4A] FIG. 4A is a waveform diagram showing the waveform of a differential signal on which common mode noise is superimposed. [Figure 4B] FIG. 4B is a waveform diagram showing the waveform of a differential signal induced in the first pulse transformer by the differential signal of FIG. 4A. [Figure 4C] 4C is a waveform diagram showing the waveform of an input differential voltage generated by an input differential voltage generating circuit from a signal derived from the differential signal induced in the first pulse transformer in FIG. 4B. [Diagram 5] FIG. 5 is a circuit diagram showing the operation of a switching power supply device using the push-pull amplifier circuit of FIG. [Figure 6] FIG. 6 is a schematic diagram showing switching noise generated by the switching module of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0009] A gate drive circuit according to an aspect of the present disclosure includes a signal conversion circuit that operates with a potential of a first ground as a reference potential and converts a gate control signal, which is a single-ended signal, into a differential signal consisting of a positive signal and a negative signal whose signal level difference corresponds to the gate control signal; a first pulse transformer having a primary winding and a secondary winding that are electrically insulated from each other and each having a neutral point, the neutral point of the primary winding being set to the potential of the first ground and a positive signal and a negative signal of the differential signal being input to both ends of the primary winding, respectively; and a pair of resistance elements connected in series with each other, both ends and a connection point of the pair of resistance elements being directly electrically connected to each other. an input differential voltage generation circuit that is connected to both ends of the secondary winding of the first pulse transformer and the neutral point directly or via a transmission cable and a second pulse transformer, respectively, and generates a pair of input differential voltages across the pair of resistance elements based on the potential of the connection points; a differential amplifier circuit that is electrically connected to the input differential voltage generation circuit and differentially amplifies the pair of input differential voltages to output a pair of output differential voltages; and a gate drive signal generation circuit that is electrically connected to the differential amplifier circuit and generates a gate drive signal that is a single-ended signal based on a predetermined potential based on the pair of output differential voltages, and outputs the gate drive signal to a switching element that operates based on the potential of a second ground.
[0010] According to this configuration, the input side and the output side of the gate drive circuit are insulated from each other by the first pulse transformer, and the input side is based on the potential of the first ground, while the output side is connected to the switching element and is in a floating state based on the potential of the second ground. In this state, the gate control signal, which is a single-ended signal, is converted by the signal conversion circuit into a differential signal consisting of a positive signal and a negative signal whose signal level difference corresponds to the gate control signal, and the neutral point of the primary winding of the first pulse transformer is set to the potential of the first ground, and the differential signal is input to both ends of the primary winding. As a result, the positive signal and the negative signal are converted into a pair of single-ended voltage signals, each of which has twice the amplitude and is in opposite phase (positive and negative) to each other, induced in the winding of the same transformer as a voltage across both ends. Therefore, when common mode noise is superimposed on these positive and negative signals on the input side, the common mode noise of the positive signal and the common mode noise of the negative signal are inversely positive and negative to each other, and are offset and removed by the first pulse transformer.
[0011] Also, on the output side, both ends and a connection point of a pair of resistive elements of the input differential voltage generating circuit are electrically connected to both ends and a neutral point of the secondary winding of the first pulse transformer directly or via a transmission cable and a second pulse transformer, respectively, and a pair of input differential voltages based on the potential of the connection point are generated across the pair of resistive elements, and the pair of input differential voltages are differentially amplified by a differential amplifier circuit. Therefore, when common mode noise is superimposed on a pair of wirings directly or indirectly connected to both ends of the secondary winding of the first pulse transformer on the output side, the common mode noise of the pair of wirings has opposite positive and negative values in the pair of input differential voltages generated by the input differential voltage generating circuit, and is removed by the differential amplifier circuit. Also, since the load current of the first pulse transformer flows through the pair of resistive elements of the input differential voltage generating circuit, the impedance of the transmission path of the differential signal is reduced, and the ability to remove common mode noise is improved.
[0012] As a result, it is possible to provide a gate drive circuit capable of removing common mode noise superimposed on the output side and the input side.
[0013] The second pulse transformer may have a primary winding and a secondary winding that are electrically insulated from each other and each have a neutral point, and both ends and the neutral point of the primary winding may be electrically connected to both ends and the neutral point of the secondary winding of the first pulse transformer via the transmission cable, respectively, and the input differential voltage generating circuit may have both ends and the connection point of the pair of resistance elements connected to both ends and the neutral point of the secondary winding of the second pulse transformer, respectively.
[0014] According to this configuration, when common mode noise is superimposed on the secondary winding of the first pulse transformer and the transmission cable, the common mode noise can be removed by the second pulse transformer in the same manner as the first pulse transformer. As a result, by lengthening the transmission cable, the control device that generates the gate control signal can be located away from the switching elements, and the computer that constitutes the control device can be suitably protected from noise generated by the switching operation of the switching elements.
[0015] The two switching elements constitute a first switching element and a second switching element which are push-pull connected to each other, the differential amplifier circuit includes a first differential amplifier circuit and a second differential amplifier circuit, and the gate drive signal generation circuit includes first and second gate drive signal generation circuits, the first differential amplifier circuit is electrically connected to the input difference voltage generation circuit, and is a circuit which differentially amplifies the pair of input difference voltages to output a pair of first output difference voltages at a high potential, and the second differential amplifier circuit is electrically connected to the input difference voltage generation circuit, and is a circuit which differentially amplifies the pair of input difference voltages to output a pair of first output difference voltages at a low potential which is lower than the pair of first output difference voltages. the first gate drive signal generation circuit is a circuit that is electrically connected to the first differential amplifier circuit, generates a first gate drive signal that is the gate drive signal based on a positive potential based on the pair of first output difference voltages, and outputs the first gate drive signal to the first switching element; and the second gate drive signal generation circuit is a circuit that is electrically connected to the second differential amplifier circuit, generates a second gate drive signal that is the gate drive signal based on a negative potential based on the pair of second output difference voltages, and outputs the second gate drive signal to the second switching element.
[0016] According to this configuration, the first switching element and the second switching element, which are push-pull connected to each other, can be driven while removing common mode noise superimposed on the output side and the input side.
[0017] The gate drive signal generation circuit may be a circuit that includes a flip-flop that receives the pair of output difference voltages and outputs a single-ended signal based on a predetermined potential, and outputs the single-ended signal as the gate drive signal.
[0018] According to this configuration, the flip-flop can generate a gate drive signal that is a single-ended signal based on a predetermined potential. Also, the waveform of the pair of output difference voltages of the differential amplifier circuit can be shaped, which further enables common mode noise to be removed.
[0019] Hereinafter, specific embodiments of the present disclosure will be described with reference to the drawings. In the following, the same or corresponding elements are denoted by the same reference numerals throughout all the drawings, and their repeated description will be omitted. In addition, since the following drawings are for explaining the present disclosure, elements unrelated to the present disclosure may be omitted, dimensions may be inaccurate due to exaggeration, or may be simplified, and the shapes of corresponding elements in multiple drawings may not match. In addition, the present disclosure is not limited to the following embodiments.
[0020] (Embodiment) First, the environment in which the gate drive circuit of the present disclosure is used will be described.
[0021] [Usage environment] FIG. 1 is a circuit diagram showing a configuration of a push-pull amplifier circuit 500 in which the gate drive circuit 100 of the present disclosure is used. Referring to FIG. 1, the push-pull amplifier circuit 500 includes a pair of switching elements 60 connected in a push-pull manner and a gate drive circuit 100. The pair of switching elements 60 is configured by connecting a first switching element 61 on the high side, which is, for example, a PMOSFET, and a second switching element 62 on the low side, which is, for example, an NMOSFET, in series between a positive power supply VDD and a second ground GND2, and an output is taken out from the connection point between them. The input side and the output side of the gate drive circuit 100 are insulated, the input side is connected to a first ground GND1, and the output side is electrically connected to the pair of switching elements 60. Therefore, the output side is in a floating state with respect to the first ground GND1 on the input side. The gate drive circuit 100 generates a gate drive signal from a gate control signal 11 input from a control board 1, and drives the pair of switching elements 60 by the gate drive signal. Next, the configuration of the gate drive circuit 100 will be described.
[0022] [Configuration of the gate drive circuit 100] First, there will be described an outline of the configuration of the gate drive circuit 100. The gate drive circuit 100 includes first to third configuration examples.
[0023] {overview} FIG. 2A is a block diagram showing a first configuration example of the gate drive circuit 100 of FIG.
[0024] First, a first configuration example will be described. The first configuration example is a configuration example of a gate drive circuit 100 including a transmission cable 4 and a second pulse transformer. Referring to FIG. 2A, the gate drive circuit 100 includes a signal conversion circuit 2, a first pulse transformer 3, a transmission cable 4, a second pulse transformer 5, an input difference voltage generation circuit 6, a first differential amplifier circuit 7, a second differential amplifier circuit 8, a first gate drive signal generation circuit 9, and a second gate drive signal generation circuit 10.
[0025] The signal conversion circuit 2 operates using the potential of the first ground GND1 as a reference potential, and converts the gate control signal 11, which is a single-ended signal from the control board 1, into a differential signal 21 consisting of a positive signal 21A and a negative signal 21B, whose signal level difference corresponds to the gate control signal 11.
[0026] The first pulse transformer 3 transmits this differential signal 21 to the input differential voltage generating circuit 6 via the transmission cable 4 and the second pulse transformer 5. As a result, the input side and the output side of the gate drive circuit 100 are insulated by the first pulse transformer 3 and the second pulse transformer 5.
[0027] The input differential voltage generating circuit 6 generates a pair of input differential voltages 22A, 22B based on the transmitted differential signal 21. The first differential amplifier circuit 7 differentially amplifies the pair of input differential voltages 22A, 22B to output a pair of first output differential voltages 23A, 23B at high potential. The first gate drive signal generating circuit 9 generates a first gate drive signal 25A based on the pair of first output differential voltages 23A, 23B, with a predetermined positive potential as a reference, and outputs the first gate drive signal 25A to the first switching element 61 (see FIG. 1). On the other hand, the second differential amplifier circuit 8 differentially amplifies the pair of input differential voltages 22A, 22B to output a pair of second output differential voltages 24A, 24B at a lower potential than the pair of first output differential voltages 23A, 23B. The second gate drive signal generation circuit 10 generates a second gate drive signal 25B based on a predetermined negative potential based on the pair of second output differential voltages 24A, 24B, and outputs the second gate drive signal 25B to the second switching element 62 (see FIG. 1).
[0028] Such a first configuration example is applied when it is desired to protect a computer constituting the control board (control device) 1 by placing it as far away as possible from a source of common mode noise.
[0029] Next, a second configuration example will be described. FIG. 2B is a block diagram showing a second configuration example of the gate drive circuit 100 of FIG. 1. Referring to FIG. 2B, in the second configuration example, the transmission cable 4 and the second pulse transformer 5 are omitted. Therefore, in the second configuration example, the input side and the output side of the gate drive circuit 100 are insulated by the first pulse transformer 3. In addition, the input differential voltage generating circuit 6 generates a pair of input differential voltages 22A, 22B based on the differential signal 21 output to the secondary winding of the first pulse transformer 3. Since the other configurations are the same as those in the first configuration example, the description thereof will be omitted. Such a second configuration example is applied when it is not necessary to keep the control board 1 away from the source of common mode noise.
[0030] Next, a third configuration example will be described. In the third configuration example, the gate drive circuit 100 includes only one set of a differential amplifier circuit and a gate drive signal generation circuit (for example, a first differential amplifier circuit 7 and a first gate drive signal generation circuit 9, or a second differential amplifier circuit 8 and a second gate drive signal generation circuit 10). The rest of the configuration is the same as the first or second configuration example, so a description thereof will be omitted. Such a third configuration example is applied when driving a single switching element (for example, the first switching element 61 or the second switching element 62 in FIG. 1).
[0031] Next, a detailed configuration and operation of the gate drive circuit 100 of the first configuration example in Fig. 2A will be described. Note that the second and third configuration examples are simply obtained by omitting the elements of the first configuration example, and therefore detailed configurations and operations thereof will not be described.
[0032] {Detailed configuration} FIG. 3 is a circuit diagram showing an example of a specific circuit configuration of the first configuration example of the gate drive circuit 100 of FIG. 2A.
[0033] 3, the circuit shown in FIG. 3 includes the gate drive circuit 100 of FIG. 2A and a pair of push-pull-connected switching elements 60 of FIG.
[0034] The signal conversion circuit 2 includes a logic circuit 31 , a positive signal generation circuit 32 , and a negative signal generation circuit 33 .
[0035] The logic circuit 31 generates the in-phase signal 12A and the anti-phase signal 12B from the gate control signal 11 from the control board 1 using a logic circuit.
[0036] The positive signal generating circuit 32 is configured by a pair of push-pull connected transistors Q1 and Q2, which are connected to a 5V positive power supply and a first ground GND1 via resistor elements R3 and R4, respectively. Note that a diode facing in the opposite direction is connected in parallel to the pair of transistors Q1 and Q2. The transistors Q1 and Q2 are configured by, for example, a PMOSFET and an NMOSFET, and the in-phase signal 12A from the logic circuit 31 is input to their gates via the resistor element R1. As a result, the positive signal generating circuit 32 outputs a positive signal obtained by amplifying the in-phase signal 12A from the connection point between the transistors Q1 and Q2.
[0037] The negative signal generating circuit 33 is configured by a pair of push-pull connected transistors Q3 and Q4, which are connected to a 5V positive power supply and a first ground GND1 via resistor elements R5 and R6, respectively. Diodes facing in the opposite direction are connected in parallel to the pair of transistors Q3 and Q4. The transistors Q3 and Q4 are configured by, for example, a PMOSFET and an NMOSFET, and the antiphase signal 12B from the logic circuit 31 is input to their gates via a resistor element R2. As a result, the negative signal generating circuit 33 outputs a negative signal 21B obtained by amplifying the antiphase signal 12B from the connection point between the transistors Q3 and Q4.
[0038] The first pulse transformer 3 has a primary winding and a secondary winding that are electrically insulated from each other and have neutral points MP1 and MP2, respectively. The neutral point MP1 of the primary winding is connected to a first ground GND1. A first end EP1 of the primary winding is connected to a connection point between a transistor Q1 and a transistor Q2 of a positive signal generating circuit 32, and a positive signal 21A is input to the first end EP1. A second end EP2 of the primary winding is connected to a connection point between a transistor Q3 and a transistor Q4 of a negative signal generating circuit 33, and a negative signal 21B is input to the second end EP2.
[0039] The second pulse transformer 5 has a primary winding and a secondary winding which are electrically insulated from each other and have neutral points MP3 and MP4, respectively. A first end EP5, a second end EP6, and a neutral point MP3 of the primary winding are connected to a first end EP3, a second end EP4, and a neutral point MP2 of the secondary winding of the first pulse transformer 3, respectively, via a transmission cable 4.
[0040] The input differential voltage generating circuit 6 has a pair of resistor elements R9, R10 connected in series. The pair of resistor elements R9, R10 have appropriate resistance values that are equal to each other. It is preferable that the resistance values of the pair of resistor elements R9, R10 are equal to each other from the viewpoint of completely canceling out common mode noise. However, the resistance values of the pair of resistor elements R9, R10 do not have to be equal to each other. Even in this case, the common mode noise can be reduced, although imperfectly. The high potential side end, the low potential side end, and the connection point N1 of the pair of resistor elements R9, R10 are connected to the first terminal EP7, the second terminal EP8, and the neutral point MP4 of the secondary winding of the second pulse transformer 5, respectively. As a result, a pair of input differential voltages 22A, 22B based on the potential of the connection point N1 are generated across the pair of resistor elements R9, R10.
[0041] The first differential amplifier circuit 7 includes a pair of transistors Q5 and Q6 as amplifying elements. One of the transistors Q5 is connected to a positive power supply VCC via a transistor Q7 and a resistor element R19, and is connected to a negative power supply VEE via a common resistor element R21. The other transistor Q6 is connected to a positive power supply VCC via a transistor Q8 and a resistor element R20, and is connected to a negative power supply VEE via a common resistor element R21. The pair of transistors Q5 and Q6 are, for example, npn-type bipolar transistors. The base of the transistor Q5 is connected to the high-potential ends of the pair of resistor elements R9 and R10 via a base resistor element R17, and an input difference voltage 22A (high-potential side difference voltage) is input to the base of the transistor Q5. The base of the transistor Q6 is connected to the low-potential ends of the pair of resistor elements R9 and R10 via a base resistor element R18, and an input difference voltage 22B (low-potential side difference voltage) is input to the base of the transistor Q6.
[0042] The gate drive circuit 100 also includes a circuit for resistively dividing the voltage between the positive power supply VCC and the negative power supply VEE. In this circuit, for example, four resistor elements R11 to R14 are connected in series between the positive power supply VCC and the negative power supply VEE, and the resistor elements R11 and R14 have the same resistance value, and the resistor elements R12 and R13 have the same resistance value. As a result, a connection point N2 between the resistor elements R12 and R13 has an intermediate potential between the positive power supply VCC and the negative power supply VEE, and this connection point N2 is connected to a connection point N1 of the input difference voltage generating circuit 6. As a result, the potential of the connection point N1 is fixed by the positive power supply VCC and the negative power supply VEE, but this configuration may be omitted.
[0043] The bases of the transistors Q7 and Q8 are connected to the connection point between the resistor elements R11 and R12, and the resistance values of these resistor elements R11 and R12 are appropriately selected so that the transistors Q7 and Q8 have a predetermined high resistance value.
[0044] With the above configuration, the first differential amplifier circuit 7 differentially amplifies the pair of input differential voltages 22A and 22B, and outputs a pair of first output differential voltages 23A and 23B to the connection point N3 and the connection point N4, respectively.
[0045] The second differential amplifier circuit 8 includes a pair of transistors Q9 and Q10 as amplifying elements. One of the transistors Q9 is connected to a positive power supply VCC via a common resistor element R22, and is connected to a negative power supply VEE via a transistor Q11 and a resistor element R23. The other transistor Q10 is connected to a positive power supply VCC via a common resistor element R22, and is connected to a negative power supply VEE via a transistor Q12 and a resistor element R24. The pair of transistors Q9 and Q10 are, for example, pnp-type bipolar transistors. The base of the transistor Q9 is connected to the high-potential end of the pair of resistor elements R9 and R10 via a base resistor element R16, and an input difference voltage 22A (high-potential side difference voltage) is input to the base of the transistor Q9. The base of the transistor Q10 is connected to the low-potential end of the pair of resistor elements R9 and R10 via a base resistor element R15, and an input difference voltage 22B (low-potential side difference voltage) is input to the base of the transistor Q9.
[0046] The bases of the transistors Q11 and Q12 are connected to the connection point between the resistor elements R13 and R14, and the resistance values of these resistor elements R13 and R14 are appropriately selected so that the transistors Q11 and Q12 have a predetermined high resistance value.
[0047] With the above configuration, the second differential amplifier circuit 8 differentially amplifies the pair of input differential voltages 22A and 22B, and outputs a pair of second output differential voltages 24A and 24B to the connection point N5 and the connection point N6, respectively.
[0048] The first gate drive signal generating circuit 9 is composed of a waveform shaping circuit for a square wave. For example, an RS flip-flop, which is a logic circuit, is used as the waveform shaping circuit. This RS flip-flop operates with a predetermined high potential as a reference. For example, in this RS flip-flop, the set input terminal is connected to the connection point N3 via a resistor element R25, the reset input terminal is connected to the connection point N4 via a resistor element R26, and the set output terminal is connected to the gate of the first switching element 61. Since a pair of first output difference voltages 23A and 23B consisting of single-ended signals in opposite phases are input to the set input terminal and the reset input terminal, a single-ended signal in phase with the first output difference voltage 23A is output to the set output terminal. The first gate drive signal generating circuit 9 outputs this single-ended signal to the first switching element 61 as the first gate drive signal 25A.
[0049] The second gate drive signal generating circuit 10 is composed of a waveform shaping circuit for a square wave. For example, an RS flip-flop, which is a logic circuit, is used as the waveform shaping circuit. This RS flip-flop operates with a predetermined low potential as a reference. For example, in this RS flip-flop, the set input terminal is connected to the connection point N5 via a resistor element R28, the reset input terminal is connected to the connection point N6 via a resistor element R27, and the set output terminal is connected to the gate of the second switching element 62. Since a pair of second output difference voltages 24A and 24B consisting of single-ended signals in opposite phases are input to the set input terminal and the reset input terminal, a single-ended signal in phase with the second output difference voltage 24A is output to the set output terminal. The second gate drive signal generating circuit 10 outputs this single-ended signal to the second switching element 62 as the second gate drive signal 25B.
[0050] It should be noted that other rectangular wave shaping circuits may be used as the waveform shaping circuit.
[0051] [Operation of the gate drive circuit 100] Next, the operation of the gate drive circuit 100 configured as above will be described with reference to FIG. 3 and FIG. 4A to FIG. 4C. FIG. 4A is a waveform diagram showing the waveform of the differential signal 21 on which common mode noise is superimposed. The upper waveform diagram of FIG. 4A shows the waveform of the positive signal 21A, and the lower waveform diagram of FIG. 4A shows the waveform of the negative signal 21B. FIG. 4B is a waveform diagram showing the waveform of the differential signal 21 induced in the first pulse transformer 3 by the differential signal 21 of FIG. 4A. FIG. 4C is a waveform diagram showing the waveforms of the input differential voltages 22A and 22B generated by the input differential voltage generating circuit 6 from the signal derived from the differential signal 21 induced in the first pulse transformer 3 of FIG. 4B.
[0052] 3, a logic circuit 31 generates an in-phase signal 12A and an anti-phase signal 12B from a gate control signal 11 from a control board 1. A positive signal generating circuit 32 outputs a positive signal 21A obtained by amplifying the in-phase signal 12A. A negative signal generating circuit 33 outputs a negative signal 21B obtained by amplifying the anti-phase signal 12B. The positive signal 21A and the negative signal 21B are input to a first end EP1 and a second end EP2 of a primary winding of a first pulse transformer 3, respectively.
[0053] 4A, the positive signal 21A and the negative signal 21B are both single-ended signals that take two values, a high level of a positive voltage (5V) and a low level of zero voltage (potential of the first ground GND1: 0V), and have opposite phases to each other. At time t0, the positive signal 21A and the negative signal 21B are input to the first end EP1 and the second end EP2 of the primary winding, respectively.
[0054] In the first half cycle of the positive signal 21A and the negative signal 21B, at time t0, the positive voltage of the positive signal 21A is applied to the first terminal EP1 and the zero voltage of the negative signal 21B is applied to the second terminal EP2 in the primary winding of the first pulse transformer, so that an excitation current flows from the first terminal EP1 to the neutral point MP1. Referring to FIG. 4B, this induces a voltage from the second terminal EP2 to the first terminal EP1 in the primary winding of the first pulse transformer 3. In this case, since the potential of the neutral point MP1 of the primary winding is 0V, the voltage V1 of the first terminal EP1 becomes a positive voltage. On the other hand, since the second terminal EP2 is connected to the first ground GND1 via the resistive element R8 at this time t0, the voltage V2 of the second terminal EP2 becomes a negative voltage, and a current flows from the neutral point MP1 to the second terminal EP2. At this time, a voltage according to the turns ratio of the first pulse transformer 3 and the second pulse transformer 5 is induced in the secondary winding of the first pulse transformer 3 and the primary winding and secondary winding of the second pulse transformer 5 by the above excitation current.
[0055] In the next half cycle of the positive signal 21A and the negative signal 21B, at time t1, the zero voltage of the positive signal 21A is applied to the first terminal EP1 and the positive voltage of the negative signal 21B is applied to the second terminal EP2 in the primary winding of the first pulse transformer 3, so that an excitation current flows from the second terminal EP2 to the neutral point MP1. This induces a voltage from the first terminal EP1 to the second terminal EP2 in the primary winding of the first pulse transformer 3. In this case, since the potential of the neutral point MP1 of the primary winding is 0V, the voltage V2 of the second terminal EP2 becomes a positive voltage. On the other hand, since the first terminal EP1 is connected to the first ground GND1 via the resistive element R7 at this time t1, the voltage V1 of the first terminal EP1 becomes a negative voltage, and a current flows from the neutral point MP1 to the first terminal EP1. At this time, a voltage according to the turn ratio of the first pulse transformer 3 and the second pulse transformer 5 is induced in the secondary winding of the first pulse transformer 3 and the primary winding and secondary winding of the second pulse transformer 5 by the above excitation current. After that (t2, t3, ...), the above one cycle is repeated.
[0056] In this way, the positive signal 21A and the negative signal 21B are converted by the first pulse transformer 3 into a pair of single-ended voltage signals having voltages V1 and V2, respectively, with twice the amplitude and in opposite phases (positive and negative are opposite) to each other, and are transmitted to the secondary winding of the second pulse transformer 5 via the transmission cable 4.
[0057] Here, the common mode noise removal action on the input side of the gate drive circuit 100 will be described. With reference to FIG. 4A, for example, it is assumed that common mode noise is superimposed on the positive signal 21A and the negative signal 21B between time t0 and time t1. With reference to FIG. 3, the common mode noise superimposed on the positive signal 21A causes an excitation current to flow between the first end EP1 and the neutral point MP1 of the primary winding of the first pulse transformer 3, and the common mode noise superimposed on the negative signal 21B causes an excitation current to flow between the second end EP2 and the neutral point MP1 of the primary winding of the first pulse transformer 3. However, as shown in FIG. 4B, since both excitation currents are currents in the opposite directions, voltages with opposite positive and negative polarities are induced in the primary windings, and the two are offset by each other. In this way, the common mode noise superimposed on the positive signal 21A and the negative signal 21B is removed from the pair of single-ended voltage signals converted from the positive signal 21A and the negative signal 21B by the first pulse transformer 3. Note that the common mode noise superimposed on the transmission cable 4 is also removed from the pair of single-ended voltage signals by the second pulse transformer 5 through the same action as described above.
[0058] 3, in the input differential voltage generating circuit 6, the input differential voltages 22A and 22B are generated from a pair of single-ended voltage signals transmitted to the secondary winding of the second pulse transformer 5 as follows. Referring to FIG. 4C, a single-ended voltage signal corresponding to the voltage V1 in FIG. 4B appears at the high-potential end of the resistor element R9. When the connection point N2 is used as a reference, the intermediate voltage of the amplitude of this single-ended voltage signal becomes a low-level zero voltage, so that the single-ended voltage signal has a waveform as shown in the upper part of FIG. 4C. On the other hand, a single-ended voltage signal corresponding to the voltage V2 in FIG. 4B appears at the low-potential end of the resistor element R10. When the connection point N2 is used as a reference, the intermediate voltage of the amplitude of this single-ended voltage signal becomes a low-level zero voltage, so that the single-ended voltage signal has a waveform as shown in the lower part of FIG. 4C. Therefore, the pair of input differential voltages 22A and 22B have waveforms corresponding to the positive signal 21A and the negative signal 21B in FIG. 4A, respectively.
[0059] In the input differential voltage generating circuit 6, a pair of resistor elements R9 and R10 pass a load current through the second pulse transformer 5, and a corresponding load current also flows through the first pulse transformer 3. Fig. 3 shows the current through the transmission path of the differential signal 21 when the positive signal 21A is at a high level. This reduces the impedance of the first pulse transformer 3 and the second pulse transformer 5, allowing a large current to flow through the transmission path of the differential signal 21 including the first pulse transformer 3, the transmission cable 4, and the second pulse transformer 5, thereby improving the ability to remove common-mode noise on the input side of the gate drive circuit 100.
[0060] 3, when common mode noise is superimposed on a pair of wirings extending from the secondary winding of the second pulse transformer 5 to the first and second differential amplifier circuits 7, 8, the common mode noise on the pair of wirings has opposite positive and negative signals in the pair of input differential voltages 22A, 22B generated by the input differential voltage generation circuit 6. The first and second differential amplifier circuits 7, 8 differentially amplify the pair of input differential voltages 22A, 22B, thereby removing the superimposed common mode noise.
[0061] In addition, due to the state of the wiring from the secondary winding of the second pulse transformer 5 to the first and second differential amplifier circuits 7 and 8, the timings at which the pair of input differential voltages 22A and 22B are input to the first and second differential amplifier circuits 7 and 8 may be slightly different from each other, and when the first and second differential amplifier circuits 7 and 8 operate at high speed, the slight difference in timing may prevent the common mode noise from being completely removed. However, since the first and second gate drive signal generating circuits 9 and 10 are configured with a waveform shaping circuit, the waveforms of the pair of first output differential voltages 23A and 23B and the pair of second output differential voltages 24A and 24B output from the first and second differential amplifier circuits 7 and 8 are shaped, thereby removing the remaining components of the common mode noise from the pair of first output differential voltages 23A and 23B and the pair of second output differential voltages 24A and 24B. In particular, if the waveform shaping circuit is a flip-flop, the noise in which the common mode noise is converted to normal mode in the circuit at the previous stage is preferably removed. In this manner, common mode noise is removed at the output side of the gate drive circuit 100.
[0062] [Mounting on the board] 3, in the push-pull amplifier circuit 500, the signal conversion circuit 2 and the first pulse transformer 3 are mounted on a first board 81, and the second pulse transformer 5, the input difference voltage generation circuit 6, the first differential amplifier circuit 7, the second differential amplifier circuit 8, the first gate drive signal generation circuit 9, the second gate drive signal generation circuit 10, and a pair of switching elements 60 are mounted on a second board 82. The secondary winding of the first pulse transformer 3 on the first board 81 and the primary winding of the second pulse transformer 5 on the second board 82 are connected by a transmission cable 4.
[0063] Therefore, by arranging the second board 82, for example, near a switching module 800 (see Figure 5) driven by a pair of switching elements 60, and extending the transmission cable 4 to arrange the first board 81 away from the switching module 800 and near the control board 1, the computer constituting the control board 1 can be suitably protected from common mode noise generated by the switching operation of the switching module 800.
[0064] [Application to switching power supplies] Fig. 5 is a circuit diagram showing the operation of a switching power supply device 1000 using the push-pull amplifier circuit 500 of Fig. 3. In Fig. 3, reference numerals of detailed elements are omitted in order to make the drawing easier to see.
[0065] 5, the switching power supply device 1000 includes a switching module 800 and first and second push-pull amplifier circuits 500A and 500B. The switching module 800 includes a high-side switching element SWH and a low-side switching element SWL. The high-side switching element SWH and the low-side switching element SWL are configured by, for example, IGBTs. In addition, a reverse diode is connected in parallel to each of the high-side switching element SWH and the low-side switching element SWL.
[0066] The first push-pull amplifier circuit 500A includes a first gate drive circuit 100A and a first pair of switching elements 60A. The second push-pull amplifier circuit 500B includes a second gate drive circuit 100B and a second pair of switching elements 60B.
[0067] The high-side switching element SWH is connected to a first pair of switching elements 60A of the first push-pull amplifier circuit 500A, and the output of the first pair of switching elements 60A is input to its gate. The low-side switching element SWL is connected to a second pair of switching elements 60B of the second push-pull amplifier circuit 500B, and the output of the second pair of switching elements 60B is input to its gate. In addition, the control board 1 and the signal conversion circuits 2 of the first and second gate drive circuits 100A and 100B are grounded. In addition, the first pair of switching elements 60A is connected to the frame ground, and the second pair of switching elements 60B is connected to the signal ground.
[0068] In the switching power supply device 1000 configured as above, the high-side gate control signal 11A is input from the control board 1 to the logic circuit 31 of the first gate drive circuit 100A. Then, the first and second gate drive signals are generated in the first gate drive circuit 100A, and the high-side gate drive signal 26A is output from the first pair of switching elements 60A to the gate of the high-side switching element SWH. On the other hand, the low-side gate control signal 11B is input from the control board 1 to the logic circuit 31 of the second gate drive circuit 100B. Then, the second gate drive circuit 100B generates the first and second gate drive signals, and the low-side gate drive signal 26B is output from the second pair of switching elements 60B to the gate of the low-side switching element SWL. Here, the high-side gate control signal 11A and the low-side gate control signal 11B are out of phase with each other, as shown in FIG. 5.
[0069] As a result, the high-side switching element SWH and the low-side switching element SWL are turned on and off at different timings, and the control power of the switching module 800 is output from the connection point Nout between the high-side switching element SWH and the low-side switching element SWL.
[0070] By the way, the voltage (potential) Vm of the connection point Nout fluctuates by turning on and off the high side switching element SWH and the low side switching element SWL, respectively. This fluctuation in the voltage Vm of the connection point Nout generates switching noise as shown in FIG. 6. FIG. 6 is a schematic diagram showing switching noise generated by the switching module 800 of FIG. 5. In FIG. 6, Vm1 indicates the voltage fluctuation of the connection point Nout when the low side switching element SWL turns on while the high side switching element SWH is off, and Vm2 indicates the voltage fluctuation of the connection point Nout when the low side switching element SWL turns off while the high side switching element SWH is on. The voltage fluctuation Vm1 and the voltage fluctuation Vm2 occur at different timings, but for convenience, they are shown to occur at the same timing in FIG. 6. Note that FIG. 6 was created by tracing an image of a waveform of an actually obtained voltage, so the waveform is not accurate.
[0071] When the voltage Vm (Vm1, Vm2) of the connection point Nout fluctuates as shown in Fig. 6, switching noise is radiated from the connection point Nout. Then, this switching noise is superimposed on the wiring of the first and second gate drive circuits 100A, 100B as common mode noise. However, the common mode noise superimposed on the wiring of the first and second gate drive circuits 100A, 100B is removed as described above.
[0072] As described above, the gate drive circuit 100 of the present disclosure can remove common mode noise superimposed on the output side and the input side. In addition, the computer constituting the control board 1 can be suitably protected from common mode noise generated by the switching operation of the switching module 800.
[0073] Numerous modifications and other embodiments will be apparent to those skilled in the art in light of the above description, and therefore the above description is to be construed as illustrative only. [Industrial Applicability]
[0074] The gate drive circuit of the present invention is useful as a gate drive circuit capable of removing common mode noise superimposed on the output side and the input side. [Explanation of symbols]
[0075] 1 Control Board 2. Signal conversion circuit 3. First Pulse Transformer 4 Transmission cable 5. Second Pulse Transformer 6 Input Difference Voltage Generation Circuit 7 First differential amplifier circuit 8 Second differential amplifier circuit 9. First gate drive signal generating circuit 10 Second gate drive signal generating circuit 11 Gate control signal 12A in-phase signal 12B Anti-phase signal 21 Differential Signal 21A Positive Signal 21B Negative signal 22A, 22B Input differential voltage 23A, 23B First output differential voltage 24A, 24B Second output differential voltage 25A First Gate Drive Signal 25B Second gate drive signal 26A high side gate drive signal 26B Low side gate drive signal 31 Logic Circuits 32 Positive signal generating circuit 33 Negative signal generating circuit 60 Pair of switching elements 61 First switching element 62 Second switching element 81 First board 82 Second board 100 Gate drive circuit 500 Push-pull amplifier circuit 800 Switching Module 1000 Switching Power Supply GND1 First ground GND2 Second ground
Claims
1. a signal conversion circuit that operates using the potential of the first ground as a reference potential and converts a gate control signal, which is a single-ended signal, into a differential signal consisting of a positive signal and a negative signal whose signal level difference corresponds to the gate control signal; a first pulse transformer having a primary winding and a secondary winding that are electrically insulated from each other and each have a neutral point, the neutral point of the primary winding being set to the potential of the first ground, and a positive signal and a negative signal of the differential signal being input to both ends of the primary winding, respectively; an input differential voltage generating circuit having a pair of resistor elements connected in series with each other, the opposite ends and a connection point of the pair of resistor elements being connected to the opposite ends and the neutral point of the secondary winding of the first pulse transformer directly or via a transmission cable and a second pulse transformer, and generating a pair of input differential voltages across the pair of resistor elements with the potential of the connection point as a reference; a differential amplifier circuit electrically connected to the input differential voltage generation circuit, which differentially amplifies the pair of input differential voltages and outputs a pair of output differential voltages; a gate drive signal generation circuit electrically connected to the differential amplifier circuit, which generates a gate drive signal that is a single-ended signal based on a predetermined potential based on the pair of output differential voltages, and outputs the gate drive signal to a switching element that operates based on the potential of a second ground.
2. the second pulse transformer has a primary winding and a secondary winding that are electrically insulated from each other and each have a neutral point, and both ends and the neutral point of the primary winding are electrically connected to both ends and the neutral point of the secondary winding of the first pulse transformer, respectively, via the transmission cable; 2. The gate drive circuit according to claim 1, wherein the input differential voltage generating circuit has both ends and the connection point of the pair of resistive elements connected to both ends and the neutral point of the secondary winding of the second pulse transformer, respectively.
3. the two switching elements constitute a first switching element and a second switching element that are push-pull connected to each other, The differential amplifier circuit includes a first differential amplifier circuit and a second differential amplifier circuit, The gate drive signal generation circuit includes first and second gate drive signal generation circuits, The first differential amplifier circuit is electrically connected to the input differential voltage generation circuit and is a circuit that differentially amplifies the pair of input differential voltages to output a pair of high-potential first output differential voltages. The second differential amplifier circuit is electrically connected to the input difference voltage generation circuit and differentially amplifies the pair of input difference voltages to output a pair of second output difference voltages at a lower potential than the pair of first output difference voltages. The first gate drive signal generation circuit is electrically connected to the first differential amplifier circuit and generates a first gate drive signal, which is the gate drive signal referenced to a positive potential, based on the pair of first output differential voltages, and outputs the first gate drive signal to the first switching element.
3. The gate drive circuit according to claim 1, wherein the second gate drive signal generation circuit is electrically connected to the second differential amplifier circuit, generates a second gate drive signal, which is the gate drive signal based on a negative potential, based on the pair of second output difference voltages, and outputs the second gate drive signal to the second switching element.
4. The gate drive circuit according to claim 1 or 2, wherein the gate drive signal generation circuit includes a flip-flop that receives the pair of output differential voltages and outputs a single-ended signal referenced to a predetermined potential, and outputs the single-ended signal as the gate drive signal.