Method for electronic arrangement and electronic arrangement device
Patent Information
- Application Number
- JP2023089123
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-05-30
- Publication Date
- 2026-02-19
AI Technical Summary
Conventional quantum computers face challenges in efficiently performing qubit operations due to the need for numerous control lines, leading to spatial constraints and potential collisions during electron movement, which can result in undesired calculation results and deadlocks.
A quantum computer configuration with a quantum bit array, bus region, aisle area, and sheet area, allowing controlled electron movement through specific channels to avoid collisions and deadlocks, enabling efficient qubit operations.
The proposed configuration allows for efficient and deadlock-free qubit operations by ensuring electrons move according to predefined rules, ensuring desired calculation results without collisions.
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Abstract
Description
[Technical field]
[0001] The present invention relates to an electron configuration method and an electron configuration device. [Background technology]
[0002] To realize a quantum computer, it is necessary to implement quantum bits that realize the superposition of the values 0 and 1.
[0003] For example, in a silicon-electron quantum computer, quantum dots are implemented using field-effect transistors or the like, and quantum bits are realized by trapping electrons in them.
[0004] Arithmetic operations (gate operations) on the quantum bit implemented in this way are performed by applying a static magnetic field or an electromagnetic pulse to the quantum bit.
[0005] These calculations require control lines to apply voltages and currents to the electrodes that control the quantum bits. In a design that provides individual control lines for each quantum bit, the number of control lines increases as the number of quantum bits increases.
[0006] On the other hand, given the spatial constraints on the placement area of the control lines, implementing a large number of quantum bits becomes extremely difficult.
[0007] To address this problem, a method of simultaneously controlling multiple quantum bits with one control line is effective, as shown in Patent Document 1. In the technology shown in Patent Document 1, quantum bits are arranged in an array, and a common control line is provided for each column or row. Operations on the quantum bits are then realized by this control line.
[0008] More specifically, the present invention relates to an electron arrangement device having a first layer provided on a fin and a second layer provided on the first layer, the fin having a quantum bit array in which a plurality of quantum bits are arranged in a row in a first direction, and an interaction array in which a plurality of quantum bit interactions are arranged in a row in the first direction, the quantum bit array and the interaction array being arranged alternately in a second direction different from the first direction, the first layer having a first gate electrode array arranged in the first direction and controlling the quantum bits of the quantum bit array, and a second gate electrode array arranged in the first direction and controlling the quantum bit-to-quantum bit interactions of the interaction array, the second layer having a third gate electrode array arranged in the second direction and a fourth gate electrode array arranged adjacent to the third gate electrode array in the second direction, the third gate electrode array and the fourth gate electrode array controlling some of the quantum bits and some of the quantum bit-to-quantum bit interactions, respectively. [Prior art documents] [Patent documents]
[0009] [Patent Document 1] Patent Publication No. 2021-027142 [Non-patent literature]
[0010] [Non-Patent Document 1] Li,Gushu,Yufei Ding,and Yuan Xie.“Tackling the qubit mapping problem for NISQ-era quantum devices.”ASPLOS 2019.arXiv:1809.02573 Summary of the Invention [Problem to be solved by the invention]
[0011] However, in the above-mentioned conventional technology, the control lines are common to each column or row. Therefore, when an arithmetic operation is performed on a certain quantum bit, the same arithmetic operation is also performed on unrelated quantum bits in the same column or row. As a result, a new problem occurs in which an unexpected arithmetic result is obtained.
[0012] As a means to solve the above problem, there are cases where quantum bit movement operations can be utilized in silicon electronic quantum computers.
[0013] A quantum bit transfer operation is an operation in which an electron constituting a quantum bit is spatially moved to an adjacent quantum dot (which is also empty and has no electrons present).
[0014] This movement operation allows the isolation of unrelated qubits from the qubits it controls, potentially reducing unwanted influences on the qubits.
[0015] In addition, primitive operations in quantum computers include one-qubit operations that manipulate one quantum bit, and two-qubit operations that allow two quantum bits to interact with each other.
[0016] To realize a two-qubit operation, the two target qubits must be placed adjacent to each other. However, the number of qubits that can be placed adjacent to each other is finite. Therefore, in a quantum program consisting of a large number of qubits, there may be pairs of qubits that cannot be placed adjacent to each other.
[0017] The quantum bit movement operation is also an effective means of solving this problem. When performing a two-qubit operation on two quantum bits that are not adjacent to each other, the quantum bits can be made adjacent by moving one (or both) of the electrons using the above-mentioned movement operation.
[0018] The above-mentioned movement operation is realized by applying a voltage to the electrodes, similar to the arithmetic operation, and therefore there is a restriction that the movement operation can be performed on unrelated electrons in the same column or row as the electron to be moved.
[0019] Therefore, in order to move the electron to the desired position, it is necessary to determine the movement operation procedure taking into account the above constraints. For example, consider moving electron A downward to make it adjacent to electron B (see Figure 4). In this case, electron C, which is in the same row as A, will also move downward. However, since electron D is located in the destination of C, performing this move operation may cause electrons C and D to collide, making it impossible to properly maintain quantum information. Therefore, in order to make electron A and B adjacent to each other, a different move procedure must be devised.
[0020] Thus, under the above constraints, some transfer operations cannot be performed in order to avoid collisions of electrons, and a combination of the transfer operations that can be performed may not be able to perform a particular quantum bit operation.
[0021] For example, the example in Figure 4 shows two types of movement operations for executing a two-qubit operation between electrons A and B. Regardless of which operation is selected, the two-qubit operation between electrons A and B can be executed. However, if the operation in Figure 4 is selected, the arrangement will not be able to execute the two-qubit operation between electrons C and D.
[0022] Thus, when performing multiple quantum bit operations under the above constraints, there is a problem in that it is possible to reach an impasse in which it is not possible to perform the desired quantum bit operations.
[0023] For example, the following technology has been proposed as a conventional technology for dealing with a similar problem (see Non-Patent Document 1): In this technology, in a superconducting quantum bit array, in order to place specific quantum bits adjacent to each other, a SWAP operation is performed, which is an arithmetic operation for exchanging quantum information between two quantum bits.
[0024] However, the premise of this method is that the quantum bit array targeted by this method has a structure that allows any quantum bit to be reached from a certain quantum bit. Therefore, no matter what procedure is used to execute the SWAP operation, it will not reach an impasse (the number of times the SWAP operation is executed depends on the procedure for executing the operation). Therefore, the above method does not include any measures to avoid reaching an impasse.
[0025] In addition, the above-mentioned method does not assume row or column-based calculations. Therefore, it is difficult to directly apply it to the problem addressed by the present invention. For these reasons, the conventional technology cannot avoid reaching a deadlock in which it is not possible to execute the desired quantum bit calculations.
[0026] Therefore, an object of the present invention is to provide a technique that can efficiently obtain a desired calculation result while appropriately avoiding deadlocks in quantum bit operations involving a large number of quantum bits. [Means for solving the problem]
[0027] The electron placement method of the present invention that solves the above-mentioned problems is characterized in that a quantum computer has a quantum bit array composed of a plurality of quantum dots capable of storing electrons, a bus region that crosses or runs across the quantum bit array, an isle region in the quantum bit array that is perpendicular to the bus region, and a sheet region between the bus region and the isle region in which quantum bits are placed, and in an environment in which the sheet region and the bus region are connected by the isle region, a first quantum bit initially placed in a specified sheet region is made to reach the bus region through the isle region connected to the sheet region, and is moved through the bus region to a position adjacent to a second quantum bit to be operated on.
[0028] The electron placement device of the present invention is a quantum computer having a quantum bit array composed of a plurality of quantum dots capable of storing electrons, a bus region that crosses or runs across the quantum bit array, an isle region in the quantum bit array that is perpendicular to the bus region, and a sheet region between the bus region and the isle region in which quantum bits are placed, and in an environment in which the sheet region and the bus region are connected by the isle region, a first quantum bit initially placed in a specific sheet region reaches the bus region through the isle region connected to the sheet region, and is moved through the bus region to a position adjacent to a second quantum bit to be operated on. Effect of the Invention
[0029] According to the present invention, it is possible to efficiently obtain a desired calculation result while appropriately avoiding deadlocks in quantum bit operations in which a large number of quantum bits are arranged. [Brief description of the drawings]
[0030] [Figure 1] FIG. 2 is a diagram illustrating a configuration example of a quantum bit array according to the present embodiment. [Figure 2A] FIG. 2 is a diagram showing an example of electron transfer rules in this embodiment. [Figure 2B] FIG. 2 is a diagram showing an example of electron transfer rules in this embodiment. [Figure 3A] FIG. 11 is a diagram illustrating an example of block control in the present embodiment. [Figure 3B] FIG. 11 is a diagram illustrating an example of block control in the present embodiment. [Figure 3C] FIG. 11 is a diagram illustrating an example of block control in the present embodiment. [Figure 4] FIG. 13 is a diagram showing an example of electron transfer when a deadlock occurs in this embodiment. [Diagram 5] FIG. 1 is a diagram illustrating an example of the configuration of a quantum computer system according to an embodiment of the present invention. [Figure 6] 1 is a diagram showing an example of electron configuration in a quantum bit array according to the present embodiment. FIG. [Figure 7] FIG. 1 is a diagram showing an example of electron transfer in this embodiment. [Figure 8] FIG. 2 is a diagram showing an example of a flow of an electron arrangement method according to the present embodiment. [Figure 9] FIG. 1 is a diagram showing an example of electron transfer in this embodiment. [Figure 10] FIG. 1 is a diagram illustrating an example of a quantum bit operation in this embodiment. [Figure 11] FIG. 2 is a diagram showing a detailed example of electron transfer in this embodiment. [Figure 12] FIG. 2 is a diagram showing a detailed example of electron transfer in this embodiment. [Figure 13] FIG. 2 is a diagram showing a detailed example of electron transfer (return to the original position) in this embodiment. [Figure 14] FIG. 2 is a diagram showing a detailed example of electron transfer (return to the original position) in this embodiment. [Figure 15] FIG. 2 is a diagram showing a detailed example (domestic collision) of electron transfer in this embodiment. [Figure 16] FIG. 13 is a diagram showing another configuration example (increasing the isle region) of the quantum bit array in this embodiment. [Figure 17] FIG. 13 is a diagram showing another configuration example (increased bus area) of the quantum bit array in this embodiment. [Figure 18] FIG. 13 is a diagram showing another configuration example (with a fixed calculation area) of the quantum bit array in this embodiment. [Figure 19] FIG. 1 is a diagram showing an example of electron transfer in this embodiment. [Figure 20] FIG. 2 is a diagram showing a detailed example of electron transfer in this embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0031] <Quantum bit array configuration and movement rules> Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. Fig. 1 is a diagram showing a configuration example of a quantum bit array implemented in an electron arrangement device of this embodiment. The electron arrangement device 100 shown in Fig. 1 is a quantum computer that can efficiently obtain a desired calculation result while appropriately avoiding deadlocks in quantum bit operations in which a large number of quantum bits are arranged.
[0032] The quantum bit array in this embodiment is configured in such a way that multiple quantum dots are appropriately connected by channels, as shown in the example of FIG. 1, and quantum bits are configured by placing electrons in the quantum dots in this configuration.
[0033] The electrons constituting the quantum bit can move to the adjacent quantum dot through the channel. However, only the movement according to the movement rules shown in Figures 2A and 2B is permitted, and there are restrictions on the manner of movement. For example, in the case of movement in the Y-axis direction (the vertical direction in the lattice constituting the quantum bit array in the figure), when an electron of a certain quantum bit (quantum bit "A" in the figure) is moved, other quantum bits in the same row (quantum bits "B", "C", and "D" in the figure) also move at the same time.
[0034] However, each source quantum dot and the destination quantum dot must be connected by a channel, and if no channel exists, the quantum dot will not move.
[0035] In addition, if an electron is already present in the destination quantum dot, the electrons will collide and the transfer will be impossible. In other words, transfer is permitted only when the source and destination quantum dots are connected by a channel and the destination quantum dot is empty (no electrons are present).
[0036] The same restrictions and modes of movement are observed in the X-axis direction as shown in Figure 2B. Electrons in the same column move simultaneously, but only if the quantum dots are connected by channels and if there are no electrons present in the quantum dot at the destination.
[0037] However, as an exceptional operation technique for the above-mentioned movement restrictions, it is also possible to adopt a so-called block control technique (known technique). As shown in Figures 3A to 3C, this block control allows only specific electrons to move in the X-axis direction if the movement source is a "column without vertical channels (normal column)" and the movement destination is a "column with vertical channels," or allows movement if the movement source is a "column with vertical channels" and the movement destination is a "column without vertical channels (normal column)."
[0038] In this block control, when electrons are adjacent, for example, when quantum bit electron "2" and quantum bit electron "4" are adjacent in Figures 3B and 3C, the condition for movement is that no electrons are present in the quantum dots in the rear row of the destination quantum dot row (vertical channel row). However, even if the destination vertical channel row is the end row of the array, block control, i.e. movement, is possible even if the electrons are adjacent. <The current situation is at an impasse> A quantum computer (electron placement device) repeats the movement operation of the electrons present in the quantum dots that are the object of movement under the above-mentioned movement restrictions, and moves the electrons to the desired position (the quantum dot adjacent to the quantum dot of the electron that is the object of the quantum bit operation). However, when performing such movement ad-hoc, a situation may arise where the electron cannot move due to movement restrictions during or at the destination, i.e., where the electrons are stuck.
[0039] This state is illustrated in Fig. 4. In either case, the movement restriction is based on the specification of block control, but by employing the electron arrangement method of this embodiment, such a deadlocked situation can be avoided efficiently and accurately. <Example of the configuration of an electron arrangement device> The electron configuration device 100 of this embodiment is configured with either the quantum computer 100 or the quantum compiler device 200 shown in FIG. 5 (of course, a system in which these are appropriately linked may be defined as the electron configuration device).
[0040] For example, quantum computer 100 includes a quantum bit array control unit 110 that controls the movement of electrons in quantum bit array 101. Quantum compiler 200 also includes a quantum bit control procedure generator 210 that generates quantum bit control procedure 203 based on structural information 201 (e.g., information on bus regions, aisle regions, and seat regions) of quantum bit array 101 and quantum bit operation information 202 (quantum program).
[0041] This quantum bit control procedure 203 is provided to the quantum bit array control unit 110 of the quantum computer 100, and is used as procedure information for the operation of moving electrons in the actual quantum bits. The above-mentioned procedure information is information on the bus, aisle, and sheet areas on the quantum bit array, and procedure information for moving quantum bits (electrons constituting the quantum bits) in the order of sheet area → aisle area → bus area. In other words, the quantum computer 100 moves the quantum bits in the order of sheet area → aisle area → bus area based on the procedure information for such movement operations.
[0042] It should be noted that the hardware configuration of the quantum computer 100 and the quantum compiler device 200 is assumed to be, for example, based on a silicon quantum dot system (a so-called silicon quantum computer), but is not limited to this. <Electron placement and movement in quantum bit arrays> An example of electron arrangement in the quantum bit array of this embodiment is shown in Fig. 6. As shown in the figure, the quantum bit array of this embodiment is configured with a bus area that crosses the quantum bit storage area and an aisle area for each quantum bit to access the bus area, and the area surrounded by this bus area and aisle area is defined as a sheet area. The sheet area becomes the fixed position (initial arrangement position) of the electrons.
[0043] In this state, as shown in the example of electron movement in Figure 7, the electron of a quantum bit (the electron in the second row of the first column) moves through the bus region and the aisle region to an adjacent position (the sixth row of the sixth column in the figure) of another quantum bit (the sixth row of the seventh column in the figure).
[0044] After the calculation operation is performed, the object returns to the original sheet area (the second row of the first column) via the same path. In this way, it is guaranteed that the object can return to the original position (the original position in the sheet area) after the calculation operation is performed, so there is no risk of getting stuck in the conventional ad-hoc movement operation.
[0045] Such a form of migration is shown in the flow in Fig. 8. That is, the quantum computer 100 acquires the quantum bit control procedure 203 from the quantum compiler 200 (s10). Of course, the quantum computer 100 may have the same configuration and functions as the quantum compiler 200 and generate the quantum bit control procedure 203 by itself. Similarly, the quantum compiler 200 may be the entity that executes this flow, and a situation may be adopted in which the quantum compiler 200 has the configuration and functions of the quantum computer 100.
[0046] The above-mentioned quantum bit control procedure 203 defines a bus region that crosses or traverses the quantum bit array, an isle region in the quantum bit array that is perpendicular to the bus region, and a sheet region between the bus region and the isle region in which quantum bits are arranged, and includes configuration information in which the sheet region and the bus region are connected by the isle region, and procedure information for moving a desired electron through a quantum dot in the quantum bit array under such configuration.
[0047] In addition, based on the quantum bit control procedure 203 obtained in s10, the quantum computer 100 causes the first quantum bit initially placed in a specified sheet area to reach the bus area through the aisle area connected to that sheet area (s11).
[0048] Furthermore, quantum computer 100 moves the quantum bit that has reached the bus region in s11, via the bus region, to a quantum dot located adjacent to the second quantum bit that is the subject of the operation (s12).
[0049] Furthermore, the quantum computer 100 executes a quantum bit operation (for example, one shown in FIG. 10) using the quantum bits adjacent to each other at s12 (s13), and ends the process by outputting the result (s14). After that, the quantum computer 100 returns the quantum bit to its original position via the same route. In addition to the above-mentioned moving method, the quantum bit may be returned to its original position by a chain reaction with other quantum bits, as shown in FIG. 9.
[0050] In any case, by performing movement and returning to the original position according to this operating method, any electron can be moved from the initial position (original position) to the adjacent position of any other electron, and can always be returned to the initial position afterwards.
[0051] Each figure shows an example of the process of s13 in the above flow, that is, the movement procedure (Figs. 11-12) for executing the quantum bit operation (Fig. 10) and the subsequent return to the original position (Figs. 13-15). In this case, an example is shown in which the quantum bit "q1" existing in the second row of the first column (original position) is moved to the adjacent quantum dot of the quantum bit "q2" to be operated on, while taking into account the movement restrictions mentioned above. Naturally, the movement also takes into account the principle of simultaneous simultaneous movement of electrons in each direction of the X-axis and Y-axis. <Increase in aisle and bus areas> 16 shows another example of the configuration of the quantum bit array in this embodiment (increasing the number of isle regions). In the above example, isle regions are configured every two columns in the quantum bit array to perform quantum bit movement, but isle regions may be configured every other column.
[0052] By adopting this configuration, it is expected that the constraints on the movement of quantum bits will be reduced and the movement efficiency will be improved compared to when the isle regions are arranged in alternating rows.
[0053] Similarly, the bus area may be increased as shown in Fig. 17. In the above example, only one bus area is arranged on the quantum bit array, but in the example of Fig. 17, the bus areas are arranged every two rows, resulting in a total of two bus areas.
[0054] By adopting such a configuration, it is expected that the constraints on quantum bit movement operations will be reduced and movement efficiency will be improved compared to when there is only one bus area. <Fixing the calculation area> Here, assume that the quantum bit array has a quantum bit operation region fixed to, for example, the seventh and eighth columns, as shown in Fig. 17. For example, if there is a quantum bit X (the one in the second row of the third column) to be moved and a quantum bit Y (the one in the sixth row of the first column) to be operated on, quantum computer 100 will move both X and Y to the fixed region (the seventh and eighth columns) that is specified as the operation region.
[0055] The quantum bit X to be moved is in the fourth row of the eighth column, and the quantum bit Y to be operated on is in the fourth row of the seventh column, i.e., the electrons are transferred to quantum dots adjacent to each other. A specific example of the movement operation is shown in Fig. 20, but the movement operation itself, while taking into account the constraints already mentioned, is performed by reaching the bus region through the aisle region connected to the sheet region in the original position, and then moving to a specified position in the fixed region through the bus region.
[0056] Although the best mode for carrying out the present invention has been specifically described above, the present invention is not limited to this, and various modifications can be made without departing from the spirit and scope of the present invention.
[0057] The description of this specification makes at least the following clear: That is, in the electron configuration method of this embodiment, the quantum computer may move the first quantum bit through the bus region to an isle region connected to the sheet region of the second quantum bit, and move the first quantum bit through the isle region to a position adjacent to the second quantum bit.
[0058] This enables electrons to move smoothly through the isle region to a position (quantum dot) adjacent to the quantum bit that is the subject of the calculation.
[0059] In addition, in the electron configuration method of this embodiment, the quantum computer may cause the second quantum bit to reach the bus region through an aisle region connected to the sheet region, and cause the first quantum bit and the second quantum bit to be adjacent to each other in the bus region.
[0060] According to this, the quantum bit to be moved and the quantum bit to be operated on are adjacent to each other in a bus region where movement is facilitated, making it possible to carry out efficient quantum bit operations.
[0061] Furthermore, in the electron configuration method of this embodiment, the quantum computer may cause the first quantum bit to reach the bus region through an isle region connected to the sheet region, and through the bus region to reach an isle region connected to the sheet region of the second quantum bit, and cause the second quantum bit to reach the isle region connected to the sheet region, so that the first quantum bit and the second quantum bit are adjacent to each other in the isle region connected to the sheet region of the second quantum bit.
[0062] According to this, the quantum bit to be moved and the quantum bit to be operated on are adjacent to each other in an isle region where movement is facilitated, making it possible to carry out efficient quantum bit operations.
[0063] Furthermore, in the electron configuration method of this embodiment, the quantum computer may hold an arithmetic region in the quantum bit array capable of performing arithmetic operations on quantum bits, and cause the first quantum bit to reach the bus region through an isle region connected to the sheet region and reach the arithmetic region through the bus region, and cause the second quantum bit to reach the bus region through an isle region connected to the sheet region and reach the arithmetic region through the bus region, thereby causing the first quantum bit and the second quantum bit to be adjacent to each other in the arithmetic region.
[0064] This makes it possible to place the quantum bit to be moved and the quantum bit to be operated on in a fixed calculation area (for example, a specific area widely reserved for calculations), enabling efficient quantum bit calculations to be performed.
[0065] Furthermore, in the electron configuration method of the present embodiment, the quantum computer may be configured to, in the quantum bit array, move other quantum bits in the same column or row as a specific quantum bit in unison in the same direction as the specific quantum bit, in conjunction with the movement of the specific quantum bit.
[0066] This makes it possible to move and manipulate quantum bits in each column and each row under the principle of simultaneous movement.
[0067] Furthermore, in the electron configuration method of this embodiment, the quantum computer executes block control in which, when the other quantum bits are moved all at once in the quantum bit array, only a specific quantum bit among the other quantum bits is left in its initial position without being moved, and the bus region may be defined and operated parallel to the possible movement directions of the block control.
[0068] According to this, so-called block control can be applied to the operation of moving electrons, which makes it possible to more flexibly select a moving path, etc. [Explanation of symbols]
[0069] 1 Network 100 Quantum computer (electron configuration device) 101 Qubit Array 110 Quantum bit array control unit 200 Quantum Compiler 201 Quantum bit array structure information 202 Quantum bit operation information 203 Quantum bit control procedure 210 Quantum bit control procedure generation unit
Claims
1. Quantum computers, In a quantum bit array composed of a plurality of quantum dots capable of storing electrons, a bus region that crosses or runs across the quantum bit array, an isle region in the quantum bit array that is orthogonal to the bus region, and a sheet region between the bus region and the isle region in which quantum bits are arranged, wherein the sheet region and the bus region are connected by the isle region; a first quantum bit initially placed in a predetermined sheet area is caused to reach the bus area through an aisle area connected to the sheet area, and is moved through the bus area to a position adjacent to a second quantum bit to be operated on; A method for arranging electrons.
2. The quantum computer In the movement of the first quantum bit, the first quantum bit is moved through the bus region to an isle region connected to a seat region of a second quantum bit, and then moved through the isle region to a position adjacent to the second quantum bit.
2. The electron configuration method according to claim 1 .
3. The quantum computer the second quantum bit reaches the bus region through an isle region connected to the seat region, and the first quantum bit and the second quantum bit are adjacent to each other in the bus region; 2. The electron configuration method according to claim 1 .
4. The quantum computer allowing the first quantum bit to reach the bus region through an isle region connected to the seat region, and through the bus region to reach an isle region connected to the seat region of the second quantum bit; allowing the second qubit to reach an isle region connected to the sheet region; the first quantum bit and the second quantum bit are adjacent to each other at the isle region connected to the sheet region of the second quantum bit; 2. The electron configuration method according to claim 1 .
5. The quantum computer In the quantum bit array, an operation area capable of performing an operation on a quantum bit is maintained; the first quantum bit reaches the bus region through an isle region connected to the sheet region, and reaches the operation region through the bus region, and the second quantum bit reaches the bus region through an isle region connected to the sheet region, and reaches the operation region through the bus region, thereby making the first quantum bit and the second quantum bit adjacent to each other in the operation region; 2. The electron configuration method according to claim 1 .
6. The quantum computer In the quantum bit array, as a predetermined quantum bit moves, other quantum bits in the same column or row as the predetermined quantum bit are moved simultaneously in the same direction as the predetermined quantum bit.
2. The electron configuration method according to claim 1 .
7. The quantum computer In the quantum bit array, when the other quantum bits are moved en masse, block control is executed to leave only a specific quantum bit among the other quantum bits at an initial position without moving the specific quantum bit, and the bus region is defined and operated parallel to the possible movement direction of the block control.
7. The electron configuration method according to claim 6.
8. A quantum computer, In a quantum bit array composed of a plurality of quantum dots capable of storing electrons, a bus region that crosses or runs across the quantum bit array, an isle region in the quantum bit array that is orthogonal to the bus region, and a sheet region between the bus region and the isle region in which quantum bits are arranged, wherein the sheet region and the bus region are connected by the isle region; A first quantum bit initially placed in a predetermined sheet area is caused to reach the bus area through an aisle area connected to the sheet area, and is moved through the bus area to a position adjacent to a second quantum bit to be operated on. An electron configuration device characterized by: