Integrated circuit element

Abstract

To provide an integrated circuit element with maximized process margin and improved reliability.SOLUTION: An integrated circuit element of the invention includes: a substrate including a cell region and a core region; a plurality of bit line structures arranged mutually isolated on the cell region, and including a bit line conductive film and a bit line capping film on the bit line conductive film; and a plurality of landing pads arranged on the plurality of bit line structures, and electrically connected to the substrate. The core region includes: a gate structure and a core capping film arranged on the gate structure; a direct contact plug extending perpendicular to the substrate; first peripheral circuit wiring patterns extending mutually isolated on a first plane at a first level of the substrate; and second peripheral circuit wiring patterns extending mutually isolated on a second plane at a second level different from the first level on the substrate.SELECTED DRAWING: Figure 7F

Description

[Technical field]

[0001] The present invention relates to integrated circuit devices, and more particularly to integrated circuit devices that include bit line peripheral (BLP) circuitry. [Background technology]

[0002] Recently, with the development of electronic technology, the downscaling of integrated circuit elements is progressing rapidly, and the feature size of the integrated circuit elements is becoming smaller, which necessitates the development of new structures that improve the electrical reliability of conductive patterns formed in a narrow area. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-96376 A Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE PRESENT DISCLOSURE The present invention has been made in consideration of the above-mentioned conventional techniques, and an object of the present invention is to provide an integrated circuit device having improved reliability by maximizing process margins.

[0005] Furthermore, the problems to be solved by the technical idea of ​​the present invention are not limited to those described below, and other problems will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] In order to achieve the above object, an integrated circuit device according to one aspect of the present invention includes a substrate including a cell region and a core region, a plurality of bit line structures arranged spaced apart from each other on the cell region, the bit line structures including a bit line conductive film and a bit line capping film on the bit line conductive film, and a plurality of landing pads arranged on the plurality of bit line structures and electrically connected to the substrate, wherein the core region includes a gate structure and a core capping film arranged on the gate structure, a direct contact plug extending perpendicular to the substrate, first peripheral circuit wiring patterns extending spaced apart from each other on a first plane at a first level on the substrate, and second peripheral circuit wiring patterns extending spaced apart from each other on a second plane at a second level different from the first level on the substrate.

[0007] According to another aspect of the present invention, an integrated circuit device is provided that includes a substrate including a cell region and a core region; a plurality of bit line structures extending parallel to each other in a first horizontal direction in the cell region; a plurality of buried contacts electrically connected to the cell region and filling a portion of a space between the plurality of bit line structures; a plurality of landing pads disposed on the plurality of buried contacts in the space between the plurality of bit line structures; a gate structure and a direct contact plug disposed in the core region; a first peripheral circuit wiring pattern disposed at a level higher than a top surface of the gate structure and having a plurality of first peripheral circuit wiring pattern recesses; an insulating layer filling the plurality of first peripheral circuit wiring pattern recesses and covering an upper portion of the first peripheral circuit wiring pattern; and a second peripheral circuit wiring pattern formed on the insulating layer.

[0008] According to another aspect of the present invention, an integrated circuit device includes a substrate including a cell region having a first active region and a peripheral circuit region having a second active region, a direct contact contacting the first active region in the cell region, a bit line structure disposed on the direct contact, a capacitor structure electrically connected to the first active region, a gate structure disposed on the second active region in the peripheral circuit region, a first peripheral circuit wiring pattern disposed adjacent to the gate structure and electrically connected to the second active region, a second peripheral circuit wiring pattern disposed on the first peripheral circuit wiring pattern, a wiring insulating layer between the first peripheral circuit wiring pattern and the second peripheral circuit wiring pattern, and a contact plug penetrating the wiring insulating layer and connected to at least one of the first peripheral circuit wiring pattern and the second peripheral circuit wiring pattern, wherein the wiring insulating layer extends to the cell region, and the capacitor structure includes a dummy electrode in contact with an upper surface of the wiring insulating layer. Effect of the Invention

[0009] According to the present invention, by including a BLP circuit formed in a two-layer structure, it is possible to provide an integrated circuit device with maximized process margins and improved reliability. [Brief description of the drawings]

[0010] [Figure 1] 1 is a block diagram illustrating an exemplary configuration of an integrated circuit device according to an embodiment of the present invention; [Diagram 2] 1 is a plan view illustrating an exemplary layout configuration of integrated circuit elements according to an embodiment of the technical concept of the present invention; [Diagram 3] 2 is a schematic planar layout for explaining a main configuration of a cell array region of an integrated circuit device according to an embodiment of the present invention; [Figure 4A] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 4B] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 4C] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 4D] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 4E] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 4F] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 4G] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 4H] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 4I] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 4J] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 4K] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 4L] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 5A] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 5B] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 5C] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 5D] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 5E] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 5F] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 5G] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 5H] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 5I] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 5J] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 5K] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 6A] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 6B]1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 6C] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 6D] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 6E] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 6F] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 6G] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 6H] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 7A] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 7B] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 7C] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 7D] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 7E] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 7F] 1A to 1C are cross-sectional views illustrating an example method for manufacturing an integrated circuit device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used to designate the same components in the drawings, and redundant description thereof will be omitted.

[0012] The present embodiment can be modified in various ways and has various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description of the invention. However, this is not intended to limit the technical scope to a specific embodiment, and should be understood to include all modifications, equivalents, or alternatives within the disclosed ideas and technical scope. In describing the embodiments, if a specific description of related publicly known technology is deemed to make the gist unclear, the detailed description will be omitted.

[0013] FIG. 1 is a block diagram illustrating an exemplary configuration of an integrated circuit device 100 according to an embodiment of the inventive concept.

[0014] 1, the integrated circuit device 100 includes a first region 22 and a second region 24. The first region 22 is a memory cell region of the DRAM device, and the second region 24 is a peripheral circuit region of the DRAM device. The first region 22 includes a memory cell array 22A. The second region 24 includes a row decoder 52, a sense amplifier 54, a column decoder 56, a self-refresh control circuit 58, a command decoder 60, an MRS / EMRS (Mode Register Set / Extended Mode Register Set) circuit 62, an address buffer 64, and a data input / output circuit 66.

[0015] FIG. 2 is a plan view for explaining an exemplary layout configuration of the integrated circuit element 100 illustrated in FIG.

[0016] 2, the integrated circuit element 100 includes a plurality of first regions 22. Each of the first regions 22 is surrounded by a second region 24.

[0017] Each of the first regions 22 is a cell array region MCA of a DRAM device, and the second region 24 is a region in which peripheral circuits of the DRAM device are formed and a core region (hereinafter referred to as a "peripheral circuit region"). In the first regions 22, the cell array region MCA includes the memory cell array 22A described with reference to FIG.

[0018] The second region 24 includes a sub-word line driver block SWD, a sense amplifier block S / A, and a conjunction block CJT. A plurality of bit line sense amplifiers are arranged in the sense amplifier block S / A. The conjunction block CJT is arranged at a point where the sub-word line driver block SWD and the sense amplifier block S / A intersect. A power driver and a ground driver for driving the bit line sense amplifiers are arranged in the conjunction block CJT. Peripheral circuits such as an inverter chain and an input / output circuit are further formed in the second region 24.

[0019] FIG. 3 is a schematic planar layout for explaining a main configuration of the cell array area MCA illustrated in FIG.

[0020] Referring to FIG. 3, the cell array region MCA includes a plurality of cell active regions A1. The plurality of cell active regions A1 are arranged to have their major axes in a diagonal direction with respect to a first horizontal direction (X direction) and a second horizontal direction (Y direction). A plurality of word lines WL extend parallel to each other along the first horizontal direction (X direction) across the plurality of cell active regions A1. A plurality of bit lines BL extend parallel to each other along the second horizontal direction (Y direction) on the plurality of word lines WL. The plurality of bit lines BL are connected to the plurality of cell active regions A1 through direct contacts DC. A plurality of buried contacts BC are formed between two adjacent bit lines BL among the plurality of bit lines BL. The plurality of buried contacts BC are arranged in a line along the first horizontal direction (X direction) and the second horizontal direction (Y direction). A plurality of conductive landing pads LP are formed on the plurality of buried contacts BC. The buried contacts BC and the conductive landing pads LP serve to connect a lower electrode (not shown) of a capacitor (capacitor structure) formed on the bit lines BL to the cell active region A1. The conductive landing pads LP are arranged to partially overlap the buried contacts BC.

[0021] 3 is formed through a series of steps including a plurality of exposure steps. In an exemplary embodiment, the series of steps for forming the plurality of conductive landing pads LP includes a photolithography step using extreme ultraviolet (EUV).

[0022] 4A to 4L, 5A to 5K, 6A to 6H, and 7A to 7F are cross-sectional views showing a process sequence to explain an exemplary manufacturing method of an integrated circuit device according to an embodiment of the technical idea of ​​the present invention. More specifically, in FIGS. 4A to 4L, 5A to 5K, 6A to 6H, and 7A to 7F, (a) is a cross-sectional view showing a process sequence of a part of the cell array region MCA along line A-A' in FIG. 3, and (b) is a cross-sectional view showing a process sequence of a part of the peripheral circuit region CORE / PERI. In FIGS. 5A to 5K, 6A to 6H, and 7A to 7F, for convenience of illustration, the illustration of a part of the configuration exemplified in FIG. 4L is omitted.

[0023] First, with reference to FIGS. 4A to 4L, an illustrative method for manufacturing an integrated circuit device according to the technical concept of the present invention will be described in order with specific examples.

[0024] Referring to FIG. 4A, a plurality of isolation trenches T1 and a plurality of isolation films 212 are formed in a substrate 210 having a cell array region MCA and a peripheral circuit region CORE / PERI, thereby defining a plurality of cell active regions A1 in the cell array region MCA of the substrate 210 and a peripheral active region A2 in the peripheral circuit region CORE / PERI.

[0025] After forming a plurality of word line trenches (not shown) extending parallel to each other in the substrate 210 in the cell array region MCA, a plurality of gate dielectric layers, a plurality of word lines, and a plurality of buried insulating layers are sequentially formed in the plurality of word line trenches. The plurality of word lines constitute the plurality of word lines WL illustrated in FIG. 3. Impurity ions are implanted into both sides of the plurality of word lines WL in the plurality of cell active regions A1 to form a plurality of source / drain regions on the plurality of cell active regions A1. In an exemplary embodiment, the plurality of source / drain regions are formed before forming the plurality of word lines WL.

[0026] Thereafter, a buffer film 222 is formed on the main surface 210M of the substrate 210 in the cell array region MCA, and a gate dielectric film 224 is formed on the main surface 210M of the substrate 210 in the peripheral circuit region CORE / PERI. The buffer film 222 includes a first insulating film 222A and a second insulating film 222B. The first insulating film 222A and the second insulating film 222B are each made of an oxide film, a nitride film, or a combination thereof.

[0027] 4B, a lower conductive layer 230 is formed on the buffer layer 222 in the cell array region MCA and the gate dielectric layer 224 in the peripheral circuit region CORE / PERI. The lower conductive layer 230 is made of doped polysilicon.

[0028] 4C, a mask pattern M21 is formed on the lower conductive layer 230 in the cell array region MCA and the peripheral circuit regions CORE / PERI, and then the lower conductive layer 230 exposed through the openings M210 of the mask pattern M21 in the cell array region MCA is etched, and as a result, a portion of the exposed substrate 210 and a portion of the isolation layer 212 are etched to form a direct contact hole DCH exposing the cell active region A1 of the substrate 210. The mask pattern M21 is made of an oxide film, a nitride film, or a combination thereof.

[0029] 4D, the mask pattern M21 is removed from the result of FIG. 4C, and direct contacts DC are formed in the direct contact holes DCH in the cell array region MCA. In an exemplary process for forming the direct contacts DC, a conductive layer is formed in the direct contact holes DCH and on the lower conductive layer 230 to a thickness sufficient to fill the direct contact holes DCH, and the conductive layer is etched back so that the conductive layer remains only in the direct contact holes DCH. The conductive layer is made of doped polysilicon, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof.

[0030] Referring to FIG. 4E, in the cell array region MCA and the peripheral circuit regions CORE / PERI, an intermediate conductive layer 232, an upper conductive layer 234, and a lower insulating capping layer 236 are sequentially formed on the lower conductive layer 230 and the direct contacts DC.

[0031] The middle conductive layer 232 and the top conductive layer 234 are each comprised of TiN, TiSiN, W, tungsten silicide, or a combination thereof. The bottom insulating capping layer 236 is comprised of silicon nitride. In an exemplary embodiment, the middle conductive layer 232 is comprised of TiN, TiSiN, or a combination thereof, and the top conductive layer 234 is comprised of W. The bottom insulating capping layer 236 is comprised of silicon nitride.

[0032] 4F, in the result of FIG. 4E, while the cell array region MCA is covered with a mask pattern (not shown), the gate dielectric layer 224, the lower conductive layer 230, the intermediate conductive layer 232, the upper conductive layer 234, and the lower insulating capping layer 236 in the peripheral circuit region CORE / PERI are patterned to form a gate electrode 240 consisting of a lower conductive pattern 230A, an intermediate conductive pattern 232A, and an upper conductive pattern 234A on the gate dielectric layer 224, and a gate capping pattern 236A covering the gate electrode 240. Then, insulating spacers 242 are formed on both side walls of the gate structure PG consisting of a stacked structure of the gate dielectric layer 224, the gate electrode 240, and the gate capping pattern 236A, and an ion implantation process is performed to form source / drain regions in the peripheral active region A2 on both sides of the gate structure PG. In an exemplary embodiment, the insulating spacers 242 are made of an oxide film, a nitride film, or a combination thereof.

[0033] Thereafter, the mask pattern covering the cell array region MCA is removed to expose the lower insulating capping layer 236 of the cell array region MCA, and an insulating thin film 244 is formed to cover the entire surface of the exposed resultant structure of the cell array region MCA and the peripheral circuit regions CORE / PERI. Thereafter, an interlayer insulating film 246 is formed in the peripheral circuit regions CORE / PERI to fill the space around the gate structure PG. The insulating thin film 244 is made of a silicon nitride film. The interlayer insulating film 246 is made of, but is not limited to, TOSZ (Tonen Silazene).

[0034] 4G, an upper insulating capping layer 250 is formed on the insulating thin film 244 in the cell array region MCA and the interlayer insulating film 246 in the peripheral circuit region CORE / PERI. The upper insulating capping layer 250 is made of a silicon nitride film.

[0035] Referring to FIG. 4H, while the upper insulating capping layer 250 in the peripheral circuit region CORE / PERI is covered with a mask pattern M22, the upper insulating capping layer 250, the insulating thin film 244, and the lower insulating capping layer 236 in the cell array region MCA are patterned using a photolithography process to form a lower insulating capping pattern 236B, an insulating thin film pattern 244A, and an upper insulating capping pattern 250A stacked in sequence on the upper conductive layer 234.

[0036] Referring to FIG. 4I, with the upper insulating capping layer 250 in the peripheral circuit region CORE / PERI covered with the mask pattern M22, the upper conductive layer 234, the intermediate conductive layer 232, and the lower conductive layer 230 are etched using the lower insulating capping pattern 236B, the insulating thin film pattern 244A, and the upper insulating capping pattern 250A in the cell array region MCA as etching masks to form a plurality of bit lines BL consisting of the lower conductive pattern 230B, the intermediate conductive pattern 232B, and the upper conductive pattern 234B.

[0037] Thereafter, a plurality of insulating spacers 252 are formed to cover both side walls of the insulating capping structure including the lower insulating capping pattern 236B, the insulating thin film pattern 244A, and the upper insulating capping pattern 250A, and both side walls of the bit lines BL. The insulating spacers 252 are formed to fill the direct contact holes DCH around the direct contacts DC. After the insulating spacers 252 are formed, line spaces LS remain between the bit lines BL. The height of the upper insulating capping pattern 250A is reduced by an etching process performed during the formation of the bit lines BL and the insulating spacers 252.

[0038] 4J, with the upper insulating capping layer 250 in the peripheral circuit region CORE / PERI covered with a mask pattern M22, a plurality of insulating fences (not shown) are formed between the plurality of bit lines BL in the cell array region MCA. As a result, one line space LS is separated into a plurality of columnar contact spaces CS1. The horizontal width of the plurality of contact spaces CS1 is limited by the respective plurality of insulating spacers 252 and the plurality of insulating fences. During the formation of the plurality of insulating fences, the upper insulating capping pattern 250A and the insulating spacers 252 are exposed to an etching atmosphere, so that the upper insulating capping pattern 250A and the insulating spacers 252 are consumed and their heights are further reduced.

[0039] Thereafter, a portion of the structure exposed through the contact spaces CS1 is removed to form recess spaces RS exposing the cell active regions A1 of the substrate 210 between the bit lines BL.

[0040] 4K, in a state where the upper insulating capping layer 250 in the peripheral circuit region CORE / PERI is covered with a mask pattern M22, similar to the result of FIG 4J, a plurality of lower contact plugs 256 are formed to fill a portion of the contact space CS1 between each of the plurality of bit lines BL while filling a plurality of recess spaces RS between each of the plurality of bit lines BL in the cell array region MCA. The plurality of lower contact plugs 256 are made of doped polysilicon.

[0041] Then, the mask pattern M22 is removed from the peripheral circuit region CORE / PERI to expose the upper insulating capping layer 250, and then, with the mask pattern (not shown) covering the cell array region MCA, the upper insulating capping layer 250, the interlayer insulating film 246, and the insulating thin film 244 are etched in the peripheral circuit region CORE / PERI to form a plurality of contact spaces CS2 that expose the peripheral active region A2 of the substrate 210.

[0042] After removing a mask pattern (not shown) covering the cell array region MCA, a metal silicide film 258A is formed on the lower contact plug 256 exposed through the contact spaces CS1 in the cell array region MCA, and a metal silicide film 258B is formed on the surface of the peripheral active region A2 exposed through the contact spaces CS2 in the peripheral circuit region CORE / PERI. The metal silicide films 258A and 258B are formed simultaneously or in separate processes. The metal silicide films 258A and 258B are each made of, but not limited to, cobalt silicide, nickel silicide, or manganese silicide. In an exemplary embodiment, the process of forming the metal silicide films 258A and 258B may be omitted.

[0043] 4L, a plurality of first contact plugs 262 are formed to fill the contact spaces CS1 remaining on the metal silicide film 258A in the cell array region MCA of the resultant structure of FIG. 4K, and a plurality of second contact plugs 264 are formed to fill the contact spaces CS2 in the peripheral circuit region CORE / PERI of the resultant structure of FIG. 4K. In this specification, the plurality of first contact plugs 262 are also referred to as a plurality of contact plugs, and the plurality of second contact plugs 264 are also referred to as direct contact plugs. In an exemplary embodiment, the process of forming the plurality of first contact plugs 262 and the process of forming the plurality of second contact plugs 264 are performed simultaneously.

[0044] In the cell array region MCA, the bit lines BL, the lower insulating capping pattern 236B, the insulating thin film pattern 244A, the upper insulating capping pattern 250A, and a pair of insulating spacers 252 covering their respective sidewalls constitute a bit line structure. In the cell array region MCA, a plurality of first contact plugs 262 are respectively disposed between the plurality of bit line structures on the substrate 210. In the peripheral circuit region CORE / PERI, a plurality of second contact plugs 264 are respectively configured to be electrically connected to source / drain regions formed in the substrate 210.

[0045] The first contact plugs 262 and the second contact plugs 264 are each made of a metal, a conductive metal nitride, or a combination thereof. In an exemplary embodiment, the first contact plugs 262 and the second contact plugs 264 are each made of TiN, W, or a combination thereof. In one example, the first contact plugs 262 and the second contact plugs 264 are each made of only a TiN film. In another example, the first contact plugs 262 and the second contact plugs 264 are each made of a stacked structure of a TiN barrier film and a W film.

[0046] In the cell array region MCA, the upper surfaces of the first contact plugs 262, the upper insulating capping patterns 250A, and the insulating spacers 252 are planarized to extend on the same plane. In the peripheral circuit region CORE / PERI, the upper surfaces of the second contact plugs 264 and the upper insulating capping layer 250 are planarized to extend on the same plane. In an exemplary embodiment, after the first contact plugs 262 and the second contact plugs 264 are formed, the uppermost surfaces of the upper insulating capping patterns 250A and the insulating spacers 252 of the first contact plugs 262, the second contact plugs 264, and the bit line structures are located at the same vertical level. The term "vertical level" as used herein refers to the distance along the vertical direction from the main surface 210M of the substrate 210.

[0047] Next, with reference to FIGS. 5A to 5K, illustrative methods for manufacturing an integrated circuit device according to the technical concept of the present invention will be described in order with specific examples.

[0048] 5A, a first conductive layer 266 is formed in the cell array region MCA and the peripheral circuit regions CORE / PERI in the resultant structure of FIG. 4L. The first conductive layer 266 is formed to cover the first contact plugs 262 in the cell array region MCA and to cover the second contact plugs 264 in the peripheral circuit regions CORE / PERI.

[0049] The first conductive layer 266 is made of a metal, a conductive metal nitride, or a combination thereof. In an exemplary embodiment, the first conductive layer 266 is made of TiN, W, or a combination thereof. In one example, the first conductive layer 266 is made of only a TiN film. In another example, the first conductive layer 266 is made of a stacked structure of a TiN barrier film and a W film.

[0050] 5B, a first mask layer ML1, a second mask layer ML2, a third mask layer ML3, and a fourth mask layer ML4 are formed in the cell array region MCA and the peripheral circuit region CORE / PERI, successively covering the first conductive layer 266, and a photoresist pattern MP11 covering the fourth mask layer ML4 is formed. Although a total of four mask layers ML1, ML2, ML3, and ML4 are used in FIG. 5B, the number of mask layers is not limited thereto.

[0051] In an exemplary embodiment, the first mask layer ML1 is made of an amorphous carbon layer (ACL), the second mask layer ML2 is made of a polysilicon film, the third mask layer ML3 is made of an SOH film, and the fourth mask layer ML4 is made of a SiON film, but is not limited thereto. The photoresist pattern MP11 is obtained from an EUV (extreme ultraviolet) resist film, a KrF excimer laser resist film, an ArF excimer laser resist film, or an F2 excimer laser resist film.

[0052] In an exemplary embodiment, the photoresist pattern MP11 is obtained from an EUV resist film. For example, in a state where the EUV resist film is exposed in the cell array region MCA and the peripheral circuit regions CORE / PERI, the EUV resist film is exposed to an EUV light source only in the cell array region MCA among the cell array region MCA and the peripheral circuit regions CORE / PERI, and the exposed EUV resist film is developed to form the photoresist pattern MP11.

[0053] Referring to FIG. 5C, the fourth mask layer ML4 and the third mask layer ML3 are sequentially etched using the photoresist pattern MP11 as an etching mask in the resultant structure of FIG. 5B.

[0054] 5D, an oxide film 267 is formed to fill the gaps between the third mask layer ML3, the fourth mask layer ML4, and the photoresist pattern MP11 that remain unetched in the cell array region MCA, and an etch-back process is performed, so that the height of the top surface of the oxide film 267 and the height of the top surface of the photoresist pattern MP11 are at the same vertical level.

[0055] Referring to FIG. 5E, the third mask layer ML3, the fourth mask layer ML4, and the photoresist pattern MP11 remaining in the cell array region MCA of FIG. 5D are removed through a strip process, and then the first mask layer ML1 and the second mask layer ML2 are also etched to obtain the result of FIG. 5F.

[0056] 5G, the first conductive layer 266 exposed in the cell array region MCA in the result of FIG. 5F is removed to expose the upper surfaces of the first contact plugs 262 and the upper insulating capping patterns 250A. Then, a portion of each of the first contact plugs 262 is removed to form a first recessed contact plug 262R from the first contact plugs 262. As a result, a recess space URS is formed on the first recessed contact plug 262R between each of the upper insulating capping patterns 250A included in the bit line structures. After forming the first recessed contact plugs 262R, the vertical level of the top surface of each of the first recessed contact plugs 262R is located farther from the substrate 210 than the vertical level of the top surface of each of the bit lines BL. In this specification, each of the first recessed contact plugs 262R is also referred to as a recessed contact plug.

[0057] After the first recess contact plugs 262R and the first recess spaces URS are formed in the cell array region MCA, the first mask layer ML1 in the peripheral circuit region CORE / PERI is removed to expose the top surface of the first conductive layer 266.

[0058] Referring to FIG. 5H, an insulating film 270 is formed to cover the result of FIG. 5G in the cell array region MCA and the peripheral circuit region CORE / PERI, and a fifth mask layer ML5 and a sixth mask layer ML6 made of different materials are formed on the insulating film 270, and a photoresist pattern MP12 is formed on the sixth mask layer ML6.

[0059] In an exemplary embodiment, the insulating film 270 is made of, but is not limited to, a silicon nitride film. The fifth mask layer ML5 is made of, but is not limited to, an ACL film. The sixth mask layer ML6 is made of, but is not limited to, a SiON film.

[0060] The photoresist pattern MP12 is obtained from an EUV resist film, a KrF excimer laser resist film, an ArF excimer laser resist film, or an F2 excimer laser resist film. In an exemplary embodiment, the photoresist pattern MP12 is obtained from an EUV resist film. The photoresist pattern MP12 is formed through a process similar to that described for the formation of the photoresist pattern MP22 with reference to FIG. 5B. However, in a state where the EUV resist film is exposed in the cell array region MCA and the peripheral circuit region CORE / PERI, the EUV resist film is exposed to an EUV light source only in the cell array region MCA among the cell array region MCA and the peripheral circuit region CORE / PERI, and the exposed EUV resist film is developed to form the photoresist pattern MP12.

[0061] 5I, the sixth mask layer ML6 and the fifth mask layer ML5 are sequentially etched using the photoresist pattern MP12 as an etching mask in the resultant structure of FIG. 5H, and the insulating film 270 is patterned using the resultant structure as an etching mask to form an intaglio insulating pattern 270P. Then, unnecessary film on the intaglio insulating pattern 270P is removed to expose the top surface of the intaglio insulating pattern 270P.

[0062] The recessed insulating pattern 270P is disposed on the plurality of bit line structures and the plurality of first recessed contact plugs 262R in the cell array region MCA, and is formed to have a plurality of openings 270H disposed at positions shifted horizontally from the plurality of first recessed contact plugs 262R.

[0063] Referring to Fig. 5J, a second conductive layer 272 is formed on the resultant structure of Fig. 5I. The second conductive layer 272 is formed to fill the recess spaces URS (see Fig. 5G) and the cutoff spaces COS (see Fig. 5I) in the cell array region MCA and to contact upper surfaces of the first recess contact plugs 262R, respectively.

[0064] The second conductive layer 272 is made of a metal, a conductive metal nitride, or a combination thereof. In an exemplary embodiment, the second conductive layer 272 is made of TiN, W, or a combination thereof. In one example, the second conductive layer 272 is made of only a TiN film. In another example, the second conductive layer 272 is made of a stacked structure of a TiN barrier film and a W film.

[0065] 5K, in the result of FIG. 5J, the second conductive layer 272 is etched back to form a plurality of conductive landing pads LP in the cell array region MCA and to expose the top surface of the intaglio insulating pattern 270P in the peripheral circuit region CORE / PERI.

[0066] In the cell array region MCA, the conductive landing pads LP fill the recess spaces URS (see FIG. 5G) and the cutoff spaces COS (see FIG. 5I) and contact the upper surfaces of the first recessed contact plugs 262R. The upper surfaces of the conductive landing pads LP are closer to the substrate 210 than the upper surface of the recessed insulating pattern 270P. Thus, after the conductive landing pads LP are formed, a portion of the recessed insulating pattern 270P protrudes from the upper portions of the conductive landing pads LP.

[0067] Next, an exemplary method for manufacturing an integrated circuit device according to the technical concept of the present invention will be described in detail with reference to Figures 6A to 6H. The process of Figures 6A to 6H includes a process for forming a first peripheral circuit wiring pattern BLP1.

[0068] Referring to FIG. 6A, the recessed insulating pattern 270P in the cell array region MCA and the peripheral circuit regions CORE / PERI is partially removed, so that in the cell array region MCA, the top surface of the recessed insulating pattern 270P and the top surfaces of each of the multiple conductive landing pads LP are at the same vertical level, and in the peripheral circuit regions CORE / PERI, the top surface of the first conductive layer 266 is exposed.

[0069] 6B, a seventh mask layer ML7 and an eighth mask layer ML8 sequentially covering the first conductive layer 266 are formed in the cell array region MCA and the peripheral circuit region CORE / PERI, and a photoresist pattern MP13 covering the eighth mask layer ML8 is formed.

[0070] In an exemplary embodiment, the seventh mask layer ML7 is made of ACL and the eighth mask layer ML8 is made of SiON film, but is not limited thereto. The photoresist pattern MP13 is obtained from an EUV (extreme ultraviolet) resist film, a KrF excimer laser resist film, an ArF excimer laser resist film, or an F2 excimer laser resist film.

[0071] In an exemplary embodiment, the photoresist pattern MP13 is obtained from an EUV resist film. For example, in a state where the EUV resist film is exposed in the cell array region MCA and the peripheral circuit region CORE / PERI, the EUV resist film is exposed only in the peripheral circuit region CORE / PERI among the cell array region MCA and the peripheral circuit region CORE / PERI to an EUV light source, and the exposed EUV resist film is developed to form the photoresist pattern MP13.

[0072] Referring to FIG. 6C, the seventh mask layer ML7 and the eighth mask layer ML8 are sequentially etched using the photoresist pattern MP13 in the resultant structure of FIG. 6B as an etching mask, and then, referring to FIG. 6D, the first conductive layer 266 is patterned using the resulting structure as an etching mask to form a first peripheral circuit wiring pattern BLP1.

[0073] Some of the first peripheral circuit wiring patterns BLP1 are connected to the second contact plugs 264. After the first peripheral circuit wiring patterns BLP1 are formed, unnecessary films are removed to expose the upper surfaces of the landing pads LP and the recessed insulating pattern 270P in the cell array region MCA and the first peripheral circuit wiring patterns BLP1 in the peripheral circuit regions CORE / PERI.

[0074] Referring to Figures 6E and 6F, an insulating structure 271 is formed in the peripheral circuit region CORE / PERI to fill the spaces between each of the first peripheral circuit wiring patterns BLP1 and cover the upper surfaces of the multiple landing pads LP and the recessed insulating pattern 270P in the cell array region MCA, and a ninth mask layer ML9, a tenth mask layer ML10 and a photoresist pattern MP14 are sequentially formed to cover the first peripheral circuit wiring pattern BLP1 and the insulating structure 271.

[0075] In an exemplary embodiment, the ninth mask layer ML9 is made of SOH, and the tenth mask layer ML10 is made of SiON film, but is not limited thereto. The photoresist pattern MP14 is obtained from a KrF excimer laser resist film, an ArF excimer laser resist film, or an F2 excimer laser resist film.

[0076] Referring to FIG. 6G, at least a portion of the insulating structure 271 formed in the peripheral circuit region CORE / PERI is patterned using a photolithography process until the top surfaces of the plurality of second contact plugs 264 are exposed.

[0077] 6H, a third conductive layer 282 is formed on the resultant structure of FIG. 6G. The third conductive layer 282 is formed to fill a space (see FIG. 6G) in the peripheral circuit region CORE / PERI where a portion of the insulating structure 271 is etched to expose the top surface of the second contact plug 264, and to contact the exposed top surface of the second contact plug 264.

[0078] The third conductive layer 282 is made of a metal, a conductive metal nitride, or a combination thereof. In an exemplary embodiment, the third conductive layer 282 is made of TiN, W, or a combination thereof. In one example, the third conductive layer 282 is made of only a TiN film. In another example, the third conductive layer 282 is made of a stacked structure of a TiN barrier film and a W film.

[0079] Next, an exemplary method for manufacturing an integrated circuit device according to the technical concept of the present invention will be described in detail with reference to Figures 7A to 7F. The process of Figures 7A to 7F includes a process for forming a second peripheral circuit wiring pattern BLP2.

[0080] 7A, an eleventh mask layer ML11, a twelfth mask layer ML12, and a photoresist pattern MP15 are formed in the cell array region MCA and the peripheral circuit region CORE / PERI to sequentially cover the third conductive layer 282.

[0081] In an exemplary embodiment, the eleventh mask layer ML11 is made of ACL and the twelfth mask layer ML12 is made of SiON film, but is not limited thereto. The photoresist pattern MP15 is obtained from an EUV (extreme ultraviolet) resist film, a KrF excimer laser resist film, an ArF excimer laser resist film, or an F2 excimer laser resist film.

[0082] In an exemplary embodiment, the photoresist pattern MP15 is obtained from an EUV resist film. For example, in a state where the EUV resist film is exposed in the cell array region MCA and the peripheral circuit region CORE / PERI, the EUV resist film is exposed to an EUV light source only in the peripheral circuit region CORE / PERI among the cell array region MCA and the peripheral circuit region CORE / PERI, and the exposed EUV resist film is developed to form the photoresist pattern MP15.

[0083] Referring to FIG. 7B, in the result of FIG. 7A, the 11th mask layer ML11 and the 12th mask layer ML12 are sequentially etched using the photoresist pattern MP15 as an etching mask, and then, referring to FIG. 7C, the resulting result is used as an etching mask to pattern the third conductive layer 282 to form a second peripheral circuit wiring pattern BLP2.

[0084] Some of the second peripheral circuit wiring patterns BLP2 are connected to a plurality of second contact plugs 264. After the second peripheral circuit wiring patterns BLP2 are formed, unnecessary layers are removed to expose the top surfaces of the third conductive layer 282 in the cell array region MCA and the second peripheral circuit wiring patterns BLP2 in the peripheral circuit regions CORE / PERI.

[0085] 7D, an insulating structure 273 is formed to fill spaces between the second peripheral circuit wiring patterns BLP2 in the peripheral circuit region CORE / PERI, such that the upper surface of the insulating structure 273 is coplanar with the upper surface of the second peripheral circuit wiring patterns BLP2.

[0086] 7E and 7F, in the peripheral circuit region CORE / PERI, a photoresist pattern MP16 is formed on the second peripheral circuit wiring pattern BLP2 and the upper surface of the insulating structure 273 (see FIG. 7E), and the third conductive layer 282 in the cell array region MCA is etched using the photoresist pattern MP16 as an etching mask. Through the above process, the peripheral circuit wiring patterns BLP1 and BLP2 formed in a two-layer structure are formed.

[0087] In this case, the second peripheral circuit wiring pattern BLP2 is formed to the same thickness as the first peripheral circuit wiring pattern BLP1, and the vertical level of the top surface of the first peripheral circuit wiring pattern BLP1 is lower than the vertical level of the bottom surface of the second peripheral circuit wiring pattern BLP2. The second peripheral circuit wiring pattern BLP2 contains the same material as the constituent material of the first peripheral circuit wiring pattern BLP1.

[0088] In this specification, a case has been described in which the landing pad LP is formed on the cell array region MCA and then the first peripheral circuit wiring pattern BLP1 is formed on the peripheral circuit region CORE / PERI, but the technical idea of ​​the present invention is not limited thereto. First, the first peripheral circuit wiring pattern BLP1 may be formed on the peripheral circuit region CORE / PERI, and then the landing pad LP may be formed in the cell array region MCA.

[0089] As described above, the drawings and the specification disclose exemplary embodiments. Although specific terms are used in the present specification to describe the embodiments, these terms are used only for the purpose of describing the technical idea of ​​the present invention, and are not used to limit the meaning or the scope of the present invention. Therefore, a person having ordinary knowledge in the art will understand that various modifications and equivalent other embodiments are possible. [Explanation of symbols]

[0090] 210 Substrate 212 Element isolation film 222 Buffer film 224 Gate dielectric film 230 Lower conductive layer 230A, 230B Lower conductive pattern 232A, 232B Intermediate conductive pattern 234 Upper conductive layer 234A, 234B Upper conductive pattern 236 Lower insulating capping layer 236A Gate Capping Pattern 236B Lower insulation capping pattern 240 Gate electrode 242, 252 Insulating spacer 244 Insulating Thin Film 246 Interlayer insulating film 250 Top insulating capping layer 250A Upper insulation capping pattern 256 Bottom Contact Plug 258A, 258B Metal silicide film 262 First contact plug 262R 1st recess contact plug 264 Second Contact Plug 266 First conductive layer 267 Oxide Film 270 Insulating Film 270P engraved insulation pattern 271, 273 Insulating structures 272 Second conductive layer 282 Third conductive layer MCA cell array region CORE / PERI Peripheral circuit area MP16 Photoresist pattern BLP1 First peripheral circuit wiring pattern BLP2 Second peripheral circuit wiring pattern LP Landing Pad

Claims

1. a substrate including a cell region and a core region; a plurality of bit line structures spaced apart from one another on the cell region, the bit line structures including a bit line conductive layer and a bit line capping layer on the bit line conductive layer; a plurality of landing pads disposed on the plurality of bit line structures and electrically coupled to the substrate; The core region is a gate structure and a core capping film disposed on the gate structure; a direct contact plug extending perpendicular to the substrate; a first peripheral circuit wiring pattern extending on a first plane at a first level on the substrate and spaced apart from one another; and second peripheral circuit wiring patterns extending spaced apart from one another on a second plane at a second level on the substrate, the second level being different from the first level.

2. 2. The integrated circuit device of claim 1, wherein the first plane and the second plane are each parallel to the substrate.

3. 2. The integrated circuit device of claim 1, wherein the height of said second level is greater than the height of said first level.

4. 2. The integrated circuit device of claim 1, further comprising an insulating structure separating the first peripheral circuit wiring pattern and the second peripheral circuit wiring pattern.

5. the second peripheral circuit wiring pattern includes the same material as the first peripheral circuit wiring pattern; 5. The integrated circuit device of claim 4, wherein the insulating structure disposed on the plurality of landing pads and separating the first peripheral circuit wiring pattern and the second peripheral circuit wiring pattern comprises silicon nitride.

6. At least a portion of the first peripheral circuit wiring pattern is 2. The integrated circuit element according to claim 1, wherein the element is electrically connected to the direct contact plug.

7. a substrate including a cell region and a core region; a plurality of bit line structures extending parallel to each other in a first horizontal direction in the cell region; a plurality of buried contacts electrically connected to the cell region and filling a portion of spaces between the plurality of bit line structures; a plurality of landing pads disposed on the plurality of buried contacts in spaces between the plurality of bit line structures; a gate structure and a direct contact plug disposed in the core region; a first peripheral circuit wiring pattern disposed at a level higher than a top surface of the gate structure and having a plurality of first peripheral circuit wiring pattern recesses; an insulating layer filling the first peripheral circuit wiring pattern recesses and covering an upper portion of the first peripheral circuit wiring pattern; a second peripheral circuit wiring pattern formed on said insulating layer.

8. 8. The integrated circuit device of claim 7, further comprising a plurality of capacitor structures including a plurality of lower electrodes electrically connected to the plurality of landing pads, an upper electrode, and a capacitor dielectric layer interposed between the plurality of lower electrodes and the upper electrode.

9. a substrate including a cell region having a first active region and a peripheral circuit region having a second active region; a direct contact in contact with the first active region in the cell region; a bit line structure disposed on the direct contact; a capacitor structure electrically connected to the first active region; a gate structure disposed on the second active region in the peripheral circuit region; a first peripheral circuit wiring pattern disposed adjacent to the gate structure and electrically connected to the second active region; a second peripheral circuit wiring pattern disposed on the first peripheral circuit wiring pattern; a wiring insulating layer between the first peripheral circuit wiring pattern and the second peripheral circuit wiring pattern; a contact plug penetrating the wiring insulating layer and connected to at least one of the first peripheral circuit wiring pattern and the second peripheral circuit wiring pattern, the wiring insulating layer extends to the cell region; The integrated circuit device according to claim 1, wherein the capacitor structure includes a dummy electrode in contact with an upper surface of the wiring insulating layer.

10. a vertical level of an uppermost surface of the first peripheral circuit wiring pattern is lower than a vertical level of a lowermost surface of the second peripheral circuit wiring pattern; 10. The integrated circuit device of claim 9, wherein the second peripheral circuit wiring pattern includes the same material as the first peripheral circuit wiring pattern.

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