Chip module using conductive pillars to couple passive component devices to conductive traces within a metallization structure to form passive components - Patents.com

Abstract

Mobile phones and other mobile devices communicate wirelessly by transmitting and receiving RF signals. Transmitters and receivers in wireless devices process RF signals within certain frequency ranges or bands. Signals at other frequencies may be blocked or filtered out by lumped element circuits or lumped element filters consisting of passive electrical components such as inductors, capacitors, and resistors. A passive component device or integrated passive device is an example of a lumped element filter fabricated with passive components on a die. In a mobile device, a passive component device and one or more integrated circuits or other chips used for signal processing are interconnected by being mounted (i.e., bonded) on a metallization structure or package substrate in a chip module or multi-chip module. The demand for miniaturization of handheld mobile devices drives the need to reduce the size of the chip modules in the mobile device.

Description

[Technical field]

[0001] Priority Application This application claims priority to U.S. patent application Ser. No. 17 / 166,430, filed Feb. 3, 2021, entitled “CHIP MODULES EMPLOYING CONDUCTIVE PILLARS TO COUPLE A PASSIVE COMPONENT DEVICE TO CONDUCTIVE TRACES IN A METALLIZATION STRUCTURE TO FORM A PASSIVE COMPONENT,” which is incorporated by reference in its entirety.

[0002] The field of the disclosure relates generally to chip modules, including multi-chip modules (MCMs), and more particularly to reducing the area of ​​passive component device radio frequency (RF) filters within chip modules. [Background technology]

[0003] A lumped element filter is an electrical circuit that blocks or allows the passage of radio frequency (RF) signals of a selected frequency range in an electronic device for RF electrical communication. A lumped element filter includes passive components such as inductors, capacitors, and / or resistors that may be formed between interconnect layers on a substrate in a passive component device or die. A passive component device, also known as an integrated passive device, is a flip-chip type device in which the passive components are formed with metal traces in one or more interconnect layers in a dielectric structure disposed on one side of a substrate in a back-end of line (BEOL) process. One example of a passive component device is a passive-on-glass (POG) device that includes a glass substrate to provide enhanced electrical isolation. A metal-insulator-metal (MIM) capacitor is one example of a passive component that may be formed in a passive component device by forming metal traces adjacent to each other in different interconnect layers of the passive component device. In another example, an inductor may be formed in a passive component device as a two-dimensional (2D) (e.g., horizontal) spiral or helix metal trace in one interconnect layer of a dielectric structure. As another example, a three-dimensional (3D) inductor may be formed in a passive component device by metal traces in multiple dielectric layers of a dielectric structure with vias disposed through the dielectric structure to electrically couple the metal traces together in a 3D coil. The passive component device may be packaged with external interconnects (e.g., solder bumps) and electrically coupled to a supporting metallization structure (e.g., a package substrate with a redistribution layer) to integrate the passive component device into a circuit.

[0004] Passive component devices are often used in chip modules, such as RF front-end chip modules used in telecommunications devices. In response to the demand for smaller and cheaper electronic devices, there is an incentive to reduce the size of chip modules, including chip modules that use POG devices, such as RF front-end chip modules. Summary of the Invention [Means for solving the problem]

[0005] Aspects disclosed herein include chip modules that use conductive pillars to couple passive component devices to conductive traces within a metallization structure to form passive components. An exemplary chip module includes multiple conductive pillars that couple conductive traces of a passive component device to conductive traces of a metallization structure to form a passive component that extends between the metallization structure and the passive component device. The conductive traces can be present in any interconnect layer within the passive component device and in any redistribution layer of the metallization structure. The passive components utilize the area of ​​the chip module between the passive component device and the metallization structure rather than consuming space within the passive component device. The area occupied by the passive components can be reduced due to the conductive pillars having a smaller center-to-center distance compared to solder bumps. The conductive pillars are also a lower resistance connection than solder bumps.

[0006] As an example of a passive component, a three-dimensional (3D) inductor including a core region between a metallization structure and a passive component device can be formed by using conductive pillars to couple the conductive traces of the passive component device to the metallization structure. As a result of using the conductive pillars, the cross-sectional height of the core region provides increased inductance. The smaller center-to-center distance between the conductive pillars increases the coil density and provides inductance in a smaller area. The low resistance of the conductive pillars provides a higher Q value in the 3D inductor. By integrating the passive components into an area including the passive component device, the metallization structure, and the area between the passive component device and the metallization structure, the area of ​​a chip module, such as a radio frequency (RF) front-end module, is reduced.

[0007] In this regard, in one exemplary embodiment, a chip module is disclosed. The chip module includes a metallization structure including a first conductive trace. The chip module also includes a passive component device. The passive component device includes a dielectric structure disposed adjacent to the substrate. The passive component device also includes a second conductive trace disposed within the dielectric structure. The chip module also includes a passive component including at least one conductive pillar coupled to the first conductive trace and the second conductive trace.

[0008] In another exemplary aspect, a multi-chip module (MCM) is disclosed. The MCM includes a passive component device. The passive component device includes a dielectric structure disposed on a substrate. The passive component device also includes a first conductive trace disposed within the dielectric structure. The MCM also includes a metallization structure including a second conductive trace. The MCM also includes a passive component including at least one conductive pillar coupled to the first conductive trace and the second conductive trace. The MCM also includes an integrated circuit (IC) die coupled to the metallization structure and the passive component.

[0009] In another exemplary aspect, a method is disclosed. The method includes forming a metallization structure including a first conductive trace. The method also includes forming a passive component device. The passive component device includes a dielectric structure disposed adjacent to the substrate. The passive component device also includes a second conductive trace disposed within the dielectric structure. The method also includes forming the passive component including at least one conductive pillar coupled to the first conductive trace and the second conductive trace. [Brief description of the drawings]

[0010] [Figure 1A] FIG. 2 is a cross-sectional side view of a passive component device bonded to a surface of a metallization structure by solder bumps. [Figure 1B] 1B is a top plan view of a two-dimensional (2D) spiral inductor formed in a first interconnect layer in the passive component device of FIG. 1A including an underpass connection to a second interconnect layer. [Diagram 2] FIG. 1 is a cross-sectional side view of an exemplary chip module including multiple conductive pillars that serially couple at least one conductive trace in an interconnect layer of a passive component device with at least one conductive trace of a redistribution layer of a metallization structure to form a high density three dimensional (3D) coil of an inductor having a core region between the metallization structure and the passive component device. [Diagram 3] FIG. 13 is a cross-sectional side view of another exemplary chip module including multiple conductive pillars coupled to a first interconnect layer coupled by vias to another interconnect layer within a metallization structure to increase the cross-sectional height of a core region of a 3D inductor. [Figure 4] 3 is a cross-sectional side view of an example multi-chip module (MCM) of the chip module of FIG. 2 having an IC die bonded to a metallization structure. [Diagram 5] 5 is a flow chart of a method for manufacturing the exemplary chip module shown in FIGS. 2-4. [Figure 6] 3 is a perspective view illustrating a coil turn of the 3D inductor of FIG. 2 formed by conductive pillars that serially couple conductive traces in an interconnect layer of a passive component device and conductive traces of a metallization structure. [Figure 7A] FIG. 1 is a plan view of multiple 3D inductors in an exemplary chip module from a bottom view showing only the conductive traces of a metallization structure coupled in series with conductive traces in a passive component device to form a passive component filter. [Figure 7B] FIG. 6B is a side perspective view of the example chip of FIG. 6A more clearly showing multiple conductive pillars that serially couple conductive traces in a metallization structure with conductive traces in a passive component device to form multiple 3D inductor coils. [Figure 8] FIG. 1 is a bottom plan view of an exemplary chip module including multiple 3D coils extending between a metallization structure and a passive component device, including a spiral 2D inductor formed in an interconnect layer. [Figure 9]FIG. 9 is a bottom plan view of an exemplary chip module in which a spiral 2D inductor is formed in the interconnect layer of a passive component device above the interconnect layer containing the conductive traces of the 3D coil inductor to reduce the area of ​​the chip module compared to the chip module of FIG. [Figure 10] FIG. 10 is a block diagram of an exemplary wireless communication device including a radio frequency (RF) module, such as the chip modules of FIGS. 2-4, 7A-7B, 8 and 9. [Figure 11] FIG. 11 is a block diagram of an exemplary processor-based system including a chip module including a conductive pillar that serially couples at least one conductive trace in an interconnect layer of a passive component device with at least one conductive trace of a redistribution layer of a metallization structure to form a high-density 3D coil of an inductor having a core region between the metallization structure and the passive component device, according to any of the embodiments shown in FIGS. 2-4, 7A-7B, 8, and 9, and disclosed herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Several exemplary aspects of the present disclosure will now be described with reference to the drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0012] Aspects disclosed herein include chip modules that use conductive pillars to couple passive component devices to conductive traces within a metallization structure to form passive components. An exemplary chip module includes multiple conductive pillars that couple conductive traces of a passive component device to conductive traces of a metallization structure to form a passive component that extends between the metallization structure and the passive component device. The conductive traces can be present in any interconnect layer within the passive component device and in any redistribution layer of the metallization structure. The passive components utilize the area of ​​the chip module between the passive component device and the metallization structure rather than consuming space within the passive component device. The area occupied by the passive components can be reduced due to the conductive pillars having a smaller center-to-center distance compared to solder bumps. The conductive pillars are also a lower resistance connection than solder bumps.

[0013] Mobile phones and other mobile devices communicate wirelessly by transmitting and receiving RF signals. Transmitters and receivers in wireless devices process RF signals within certain frequency ranges or bands. Signals at other frequencies may be blocked or filtered out by lumped element circuits or lumped element filters consisting of passive electrical components such as inductors, capacitors, and resistors. A passive component device or integrated passive device is an example of a lumped element filter fabricated with passive components on a die. In a mobile device, a passive component device and one or more integrated circuits (ICs) or other chips used for signal processing are interconnected by being mounted on (i.e., physically and electrically coupled to) a metallization structure or package substrate in a chip module or multi-chip module (MCM). The demand for miniaturization of handheld mobile devices drives the need to reduce the size of the chip modules in the mobile device. The size of the chip module may be reduced by reducing the size of the components therein and / or by more efficiently integrating the internal components within the space of the chip module.

[0014] 1A is a cross-sectional side view of a passive component device 100 coupled to a metallization structure 102 by solder bumps 104. The passive component device 100 includes a dielectric structure 106 formed on one side of a substrate 108 of insulating material. The passive component device 100 includes a passive component, such as a metal-insulator-metal (MIM) capacitor 110, formed within the dielectric structure 106. The passive component device 100 may also be referred to as a passive-on-glass (POG) device 112 if the substrate 108 is formed of glass. The passive component device 100 is mounted on the metallization structure 102 in a flip-chip fashion.

[0015] The dielectric structure 106 includes multiple interconnect layers 114 separated from one another by a dielectric material 116. Multiple conductive (e.g., metal) traces 118 are formed in each interconnect layer 114, and the conductive traces 118 of different interconnect layers 114 may be connected by vertical interconnect accesses (vias) 120. The MIM capacitor 110 is formed with a dielectric layer 122 disposed between the conductive traces 118 in a first interconnect layer (M1) and a second interconnect layer (M2). The passive component device 100 is electrically coupled and physically mounted to the metallization structure 102 by solder bumps 104. Portions of the dielectric material 116 are removed to expose contacts 124 in a top interconnect layer 114 (e.g., M4) of the dielectric structure 106, and the solder bumps 104 are formed on the contacts 124. The solder bumps 104 may be electrically coupled to conductive traces 126 in the metallization structure 102 to provide an electrical connection between the passive component device 100 and other circuitry (not shown) coupled to the metallization structure 102, such as an IC that includes an amplifier or other circuitry for signal processing.

[0016] The passive component device 100 also includes an inductor 128, shown in top plan view in FIG. 1B. The inductor 128 is formed as a two-dimensional (2D) spiral or helix shape in a conductive trace 130 in one of the interconnect layers 114. A first end 132 of the spiral or helix shaped conductive trace 130 is coupled to a first contact 134. A second contact 136 inside the spiral shaped conductive trace 130 is coupled to an underpass 138 that leads to a second contact 140, where the "underpass" 138 is connected by a via (not shown). Thus, the inductor 128 is formed mostly in a single interconnect layer 114, but also requires a conductive trace (e.g., the underpass 138) in another interconnect layer 114. The inductor 128 may be sufficient for some applications for low band frequencies (e.g., below 2 gigahertz (GHz)), but where a higher inductance is needed. Fabricating a single-layer helix (i.e., 2D) higher inductance inductor such as inductor 128 would require a larger area of ​​interconnect layer 114, increasing the size of passive component device 100, which is counter to the desire for miniaturization. Therefore, a different solution for creating high inductance inductors within a chip module is needed.

[0017] 2 is a cross-sectional side view of an exemplary chip module 200 including a plurality of conductive pillars 202 coupling at least one conductive trace 204 of a first plurality of conductive traces 204 to at least one conductive trace 206 of a second plurality of conductive traces 206. The at least one conductive trace 204 is in one interconnect layer 208 of a plurality of interconnect layers 208 of a passive component device 210, and the at least one conductive trace 206 is in a redistribution layer 212 of a metallization structure 214. A passive component 216 is formed by one of the conductive traces 204, one of the conductive traces 206, and at least one of the conductive pillars 202 coupled in series. In one example, these series-connected elements form one complete turn or winding 218 of a 3D coil 220 to form an inductor 222. Additional conductive pillars 202 coupling additional conductive traces 204 in series with additional conductive traces 206 can form additional turns 218 of the 3D coil 220 for higher inductance.

[0018] In this regard, the inductor 222 provided by the 3D coil 220 can have a high inductance while efficiently utilizing the otherwise unused area of ​​the chip module 200 between the passive component device 210 and the metallization structure, where the inductor 222 is formed partially in the passive component device 210, partially in the metallization structure, and partially in the space 224 between the passive component device 210 and the metallization structure 214. The core region 226 of the inductor 222 includes the space 224, which may be filled, for example, with either air, a mold compound, or another underfill (not shown). The height H of the core region 226 of the 3D coil 220 may be 1 / 2 mm or 1 / 4 mm. C200 is the distance (e.g., at least 50 micrometers (μm)) extending between the conductive trace 206 in the metallization structure 214 and the conductive trace 204 in the passive component device 210. The axis 228 of the core region 226 extends between and parallel to the passive component device 210 and the metallization structure 214. The axis 228 extends in a direction perpendicular to the image in FIG.

[0019] The interconnect layer 208 is formed in a dielectric structure 230 disposed adjacent to a substrate 232. C200 The inductor of height H C200 2 is not drawn to scale. Because the inductance of the inductor 222 increases with height, the height H provided by the use of conductive pillars 202 in the space 224 between the passive component device 210 and the metallization structure 214 is greater than the distance from the top interconnect layer 208 to the bottom interconnect layer 208. C200 allows a higher inductance inductor 222 to be formed within the chip module 200 without increasing the area. The dielectric structure 230 includes a dielectric material 234, which may be an organic dielectric, such as polyimide, between the interconnect layers 208. The dielectric structure 230 may also include a capacitor 236 (e.g., a MIM capacitor) formed by disposing another capacitor dielectric material 238, which may be an inorganic dielectric (e.g., silicon nitride (SiN)) between the two interconnect layers 208.

[0020] With regard to other materials used within the chip module 200, the interconnect layer 208, the redistribution layer 212, and the conductive pillars 202 may all be formed of a metal such as copper or another conductor. The substrate 232 may be an insulating glass material, as may the passive component device 210 be a POG device 240.

[0021] 3 illustrates another exemplary chip module 300 including a passive component device 302 coupled to a metallization structure 304 by a conductive pillar 306. An inductor 308 formed in the chip module 300 has a height H C300 The core region 310 has a height H C300 is the height H of the chip module 200 C200In the chip module 200, the conductive traces 204 of the passive component devices 210 are in the lowest (i.e., furthest from the substrate 232) interconnect layer 208 (M4), and the conductive traces 206 are in the top redistribution layer 212 of the metallization structure 214. In contrast, in the chip module 300 of FIG. 3, the height H C300 is the second lowest interconnect layer 314 (M3 PCD ) to the second highest redistribution layer 318 (M2 MS ) to the conductive traces 316 in the chip module 300. The conductive pillars 306 in the chip module 300 extend to the lowest interconnect layer 314 (M4 PCD ) in the second lowest interconnect layer 314 (M3 PCD ) is coupled by a via 326 to a contact 322 at an end 324 of the conductive trace 312 in the substrate 300 .

[0022] Height H of the core region 310 C300 is the total distance from the conductive trace 312 at the top of the core region 310 to the conductive trace 316 at the bottom of the core region 310. Specifically, the height H C300 is the distance D1 from the first conductive trace 316 to the lower end 328 of the conductive pillar 306 and the length L of the conductive pillar 306. CP and a distance D2 from the top end 330 of the conductive pillar 306 to the second conductive trace 312. In one example, the length L CP The distances D1 and D2 are determined by the thickness T of the solder connector 332 on the lower end 328 and the upper end 330 of the conductive pillar 306. S And the thickness T of via 326 V In one example, the thickness T S is between 16 μm and 24 μm, and the thickness T V is between 4 μm and 6 μm (e.g., the distance between each interconnect layer 314). Prior to bonding the passive component device 302 to the metallization structure 304, a portion of the dielectric material 334 is formed on the lowest interconnect layer 314 (M4PCD ) and a conductive pillar 306 is formed on the contact area 320. The conductive pillar 306 may be electrically coupled to a conductive trace 316 in the metallization structure 304 to provide a physical link and electrical connection for the passive component device 302 and other circuitry (not shown) coupled to the metallization structure 304. C300 To further increase, the distances D1 and D2 can be increased by forming the inductor 308 with conductive traces 312 in higher ones of the interconnect layers 314, conductive traces 316 in lower ones of the redistribution layers 318, and additional more vias 326.

[0023] 4 is a cross-sectional side view of an MCM 400 including an IC die 402 and a passive component device 404 on a metallization structure 406. In the example of FIG. 4, the IC die 402 is coupled to the metallization structure 406 by solder bumps 408 in a flip-chip manner. At least one conductive pillar 410 couples a first conductive trace 412 of the first plurality of conductive traces 412 of the passive component device 404 to a second conductive trace 414 of the second plurality of conductive traces 414 of the metallization structure 406 to form an inductor 416. As previously described, the inductor 416 is provided as a coil 418 formed of the conductive pillar 410, the conductive trace 412, and the conductive trace 414. The passive component device 404 also includes a capacitor 420 that, together with the inductor 416 and other passive components (not shown), forms a lumped component filter ("RF filter 422") electrically coupled to circuitry in the IC die 402. Thus, the IC die 402 includes an RF circuit (not shown) coupled to at least one of the inductor 416 and the capacitor 420. The MCM 400 may be an RF front-end module 424 in which the IC die 402, the passive component device 404, and optionally other chips or devices are enclosed within a molding compound 426.

[0024] 5 is a flow chart illustrating a method 500 of forming a chip module 200 as in the example shown in FIG. 2. The method includes forming a metallization structure 214 including a first conductive trace 206 (block 502). The method 500 also includes forming a passive component device 210 including a dielectric structure 230 disposed adjacent to a substrate 232 and a second conductive trace 204 disposed within the dielectric structure 230 (block 504). The method 500 further includes forming a passive component 216 including at least one conductive pillar 202 coupled to the first conductive trace and the second conductive trace 204 (block 506).

[0025] The perspective view of a 3D inductor 600 ("inductor 600") in FIG. 6 illustrates an example of any of the inductors 222, 308, 416 of FIGS. 2-4. In FIG. 6, one complete turn 602 of the inductor 600 is formed by a first conductive pillar 604, a first conductive trace 606, a second conductive pillar 608, and a second conductive trace 610. A complete turn 602 is defined as a complete rotation of the core region 614 of the inductor 600 about the core axis 612. Although it is difficult to see in the cross-sectional side views of FIGS. 2-4, the turn 602 of the inductor 600 does not form a closed loop, but rather forms a helical turn 602 around the core region 614. In particular, the inductor 600 includes a first conductive pillar 604 coupled to a first contact 616 of the first conductive trace 606. The second conductive pillar 608 is coupled to a second contact 618 of the first conductive trace 606 and to a third contact 620 of the second conductive trace 610. The inductor 600 continues with a third conductive pillar 622 coupled to a fourth contact 624 of the second conductive trace 610 and to a fifth contact 626 of a third conductive trace 628. A fourth conductive pillar 630 is coupled between a sixth contact 632 of the third conductive trace 628 and a seventh contact 634 of a fourth conductive trace 636. The fourth conductive trace 636 extends to an eighth contact 638 from which additional turns of the inductor 600 can continue.

[0026] Greater inductance can be achieved by continuing the inductor 600 with additional turns 602 around the core region 614. However, adding more turns 602 increases the length L of the inductor 600 along the core axis 612. CORE , which may cause an increase in the area of ​​the passive component device and the chip module. CORE 4. To minimize the center-to-center distance P (e.g., between the first conductive pillar 604 and the third conductive pillar 622), the center-to-center distance P (e.g., between the first conductive pillar 604 and the third conductive pillar 622) must also be minimized. The minimum center-to-center distance P (e.g., 100 μm) of the conductive pillars 604, 622 is less than the minimum center-to-center distance (e.g., >>102 μm) that can be achieved with the solder bumps 408 of FIG. 4. As a result, the turns 602 of the inductor 600 that are separated by the distance P between the conductive pillars 604 and 622 are closer together than if the inductor 600 were formed with the solder bumps 408.

[0027] The conductive pillars 604, 608 are also less expensive than the solder bumps 408, which require a gold contact layer. In addition, the conductive pillars 604, 608 are formed of a highly conductive metal, such as copper, which has a lower resistivity than the solder compound. Taking the above factors into account, the inductor 600 formed by the conductive pillars 604, 608 shown in FIG. 6 has a higher density along the core axis 612 than if the conductive pillars 604, 608 were replaced with the solder bumps 408. For the reasons explained above, the inductor 600 with the conductive pillars 604, 608 is also less expensive and has a higher Q value than if the conductive pillars 604, 608 were replaced with the solder bumps 408.

[0028] FIG. 7A is a plan view from below of an example of a passive component device 700 and a number of inductors 702, 704, and 706 in a chip module 708. A conductive trace 710 is the only visible feature of a metallization structure not otherwise shown in FIG. 7. A conductive trace 712 is formed in a dielectric structure (not otherwise shown) of the passive component device 700 described above. The conductive trace 710 is coupled to the conductive trace 712 by a conductive pillar 714. The multiple inductors 702, 704, and 706 are all contained in a lumped element circuit 716 in the passive component device 700. The inductors 702 and 704 are aligned and closely spaced to cause positive coupling. In this regard, the conductive pillar 714 coupling the conductive trace 710 and the conductive trace 712 to form the multiple inductors 702, 704, and 706 provides a high inductance that can be used in a lumped component filter to filter sub-2 GHz RF frequencies in small mobile devices.

[0029] Figure 7B is a perspective view of the chip module 708 of Figure 7A provided to more clearly show the conductive pillars 714 coupling the conductive traces 710 and 712. As shown, each of the conductive pillars 714 is coupled to the conductive traces 710 of the metallization structure by a solder joint 718. Forming the conductive pillars 714 directly on the conductive traces 712 during manufacturing of the passive component device 700 obviates the need for the solder joints 718 between the conductive pillars 714 and the conductive traces 712.

[0030] FIG. 8 is a bottom plan view of a portion of a passive component device 800 in a chip module 802, where conductive traces 804 are the only visible portion of a metallization structure not otherwise shown. The passive component device 800 includes 3D inductors 806 and 808, and also includes a 2D inductor 810. The 2D inductor 810 is a spiral conductive trace 812 in one of multiple interconnect layers 814. Although the 2D inductor 810 is formed primarily within one interconnect layer 814 of the passive component device 800, the 2D inductor 810 occupies more area of ​​the passive component device 800 for a single turn 816 than is occupied by multiple turns 818 of the 3D inductor 806. Thus, FIG. 8 illustrates the area savings provided by using the 3D inductors 806 and 808 in a filter where high inductance is required. However, some filters require both a lower level of inductance provided by 2D inductor 810 and a higher level of inductance provided by 3D inductors 806 and 808.

[0031] FIG. 9 is a bottom plan view of a passive component device 900 in a chip module 902 similar to the chip module 802 of FIG. 8. Here, the chip module 902 has passive components 904, 906, and 908 formed with conductive traces 910 of a metallization structure not otherwise shown, and conductive traces 912 in a dielectric structure (not shown) of the passive component device 900. The chip module 902 is somewhat different from the chip module 802 of FIG. 8 because, unlike the 2D inductor 810, the 2D inductor 908 is disposed between the 3D inductor 904 and a substrate 914 in a top interconnect layer 916 (e.g., M3). In the passive component device 900, the conductive traces 912 forming the 3D inductor 904 are in a bottom interconnect layer 916 away from the substrate 914 (e.g., M4), and are not in the interconnect layer 916 between the 3D inductor 904 and the substrate 914. Because the 2D inductor 908 primarily occupies only one interconnect layer 916, the 2D inductor 908 is disposed between the 3D inductor 904 and the substrate 914 to more efficiently use the area of ​​the chip module 902. Accordingly, the chip module 902 may provide the functionality of the chip module 802 in a smaller area than the chip module 802 of FIG.

[0032] FIG. 10 illustrates an exemplary wireless communication device 1000 including a radio frequency (RF) component formed of one or more ICs 1002, any of which may include a chip module including a conductive pillar that serially couples at least one conductive trace in an interconnect layer of a passive component device with at least one conductive trace of a redistribution layer of a metallization structure to form a high density 3D coil of an inductor having a core region between the metallization structure and the passive component device, according to any of the aspects illustrated in any of FIGS. 2-4, 7A-7B, 8, and 9, and disclosed herein. The wireless communication device 1000 may include or be provided within any of the above devices, as examples. As illustrated in FIG. 10, the wireless communication device 1000 includes a transceiver 1004 and a data processor 1006. The data processor 1006 may include a memory for storing data and program codes. The transceiver 1004 includes a transmitter 1008 and a receiver 1010 supporting bidirectional communication. In general, the wireless communication device 1000 may include any number of transmitters 1008 and / or receivers 1010 for any number of communication systems and frequency bands. All or a portion of the transceiver 1004 may be implemented on one or more analog ICs, RFICs (RFICs), mixed-signal ICs, etc.

[0033] The transmitter 1008 or receiver 1010 may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In a super-heterodyne architecture, the signal is frequency converted between RF and baseband in multiple stages for the receiver 1010, for example, from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct-conversion architecture, the signal is frequency converted between RF and baseband in one stage. The super-heterodyne architecture and the direct-conversion architecture may use different circuit blocks and / or have different requirements. In the wireless communication device 1000 in FIG. 10, the transmitter 1008 and receiver 1010 are implemented with a direct-conversion architecture.

[0034] On the transmit path, a data processor 1006 processes data to be transmitted and provides I and Q analog output signals to a transmitter 1008. In the exemplary wireless communication device 1000, the data processor 1006 includes digital-to-analog converters (DACs) 1012(1) and 1012(2) to convert digital signals generated by the data processor 1006 into I and Q analog output signals, e.g., I and Q output currents, for further processing.

[0035] Within the transmitter 1008, low pass filters 1014(1) and 1014(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by previous digital-to-analog conversion. Amplifiers (AMPs) 1016(1), 1016(2) amplify the signals from the low pass filters 1014(1), 1014(2), respectively, and provide I and Q baseband signals. An upconverter 1018 upconverts the I and Q baseband signals with I and Q TX LO signals from a transmit (TX) local oscillator (LO) signal generator 1022 through mixers 1020(1), 1020(2) to provide an upconverted signal 1024. A filter 1026 filters the upconverted signal 1024 to remove unwanted signals caused by frequency upconversion as well as noise in the receive frequency band. A power amplifier (PA) 1028 amplifies the upconverted signal 1024 from filter 1026 to obtain a desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 1030 and transmitted via an antenna 1032.

[0036] In the receive path, an antenna 1032 receives a signal transmitted by a base station and provides a received RF signal, which is routed through a duplexer or switch 1030 and provided to a low noise amplifier (LNA) 1034. The duplexer or switch 1030 is designed to operate at a particular RX to TX duplexer frequency separation such that the receive (RX) signal is separated from the TX signal. The received RF signal is amplified by the LNA 1034 and filtered by a filter 1036 to obtain a desired RF input signal. Downconversion mixers 1038(1), 1038(2) mix the output of the filter 1036 with I and Q RX LO signals (i.e., LO_I and LO_Q) from a RX LO signal generator 1040 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1042(1), 1042(2) and further filtered by low pass filters 1044(1), 1044(2) to obtain I and Q analog input signals, which are provided to the data processor 1006. In this example, the data processor 1006 includes ADCs 1046(1), 1046(2) to convert the analog input signals to digital signals for further processing by the data processor 1006.

[0037] In the wireless communication device 1000 of FIG. 10, a TX LO signal generator 1022 generates I and Q TX LO signals for use in frequency upconversion, and a RX LO signal generator 1040 generates I and Q RX LO signals for use in frequency downconversion. Each LO signal is a periodic signal having a particular fundamental frequency. A TX phase-locked loop (PLL) circuit 1048 receives timing information from the data processor 1006 and generates a control signal used to adjust the frequency and / or phase of the TX LO signal from the TX LO signal generator 1022. Similarly, a RX PLL circuit 1050 receives timing information from the data processor 1006 and generates a control signal used to adjust the frequency and / or phase of the RX LO signal from the RX LO signal generator 1040.

[0038] Wireless communication devices 1000 each including chip modules including conductive pillars that serially couple at least one conductive trace in an interconnect layer of a passive component device with at least one conductive trace of a redistribution layer of a metallization structure to form a high density three dimensional 3D coil of an inductor having a core region between the metallization structure and the passive component device according to any of the embodiments shown in any of Figures 2-4, 7A-7B, 8 and 9 and disclosed herein may be provided or integrated within any processor-based device. Examples include, but are not limited to, a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle part, an avionics system, a drone, and a multicopter.

[0039] In this regard, FIG. 11 illustrates an example of an exemplary processor-based system 1100 including a chip module including a conductive pillar that serially couples at least one conductive trace in an interconnect layer of a passive component device with at least one conductive trace of a redistribution layer of a metallization structure to form a high density 3D coil of an inductor having a core region between the metallization structure and the passive component device according to any of the embodiments shown in any of FIGS. 2-4, 7A-7B, 8, and 9 and disclosed herein. In this example, the processor-based system 1100 includes one or more central processing units (CPUs) 1102, which are also referred to as CPUs or processor cores, each including one or more processors 1104. The CPUs 1102 may have a cache memory 1106 coupled to the processors 1104 for fast access to temporarily stored data. As an example, the processor 1104 may include a chip module including a conductive pillar that serially couples at least one conductive trace in an interconnect layer of a passive component device with at least one conductive trace in a redistribution layer of a metallization structure to form a high density 3D coil of inductors with a core region between the metallization structure and the passive component device, as shown in any of FIGS. 2-4, 7A-7B, 8, and 9, and according to any embodiment disclosed herein. The CPU 1102 is coupled to a system bus 1108 and may interconnect master and slave devices included in the processor-based system 1100. As is well known, the CPU 1102 communicates with these other devices by exchanging address, control, and data information over the system bus 1108. For example, the CPU 1102 may communicate bus transaction requests to the memory controller 1110, as an example of a slave device. Although not shown in FIG. 11, multiple system buses 1108 may be provided, with each system bus 1108 constituting a different fabric.

[0040] Other master and slave devices may be connected to the system bus 1108. As shown in FIG. 11, these devices may include, by way of example, a memory system 1112 including a memory controller 1110 and one or more memory arrays 1114, one or more input devices 1116, one or more output devices 1118, one or more network interface devices 1120, and one or more display controllers 1122. Each of the memory system 1112, the one or more input devices 1116, the one or more output devices 1118, the one or more network interface devices 1120, and the one or more display controllers 1122 may include a chip module including a conductive pillar that serially couples at least one conductive trace in an interconnect layer of a passive component device with at least one conductive trace of a redistribution layer of a metallization structure to form a high density 3D coil of an inductor having a core region between the metallization structure and the passive component device, according to any of the embodiments shown in FIG. 2-4, 7A-7B, 8, and 9, and disclosed herein. The input devices 1116 may include any type of input device including, but not limited to, input keys, switches, voice processors, etc. The output devices 1118 may include any type of output device including, but not limited to, audio, video, other visual indicators, etc. The network interface devices 1120 may be any device configured to enable the exchange of data into and out of the network 1124. The network 1124 may be any type of network including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH network, and the Internet. The network interface devices 1120 may be configured to support any type of desired communication protocol.

[0041] The CPU 1102 may also be configured to access a display controller 1122 via the system bus 1108 to control information sent to one or more displays 1126. The display controller 1122 sends information to be displayed to the display 1126 via one or more video processors 1128, which process the information to be displayed into a format appropriate for the display 1126. The display 1126 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc. The display controller 1122, the display 1126, and / or the video processor 1128 may include a chip module including a conductive pillar that serially couples at least one conductive trace in an interconnect layer of a passive component device with at least one conductive trace of a redistribution layer of a metallization structure to form a high-density 3D coil of an inductor having a core region between the metallization structure and the passive component device, as shown in any of Figures 2-4, 7A-7B, 8, and 9, and according to any embodiment disclosed herein.

[0042] Those skilled in the art will further appreciate that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in a memory or in another computer-readable medium and executed by a processor or other processing device, or a combination of both. The master and slave devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. The memories disclosed herein may be of any type and size and may be configured to store any type of desired information. To clearly illustrate this interchangeability, the above describes various exemplary components, blocks, modules, circuits, and steps generally in terms of their functions. How such functions are implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functions in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0043] The various example logic blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0044] Aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, which may be present in, for example, a random access memory (RAM), a flash memory, a read only memory (ROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a register, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from the storage medium and write information to the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, a base station, or a server.

[0045] It should also be noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and explanations. The described operations may be performed in many different sequences other than the sequence shown. Furthermore, an operation described in a single operational step may actually be performed in several different steps. Furthermore, one or more operational steps described in the exemplary aspects may be combined. It should be understood that the operational steps shown in the flow chart may be subject to many different modifications, as will be readily apparent to those skilled in the art. Those skilled in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0046] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other examples. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. [Explanation of symbols]

[0047] 100 Passive Devices 102 Metallized structures 104 Solder Bumps 106 Dielectric Structure 108 Substrate 110 Metal-insulator-metal (MIM) capacitors 112 Passive-on-glass (POG) devices 114 Interconnection Layer 116 Dielectric Materials 118 Conductive (e.g., metal) traces 120 Vertical Interconnect Access (Via) 122 Dielectric layer 124 Contacts 126 Conductive Traces 128 Inductor 130 Conductive Traces 132 First end 134 First Contact 136 Second End 138 Underpass 140 Second Contact 200 Chip Module 202 Conductive pillar 204 first plurality of conductive traces, at least one conductive trace, conductive trace 206 second plurality of conductive traces, at least one conductive trace, conductive trace 208 Interconnection Layer 210 Passive Components Devices 212 Redistribution layer 214 Metallized structures 216 Passive Components 218 Complete Rotation or Turn 220 3D Coil 222 Inductor 224 Space 226 Core Area 228 Axis 230 Dielectric Structure 232 Substrate 234 Dielectric Materials 236 Capacitor 238 Capacitor Dielectric Materials 240 POG Devices 300 Chip Module 302 Passive Components Devices 304 Metallized structure 306 Conductive Pillar 308 Inductor 310 Core Area 312 Conductive Trace 314 Interconnection Layer 316 Conductive Trace 318 Redistribution layer 320 contact area 322 Contacts 324 End 326 Beer 328 Bottom end 330 Upper end 332 Solder Connector 334 Dielectric Materials 400 Multi-Chip Module (MCM) 402 Integrated Circuit (IC) Die 404 Passive Components Devices 406 Metallized structure 408 Solder Bumps 410 Conductive Pillar 412 first plurality of conductive traces, first conductive trace, conductive trace 414 second plurality of conductive traces, second conductive trace, conductive trace 416 Inductor 418 Coil 420 Capacitor 422 Lumped Component Filters, RF Filters 424 RF Front-End Module 426 Molding Compound 600 3D inductor, inductor 602 Full Turn 604 First conductive pillar 606 First Conductive Trace 608 Second conductive pillar 610 Second Conductive Trace 612 Core shaft 614 Core Area 616 First Contact 618 Second Contact 620 The third contact point 622 Third conductive pillar 624 The Fourth Contact 626 The fifth contact point 628 Third Conductive Trace 630 4th conductive pillar 632 The Sixth Contact 634 The Seventh Contact 636 Fourth Conductive Trace 638 The Eighth Contact Point 700 Passive Devices 702 Inductor 704 Inductor 706 Inductor 708 Chip Module 710 Conductive Trace 712 Conductive Trace 714 Conductive Pillar 716 Lumped Element Circuits 718 Solder Joint 800 Passive Devices 802 Chip Module 804 Conductive Trace 806 3D Inductor 808 3D Inductor 810 2D Inductor 812 Spiral Conductive Trace 814 Interconnection Layer 816 Single Winding 818 Multiple turns 900 Passive Devices 902 Chip Module 904 Passive Components 906 Passive Components 908 Passive Components 910 Conductive Trace 912 Conductive Trace 914 Substrate 916 Upper interconnect layer, Lower interconnect layer, Interconnect layer 1000 Wireless Communication Devices 1002 IC 1004 Transceiver 1006 Data Processor 1008 Transmitter 1010 Receiver 1012(1) Digital-to-Analog Converter (DAC) 1012(2) Digital-to-Analog Converter (DAC) 1014(1) Low-pass filter 1014(2) Low-pass filter 1016(1) Amplifier (AMP) 1016(2) Amplifier (AMP) 1018 Upconverter 1020(1) Mixer 1020(2) Mixer 1022 Transmit (TX) Local Oscillator (LO) Signal Generator 1024 upconverted signal 1026 Filter 1028 Power Amplifier (PA) 1030 Duplexer or Switch 1032 Antenna 1034 Low Noise Amplifier (LNA) 1036 Filter 1038(1) Downconversion mixer 1038(2) Downconversion mixer 1040 Receive (RX) Local Oscillator (LO) Signal Generator 1042(1) AMP 1042(2) AMP 1044(1) Low-pass filter 1044(2) Low-pass filter 1046(1) Analog-to-Digital Converter (ADC) 1046(2) Analog-to-Digital Converter (ADC) 1048 TX Phase Locked Loop (PLL) Circuit 1050 RX PLL circuit 1100 processor-based systems 1102 Central Processing Unit (CPU) 1104 Processor 1106 Cache Memory 1108 System Bus 1110 Memory Controller 1112 Memory System 1114 Memory Array 1116 Input Devices 1118 Output Device 1120 Network Interface Device 1122 Display Controller 1124 Network 1126 Display 1128 Video Processor

Claims

1. a package substrate including a metallization structure including a first conductive trace; A passive component device, comprising: a dielectric structure disposed adjacent to the substrate; and a second conductive trace disposed within the dielectric structure; and a passive component formed partially in the passive component device, partially in the metallization structure, and partially in a space between the passive component device and the metallization structure, the passive component including at least one conductive pillar coupled to the first conductive trace and the second conductive trace.

2. The chip module of claim 1 , wherein the passive components further include a three-dimensional (3D) inductor.

3. The chip module of claim 2 , wherein the 3D inductor includes a core region between the metallization structure and the passive component device.

4. The passive component device further includes a metal-insulator-metal (MIM) capacitor formed in an interconnect layer within the dielectric structure; The chip module of claim 2 , wherein the 3D inductor is coupled to the MIM capacitor in a radio frequency (RF) signal filter.

5. The 3D inductor includes a coil extending about an axis of the core region; The chip module of claim 3 , wherein said axis of said core region is parallel to said metallization structure.

6. The passive component device is a plurality of interconnect layers on the substrate; a two-dimensional (2D) spiral inductor formed within the plurality of interconnect layers between the 3D inductor and the substrate; 3. The chip module of claim 2, wherein the second conductive trace is one of a second plurality of conductive traces disposed within the plurality of interconnect layers.

7. the first conductive trace extends between a first contact and a second contact; the second conductive trace extends between a third contact and a fourth contact; The at least one conductive pillar is a first conductive pillar coupled to the first contact of the first conductive trace; a second conductive pillar coupling the second contact of the first conductive trace and the third contact of the second conductive trace; the first conductive pillar, the first conductive trace, the second conductive pillar, and the second conductive trace are coupled in series to form a first turn of the coil of the 3D inductor; the first conductive trace is one of a first plurality of conductive traces; the first plurality of conductive traces further includes a third conductive trace extending between the fifth contact and the sixth contact; the second conductive trace is one of a second plurality of conductive traces; the second plurality of conductive traces further includes a fourth conductive trace extending between the seventh contact and the eighth contact; The at least one conductive pillar is a third conductive pillar coupled between the sixth contact of the third conductive trace and the seventh contact of the fourth conductive trace; a fourth conductive pillar coupled to the eighth contact of the fourth conductive trace; 6. The chip module of claim 5, wherein the third conductive trace, the third conductive pillar, the fourth conductive trace, and the fourth conductive pillar are coupled in series to form a second turn of the coil of the 3D inductor.

8. 10. The chip module of claim 1, wherein the distance between the first conductive trace and the second conductive trace is at least 50 micrometers (.mu.m).

9. 8. The chip module of claim 7, wherein the center-to-center distance between the first conductive pillar and the third conductive pillar is at least 100 micrometers (μm).

10. The chip module of claim 1 , wherein each of the at least one conductive pillar comprises a conductive pillar having a height of at least 40 micrometers (μm).

11. the first conductive trace and the third conductive trace are in a first redistribution layer of the metallization structure; the metallization structure further comprises a second redistribution layer; the first conductive pillar, the second conductive pillar, the third conductive pillar, and the fourth conductive pillar are electrically coupled to a contact region in the second redistribution layer; the metallization structure further includes vertical interconnect accesses (vias) electrically coupling the contact regions in the second redistribution layer to the first contact, the second contact, the fifth contact, and the sixth contact; Preferably, the second conductive trace and the fourth conductive trace are in a first interconnect layer in the dielectric structure of the passive component device; the first conductive pillar, the second conductive pillar, the third conductive pillar, and the fourth conductive pillar are electrically coupled to a contact region of a second interconnect layer of the dielectric structure; 8. The chip module of claim 7, wherein the passive component device further includes vias electrically coupling the contact areas of the second interconnect layer to the third contact, the fourth contact, the seventh contact, and the eighth contact.

12. The chip module of claim 1 , wherein the substrate of the passive component device comprises a glass substrate.

13. The chip module of claim 1 further comprising a radio frequency (RF) front-end module.

14. The chip module is a multi-chip module (MCM) further comprising an integrated circuit (IC) die coupled to the metallization structure and the passive components; 10. The chip module of claim 1, wherein the IC die preferably includes radio frequency (RF) circuitry.

15. forming a package substrate including a metallization structure including a first conductive trace; Forming a passive component device, the passive component device comprising: a dielectric structure disposed adjacent to the substrate; and a second conductive trace disposed within the dielectric structure; and forming a passive component partially in the passive component device, partially in the metallization structure, and partially in a space between the passive component device and the metallization structure, the passive component including at least one conductive pillar coupled to the first conductive trace and the second conductive trace.

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