Wave throttling based on parameter buffers

Abstract

The graphics pipeline (300) includes a first shader (305) that generates first waves, a shader processor input (SPI) (310) that launches the first waves for execution, and a scan converter (360) that generates second waves for execution based on the results of the first waves processing on one or more shaders. The first waves are selectively throttled based on a comparison of the first waves in flight and the second waves pending execution on at least one second shader. A cache (340) holds information that is written to the cache in response to the first waves finishing execution on the shaders. Information is read from the cache in response to read requests issued by the second waves. In some cases, the first waves are selectively throttled by comparing how many of the first waves are in flight and how many read requests to the cache are pending.

Description

[Background technology]

[0001] A graphics processing unit (GPU) implements a graphics processing pipeline that simultaneously processes copies of commands taken from a command buffer. GPUs and other multi-threaded processing units typically implement multiple processing elements (also called processor cores or compute units) that simultaneously execute multiple instances of a single program on multiple data sets as a single wave. A hierarchical execution model is used to match the hierarchy implemented in the hardware. The execution model defines a kernel of instructions that are executed by every wave (also called wavefronts, threads, streams or work items). The graphics pipeline in a GPU includes one or more shaders that execute using the resources of the graphics pipeline, such as compute units, memory and caches. The graphics pipeline is typically divided into a geometry part that performs geometry operations on patches or other primitives that represent portions of an image. Shaders in the geometry part may include vertex shaders, hull shaders, domain shaders and geometry shaders. The geometry part of the graphics pipeline is completed when the primitives produced by the geometry part of the pipeline are rasterized (e.g., by one or more scan converters) to form a set of pixels that represent the portion of the image. Subsequent processing on the pixels is called pixel processing and includes operations performed by shaders, such as pixel shaders, that execute using the resources of the graphics pipeline.

[0002] The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by reference to the following drawings, in which: The use of the same reference numbers in different drawings indicates similar or identical items. [Brief description of the drawings]

[0003] [Figure 1] FIG. 1 is a block diagram of a processing system, according to some embodiments. [Diagram 2] FIG. 2 illustrates a graphics pipeline capable of processing high-order geometric primitives to generate a rasterized image of a three-dimensional (3D) scene at a given resolution, according to some embodiments. [Diagram 3] FIG. 2 is a block diagram of a portion of a graphics pipeline that selectively throttles waves or groups of waves fired by a geometry shader, according to some embodiments. [Figure 4] FIG. 2 is a block diagram of a first embodiment of a management circuit for selectively throttling waves or groups of waves, according to some embodiments. [Diagram 5] FIG. 4 is a block diagram of a second embodiment of a management circuit for selectively throttling waves or groups of waves, according to some embodiments. [Figure 6] FIG. 1 is a flow diagram of a method for selectively initiating a geometry shader wave or waves, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0004] Prior to dispatching a wave group (containing one or more waves) for processing by one or more shaders implemented by compute units in the shader hub, the geometry engine reserves space in a memory or cache to store output generated by processing the wave group in the shader. For example, the geometry engine may send a reservation request to the PC manager for space to hold a parameter buffer. The PC manager reserves the requested space in a level 2 (L2) cache and returns information identifying the reserved space in the L2 cache to the geometry engine. In response to receiving a reservation confirmation, the geometry engine provides the wave group to a shader processor input (SPI), which launches the wave group for processing by compute units in the shader hub. Attributes from the shader output are stored in the reserved space in the L2 cache. The positions are provided to a primitive assembler, which assembles primitives (such as triangles) and sends the primitives to a scan converter via the primitive hub. The scan converter generates pixel waves that are returned to the SPI, which fetches attributes from the L2 cache. The compute units in the shader hub then perform pixel processing on the pixel waves using the attributes retrieved from the L2 cache. Thus, there is a dependency between the graphics shader waves generated by the geometry engine and the pixel waves generated by the scan converter. This dependency means that if the geometry engine launches too many waves that write too much data to the L2 cache, it can exhaust space for other data types in the L2 cache, which can lead to excessive cache thrashing and degrade the performance of the graphics pipeline.

[0005] 1-6 disclose systems and techniques for reducing thrashing of a cache shared by geometry shaders and pixel shaders by selectively throttling geometry shader (GS) waves (or waves associated with other shaders, such as vertex shaders) fired by a shader processor input (SPI) based on a comparison of in-flight GS work generated by the scan converter to pending pixel shader (PS) work. The scan converter provides requests to the SPI to read information from the cache. Some embodiments of the management circuit maintain counters for three events: (1) a first counter for firing of GS waves, (2) a second counter of GS waves that have finished execution on a shader by writing to the cache, and (3) a third counter of the number of requests to read from the cache for PS waves generated by the scan converter. The counters are incremented in response to corresponding events being written to a windowing first-in-first-out (FIFO) buffer and decremented in response to corresponding events being read from the windowing FIFO. The management circuit determines an amount of in-flight GS work based on a difference between the first counter and the second counter. The management circuit determines an amount of pending PS work based on a difference between the second counter and a third counter. The management circuit throttles waves launched by the SPI if the amount of in-flight GS work is greater than the amount of pending PS work. Otherwise, the SPI is free to launch waves according to an algorithm such as a greedy algorithm. In some embodiments, the criteria for throttling waves is modified such that the management circuit throttles waves launched by the SPI if the amount of in-flight GS work is greater than the amount of pending PS work plus an additional factor to reduce the likelihood that throttling will starve the graphics pipeline of work.For example, the additional factor may be determined based on a measure of the burstiness of the number of reads requested by pending PS work.

[0006] FIG. 1 is a block diagram of a processing system 100 according to some embodiments. The processing system 100 includes or has access to a memory 105 or other storage components implemented using a non-transitory computer-readable storage medium, such as Dynamic Random-Access Memory (DRAM). However, in some cases, the memory 105 can be implemented using other types of memory, including Static Random-Access Memory (SRAM), non-volatile RAM, etc. The memory 105 is referred to as an external memory because it is implemented outside of the processing unit implemented in the processing system 100. The processing system 100 also includes a bus 110 to support communication between entities implemented in the processing system 100, such as the memory 105. Some embodiments of the processing system 100 include other buses, bridges, switches, routers, etc., which are not shown in FIG. 1 for clarity.

[0007] The techniques described herein may be utilized in various embodiments with any of a variety of parallel processors (e.g., vector processors, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), non-scalar processors, highly parallel processors, artificial intelligence (AI) processors, inference engines, machine learning processors, other multi-threaded processing units, etc.). FIG. 1 illustrates an example of a parallel processor, in particular a graphics processing unit (GPU) 115, according to some embodiments. The graphics processing unit (GPU) 115 renders images for presentation on a display 120. For example, the GPU 115 renders objects to generate pixel values ​​that are provided to the display 120, which uses the pixel values ​​to display images representing the rendered objects. The GPU 115 implements multiple compute units (CUs) 121, 122, 123 (collectively referred to herein as "compute units 121-123") that execute instructions simultaneously or in parallel. In some embodiments, the computation units 121-123 include one or more single-instruction-multiple-data (SIMD) units, and the computation units 121-123 are aggregated into a workgroup processor, a shader array, a shader engine, or the like. The number of computation units 121-123 implemented in the GPU 115 is a matter of design choice, and some embodiments of the GPU 115 include more or fewer computation units than shown in FIG. 1. The computation units 121-123 may be used to implement a graphics pipeline, as described herein. Some embodiments of the GPU 115 are used for general-purpose computing. The GPU 115 executes instructions, such as program code 125, stored in the memory 105, and the GPU 115 stores information, such as results of executed instructions, in the memory 105.

[0008] The processing system 100 also includes a central processing unit (CPU) 130 connected to the bus 110 and thus in communication with the GPU 115 and the memory 105 via the bus 110. The CPU 130 implements multiple processor cores 131, 132, 133 (collectively referred to herein as "processor cores 131-133") that execute instructions simultaneously or in parallel. The number of processor cores 131-133 implemented in the CPU 130 is a matter of design choice, and some embodiments include more or fewer processor cores than shown in FIG. 1. The processor cores 131-133 execute instructions, such as program code 135 stored in the memory 105, and the CPU 130 stores information, such as results of executed instructions, in the memory 105. The CPU 130 can also initiate graphics processing by issuing a draw call to the GPU 115. Some embodiments of CPU 130 implement multiple processor cores (not shown in FIG. 1 for clarity) that independently execute instructions simultaneously or in parallel.

[0009] An Input / Output (I / O) engine 145 handles input or output operations associated with the display 120 and other elements of the processing system 100, such as a keyboard, a mouse, a printer, an external disk, etc. The I / O engine 145 is coupled to the bus 110 such that the I / O engine 145 communicates with the memory 105, the GPU 115, or the CPU 130. In the illustrated embodiment, the I / O engine 145 reads information stored in an external storage component 150, which is implemented using a non-transitory computer-readable storage medium, such as a Compact Disk (CD), a Digital Video Disc (DVD), etc. The I / O engine 145 can also write information, such as results of processing by the GPU 115 or the CPU 130, to the external storage component 150.

[0010] The processing system 100 implements a pipeline circuit for executing instructions in multiple stages of a pipeline. The pipeline circuit is implemented in some embodiments of the compute units 121-123 or the processor cores 131-133. In some embodiments, the pipeline circuit including the compute units 121-123 is used to implement a graphics pipeline that executes different types of shaders, including but not limited to vertex shaders, hull shaders, domain shaders, geometry shaders, and pixel shaders. Some embodiments of the processing system 100 include one or more caches that hold information written to the cache by a shader upon completion of execution of a wave or wave group, such as a geometry shader wave group. The information written to the cache is subsequently read during execution of another wave or wave group, such as a pixel shader wave. Some embodiments of the geometry shader generate a first wave group, and a shader processor input (SPI) launches the first wave group for execution by the shader. The scan converter generates a second wave group for execution on the shader based on the results of processing the first wave group, one or more shaders. The first waves are selectively throttled based on a comparison of the in-flight first waves and the second waves pending execution on at least one shader. The cache holds information that is written to the cache in response to the first waves finishing execution on a shader. The information is read from the cache in response to read requests issued by the second waves. In some cases, the first waves are selectively throttled by comparing how many of the first waves are in-flight and how many read requests to the cache are pending.

[0011] 2 illustrates a graphics pipeline 200 capable of processing high-order geometric primitives to generate a rasterized image of a three-dimensional (3D) scene at a given resolution, according to some embodiments. The graphics pipeline 200 is implemented in some embodiments of the processing system 100 illustrated in FIG. 1. The illustrated embodiment of the graphics pipeline 200 is implemented according to the DX11 specification. Other embodiments of the graphics pipeline 200 are implemented according to other Application Programming Interfaces (APIs), such as Vulkan, Metal, DX12, etc. The graphics pipeline 200 is subdivided into a geometry processing unit 201, which comprises the portion of the graphics pipeline 200 before rasterization, and a pixel processing unit 202, which comprises the portion of the graphics pipeline 200 after rasterization.

[0012] The graphics pipeline 200 has access to storage resources 205, such as one or more memories or hierarchies of caches used to implement buffers and store vertex data, texture data, and the like. In the illustrated embodiment, the storage resources 205 include a load data store (LDS) 206 circuit used to store data. The storage resources 205 also include one or more caches 207 that cache frequently used data. The caches 207 are used to implement parameter buffers. As described herein, a wave or wave group executing on a shader of the graphics pipeline 200 finishes execution by writing the results of processing the wave or wave group to the cache 207. Shaders further downstream in the graphics pipeline 200 can issue read requests to read information from the cache 207, such as the results of processing by a wave or wave group that previously finished executing on the shader. The storage resources 205 may be implemented using some embodiments of the memory 105 shown in FIG. 1.

[0013] An input assembler 210 accesses information from storage resources 205 that is used to define objects that represent portions of a model of a scene. An example of a primitive is shown in Figure 2 as a triangle 211, although some embodiments of graphics pipeline 200 process other types of primitives. A triangle 203 includes one or more vertices 212 (only one of each is shown in Figure 2 for clarity) connected by one or more edges 214. The vertices 212 are shaded during geometry processing section 201 of graphics pipeline 200.

[0014] Vertex shader 215, implemented in software in the illustrated embodiment, logically receives as input a single vertex 212 of a primitive and outputs a single vertex. Some embodiments of shaders, such as vertex shader 215, perform single instruction, multiple data (SIMD) processing so that multiple vertices are processed simultaneously. Graphics pipeline 200 implements a unified shader model such that all shaders included in graphics pipeline 200 have the same execution platform on a shared massive SIMD compute unit. Thus, shaders, including vertex shader 215, are implemented using a common set of resources, referred to herein as a unified shader pool 216.

[0015] Hull shader 218 operates on input high-order patches or control points used to define the input patches. Hull shader 218 outputs tessellation coefficients and other patch data, such as control points for the patches processed in hull shader 218. The tessellation coefficients are stored in storage resource 205 so that they may be accessed by other entities in graphics pipeline 200.

[0016] The tessellator 220 receives objects (e.g., patches) from the hull shader 218. In some embodiments, primitives generated by the hull shader 218 are provided to the tessellator 220. The tessellator 220 generates information identifying primitives that correspond to the input object, e.g., by tessellating the input object based on tessellation factors generated by the hull shader 218. The tessellation subdivides input high-order primitives, such as patches, into a set of lower-order output primitives that represent finer levels of detail, e.g., as indicated by tessellation factors that specify the granularity of the primitives generated by the tessellation process. Thus, a model of the scene is represented by a smaller number of high-order primitives (to save memory or bandwidth), and additional detail is added by tessellating the high-order primitives.

[0017] Domain shader 224 inputs the domain location and (optionally) other patch data. Domain shader 224 operates on the information provided and generates a single vertex for output based on the input domain location and other information. In the illustrated embodiment, domain shader 224 generates primitives 222 based on triangles 211 and tessellation factors. Domain shader 224 launches primitives 222 upon completion of processing.

[0018] The geometry shader 226 receives input primitives from the domain shader 224 and outputs up to four primitives (per input primitive) generated by the geometry shader 226 based on the input primitives. In the illustrated embodiment, the geometry shader 226 generates output primitives 228 based on the tessellated primitives 222. Some embodiments of the geometry shader 226 generate waves (referred to herein as "GS waves") that are initiated by corresponding shader processor inputs (SPIs, not shown in FIG. 2 for clarity). Upon completion of execution on the shader engine, the waves write their output back to the cache 207.

[0019] One stream of primitives is provided to one or more scan converters 230, and in some embodiments up to four streams of primitives are concatenated into buffers in storage resources 205. Scan converter 230 performs shading operations and other operations such as clipping, perspective division, cutting, and viewport selection. Scan converter 230 produces a set of pixels 232 that are subsequently processed in pixel processing unit 202 of graphics pipeline 200. Some embodiments of scan converter 230 service requests to read information from cache 207, for example, by sending a request to an SPI implemented in graphics pipeline 200.

[0020] In the illustrated embodiment, pixel shader 234 inputs a pixel flow (e.g., including set of pixels 232) and outputs zero or another pixel flow depending on the input pixel flow. Output merger block 236 performs blending, depth, stencil, or other operations on the pixels received from pixel shader 234.

[0021] Some or all of the shaders in graphics pipeline 200 perform texture mapping using texture data stored in storage resources 205. For example, pixel shader 234 may read texture data from storage resources 205 and shade one or more pixels using the texture data. The shaded pixels are then provided to a display for presentation to a user.

[0022] 3 is a block diagram of a portion of a graphics pipeline 300 that selectively throttles waves or groups of waves fired by a geometry shader, according to some embodiments. The graphics pipeline 300 is implemented in some embodiments of the processing system 100 shown in FIG. 1 and the graphics pipeline 200 shown in FIG.

[0023] The geometry engine 305 generates waves or waves for geometry shaders. Thus, waves or waves generated by the geometry engine 305 are referred to as GS waves. However, in some embodiments, waves or waves are generated by or for other shaders, such as vertex shaders, in which case the waves or waves are referred to by other names, such as VS waves. The geometry engine 305 provides GS waves to the SPI 310, which selectively activates or throttles the GS waves as described herein. The geometry engine 305 also provides information to the management circuit 315 for signaling the activation of the GS waves, as indicated by arrow 320. The management circuit 315 increments a first counter 325 in response to an activation event being written to the windowing buffer 330. The management circuit 315 also decrements the first counter 325 in response to an activation event being read from the windowing buffer 330.

[0024] The SPI 310 launches the GS waves to execute on one or more shaders in the shader hub 335. The GS waves are executed by the shader hub 335, and upon completion of execution, the GS waves write the results to the cache 340. In response to writing the results to the cache 340, the shader hub 335 signals the SPI 310 that the GS waves have finished executing. The shader hub 335 sends an indication of the completion of the GS waves to the SPI 310, which in turn sends a signal (referred to herein as a "done" signal or a "done" signal) to the management circuit 315 to indicate that the GS waves have finished executing, as indicated by the arrow 345. In response to the execution end event being written to the windowing buffer 330, the management circuit 315 increments the second counter 326. In response to the execution end event being read from the windowing buffer 330, the management circuit 315 also decrements the second counter 326.

[0025] Primitive assembler 350 generates primitives by processing GS waves and provides the primitives to crossbar 355 (also called primitive hub), which provides the assembled primitives to scan converter 360. Scan converter 360 generates pixel shader (PS) waves for execution by shaders in shader hub 335. Thus, scan converter 360 signals SPI 310, as indicated by 365, which can launch the PS waves for execution in shader hub 335. SPI 310 also generates read requests to read information from cache 340 that is used by shader hub 335 to process the PS waves. In response to generating the read request, SPI 310 sends a signal to management circuit 315 indicating that a read request is pending for cache 340, as indicated by arrow 370. The management circuit 315 increments the third counter 327 in response to a read request event being written to the windowing buffer 330. The management circuit 315 also decrements the third counter 327 in response to a read request event being read from the windowing buffer 330. The read request does not leave the SPI 310 until the SPI 310 receives a “GS wave complete” signal from the management circuit 315.

[0026] Some embodiments of the management circuit 315 selectively throttle (or instruct the SPI 310 to selectively throttle) invocations from the SPI 310 based on a comparison of the number of in-flight GS waves and pending PS waves. The management circuit 315 determines a first number of in-flight first waves based on a difference between a first counter 325 and a second counter 326. The management circuit 315 also determines a second number of PS waves pending execution on shaders in the shader hub 335 based on a difference between the second counter 326 and a third counter 327. The management circuit 315 throttles (or instructs the SPI 310 to throttle) the GS waves in response to the first number being less than the second number. Some embodiments of the management circuit 315 determine an additional "bursty" factor that is applied to reduce the likelihood that throttling of the GS waves will starve the graphics pipeline 300 of work. The additional factor is determined based on an estimate of the burstiness of the read requests associated with the PS waves. In that case, the management circuit 315 throttles (or instructs the SPI 310 to throttle) the GS waves in response to the first number being less than the second number plus the additional burstiness factor.

[0027] 4 is a block diagram of a first embodiment of a management circuit 400 for selectively throttling waves or groups of waves, according to some embodiments. The first embodiment of the management circuit 400 is used to implement some embodiments of the management circuit 315 shown in FIG. 3. The management circuit 400 receives information associated with an event from an event generation circuit 405. In some embodiments, the information includes signaling indicative of a start event, a finish execution event, a read request event, etc.

[0028] The windowing buffer 410 stores information representing events in entries of the windowing buffer 410. Some embodiments of the windowing buffer 410 are implemented as a first-in, first-out (FIFO) buffer, such that events received from the event generating circuit 405 are added (or pushed) to the last entry of the windowing buffer 410 and removed (or popped) from the first entry of the windowing buffer 410.

[0029] The management circuit 400 includes a set of counters 415 that are used to count events in response to entries being added to the windowing buffer 410. In the illustrated embodiment, the set 415 includes an invocation counter 416 that counts GS waves or waves that are invoked to execute in one or more shaders, a production counter 417 that counts GS waves or waves that finish execution by writing to a cache, and a consumption counter 418 that counts read requests to the cache, for example for a PS wave. The invocation counter 416, production counter 417, and consumption counter 418 are incremented in response to corresponding events being added to the windowing buffer 410. The counters 416-418 in the set 415 are reset to 0 (or other predetermined value) during idle.

[0030] The management circuit 400 also includes a set of counters 420 that are used to count the number of activation events, produced events and consumed events contained in the windowing buffer 410. The set 420 includes a firing event counter 421 that increments by the number of firing events written to the windowing buffer 410 and decrements by the number of firing events read from the windowing buffer 410. The set 420 also includes a produced event counter 422 that increments by the number of produced events written to the windowing buffer 410 and decrements by the number of produced events read from the windowing buffer 410. The set 420 further includes a consumed event counter 423 that increments by the number of consumed events written to the windowing buffer 410 and decrements by the number of consumed events read from the windowing buffer 410.

[0031] The management circuit 400 further includes an event run counter 425 for each of the event types (e.g., launch events, produce events, and consume events). The event run counter 425 counts the burstiness of each event. The event run counter 425 for an event increments by one each time an event run is broken on the write side of the windowing buffer 410. For example, if there are 50 launch events without any produce or consume events, the LaunchRunCounter in the event run counter 425 is incremented by one. If after 50 launches there are 50 launch events and 50 produce events in the next 50 cycles, the LaunchRunCounter has a value of 51 and the ProduceRunCounter has a value of 50.

[0032] The management circuit 400 uses the values ​​of the counters 415, 420, 425 to calculate a parameter indicative of the burstiness of the event. The average burst circuit 430 calculates a per-event metric as follows: AverageBurst=EventCount / EventRunCount

[0033] The high rate circuit 435 calculates another per-event metric as follows. HighRate=EventCount+Event>AverageBurst

[0034] The values ​​generated by the average burst circuit 430 and the high rate circuit 435 are provided to the activation decision circuit 440, which uses this information in combination with the values ​​of the counters 415, 420, 425 to selectively throttle the activation of a GS wave or groups of waves.

[0035] Some embodiments of the activation decision circuit 440 selectively throttle the activation of a GS wave or group of waves based on a comparison of in-flight GS work and pending PS work. In-flight GS work (WorkInFlight) is estimated based on the difference between the values ​​of the activation counter 416 and the production counter 417. Pending PS work (WorkReady) is estimated based on the difference between the values ​​of the production counter 417 and the consumption counter 418. The activation decision circuit 440 throttles the activation of a GS wave or group of waves if the in-flight GS work is greater than the pending PS work. In some embodiments, the activation decision circuit 440 throttles the activation of a GS wave or group of waves if the following criteria are met: WorkInFlight>WorkReady+HighRate[Read]

[0036] An additional factor (HighRate[Read]) is included to account for the potential burstiness of pending PS work, e.g., read requests for a PS wave.

[0037] FIG. 5 is a block diagram of a second embodiment of a management circuit 500 for selectively throttling a wave or groups of waves, according to some embodiments. The second embodiment of the management circuit 500 is used to implement some embodiments of the management circuit 315 shown in FIG. 3. The management circuit 500 receives information associated with an event from an event generation circuit 505. In some embodiments, the information includes signaling indicating a launch event, a finish execution event, a read request event, etc. The management circuit 500 includes a set of counters 515 used to count events in response to entries being added to the windowing buffer 510. The set 515 includes a launch counter 516, a generate counter 517, and a consume counter 518. The management circuit 500 also includes a set 520 of counters 521, 522, 523 used to count the number of launch events, generate events, and consume events contained in the windowing buffer 510. An event run counter 525 counts the burstiness of each event, including launch events, generate events, and consume events.

[0038] The management circuit 500 uses the values ​​of the counters 515, 520, 525 to calculate a parameter indicative of the burstiness of the event. The average burst circuit 530 calculates a metric for each event as follows: AverageBurst=EventCount / EventRunCount

[0039] The high rate circuit 535 calculates another per-event metric as follows. HighRate=EventCount+EventAverageBurst

[0040] The low rate circuit 540 calculates another per-event metric as follows. LowRate=EventCount-EventAverageBurst

[0041] The values ​​generated by the average burst circuit 530, the high rate circuit 535 and the low rate circuit 540 are provided to the activation decision circuit 545 which uses this information in combination with the values ​​of the counters 515, 520, 525 to selectively throttle the activation of a GS wave or groups of waves.

[0042] Some embodiments of the activation decision circuit 545 selectively throttle the activation of a GS wave or waves based on a comparison of in-flight GS work and pending PS work. In-flight GS work (WorkInFlight) is estimated based on the difference between the values ​​of the activation counter 516 and the production counter 517. Pending PS work (WorkReady) is estimated based on the difference between the values ​​of the production counter 517 and the consumption counter 518. In the illustrated embodiment, the activation decision circuit 545 defines the consumption rate as follows: ConsumeRate=HighRate[Consume]-LowRate[Produce]

[0043] The activation decision circuit 545 then estimates or predicts the amount of work that is ready, for example, using the following definition: ReadyForecast=WorkReady-ConsumeRate

[0044] The activation decision circuit 545 throttles the activation of a GS wave or waves if the following criteria are met: WorkInFlight>LowRate[Launch]-ReadyForecast

[0045] If this criterion is not met, an additional GS wave or waves are initiated.

[0046] Figure 6 is a flow diagram of a method 600 for selectively activating a GS wave or groups of waves, according to some embodiments. The method 600 is implemented in some embodiments of the processing system 100 shown in Figure 1, the graphics pipeline 200 shown in Figure 2, the graphics pipeline 300 shown in Figure 3, the managing circuit 400 shown in Figure 4, and the managing circuit 500 shown in Figure 5.

[0047] At block 605, the management circuit counts GS wave group initiations. At block 610, the management circuit counts GS wave group terminations. At block 615, the management circuit counts read requests for the PS wave. At decision block 620, the management circuit compares the amount of in-flight (in FIG. 6, in-flight) GS work (determined based on the number of GS wave group initiations and terminations) to the amount of pending PS work (determined based on the number of GS wave group terminations and read requests for the PS wave). In some embodiments, the management circuit compares the amount of in-flight GS work to the sum of the amount of pending PS work and an additional factor to account for the burstiness of PS work, as described herein. If the in-flight GS work exceeds the pending PS work (possibly augmented by an additional factor), method 600 flows to block 625, where the management circuit throttles the initiation of GS waves. If the in-flight GS work is less than the pending PS work (possibly augmented by an additional factor), the method 600 flows to block 630, where the management circuitry does not throttle the launch of GS waves.

[0048] A computer-readable storage medium includes any non-transitory storage medium or combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact discs (CDs), digital versatile discs (DVDs), Blu-ray discs), magnetic media (e.g., floppy disks, magnetic tape, magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or micro-electromechanical systems (MEMS) based storage media. The computer-readable storage medium (e.g., system RAM or ROM) may be internal to the computing system, the computer-readable storage medium (e.g., a magnetic hard drive) may be permanently attached to the computing system, the computer-readable storage medium (e.g., an optical disk or Universal Serial Bus (USB)-based flash memory) may be removably attached to the computing system, or the computer-readable storage medium (e.g., network-accessible storage (NAS)) may be coupled to the computer system via a wired or wireless network.

[0049] In some embodiments, certain aspects of the techniques described above are implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied in a non-transitory computer-readable storage medium. The software may include instructions and specific data that, when executed by the one or more processors, operate the one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium may include, for example, a magnetic or optical disk storage device, a solid-state storage device such as a flash memory, a cache, a random access memory (RAM), or other non-volatile memory device(s), etc. The executable instructions stored in the non-transitory computer-readable storage medium may be implemented as source code, assembly language code, object code, or other form of instructions that can be interpreted or otherwise executed by one or more processors.

[0050] In addition to the above, it should be noted that not all activities or elements described in the summary description are required, some of the specific activities or devices may not be required, one or more additional activities may be performed, and one or more additional elements may be included. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. Also, the concepts have been described with reference to specific embodiments. However, those skilled in the art will appreciate that various changes and modifications can be made without departing from the scope of the invention as set forth in the claims. Thus, the specification and drawings should be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the invention.

[0051] Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and features from which any benefit, advantage, or solution may arise or be manifested are not to be construed as critical, essential, or essential features of any or all of the claims. Moreover, the specific embodiments described above are illustrative only, as the disclosed invention may be modified and practiced in different but similar manners apparent to those skilled in the art having the benefit of the teachings herein. No limitations are intended to the details of construction or design herein shown, other than as described in the appended claims. It is therefore apparent that the specific embodiments described above may be altered or modified, and all such variations are considered to be within the scope of the disclosed invention. Accordingly, the protection sought herein is set forth in the appended claims.

Claims

1. 1. An apparatus comprising: a wave launch circuit configured to launch a first group of waves; a scan converter circuit configured to generate a second wave based on a result of processing the first set of waves; the first waves are selectively throttled based on a comparison of the in-flight first waves to the second waves pending execution; Device.

2. a cache configured to hold stored information in response to the first waves finishing execution; The information is read by a corresponding second wave.

2. The apparatus of claim 1.

3. a first counter circuit configured to count activations of the first wave group; a second counter circuit configured to count the first waves that have completed execution by writing to the cache; a third counter circuit configured to count requests from the second wave to read from the cache.

3. The apparatus of claim 2.

4. each of the first counter circuit, the second counter circuit and the third counter circuit is incremented in response to a start event, an end of execution event and a read request event written to a windowing buffer; 4. The apparatus of claim 3.

5. each of the first counter circuit, the second counter circuit and the third counter circuit is decremented in response to the start event, the execution end event and the read request event read from the windowing buffer; 5. The apparatus of claim 4.

6. a management circuit configured to determine a first number of in-flight first waves based on a difference between the first counter circuit and the second counter circuit, and to determine a second number of pending second waves based on a difference between the second counter circuit and the third counter circuit.

6. The apparatus of claim 5.

7. the management circuitry is configured to throttle the first waves launched by the wave launch circuitry in response to the first number being less than the second number.

7. The apparatus of claim 6.

8. the management circuitry is configured to throttle the first waves launched by the wave launch circuitry in response to the first number being less than the second number plus an additional factor estimated based on burstiness of read requests associated with the second waves.

8. The apparatus of claim 7.

9. the management circuitry comprises an event run counter for counting the burstiness of read requests associated with the second wave; the event run counter is incremented in response to an interruption in successive events being written to the windowing buffer; 9. The apparatus of claim 8.

10. 1. A method comprising: a wave initiation circuit initiating a first group of waves; generating a second wave based on a result of processing the first wave group in a scan converter circuit; selectively throttling a first set of waves based on a comparison of the first set of waves that are in flight and a second set of waves that are pending execution; method.

11. writing information to a cache in response to the first waves finishing execution; The information is read by a corresponding second wave. The method of claim 10.

12. counting activations of the first wave group in a first counter circuit; counting, in a second counter circuit, the first waves that have completed execution by being written to the cache; and counting, in a third counter circuit, requests from the second wave to read from the cache.

12. The method of claim 11.

13. writing a firing event to a windowing buffer, and counting firings of the first wave group includes incrementing the first counter circuit in response to writing the firing event to the windowing buffer; reading the wake-up event from the windowing buffer, and wherein counting the wake-up of the first wave group includes decrementing the first counter circuit in response to reading the wake-up event from the windowing buffer.

13. The method of claim 12.

14. writing an end of execution event to the windowing buffer, and counting the first group of waves that have completed execution includes incrementing the second counter circuit in response to writing the end of execution event to the windowing buffer; reading the end of execution event from the windowing buffer, and counting the first group of waves that have finished executing includes decrementing the second counter circuit in response to reading the end of execution event from the windowing buffer.

14. The method of claim 13.

15. writing read request events to the windowing buffer, and counting requests from the second wave includes incrementing the third counter circuit in response to writing the read request events to the windowing buffer; reading the read request events from the windowing buffer, and wherein counting requests from the second wave includes decrementing the third counter circuit in response to reading the read request events from the windowing buffer.

14. The method of claim 13.

16. determining a first number of first waves in flight based on a difference between the first counter circuit and the second counter circuit; determining a second number of second waves pending execution based on a difference between the second counter circuit and the third counter circuit.

16. The method of claim 15.

17. selectively throttling the first group of waves includes throttling the first group of waves launched by the wave launch circuitry in response to the first number being less than the second number.

17. The method of claim 16.

18. selectively throttling the first group of waves includes throttling the first group of waves launched by the wave launch circuitry in response to the first number being less than the second number plus an additional factor estimated based on burstiness of read requests associated with the second waves.

20. The method of claim 17.

19. The method of claim 18, further comprising determining a burstiness of read requests associated with the second wave by incrementing an event run counter in response to an interruption in successive events being written to the windowing buffer.

20. The method of claim 18.

20. 1. An apparatus comprising: a scan converter circuit configured to generate a second wave based on the results of processing the first set of waves; a cache configured to hold stored information in response to the first waves finishing execution; the first wave group is selectively throttled based on a comparison of a first number of the first wave group that have been initiated and have not yet completed execution by writing to the cache and a second number of read requests to the cache from a second wave that is pending execution; Device.

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