Display panel, its manufacturing method, and display device

Abstract

Disclosed is a display panel belonging to the field of display technology, its manufacturing method, and a display device, the display panel includes a base substrate, a plurality of first pixel units, and a plurality of signal lines, the base substrate has a display area and a peripheral area, the display area includes a first display area and a second display area, the light transmittance of the first display area is greater than that of the second display area, the plurality of first pixel units are disposed on the base substrate and disposed in the first display area, the plurality of signal lines are disposed at least in the first display area and electrically connected to the plurality of first pixel units, where the plurality of signal lines include a plurality of first signal lines and a plurality of second signal lines, a first portion of each first signal line among the plurality of first signal lines is a metal signal line, a first portion of each second signal line among the plurality of second signal lines is a metal oxide signal line, the first portion of the first signal line is disposed at least in the first display area, and the first portion of the second signal line is disposed at least in the first display area.

Description

[Technical field]

[0001] This disclosure claims priority to a Chinese patent application with application number 202110939190.3 filed on August 16, 2021, titled "Display panel, its manufacturing method, and display device," the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel, a manufacturing method thereof, and a display device. [Background technology]

[0003] A full-screen display device has a high screen occupancy rate and excellent visual effects. In order to increase the screen occupancy rate of a full-screen display device, under-screen camera technology has been gradually developed in display devices such as mobile phones.

[0004] The full screen display device includes a display panel and a full display camera (FDC), the display panel has a camera display area, pixel units are arranged in the camera display area, and the camera display area can display a screen. The FDC is arranged below the display panel and faces the camera display area. Summary of the Invention [Means for solving the problem]

[0005] The embodiments of the present disclosure provide a display panel, a manufacturing method thereof, and a display device, which can improve the display uniformity of the display device.

[0006] In one aspect, the present disclosure relates to a display panel having a display area and a peripheral area at least partially surrounding the display area, the display area including a first display area and a second display area located on at least one side of the first display area, the first display area having a light transmittance greater than that of the second display area, a plurality of first pixel units disposed on the base substrate and disposed in the first display area, and a plurality of signal lines disposed at least in the first display area and electrically connected to the plurality of first pixel units, wherein the plurality of signal lines include a plurality of first signal lines and a plurality of second signal lines, a first portion of each first signal line of the plurality of first signal lines being a metal signal line, the first portion of the first signal line being disposed at least in the first display area, and a first portion of each second signal line of the plurality of second signal lines being a metal oxide signal line, the first portion of the second signal line being disposed at least in the first display area.

[0007] In one embodiment of the embodiment of the present disclosure, the first signal line includes at least one of a gate signal line, a data signal line, a reset signal line, a light emission control signal line, an initial voltage signal line, and a power supply signal line.

[0008] In one embodiment of the embodiment of the present disclosure, the first signal lines include a gate signal line and a data signal line.

[0009] In one embodiment of the present disclosure, the first signal line further includes a second portion disposed in the second display region, the second signal line further includes a second portion disposed in the second display region, and the second portion of the first signal line and the second portion of the second signal line are both metal signal lines.

[0010] In one embodiment of the present disclosure, the display panel further includes a first metal layer, a first insulating layer, and a metal oxide layer sequentially arranged on the base substrate along a direction away from the base substrate, the first signal line being arranged on the first metal layer, a first portion of at least one second signal line of the plurality of second signal lines in the first display region being arranged on the metal oxide layer, and a second portion of the second signal line in the second display region being arranged on the first metal layer, the first and second portions of the second signal line being connected via a first via penetrating the first insulating layer, and the first via being located at the boundary between the first display region and the second display region.

[0011] In one embodiment of the present disclosure, the first metal layer includes a first gate metal layer and a first source-drain metal layer, the first insulating layer includes a first passivation layer and an interlayer dielectric layer, and along a direction away from the base substrate, the first gate metal layer, the interlayer dielectric layer, the first source-drain metal layer, and the first passivation layer are sequentially stacked.

[0012] In one embodiment of the present disclosure, the display panel further includes a second insulating layer and a second metal layer, and the second metal layer, the second insulating layer, the first metal layer, the first insulating layer, and a metal oxide layer are sequentially stacked along a direction away from the base substrate, a first portion of another part of the plurality of second signal lines in the first display region is disposed in the metal oxide layer, and a second portion of the second signal line in the second display region is disposed in the second metal layer, the first portion and the second portion of the second signal line are connected via a second via penetrating the first insulating layer and the second insulating layer, and the second via is located at the boundary between the first display region and the second display region.

[0013] In one embodiment of the present disclosure, the second metal layer comprises a second gate metal layer, and the second insulating layer comprises a first gate insulating layer.

[0014] In one embodiment of the examples of the present disclosure, when a ratio of a first size of the first display area to a second size of the first display area is greater than 2, the first signal line is a gate signal line, the first size of the first display area is the size of the first display area in an extension direction of the gate signal line, and the second size of the first display area is the size of the first display area in an extension direction of a data signal line.

[0015] In one embodiment of the examples of the present disclosure, when a ratio between a first size of the first display area and a second size of the first display area is less than 0.5, the first signal line is a data signal line, the first size of the first display area is the first size of the first display area in the extension direction of a gate signal line, and the second size of the first display area is the size of the first display area in the extension direction of the data signal line.

[0016] In one embodiment of the examples of the present disclosure, when a ratio between a first size of the first display region and a second size of the first display region is 0.5 to 2, the first signal lines include gate signal lines and data signal lines, the first size of the first display region is the size of the first display region in an extension direction of the gate signal lines, and the second size of the first display region is the size of the first display region in an extension direction of the data signal lines.

[0017] In one embodiment of the examples of the present disclosure, the display panel further includes a plurality of second pixel units, the plurality of second pixel units are disposed in the second display area, the plurality of first pixel units and the plurality of second pixel units are arranged to form a plurality of rows of pixel units, the pixel units in two adjacent rows are offset from each other in the arrangement direction of the pixel units in one row, and the pixel units in the two adjacent rows of pixel units are connected via one gate signal line.

[0018] In one embodiment of the present disclosure, the gate signal line is wavy, and the peaks and valleys of the gate signal line are respectively connected to pixel units in two adjacent rows of pixel units.

[0019] In one embodiment of the embodiment of the present disclosure, the data signal line is wavy, and a peak and a valley of the data signal line are respectively connected to two adjacent pixel units in the same column of pixel units.

[0020] In one embodiment of the present disclosure, the metal signal line includes a molybdenum signal line or a titanium signal line.

[0021] In one embodiment of the present disclosure, the metal oxide signal line is a transparent metal oxide signal line.

[0022] In one embodiment of the present disclosure, the metal oxide signal line is an indium tin oxide signal line.

[0023] In another aspect, the present disclosure relates to a method for manufacturing a display panel, the method comprising: a first display region and a second display region located on at least one side of the first display region, the first display region having a light transmittance greater than that of the second display region; and forming a plurality of first pixel units and a plurality of signal lines on the base substrate, the plurality of first pixel units being disposed in the first display region, the plurality of signal lines being disposed at least in the first display region and electrically connected to the plurality of first pixel units, the plurality of signal lines including a plurality of first signal lines and a plurality of second signal lines, a first portion of each first signal line among the plurality of first signal lines being a metal signal line, the first portion of the first signal line being disposed at least in the first display region, and a first portion of each second signal line among the plurality of second signal lines being a metal oxide signal line, the first portion of the second signal line being disposed at least in the first display region.

[0024] In another aspect, the present disclosure relates to a display device including a power supply assembly and a display panel as described above, the power supply assembly for supplying power to the display panel.

[0025] In one embodiment of the present disclosure, the display device further includes a photosensor, the photosensor being disposed on a side of the display panel away from the plurality of first pixel units, and a positive projection of the photosensor onto the base substrate at least partially overlaps with the first display area.

[0026] The beneficial effects of the technical solutions according to the embodiments of the present disclosure at least include the following:

[0027] In the embodiment of the present disclosure, the light transmittance of the first display region is high, and by disposing an optical sensor (e.g., a full-screen camera) in a region corresponding to the first display region, light can be transmitted through the first display region and propagated to the optical sensor. The first portion of the first signal line in the first display region is a metal signal line, and the resistance of metal is smaller than the resistance of metal oxide, so that the resistance of the first signal line can be reduced and the load of the first signal line can be reduced. As a result, the voltage received by the pixel unit in the first display region is increased, and the difference between the voltage received by the pixel unit disposed in the first display region and the voltage received by the pixel unit in other regions is small, and the phenomenon of non-uniform display is improved. At the same time, the first portion of the second signal line is a metal oxide signal line, which ensures the light transmittance of the first display region. [Brief description of the drawings]

[0028] In order to more clearly explain the technical solutions in the embodiments of the present disclosure, the drawings used in the description of the embodiments will be briefly described below. The drawings in the following description are only some embodiments of the present disclosure, and it is obvious to those skilled in the art that other drawings can be obtained based on these drawings without any creative work.

[0029] [Figure 1] FIG. 2 is a schematic plan view of a display panel according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a schematic diagram illustrating the configuration of a display panel according to an embodiment of the present disclosure. [Diagram 3] FIG. 2 is a schematic diagram illustrating the configuration of a display panel according to an embodiment of the present disclosure. [Figure 4] FIG. 3 is a cross-sectional view of the AA plane in FIG. 2. [Diagram 5] FIG. 2 is a schematic diagram illustrating the configuration of a display panel according to an embodiment of the present disclosure. [Figure 6] FIG. 2 is a schematic diagram illustrating the configuration of a display panel according to an embodiment of the present disclosure. [Figure 7] FIG. 2 is a schematic diagram illustrating the configuration of a display panel according to an embodiment of the present disclosure. [Figure 8] FIG. 2 is a schematic diagram illustrating the configuration of a display panel according to an embodiment of the present disclosure. [Figure 9] FIG. 2 is a schematic diagram illustrating the configuration of a display panel according to an embodiment of the present disclosure. [Figure 10] FIG. 2 is a film layer schematic diagram of a pixel according to an embodiment of the present disclosure. [Figure 11] FIG. 2 is a plan view of a first display area according to an embodiment of the present disclosure. [Figure 12] FIG. 13 is a plan view of another first display area according to an embodiment of the present disclosure. [Figure 13] FIG. 2 is a pixel layout diagram of a first display area according to an embodiment of the present disclosure. [Figure 14] FIG. 13 is a plan view of another first display area according to an embodiment of the present disclosure. [Figure 15] FIG. 13 is a plan view of another first display area according to an embodiment of the present disclosure. [Figure 16] FIG. 13 is a plan view of another first display area according to an embodiment of the present disclosure. [Figure 17] FIG. 13 is a plan view of another first display area according to an embodiment of the present disclosure. [Figure 18] FIG. 11 is a pixel layout diagram of another first display area according to an embodiment of the present disclosure. [Figure 19] FIG. 13 is a plan view of another first display area according to an embodiment of the present disclosure. [Figure 20]FIG. 13 is a plan view of another first display area according to an embodiment of the present disclosure. [Figure 21] FIG. 13 is a plan view of another first display area according to an embodiment of the present disclosure. [Figure 22] FIG. 13 is a plan view of another first display area according to an embodiment of the present disclosure. [Figure 23] FIG. 11 is a pixel layout diagram of another first display area according to an embodiment of the present disclosure. [Figure 24] FIG. 2 is a schematic diagram illustrating the configuration of a display panel according to an embodiment of the present disclosure. [Diagram 25] FIG. 1 is a circuit diagram of a 7T1C pixel according to an embodiment of the present disclosure. [Figure 26] 4 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 27] 4 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 28] 1A to 1C are process diagrams of a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 29] 1A to 1C are process diagrams of a method for manufacturing a display panel according to an embodiment of the present disclosure. [Diagram 30] 1A to 1C are process diagrams of a method for manufacturing a display panel according to an embodiment of the present disclosure. [Diagram 31] 1A to 1C are process diagrams of a method for manufacturing a display panel according to an embodiment of the present disclosure. [Diagram 32] 1A to 1C are process diagrams of a method for manufacturing a display panel according to an embodiment of the present disclosure. [Diagram 33] 1A to 1C are process diagrams of a method for manufacturing a display panel according to an embodiment of the present disclosure. [Diagram 34] 1A to 1C are process diagrams of a method for manufacturing a display panel according to an embodiment of the present disclosure. [Diagram 35] 1A to 1C are process diagrams of a method for manufacturing a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure are described in more detail below with reference to the drawings.

[0031] In the related art, in order to improve the light transmittance of the camera display area and enable the FDC to receive sufficient light imaging, the signal lines between the pixel units arranged in the camera display area are all transparent metal oxide signal lines, for example, indium tin oxide (ITO) signal lines.

[0032] The resistance of the metal oxide signal line is large, generating a large load, and the voltage received by the pixel unit connected to the metal oxide signal line is smaller than the voltage received by the pixel units in other display areas, resulting in a large difference between the display effect of the camera display area and the display effect of other display areas, resulting in uneven display.

[0033] FIG. 1 is a schematic plan view of a display panel according to an embodiment of the present disclosure. Referring to FIG. 1, the display panel includes a base substrate 10, which has a display area 100 and a peripheral area 200 at least partially surrounding the display area 100. The display area 100 can be used to arrange pixel circuits, and the peripheral area 200 can be used to arrange integrated circuits, which are used to drive the pixel circuits to operate. Exemplarily, the peripheral area 200 at least partially surrounding the display area 100 indicates that the peripheral area 200 can include the display area 100, or that both sides of the display area 100 are in contact with the peripheral area 200, or that the display area 100 is aligned with the peripheral area 200, with one side of the display area 100 being in contact with the peripheral area 200.

[0034] The display area 100 includes a first display area 101 and at least a second display area 102 located on the side of the first display area 101, and the light transmittance of the first display area 101 is greater than that of the second display area 102. Since the light transmittance of the first display area 101 is high, there is no need to perform a hole drilling process on the base substrate 10, and necessary hardware components such as optical sensors can be directly disposed at a position opposite to the first display area 101, thereby realizing a true full-screen display device.

[0035] In FIG. 1, the shape of the first display area 101 is rectangular, in other embodiments, the shape of the first display area 101 may be circular, polygonal, other regular or irregular shapes, and so on.

[0036] For example, the second display area 102 located on at least one side of the first display area 101 indicates that the second display area 102 may surround the first display area 101, or that both sides of the first display area 101 are adjacent to the second display area 102, or that the first display area 101 is aligned with the second display area 102, with one side of the first display area 101 being adjacent to the second display area 102.

[0037] 1, the second display area 102 surrounds the first display area 101. Exemplarily, the first display area 101 is located in the center of the upper area of ​​the base substrate 10.

[0038] In some embodiments, the first display area 101 may be located at other positions on the base substrate 10. For example, referring to FIG. 1, the first display area 101 may be located at the upper left corner or the upper right corner of the base substrate 10.

[0039] 2 is a structural schematic diagram of a display panel according to an embodiment of the present disclosure. Referring to FIG. 2, the display panel further includes a plurality of first pixel units 20 and a plurality of signal lines 30. The plurality of first pixel units 20 are disposed on a base substrate 10 and arranged in a first display area 101. The plurality of signal lines 30 are disposed in at least the first display area 101 and electrically connected to the plurality of first pixel units 20.

[0040] FIG. 3 is a schematic diagram of a display panel according to an embodiment of the present disclosure. Referring to FIG. 3, the signal lines 30 include a plurality of first signal lines 301 and a plurality of second signal lines 302. For example, the first signal line 301 may include a gate signal line and a data signal line, and the second signal line 302 may include a reset signal line. The plurality of first pixel units 20 are arranged to form a plurality of rows of pixel units, and in the arrangement direction of the pixel units in one row, the pixel units in two adjacent rows of pixel units are offset from each other, and the pixel units in the two adjacent rows of pixel units are connected via one first signal line 301 or one second signal line 302. Both the first signal line 301 and the second signal line 302 are wavy.

[0041] A first portion of each of the plurality of first signal lines 301 is a metal signal line, and the first portion of the first signal line 301 is disposed in at least the first display area 101. A first portion of each of the plurality of second signal lines 302 is a metal oxide signal line, and the first portion of the second signal line 302 is disposed in at least the first display area 101.

[0042] In the embodiment of the present disclosure, the light transmittance of the first display region 101 is high, and a light sensor (e.g., a full-screen camera) is disposed in a region corresponding to the first display region 101, so that light can pass through the first display region 101 and propagate to the light sensor. The first portion of the first signal line 301 in the first display region 101 is a metal signal line, and the resistance of metal is smaller than the resistance of metal oxide, so that the resistance of the first signal line 301 can be reduced and the load of the first signal line can be reduced. As a result, the voltage received by the pixel unit 20 in the first display region 101 is increased, and the difference between the voltage received by the pixel unit 20 disposed in the first display region 101 and the voltage received by the pixel unit 20 in other regions is small, and the phenomenon of non-uniform display is improved. At the same time, the first portion of the second signal line 302 is a metal oxide signal line, so that the light transmittance of the first display region 101 is guaranteed.

[0043] At the same time, because the first pixel units 20 in the first display area 101 are regularly arranged and the slits between the pixel units 20 are also regularly arranged, the diffraction phenomenon is likely to occur when the light passes through the slits in the first display area 101, and the light caused by the diffraction phenomenon will further propagate to the full-screen camera, affecting the imaging effect of the full-screen camera. In the embodiment of the present disclosure, the first part of each of the first signal lines 301 among the first signal lines 301 passing through the first display area 101 is arranged as a non-transparent metal signal line, thereby breaking the regular arrangement of the slits between the pixel units 20, improving the diffraction of light, and thus improving the imaging effect of the full-screen camera.

[0044] In an embodiment of the present disclosure, the first signal line 301 further includes a second portion disposed in the second display area 102, and the second signal line 302 further includes a second portion disposed in the second display area 102, and the second portion of the first signal line 301 and the second portion of the second signal line 302 are both metal signal lines.

[0045] In the embodiment of the present disclosure, there is no need to place an optical sensor in the second display region 102, and therefore the second display region 102 does not need to have high light transmittance. By arranging both the first signal line 301 and the second signal line 302 in the second display region 102 as metal signal lines, the load on the first signal line 301 and the second signal line 302 can be reduced, the display brightness of the display panel can be increased, and the display effect can be improved.

[0046] In an embodiment of the present disclosure, the light transmittance of the first display region 101 is ensured by making a first portion of each of the multiple second signal lines 302 a transparent metal oxide signal line so that some of the signal lines 30 in the first display region 101 are transparent signal lines.

[0047] In one embodiment of the embodiment of the present disclosure, the first signal line 301 includes at least one of a gate signal line and a data signal line.

[0048] Each first pixel unit 20 includes a switch transistor and a driving transistor, the gate signal line supplies an on-voltage to the gate of the switch transistor, and the data signal line supplies an on-voltage to the gate of the driving transistor. The resistance of the transparent metal oxide signal line is large, and the on-voltage is small when the transparent metal oxide signal line is used, so that the switch thin film transistor cannot be turned on or the time until the switch thin film transistor is turned on is short, resulting in a luminance mismatch compared with the area using the metal signal line, which affects the display uniformity of the display panel. In the embodiment of the present disclosure, at least one of the gate signal line and the data signal line in the first display area 101 is replaced with a metal signal line, thereby reducing the resistance of the gate signal line or the data signal line, increasing the on-voltage of the first pixel unit 20 arranged in the first display area 101, and improving the display uniformity.

[0049] For example, the metal oxide signal line may be an indium tin oxide signal line, and the transparency of indium tin oxide is good, which ensures the transparency of the metal oxide signal line.

[0050] Referring again to FIG. 2, the display panel further includes a plurality of second pixel units 40, the plurality of second pixel units 40 being disposed in the second display area 102, and the plurality of second pixel units 40 and the plurality of first pixel units 20 being arranged to form a plurality of rows of pixel units.

[0051] Since the first pixel unit 20 and the second pixel unit 40 have poor light transmittance, in order to increase the light transmittance of the first display region 101, the size of the first pixel unit 20 is made smaller than the size of the second pixel unit 40 during fabrication, thereby increasing the light transmittance of the first display region 101.

[0052] In one embodiment of the embodiment of the present disclosure, the signal lines 30 further include a reset (Reset) signal line, an emission control (EM) signal line, an initial voltage (Vinit) signal line, and a power supply (VDD) signal line. All of the signal lines 30 except the first signal line 301 are second signal lines 302, that is, the reset signal line, the emission control signal line, the initial voltage signal line, and the power supply signal line are all second signal lines 302.

[0053] Metal signal lines have low resistance but poor light transmittance, while transparent metal oxide signal lines have high resistance but high light transmittance. Since the optical sensor is disposed in an area corresponding to the first display region 101 in the display device, it is necessary to reduce the resistance of the signal lines in the first display region 101 and ensure the light transmittance of the first display region 101. Experimental simulations have shown that signal lines such as a reset signal line, a light emission control signal line, an initial voltage signal line, and a power supply signal line have little effect on the display brightness, and by disposing these signal lines as transparent metal oxide signal lines, the light transmittance of the first display region 101 can be ensured.

[0054] In one embodiment of the present disclosure, the first signal line 301 includes a gate signal line and a data signal line, and the second signal line 302 includes a reset signal line, a light emission control signal line, an initial voltage signal line, and a power supply signal line.

[0055] In one embodiment of the present disclosure, the gate signal lines include molybdenum signal lines, and the data signal lines include titanium signal lines.

[0056] In the related art, the material of the first portion of the first signal line passing through the first display area is a metal oxide, whereas in the embodiment of the present disclosure, the material of the first portion of the first signal line passing through the first display area is a metal, so that the first signal line passing through the first display area and the first signal line not passing through the first display area can be fabricated in the same manner, i.e., the entire signal line is in the same layer.

[0057] Fig. 4 is a schematic cross-sectional view of the AA plane of Fig. 2. Referring to Fig. 4, the display panel includes a first metal layer 201, a first insulating layer 202, and a metal oxide layer 203 sequentially arranged on the base substrate 10 along a direction away from the base substrate 10, a first signal line 301 (not shown in Fig. 4) is arranged on the first metal layer 201, a first portion of at least one second signal line 302 in the first display region 101 is arranged on the metal oxide layer 203, and a second portion in the second display region 102 is arranged on the first metal layer 201, and the first and second portions of the second signal line 302 are connected via a first via 221 penetrating the first insulating layer 202, and the first via 221 is located at the boundary between the first display region 101 and the second display region 102. Here, the boundary between the first display area 101 and the second display area 102 refers to an area where the boundary where the first display area 101 and the second display area 102 are connected is located. At least one second signal line 302 among the multiple second signal lines 302 may be one second signal line 302, multiple second signal lines 302, or all of the second signal lines 302.

[0058] In the embodiment of the present disclosure, the first signal line 301 is a metal signal line and is disposed on the first metal layer 201, the second signal line 302 is a transparent metal oxide signal line in the first display area 101 and a metal line in the second display area 102, and the second signal line 302 in the first display area 101 is disposed on the metal oxide layer 203 to ensure the light transmittance of the first part of the second signal line 302. The second signal line 302 in the second display area 102 is disposed on the first metal layer 201 to reduce the resistance of the second part of the second signal line 302. At the same time, the first and second parts of the second signal line 302 are connected through the first via 221, and the effectiveness of the electrical connection is guaranteed.

[0059] In an embodiment of the present disclosure, the first metal layer 201 includes a first gate metal layer and a first source-drain metal layer, and the first insulating layer 202 includes a first passivation layer and an interlayer dielectric layer.

[0060] Exemplarily, the first signal line 301 includes one of a gate signal line and a data signal line, and the second signal line 302 includes the other of a gate signal line and a data signal line. For example, the first signal line 301 is a gate signal line, the second signal line 302 is a data signal line, and the gate signal line is disposed on the first gate metal layer 211, the data signal line in the first display area 101 is disposed on the metal oxide layer 203, and the data signal line in the second display area 102 is disposed on the first source-drain metal layer 212.

[0061] 5 is a schematic diagram of a display panel according to an embodiment of the present disclosure. Here, FIG. 4 and FIG. 5 are cross-sectional views of different cross sections, and referring to FIG. 5, the display panel includes a first gate metal layer 211, a first passivation layer 222, a first source-drain metal layer 212, an interlayer dielectric layer 223, and a metal oxide layer 203, which are sequentially arranged on the base substrate 10 along a direction away from the base substrate 10. In this case, the display panel includes only one gate metal layer and one source-drain metal layer, the first metal layer 201 includes the first gate metal layer 211 and the first source-drain metal layer 212, and the first insulating layer 202 includes the first passivation layer 222 and the interlayer dielectric layer 223. The first signal lines 301 include both gate signal lines and data signal lines, and in both the first display area 101 and the second display area 102, the gate signal lines are disposed in the first gate metal layer 211, and in both the first display area 101 and the second display area 102, the data signal lines are disposed in the first source-drain metal layer 212. Only the first signal lines 301 are shown in FIG.

[0062] 6 is a schematic diagram of a display panel according to an embodiment of the present disclosure. Referring to FIG. 6, the display panel includes a first gate metal layer 211, a first passivation layer 222, a first source-drain metal layer 212, an interlayer dielectric layer 223, and a metal oxide layer 203, and the first gate metal layer 211, the first passivation layer 222, the first source-drain metal layer 212, the interlayer dielectric layer 223, and the metal oxide layer 203 are sequentially stacked along a direction away from the base substrate 10.

[0063] Exemplarily, the second signal line 302 includes an initial voltage signal line. In the first display area 101, the second signal line 302 is disposed on the metal oxide layer 203, and in the second display area 102, the second signal line 302 is disposed on the first gate metal layer 211. Only the second signal line 302 is shown in FIG. 6 .

[0064] Exemplarily, the second signal line 302 further includes a reset signal line and a light emission control signal line. In the second display region 102, the reset signal line and the light emission control signal line are disposed in the first gate metal layer 211, and in the first display region 101, the reset signal line and the light emission control signal line are disposed in the metal oxide layer 203. The reset signal line disposed in the first display region 101 and the reset signal line disposed in the second display region 102 are electrically connected through a first via 221, and the light emission control signal line disposed in the first display region 101 and the light emission control signal line disposed in the second display region 102 are electrically connected through the first via 221, in which case the first via 221 penetrates the first passivation layer 222, the first source-drain metal layer 212, and the interlayer dielectric layer 223.

[0065] FIG. 7 is a schematic diagram of a display panel according to an embodiment of the present disclosure. Referring to FIG. 7, the display panel includes a first gate metal layer 211, a first passivation layer 222, a first source-drain metal layer 212, an interlayer dielectric layer 223, and a metal oxide layer 203 arranged on a base substrate 10. In this case, the second signal line 302 includes a power signal line. In the first display area 101, the second signal line 302 is arranged on the metal oxide layer 203, and in the second display area 102, the second signal line 302 is arranged on the first source-drain metal layer 212. Only the second signal line 302 is shown in FIG. 7.

[0066] 7, the second signal line 302 is a power signal line, and in the second display region 102, the power signal line is disposed in the first source-drain metal layer 212, and in the first display region 101, the power signal line is disposed in the metal oxide layer 203. The power signal line disposed in the first display region 101 and the power signal line disposed in the second display region 102 are electrically connected through a first via 221, in this case the first via 221 penetrates the interlayer dielectric layer 223. In other embodiments, the power signal line may be disposed in the second source-drain metal layer.

[0067] 8 is a schematic diagram of a display panel according to an embodiment of the present disclosure. Referring to FIG. 8, compared with FIG. 4, the display panel further includes a second insulating layer 204 and a second metal layer 205, and the second insulating layer 204 is disposed between the first metal layer 201 and the second metal layer 205. A first portion of the second signal line 302 of another part of the plurality of second signal lines 302 in the first display area 101 is disposed in the metal oxide layer 203, and a second portion of the second signal line 302 in the second display area 102 is disposed in the second metal layer 205, and the first and second portions of the second signal line 302 are connected through a second via 241 penetrating the first insulating layer 202 and the second insulating layer 204, and the second via 241 is located at the boundary between the first display area 101 and the second display area 102.

[0068] In one embodiment of the present disclosure, the second metal layer 205 is a second gate metal layer and the second insulating layer 204 is a first gate insulating layer.

[0069] Exemplarily, the second signal line 302 further includes a reset signal line, a light emission control signal line, an initial voltage signal line, and a power supply signal line, and in the first display area 101, the reset signal line, the light emission control signal line, the initial voltage signal line, and the power supply signal line are arranged in the metal oxide layer 203, and in the second display area 102, the reset signal line, the light emission control signal line, the initial voltage signal line, and the power supply signal line are arranged in the second gate metal layer.

[0070] In one embodiment of the present disclosure, the second metal layer 205 is a second gate metal layer and the second insulating layer 204 is a first gate insulating layer.

[0071] 9 is a schematic diagram of a display panel according to an embodiment of the present disclosure. Compared with FIG. 8, FIG. 9 shows that the display panel includes a second gate metal layer 251, a first gate insulating layer 242, a first gate metal layer 211, a first passivation layer 222, a first source-drain metal layer 212, an interlayer dielectric layer 223, and a metal oxide layer 203, which are sequentially arranged on the base substrate 10 along a direction away from the base substrate 10.

[0072] 9 again, the second signal line 302 is an initial voltage signal line, and in the second display area 102, the initial voltage signal line is disposed in the second gate metal layer 251, and in the first display area 101, the initial voltage signal line is disposed in the metal oxide layer 203. A part of the initial voltage signal line disposed in the first display area 101 and a part of the initial voltage signal line disposed in the second display area 102 are electrically connected through a second via 241, in this case, the second via 241 penetrates the first gate insulating layer 242, the first gate metal layer 211, the first passivation layer 222, the first source-drain metal layer 212, and the interlayer dielectric layer 223.

[0073] The gate signal lines are disposed in the first gate metal layer 211 , and the data signal lines are disposed in the first source-drain metal layer 212 .

[0074] 9, the display panel further includes an active layer 206, a second gate insulating layer 207, a second passivation layer 208, and a second source-drain metal layer 209. The second gate insulating layer 207 is disposed between the active layer 206 and the second gate metal layer 251, and the second passivation layer 208 is disposed between the metal oxide layer 203 and the second source-drain metal layer 209.

[0075] Here, the active layer 206 may be a polycrystalline silicon material layer, and is abbreviated as Poly layer. A second gate insulating layer 207 separates the active layer 206 from a second gate metal layer 251. A second source-drain metal layer 209 is a line transfer layer, and a second passivation layer 208 separates the first source-drain metal layer 212 from the second source-drain metal layer 209.

[0076] In the embodiment of the present disclosure, the first gate metal layer 211 and the second gate metal layer 251 include molybdenum layers, and the first source-drain metal layer 212 and the second source-drain metal layer 209 include titanium layers. The second gate insulating layer 207, the first gate insulating layer 242, the interlayer dielectric layer 223, the first passivation layer 222, and the second passivation layer 208 may be either a silicon nitride layer, a silicon oxide layer, or an epoxy resin layer.

[0077] In the embodiment of the present disclosure, the base substrate 10 may be a glass substrate or a polyimide substrate.

[0078] Above, Figures 4 to 9 show some of the film layers of the display panel. Below, with reference to Figure 10, a relatively complete film layer structure of the display panel will be described, and the film layer structure of Figure 10 corresponds to the structure of the first pixel unit 20 in the above-mentioned Figure 2.

[0079] 10 is a schematic diagram of a film layer of a pixel according to an embodiment of the present disclosure. Referring to FIG. 10, the display panel includes a buffer layer 2010, an active layer 206, a second gate insulating layer 207, a second gate metal layer 251, a first gate insulating layer 242, a first gate metal layer 211, an interlayer dielectric layer 223, a first source-drain metal layer 212, a second passivation layer 208, a planarization layer 2011, an anode layer 2012, a pixel definition layer 2013, a spacer layer 2014, a light-emitting layer 2015, a cathode layer 2016, a first inorganic packaging layer 2017, an organic packaging layer 2018, and a second inorganic packaging layer 2019, which are sequentially arranged on the base substrate 10 along a direction away from the base substrate 10. In this case, the display panel includes only one source-drain metal layer, i.e., only the first source-drain metal layer 212.

[0080] The buffer layer 2010 is disposed between the base substrate 10 and the active layer 206, and the buffer layer 2010 is used to reduce the influence on the base substrate 10 when the active layer 206 is etched.

[0081] The planarization layer 2011 is disposed on the side of the second passivation layer 208 away from the first source-drain metal layer 212, and the planarization layer 2011 is used to make the surface of the display panel on which the first source-drain metal layer 212 is fabricated more planar.

[0082] The anode layer 2012 is disposed on the side of the planarization layer 2011 away from the first source-drain metal layer 212, and the anode layer 2012 is electrically connected to the first source-drain metal layer 212. The pixel definition layer 2013 is disposed on the side of the anode layer 2012 away from the first source-drain metal layer 212, and the pixel definition layer 2013 has an opening, which communicates with the anode layer 2012, and the light-emitting layer 2015 is located in the opening. The spacer layer 2014 can be used to support a mask plate when depositing the light-emitting layer 2015. The cathode layer 2016 is disposed on the side of the light-emitting layer 2015 away from the first source-drain metal layer 212, and a voltage is formed between the cathode layer 2016 and the anode layer 2012 to control the light-emitting layer 2015 to emit light. The first inorganic packaging layer 2017, the organic packaging layer 2018, and the second inorganic packaging layer 2019 together constitute a packaging layer, which packages the display panel and ensures its integrity.

[0083] In an embodiment of the present disclosure, the pixel unit includes a capacitor 60, and referring again to FIG. 10 , a first plate 601 of the capacitor 60 is disposed on the second gate metal layer 251, and a second plate 602 of the capacitor is disposed on the first gate metal layer 211.

[0084] 10, the second gate insulating layer 207, the second gate metal layer 251, the first gate insulating layer 242, and the first gate metal layer 211 are sequentially arranged along a direction away from the base substrate 10. In other embodiments, the second gate insulating layer 207, the first gate metal layer 211, the first gate insulating layer 242, and the second gate metal layer 251 may be sequentially arranged, and the present disclosure is not limited thereto.

[0085] 11 is a plan view of a first display area according to an embodiment of the present disclosure. Referring to FIG. 11, the first display area 101 is elongated, a first size L1 of the first display area 101 is larger than a second size L2 of the first display area 101, the first size L1 of the first display area 101 is the size of the first display area 101 in the extension direction of the gate signal lines, and the second size L2 of the first display area 101 is the size of the first display area 101 in the extension direction of the data signal lines. The display device includes a plurality of light sensors 50, and the orthogonal projection of the plurality of light sensors 50 onto the display panel is in the first display area 101, and the extension direction of the plurality of light sensors 50 is parallel to the extension direction of the gate signal lines.

[0086] In FIG. 11, three optical sensors 50 are arranged in an area corresponding to a first display area 101 in the display device.

[0087] 12 is a plan view of another first display area according to an embodiment of the present disclosure. Referring to FIG. 12, the display device includes four light sensors 50. The four light sensors 50 are divided into two groups, one group includes two light sensors 50, the distance between two light sensors 50 in the same group is 0, and there is a certain gap between two adjacent groups.

[0088] In other embodiments, other numbers of photosensors 50 may be disposed within the display device, and this disclosure is not limited thereto.

[0089] For the first display area 101 shown in FIGS. 11 and 12, the ratio between the first size L1 of the first display area 101 and the second size of the first display area 101 is greater than two.

[0090] 13 is a pixel layout diagram of the first display area according to an embodiment of the present disclosure. With reference to Fig. 11 to Fig. 13, when the ratio between the first size L1 of the first display area 101 and the second size of the first display area 101 is greater than 2, the first signal line 301 is a gate signal line.

[0091] The gate signal line is electrically connected to a plurality of first pixel units 20. When a load is applied to the gate signal line, the gate voltage received by the first pixel unit 20 closer to the driving circuit becomes larger, and the gate voltage received by the first pixel unit 20 farther from the driving circuit becomes smaller. When the ratio of the first size L1 of the first display area 101 to the second size L2 of the first display area 101 is larger than 2, it means that the length of the gate signal line in the first display area 101 is larger than the length of the data signal line in the first display area 101. On the other hand, when the length of the signal line and the resistance of the resistive signal line are negatively correlated, the display non-uniformity phenomenon caused by the gate signal line becomes more prominent in the first display area 101. By arranging the gate signal line as a metal signal line, the display non-uniformity phenomenon caused by the gate signal line can be reduced and the display non-uniformity phenomenon can be improved.

[0092] In FIGS. 11 to 13, the first display area 101 extends along an extension direction of the first size L1, but in other embodiments it may also extend along other directions.

[0093] 14 is a plan view of another first display area according to an embodiment of the present disclosure. Referring to FIG. 14, the first display area 101 is also elongated, the first size L1 of the first display area 101 is smaller than the second size L2 of the first display area 101, and a plurality of optical sensors 50 are arranged in the first display area 101, and the extension direction of the plurality of optical sensors 50 is the extension direction of the second size L2.

[0094] In Fig. 14, the display device includes two light sensors 50. Fig. 15 is a plan view of another first display area according to an embodiment of the present disclosure. Referring to Fig. 15, the display device includes four light sensors 50. The four light sensors 50 are divided into two groups, one group includes two light sensors 50, the distance between two light sensors 50 in the same group is 0, and there is a certain gap between two adjacent groups.

[0095] 16 is a plan view of another first display area according to an embodiment of the present disclosure. Referring to FIG. 16, the display device includes four light sensors 50, and the distance between two adjacent light sensors 50 is zero.

[0096] 17 is a plan view of another first display area according to an embodiment of the present disclosure. Referring to FIG. 17, the display device includes three light sensors 50, and the distance between two adjacent light sensors 50 is 0.

[0097] In other embodiments, other numbers of photosensors 50 may be disposed within the display device, and this disclosure is not limited thereto.

[0098] For the first display region 101 shown in Figures 14 to 17, the ratio between the first size L1 of the first display region 101 and the second size L2 of the first display region 101 is less than 0.5. Figure 18 is a pixel layout diagram of another first display region according to an embodiment of the present disclosure. With reference to Figures 14 to 18, when the ratio between the first size L1 of the first display region 101 and the second size L2 of the first display region 101 is less than 0.5, the first signal line 301 is a data signal line.

[0099] The data signal line is the same as the gate signal line, and the data voltage received by the first pixel unit 20 closer to the driving circuit is larger, and the data voltage received by the first pixel unit 20 farther from the driving circuit is smaller. If the ratio of the first size L1 of the first display area 101 to the second size L2 of the first display area 101 is less than 0.5, it means that the length of the data signal line in the first display area 101 is larger than the length of the gate signal line in the first display area 101. In the first display area 101, the uneven display phenomenon caused by the data signal line is more prominent. By arranging the data signal line as a metal signal line, the uneven display phenomenon caused by the data signal line can be reduced and the uneven display phenomenon can be improved.

[0100] 11 to 18, the first display area 101 is elongated. In other embodiments, the first display area 101 may be block-shaped.

[0101] 19 is a plan view of another first display area according to an embodiment of the present disclosure. Referring to FIG. 19, the first display area 101 is block-shaped, the difference between the first size L1 of the first display area 101 and the second size L2 of the first display area 101 is not large, and three optical sensors 50 are arranged in the first display area 101, and the three optical sensors 50 are arranged in a triangle.

[0102] In Fig. 19, the display device includes three light sensors 50. Fig. 20 is a plan view of another first display area according to an embodiment of the present disclosure. Referring to Fig. 20, the display device includes four light sensors 50, and the four light sensors 50 are arranged in a square.

[0103] 21 is a plan view of another first display area according to an embodiment of the present disclosure. Referring to FIG. 21, the display device includes five light sensors 50, and the five light sensors 50 are arranged in a pentagon.

[0104] 22 is a plan view of another first display area according to an embodiment of the present disclosure. Referring to FIG. 22, the display device includes six light sensors 50, and the six light sensors 50 are arranged in a hexagon.

[0105] In other embodiments, other numbers of photosensors 50 may be disposed within the display device, and this disclosure is not limited thereto.

[0106] 19 to 22, the ratio between the first size L1 of the first display region 101 and the second size L2 of the first display region 101 is 0.5 to 2. FIG. 23 is a pixel layout diagram of another first display region according to an embodiment of the present disclosure. With reference to FIGS. 19 to 23, when the ratio between the first size L1 of the first display region 101 and the second size L2 of the first display region 101 is 0.5 to 2, the first signal line 301 includes a gate signal line and a data signal line.

[0107] When the ratio of the first size L1 of the first display region 101 to the second size L2 of the first display region 101 is 0.5 to 2, it means that in the first display region 101, the difference between the length of the gate signal lines and the length of the data signal lines is not large, and the difference between the non-uniform display phenomenon caused by the gate signal lines and the non-uniform display phenomenon caused by the data signal lines is also not large, and the non-uniform display phenomenon caused by the data signal lines becomes more noticeable in the first display region 101. By arranging the gate signal lines and the data signal lines as metal signal lines, it is possible to simultaneously reduce the non-uniform display phenomenon caused by the gate signal lines and the non-uniform display phenomenon caused by the data signal lines, and improve the non-uniform display phenomenon.

[0108] Fig. 24 is a schematic diagram of a display panel according to an embodiment of the present disclosure. Referring to Fig. 24, the display panel includes a plurality of first pixel units 20 and a plurality of second pixel units 40. The plurality of first pixel units 20 and the plurality of second pixel units 40 are arranged to form a plurality of rows of pixel units, and in the arrangement direction of the pixel units in one row, the pixel units in the pixel units in two adjacent rows are shifted from each other, and the pixel units in the pixel units in the two adjacent rows are connected via one gate signal line.

[0109] By staggering the pixel units in multiple columns, more pixel units can be arranged in the same area, and the density of the pixel units can be increased, thereby improving the resolution of the display panel and further enhancing the display effect. At the same time, the pixel units in two adjacent rows are connected by gate signal lines, which avoids complex wiring and simplifies the circuit structure.

[0110] 3 and 24, the gate signal line is wavy, and the peaks and valleys of the gate signal line are connected to the first pixel unit 20 or the second pixel unit 40 respectively.

[0111] Referring again to FIG. 3 and FIG. 24, the data signal lines are similarly wavy.

[0112] In the embodiment of the present disclosure, the first pixel unit 20 and the second pixel unit 40 both include a 7T1C pixel circuit.

[0113] 25 is a circuit diagram of a 7T1C pixel according to an embodiment of the present disclosure. Referring to FIG. 25, the pixel circuit includes a first switch transistor T1, a first compensation transistor T2, a first reset transistor T3, a second reset transistor T4, a driving transistor T5, a first emission control transistor T6, a second emission control transistor T7, and a capacitor Cst.

[0114] A control electrode of the first switch transistor T1 is electrically connected to one gate line via a first scanning signal terminal (Scan[n]), a first electrode of the first switch transistor T1 is electrically connected to one data line via a data input terminal (Date[m]), and a second electrode of the first switch transistor T1 is electrically connected to a first node N1.

[0115] The control electrode of the first compensation transistor T2 is electrically connected to one gate line via a first scanning signal terminal (Scan[n]), the first electrode of the first compensation transistor T2 is electrically connected to a second node N2, and the second electrode of the first compensation transistor T2 is electrically connected to a third node N3.

[0116] The control electrode of the first reset transistor T3 is electrically connected to another gate line via a second scanning signal terminal (Scan[n-1]), the first electrode of the first reset transistor T3 is electrically connected to an initial voltage signal line via an initialization voltage terminal (Vinit), and the second electrode of the first reset transistor T3 is electrically connected to a third node N3.

[0117] The control electrode of the second reset transistor T4 is electrically connected to one gate line via a first scanning signal terminal (Scan[n]), the first electrode of the second reset transistor T4 is electrically connected to an initial voltage signal line via an initialization voltage terminal (Vinit), and the second electrode of the second reset transistor T4 is electrically connected to a fourth node N4.

[0118] The control pole of the driving transistor T5 is electrically connected to the third node N3, the first pole of the driving transistor T5 is electrically connected to the first node N1, and the second pole of the driving transistor T5 is electrically connected to the second node N2.

[0119] A control electrode of the first light emission control transistor T6 is electrically connected to the light emission control signal line via a light emission control signal terminal (EM[n]), a first electrode of the first light emission control transistor T6 is electrically connected to a first node N1, and a second electrode of the first light emission control transistor T6 is electrically connected to a fifth node N5. The fifth node N5 is electrically connected to the power supply signal line via a first voltage signal terminal (ELVDD).

[0120] The control electrode of the second light-emitting control transistor T7 is electrically connected to the light-emitting control signal line via the light-emitting control signal terminal (EM[n]), the first electrode of the second light-emitting control transistor T7 is electrically connected to the second node N2, and the second electrode of the second light-emitting control transistor T7 is electrically connected to the fourth node N4.

[0121] A first plate of the capacitor Cst is electrically connected to a fifth node N5, and a second plate of the capacitor Cst is electrically connected to a third node N3.

[0122] Referring again to FIG. 25, the pixel circuit further includes a light emitting diode LED, and the fourth node N4 is electrically connected to one end of the light emitting diode LED, and one end of the light emitting diode LED is electrically connected to the second voltage signal terminal (ELVSS).

[0123] The 7T1C pixel circuit of the embodiments of the present disclosure is just one example, and in other embodiments, the pixel circuit may have other configurations, for example, the pixel circuit is a 2T1C pixel circuit.

[0124] 26 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present disclosure, where the display panel has a first display area that transmits light, and referring to FIG. 26, the method for manufacturing includes the following steps:

[0125] In step S401, a base substrate is prepared.

[0126] Here, the base substrate has a display area and a peripheral area at least partially surrounding the display area, the display area includes a first display area and a second display area located on at least one side of the first display area, and the light transmittance of the first display area is greater than the light transmittance of the second display area.

[0127] In the embodiments of the present disclosure, the base substrate may be a glass substrate or a polyimide substrate.

[0128] In step S402, a plurality of first pixel units and a plurality of signal lines are formed on a base substrate.

[0129] Here, the multiple first pixel units are arranged in the first display area, the multiple signal lines are arranged at least in the first display area and electrically connected to the multiple first pixel units, the multiple signal lines include multiple first signal lines and multiple second signal lines, a first portion of each first signal line among the multiple first signal lines is a metal signal line, the first portion of the first signal line is arranged at least in the first display area, and a first portion of each second signal line among the multiple second signal lines is a metal oxide signal line, the first portion of the second signal line is arranged at least in the first display area.

[0130] Exemplarily, step S402 may include the following steps:

[0131] 27 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present disclosure. Referring to FIG. 27, the method includes the following steps:

[0132] In S421, an active layer is formed on one side of a base substrate.

[0133] Exemplarily, the active layer may be a polycrystalline silicon layer. FIG. 28 is a process diagram of a method for manufacturing a display panel according to an embodiment of the present disclosure. Referring to FIG. 28, an active film is formed on one side of a base substrate by deposition, and then the active film is graphically patterned by a patterning process to obtain an active layer 206 shown in FIG. 28. Note that the active layer 206 includes active patterns corresponding to a plurality of pixel units, and as shown in FIG. 28, the center is a complete active pattern, and the four corners are parts of the other four active patterns. In FIGS. 29 to 35, similar to FIG. 28, the center is a pattern of a pixel unit, and the four corners are parts of the other pixel units. Here, the display panel shown in FIGS. 28 to 35 is disposed in a first display area.

[0134] In S422, a second gate insulating layer is formed on the side of the active layer remote from the base substrate.

[0135] Exemplarily, the second gate insulating layer may be a silicon nitride layer, and the second gate insulating layer can be formed on one side of the active layer by deposition, and the second gate insulating layer covers the active layer.

[0136] In S423, a first gate metal layer is formed on the side of the second gate insulating layer remote from the base substrate.

[0137] 29 is a process diagram of a method for manufacturing a display panel according to an embodiment of the present disclosure. Referring to FIG. 29, a first gate metal layer 211 is formed on a second gate insulating layer. In a first display area, the first gate metal layer includes a second electrode 602 of a capacitor, a control electrode G of a thin film transistor, and a gate signal line Gate.

[0138] In an embodiment of the present disclosure, in the first display area and the second display area, the gate signal line Gate is arranged on a first gate metal layer, and in the second display area, the reset signal line and the first portion of the emission control signal line are arranged on the first gate metal layer.

[0139] Exemplarily, the first gate metal layer may be a molybdenum layer, and the first gate metal layer can be obtained by forming a first gate metal thin film on one side of the first gate insulating layer by sputtering, and then graphically patterning the first gate metal thin film by a patterning process.

[0140] In S424, a first gate insulating layer is formed on the side of the first gate metal layer remote from the base substrate.

[0141] Exemplarily, the first gate insulating layer may be a silicon nitride layer, and the first gate insulating layer may be formed on one side of the second gate metal layer by deposition, and the first gate insulating layer covers the second gate metal layer.

[0142] In S425, a second gate metal layer is formed on the side of the first gate insulating layer away from the base substrate.

[0143] Exemplarily, the second gate metal layer may be a molybdenum layer. Figure 30 is a process diagram of a method for manufacturing a display panel according to an embodiment of the present disclosure. Referring to Figure 30, a second gate metal thin film is formed on one side of a first gate insulating layer by sputtering, and then the second gate metal thin film is graphically patterned to obtain a second gate metal layer 251. In the first display area, the second gate metal layer 251 includes a first plate 601 of a capacitor.

[0144] In S426, a first passivation layer is formed on the side of the second gate metal layer away from the base substrate.

[0145] Exemplarily, the first passivation layer may be a silicon nitride layer, and the first passivation layer may be formed on one side of the second gate metal layer by evaporation.

[0146] 31 is a process diagram of a method for manufacturing a display panel according to an embodiment of the present disclosure. Referring to FIG 31, a first via 221 is formed in a first passivation layer.

[0147] Illustratively, the first via 221 may be formed by etching.

[0148] In S427, a first source-drain metal layer is formed on the side of the first passivation layer remote from the base substrate.

[0149] 32 is a process diagram of a method for manufacturing a display panel according to an embodiment of the present disclosure. Referring to FIG. 32, a first source-drain metal thin film is formed on one side of a first passivation layer by sputtering, and then the first source-drain metal thin film is patterned to obtain a first source-drain metal layer 212.

[0150] In the embodiment of the present disclosure, the data signal line Date is disposed in the first source-drain metal layer.

[0151] In S428, an interlevel dielectric layer is formed on a side of the first source-drain metal layer remote from the base substrate.

[0152] Illustratively, the interlevel dielectric layer may be a silicon nitride layer, and the interlevel dielectric layer may be formed on one side of the metal oxide layer by vapor deposition.

[0153] In S429, a metal oxide layer is formed on the side of the interlevel dielectric layer away from the base substrate.

[0154] 33 is a process diagram of a method for manufacturing a display panel according to an embodiment of the present disclosure. Referring to FIG. 33, a metal oxide thin film is formed on one side of an interlayer dielectric layer by sputtering, and then a metal oxide layer 203 can be obtained by graphically patterning the metal oxide thin film through a patterning process.

[0155] In an embodiment of the present disclosure, in the first display area, the reset signal line Reset, the emission control signal line EM, and the second portion of the initial voltage signal line Vinit are all arranged in the metal oxide layer 203, and the first portion of the power supply signal line VDD is arranged in the metal oxide layer.

[0156] Here, the first and second parts of the reset signal line are electrically connected via a first via, the first and second parts of the light emission control signal line are electrically connected via the first via, and the first and second parts of the initial voltage signal line are electrically connected via a second via.

[0157] In S4210, a second passivation layer is formed on the side of the metal oxide layer away from the base substrate.

[0158] Exemplarily, the second passivation layer may be a silicon nitride layer, and the first passivation layer may be formed on one side of the first source-drain metal layer by first source-drain metal layer deposition.

[0159] In S4211, a second source / drain metal layer is formed on the side of the second passivation layer away from the base substrate.

[0160] Exemplarily, the second source-drain metal layer may be a titanium layer. FIG. 34 is a process diagram of a method for manufacturing a display panel according to an embodiment of the present disclosure. Referring to FIG. 34, a second source-drain metal thin film is formed on one side of a second passivation layer by sputtering, and then the second source-drain metal thin film is graphically patterned by a patterning process to obtain a second source-drain metal layer 209. In FIG. 34, the second source-drain metal layer 209 shields the first source-drain metal layer 212. A second portion of a power signal line is disposed in the second source-drain metal layer 209.

[0161] Finally, other film layers of the display panel, such as a planarization layer, a pixel definition layer, a light-emitting layer, and a packaging layer, are formed on the second source-drain metal layer to complete the fabrication of the display panel.

[0162] 35 is a process diagram of a method for manufacturing a display panel according to an embodiment of the present disclosure. Referring to FIG. 35, an anode layer 2012 is formed on the second source-drain metal layer 209.

[0163] In order to clarify the manufacturing process of the metal layer and the metal oxide layer, the manufacturing process diagram of the insulating layer is omitted from the above manufacturing process diagram.

[0164] An embodiment of the present disclosure further provides a display device, which includes a power supply assembly and the above display panel, where the power supply assembly is for supplying power to the display panel.

[0165] In a specific embodiment, the display device according to the embodiment of the present disclosure may be any product or part with a display function, such as a mobile phone, a tablet, a television, a display, a laptop, a digital photo frame, or a navigation system.

[0166] In one embodiment of the present disclosure, the display device further includes a light sensor, the light sensor being disposed on a side of the display panel away from the plurality of first pixel units, and a positive projection of the light sensor onto the base substrate at least partially overlaps with the first display area.

[0167] The above are merely preferred embodiments of the present application, and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of the present disclosure. [Explanation of symbols]

[0168] 100 display area 200 Surrounding Area 10 Base Board 101 First display area 102 Second display area 20 pixel units 30 Signal Line 301 First signal line 302 Second signal line 201 First metal layer 202 First insulating layer 203 Metal oxide layer 221 First Via 211 First gate metal layer 212 First source / drain metal layer 222 First passivation layer 223 Interlayer dielectric layer 204 Second insulating layer 205 Second metal layer 241 Second Via 251 Second gate metal layer 242 First gate insulating layer 206 Active Layer 207 Second gate insulating layer 208 Second Passivation Layer 209 Second source / drain metal layer 2010 Buffer Layer 2011 Planarization layer 2012 Anode layer 2013 Pixel Definition Layer 2014 Spacer layer 2015 Emitting layer 2016 Cathode layer 2017 First inorganic packaging layer 2018 Organic Packaging Layer 2019 The second inorganic packaging layer L1 First size L2 Second size 40 Second pixel unit 50 Light Sensor 60 Capacitor 601 First plate 602 Second plate

Claims

1. a base substrate having a display area and a peripheral area at least partially surrounding the display area, the display area including a first display area and a second display area located at least on one side of the first display area, and a light transmittance of the first display area being greater than a light transmittance of the second display area; a plurality of first pixel units disposed on the base substrate and in the first display area; a plurality of signal lines disposed in at least the first display area and electrically connected to the plurality of first pixel units; Including, the plurality of signal lines include a plurality of first signal lines and a plurality of second signal lines, a first portion of each first signal line among the plurality of first signal lines is a metal signal line, and the first portion of the first signal line is disposed in at least the first display region; and a first portion of each second signal line among the plurality of second signal lines is a metal oxide signal line, and the first portion of the second signal line is disposed in at least the first display region. A display panel characterized by:

2. 2. The display panel according to claim 1, wherein the first signal lines include at least one of a gate signal line, a data signal line, a reset signal line, a light emission control signal line, an initial voltage signal line, and a power supply signal line.

3. 3. The display panel according to claim 2, wherein the first signal lines include gate signal lines and data signal lines.

4. 2. The display panel according to claim 1, wherein the first signal line further includes a second portion disposed in the second display region, the second signal line further includes a second portion disposed in the second display region, and the second portion of the first signal line and the second portion of the second signal line are both metal signal lines.

5. The semiconductor device further includes a first metal layer, a first insulating layer, and a metal oxide layer sequentially disposed on the base substrate along a direction away from the base substrate; the first signal line is disposed on the first metal layer; a first portion of at least one second signal line among the plurality of second signal lines in the first display region is disposed on the metal oxide layer, a second portion of the second signal line in the second display region is disposed on the first metal layer, the first portion and the second portion of the second signal line are connected via a first via that penetrates the first insulating layer, and the first via is located at a boundary between the first display region and the second display region; 5. The display panel according to claim 4, wherein:

6. the first metal layer includes a first gate metal layer and a first source / drain metal layer, and the first insulating layer includes a first passivation layer and an interlayer dielectric layer; the first gate metal layer, the interlayer dielectric layer, the first source / drain metal layer, and the first passivation layer are sequentially stacked along a direction away from the base substrate; 6. The display panel according to claim 5, wherein:

7. The semiconductor device further includes a second insulating layer and a second metal layer, and the second metal layer, the second insulating layer, the first metal layer, the first insulating layer, and the metal oxide layer are sequentially stacked along a direction away from the base substrate; a first portion of another part of the second signal lines in the first display region is disposed in the metal oxide layer, a second portion of the other part of the second signal lines in the second display region is disposed in the second metal layer, the first portion and the second portion of the second signal line are connected via a second via that penetrates the first insulating layer and the second insulating layer, and the second via is located at the boundary between the first display region and the second display region; 6. The display panel according to claim 5, wherein:

8. The display panel according to claim 7 , wherein the second metal layer includes a second gate metal layer, and the second insulating layer includes a first gate insulating layer.

9. 2. The display panel according to claim 1, wherein, when a ratio of a first size of the first display region to a second size of the first display region is greater than 2, the first signal lines are gate signal lines, the first size of the first display region is the size of the first display region in the extension direction of the gate signal lines, and the second size of the first display region is the size of the first display region in the extension direction of the data signal lines.

10. 2. The display panel according to claim 1, wherein, when a ratio between a first size of the first display region and a second size of the first display region is less than 0.5, the first signal lines are data signal lines, the first size of the first display region is the first size of the first display region in the extension direction of gate signal lines, and the second size of the first display region is the size of the first display region in the extension direction of the data signal lines.

11. 2. The display panel according to claim 1, wherein, when a ratio of a first size of the first display region to a second size of the first display region is 0.5 to 2, the first signal lines include gate signal lines and data signal lines, the first size of the first display region is the size of the first display region in the extension direction of the gate signal lines, and the second size of the first display region is the size of the first display region in the extension direction of the data signal lines.

12. the display panel further includes a plurality of second pixel units, the plurality of second pixel units are disposed in the second display area, the plurality of first pixel units and the plurality of second pixel units are arranged to form a plurality of rows of pixel units, and pixel units in two adjacent rows are shifted from each other in an arrangement direction of the pixel units in one row; The pixel units in two adjacent rows are connected via one gate signal line.

2. The display panel according to claim 1, wherein:

13. 13. The display panel according to claim 12, wherein the gate signal lines are wavy, and peaks and valleys of the gate signal lines are respectively connected to pixel units in two adjacent rows of pixel units.

14. 13. The display panel according to claim 12, wherein the data signal lines are wavy, and peaks and valleys of the data signal lines are respectively connected to two adjacent pixel units in the same column of pixel units.

15. 2. The display panel according to claim 1, wherein the metal signal lines include molybdenum signal lines or titanium signal lines.

16. 2. The display panel according to claim 1, wherein the metal oxide signal lines are transparent metal oxide signal lines.

17. 17. The display panel of claim 16, wherein the metal oxide signal lines are indium tin oxide signal lines.

18. preparing a base substrate having a display area and a peripheral area at least partially surrounding the display area, the display area including a first display area and a second display area located at least on one side of the first display area, the first display area having a light transmittance greater than that of the second display area; forming a plurality of first pixel units and a plurality of signal lines on the base substrate; Including, the plurality of first pixel units are disposed in the first display area; a plurality of signal lines are disposed in at least the first display area and electrically connected to the plurality of first pixel units, the plurality of signal lines including a plurality of first signal lines and a plurality of second signal lines, a first portion of each first signal line among the plurality of first signal lines being a metal signal line, the first portion of the first signal line being disposed in at least the first display area; and a first portion of each second signal line among the plurality of second signal lines being a metal oxide signal line, the first portion of the second signal line being disposed in at least the first display area.

10. A display panel manufacturing method comprising:

19. 18. A display device comprising a power supply assembly and a display panel according to any one of claims 1 to 17, the power supply assembly being for supplying power to the display panel.

20. 20. The display device of claim 19, further comprising a photosensor, the photosensor being disposed on a side of the display panel away from the plurality of first pixel units, and a normal projection of the photosensor onto the base substrate at least partially overlapping with the first display area.

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