Address translation circuit and method for performing address translation

Abstract

The address translation circuit is responsive to receiving a first address and an identifier to perform an address translation from a first address to a second address by performing a translation table walk including one or more translation lookups in a plurality of translation tables indexed based on corresponding portions of the first address. The address translation circuit is further configured to perform a metadata table walk to determine metadata specific to the identifier and associated with the address translation. The metadata table walk includes one or more metadata lookups in a plurality of metadata lookup tables, each of the one or more metadata lookups corresponding to one of the one or more translation lookups and indexed based on the same portion of the first address as the translation.

Description

[Technical field]

[0001] The present invention relates to an address translation circuit and method for performing address translation.

[0002] An address translation circuit is provided for performing a translation between the first address and the second address. The translation table walk includes performing a series of translation lookups in a plurality of translation tables indexed based in part on the first address.

[0003] In some configurations, an address translation circuit is provided that, in response to receiving a first address and an identifier, performs an address translation from the first address to a second address by performing a translation table walk including one or more translation lookups in a plurality of translation tables indexed based on corresponding portions of the first address, and a metadata table walk to determine metadata specific to the identifier and associated with the address translation, the metadata table walk including one or more metadata lookups in a plurality of metadata lookup tables, each of the one or more metadata lookups corresponding to one of the one or more translation lookups and indexed based on the same portion of the first address as the translation lookup.

[0004] In some configurations, a method is provided for performing an address translation using an address translation circuit in response to receiving a first address and an identifier, the method including: performing an address translation from the first address to a second address by performing a translation table walk including one or more translation lookups in a plurality of translation tables indexed based on corresponding portions of the first address; and performing a metadata table walk to determine metadata specific to the identifier and associated with the address translation, the metadata table walk including one or more metadata lookups in a plurality of metadata lookup tables, each of the one or more metadata lookups corresponding to one of the one or more translation lookups and indexed based on the same portion of the first address as the translation lookup.

[0005] In some configurations, a computer readable medium is provided for storing computer readable code for producing an address translation circuit of any preceding claim.

[0006] In some configurations, the computer readable medium is a non-transitory computer readable medium. [Brief description of the drawings]

[0007] The present technique will be further described, by way of example only, with reference to embodiments thereof illustrated in the accompanying drawings, in which:

[0008] [Figure 1] 1A-1D are schematic diagrams illustrating data processing apparatus according to various configurations of the present technology; [Diagram 2] 1A-1D are schematic diagrams illustrating address translation circuits according to various configurations of the present technology; [Diagram 3] 1A-1C are schematic diagrams illustrating further details of address translation circuitry in accordance with various configurations of the present technology; [Figure 4a] 4A-4C are schematic diagrams illustrating further details of address translation circuitry in accordance with various configurations of the present technique; [Figure 4b] 4A-4C are schematic diagrams illustrating further details of address translation circuitry in accordance with various configurations of the present technique; [Figure 5a] 1 illustrates an arrangement of a conversion table in a memory according to a typical example of memory management. [Figure 5b] 1 illustrates an arrangement of a conversion table in a memory according to a typical example of memory management. [Figure 5c] 3A-3D illustrate schematic arrangements of translation tables in memory according to various configurations of the present technique; [Figure 6] 1 illustrates a schematic representation of a translation process using address translation circuitry according to various configurations of the present technique; [Figure 7a] 3 illustrates a schematic representation of a translation table hierarchy according to various configurations of the present technique; [Figure 7b] 1 illustrates a schematic of a metadata table hierarchy according to various configurations of the present technique; [Figure 8] 4 illustrates generally how permission metadata is determined from default permission metadata according to various configurations of the present technique; [Figure 9] 3A-3C illustrate schematic layouts of a translation lookaside buffer according to various configurations of the present technique; [Figure 10] 3 illustrates generally a series of steps performed by address translation circuitry according to various configurations of the present technique; [Figure 11] 1A-1D are schematic diagrams illustrating the fabrication of address translation circuits according to various configurations of the present technique;

[0009] In some configurations, an address translation circuit is provided that, in response to receiving a first address and an identifier, performs an address translation from a first address to a second address by performing a translation table walk. The translation table walk includes one or more translation lookups in a plurality of translation tables indexed based on corresponding portions of the first address. Additionally, the address translation circuit is configured, in response to receiving the first address, to perform a metadata table walk to determine metadata specific to the identifier and associated with the address translation. The metadata table walk includes one or more metadata lookups in a plurality of metadata lookup tables, each of the one or more metadata lookups corresponding to one of the one or more translation lookups and indexed based on the same portion of the first address as the translation lookup.

[0010] An address translation circuit is often provided to perform a translation between a first address and a second address. In some systems, a set of first addresses and a corresponding set of second addresses are shared among multiple processes, and the process requesting the translation is identified using an identifier. However, it is often the case that each of the processes has different metadata that is specific to the second address and is typically defined by the final translation table of the translation table walk. In such cases, an address translation circuit is typically provided that performs a different translation table walk depending on the identifier. The inventors have recognized that this approach has several disadvantages. First, a complete set of one or more translation tables is required for each of the multiple processes, doubling the space required to store the translation tables. Second, if the operating system controlling the memory determines that an address translation requires remapping, the remapping must be performed once for each of the different translation tables, resulting in an increased processing burden and increased latency. Thus, a translation table walk is provided to perform both a translation table walk to determine the address translation between the first address and the second address, and a metadata table walk to determine metadata associated with the performed address translation and specific to the identifier. In other words, the metadata is specific to both the identifier and the second address determined as part of the translation table walk. The metadata table walk and the translation table walk are each determined using the first address. In particular, for each of the one or more translation lookups, there is a corresponding metadata lookup, and both the translation lookup and the metadata lookup are indexed using the same portion of the first address. The result of the translation table walk is a pointer to a translation table entry that stores the second address, and the result of the metadata table walk is a pointer to a metadata table that stores the metadata associated with the identifier. In this way, only a single set of one or more translation tables is needed, thereby reducing the processing burden when translation table remapping is required.In some configurations, the metadata tables are distinct from the translation tables, in other words, there is no overlap between the set of tables used as translation tables and the set of tables used as metadata tables.

[0011] The timing at which the translation table walk and the metadata table walk are performed can be defined in various ways. In some configurations, the address translation circuit is configured to perform the translation table walk and the metadata table walk in parallel. In such configurations, at least a portion of the address translation circuit is duplicated so that the address translation circuit can track the translation table walk and the metadata table walk simultaneously. Such a configuration reduces the latency associated with performing the two table walks at the expense of minimal additional circuitry. Alternatively, in some configurations, the address translation circuit is configured to perform the translation table walk and the metadata table walk sequentially, with the translation table walk and the metadata table walk each being performed using the same functional circuitry. In such configurations, only a single circuit is provided for performing the table walks, and the address translation circuit is configured to perform one of the translation table walk and the metadata table walk sequentially before the other of the translation table walk and the metadata table walk. In some configurations, the address translation circuit is configured to perform the translation table walk before the metadata table walk. In such configurations, the second address can be returned so that an access based on the second address can be initiated before the metadata is returned. The result of the access can be used or discarded depending on the returned metadata. This approach has the advantage that data access can be initiated without additional latency that may result from a metadata table walk. In an alternative configuration, the metadata table walk can be performed sequentially first. The address translation circuit is then configured to perform a translation table walk or discard the first address and not perform a translation table walk depending on the result of the metadata table walk. Advantageously, this approach removes the requirement to perform a subset of the translation table walk depending on the result of the metadata table walk. For example, if the metadata is such that an access based on an address translation should not be performed, there is no need to perform a translation table walk.

[0012] The translation table walk and the metadata table walk are each based on one or more lookups in a corresponding number of tables. In some configurations, a single translation table is used for the translation table walk, resulting in a single translation lookup in the translation table walk, and a single metadata table is used for the metadata table walk, resulting in a single metadata lookup in the metadata table walk. However, in some alternative configurations, the one or more translation lookups are multiple sequential translation lookups, and the one or more metadata lookups are multiple sequential metadata lookups. In this way, the translation information stored in the translation table and the metadata stored in the metadata table can be distributed throughout memory, enhancing the ability to dynamically reconfigure the space provided for storing the translation table and the metadata table.

[0013] In some configurations, the address translation circuitry is configured to determine identifier-specific metadata based on data returned from a sequential final metadata lookup of the sequential metadata lookups, the data returned from the sequential final metadata lookup associating a plurality of identifiers with corresponding metadata. The format of the data returned from the sequential final metadata lookup may be defined in various ways. In some configurations, the data returned from the sequential final metadata lookup stores information indicative of the identifiers and the corresponding metadata. In such configurations, the address translation circuitry is configured to perform a lookup using the identifiers in the data returned from the sequential final metadata lookup to determine the corresponding metadata. In other configurations, the returned data stores a known length of metadata associated with each identifier starting at a fixed bit position associated with that identifier. In such configurations, the address translation circuitry is configured to determine the metadata associated with the identifier from the metadata starting at a fixed bit position associated with that identifier.

[0014] In some configurations, the identifier-specific metadata is permission metadata. The permission metadata determines access permissions specific to the identifier to be used when accessing the second address. In some configurations, the permission metadata includes data indicative of at least one of a read permission, a write permission, and an execute permission that defines whether a process having the identifier can perform read access, write access, and execute access to the second address.

[0015] The permission metadata can be determined from the data returned from the sequential final metadata lookup in various ways. In some configurations, the returned data is a set of read, write, and execute permission bits. In such configurations, the permissions are determined entirely from the metadata table walk and are independent of the translation table walk. In an alternative configuration, the address translation circuit is configured to determine default permission metadata from the address translation and, in response to obtaining the data returned from the sequential final metadata lookup, determine the permission metadata by combining the default permission metadata with the data returned from the sequential final metadata lookup. Typically, the translation table stores information indicative of the permission bits. This configuration therefore does not require any modification to the format of the translation table, and therefore the translation table may also be read by legacy configurations.

[0016] The combination of the default permission metadata and the data returned from the sequential final lookup can be defined in various ways. In some configurations, the default permission metadata defines a set of maximum permissions associated with the address translation, and the data returned from the sequential final metadata lookup defines a limit on the set of maximum permissions. In such configurations, the default permissions can be the permissions associated with a more privileged process, and the data returned from the sequential final metadata lookup can define a further limit associated with a less privileged process, for example, that shares the same set of second addresses. In some configurations, the data returned from the sequential final metadata lookup can be of the same format as the default permission data, and the data returned from the sequential final metadata lookup is subtracted from the default permission data to result in a reduced set of permissions. The data returned from the sequential final metadata lookup can be associated with a single permission bit (either read, write, or execute). Alternatively, the data returned from the sequential final metadata lookup can be associated with multiple permissions or all permissions.

[0017] In some alternative configurations, the default permission metadata defines a set of minimum permissions associated with the address translation, and the data returned from the sequential final metadata lookup defines an extension of the set of minimum permissions. In such configurations, the default permissions may be the permissions associated with a less privileged process, and the data returned from the sequential final metadata lookup may define an enhanced set of permissions associated with a more privileged process accessing the same set of second addresses. In some configurations, the data returned from the sequential final metadata lookup may be in the same format as the default permission data, and the data returned from the sequential final metadata lookup is added to the default permission data. The data returned from the sequential final metadata lookup may be associated with a single permission bit (either read, write, or execute). Alternatively, the data returned from the sequential final metadata lookup may be associated with multiple permissions or all permissions.

[0018] The plurality of metadata tables may be defined as a complete set of tables in which a metadata table exists for each of the plurality of translation tables. In such configurations, a complete metadata table walk is always possible. However, in some configurations, metadata tables are provided in which a metadata table exists only if there is a difference in the permission data associated with different identifiers. In such configurations, the address translation circuit is configured to set identifier-specific metadata based on default permission metadata in response to an indication returned from one of the sequential metadata lookups that the remainder of the sequential metadata lookup is undefined. Thus, if the metadata lookup returns an invalid entry, the address translation circuit can still provide permission metadata associated with the second address. By providing an address translation circuit responsive in this manner, the set of metadata tables required is reduced, and as a result, the storage space required for the metadata tables is reduced.

[0019] In some configurations, the address translation circuit is configured to trigger a fault indication in response to determining that the identifier is different from each of the plurality of identifiers. In particular, when the sequentially final metadata translation table stores metadata associated with a subset of the possible identifiers, the address translation circuit determines that the absence of authorization data associated with the identifier is an indication that the process associated with the identifier is a process that is not associated with the second address. Thus, the address translation circuit returns a fault indication without outputting the second address.

[0020] In some configurations, the address translation circuitry includes a translation lookaside buffer for storing address translations between the first address and the second address and corresponding metadata associated with the address translation. The translation lookaside buffer thus acts as a cache for the translations, storing data returned from the translation table walk and data returned from the metadata table walk in association with the first address. The translation lookaside buffer can take a variety of forms. In some configurations, the translation lookaside buffer is a single translation lookaside buffer where the width of each entry is increased to store both the second address and the data returned from the sequential final metadata lookup. In this manner, the translation lookaside buffer can be provided with minimal extra storage. In an alternative configuration, the translation lookaside buffer includes multiple regions, each region associated with a different identifier. This approach requires additional circuitry, but allows a different set of first addresses to be stored for each identifier, thus resulting in a wider coverage of the set of second addresses.

[0021] In some configurations, the identifier is one of a predetermined number of identifiers and the translation lookaside buffer is configured to store, as the corresponding metadata, metadata specific to each of the predetermined number of identifiers. In an alternative configuration, only metadata associated with a subset of the predetermined number of identifiers is stored in the translation lookaside buffer and the address translation circuitry is configured to compare the identifier with tag data stored in the translation lookaside buffer in association with the metadata specific to that identifier.

[0022] The address translation circuitry may be any structure that provides the functionality of address translation. However, in some configurations, the address translation circuitry is configured to perform an address translation in which the first address is an intermediate physical address and the second address is a physical address. The intermediate physical address is, for example, an address that has already been translated by a virtual machine between a virtual address associated with the virtual machine and the intermediate physical address. In such configurations, the address translation is a second state address translation.

[0023] In some configurations, the identifier identifies one virtual machine among multiple virtual machines hosted on the data processing circuit associated with the address translation circuit, the multiple virtual machines sharing the same set of second addresses. The multiple virtual machines sharing the same set of addresses may each have different permissions associated with them. In particular, a more privileged virtual machine may have read, write, and execute access to a set of second addresses that a less privileged virtual machine sharing the same set of second addresses is prohibited from accessing. In such a scenario, the metadata associated with the less privileged virtual machine defines a reduced set of permissions. In particular, the less privileged virtual machine may not be able to read, write, or execute a particular set of second addresses. Using the techniques described herein, the metadata translation table can be configured to define holes in the mapping between the address translation tables that are specific to the less privileged virtual machine. If data stored in the set of second addresses is moved to a different set of second addresses, only the translation table needs to be updated to redefine the mapping. When the translation table is redefined, the metadata table is maintained and the defined holes in the mapping remain.

[0024] In some configurations, the address translation circuitry comprises a storage circuit for storing a base translation table address pointing to a sequentially first translation table of the plurality of translation tables and a base metadata lookup table address pointing to a sequentially first metadata lookup table of the plurality of metadata lookup tables. In configurations where the metadata table walk and the translation table walk are performed in parallel, the storage circuitry comprises a base translation table storage device defining the base translation address and associated with the functional circuit performing the translation table walk. Additionally, the storage circuitry comprises a base metadata storage device defining the base metadata lookup table address and associated with the functional circuit performing the metadata translation table walk. In configurations where a single functional unit is provided for sequentially performing the translation table walk and the metadata table walk, the storage circuitry is provided such that the single functional unit can access the base metadata lookup table address and the base translation table address. In some configurations, the storage circuitry comprises a base translation register for storing the base translation table address and a base metadata register for storing the base metadata lookup table address.

[0025] In some configurations, a computer readable medium is provided that stores computer readable code for the manufacture of address translation circuitry according to any of the above configurations. In some configurations, the computer readable code is used in one or more stages of a semiconductor design and manufacturing process, including an electronic design automation (EDA) stage, to manufacture integrated circuits comprising devices embodying concepts. The computer readable code may additionally or alternatively enable definition, modeling, simulation, verification and / or testing of devices embodying concepts described herein.

[0026] For example, computer readable code for producing a device embodying the concepts described herein can be embodied in code defining a Hardware Description Language (HDL) representation of the concept. For example, the code can define a Register-Transfer-Level (RTL) abstraction of one or more logic circuits to define a device embodying the concept. The code may define an HDL representation of one or more logic circuits embodying the device using intermediate representations such as Verilog, SystemVerilog, Chisel, or Very High-Speed ​​Integrated Circuit Hardware Description Language (VHDL) and FIRRTL. The computer readable code can provide a definition embodying the concept using system level modeling languages ​​such as SystemC and SystemVerilog or other behavioral representations of the concept that can be interpreted by a computer to enable simulation, functional and / or formal verification, and testing of the concept.

[0027] Additionally or alternatively, the computer readable code may define a low level description of an integrated circuit component embodying the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer readable representations of the integrated circuit component may be generated by applying one or more logic synthesis processes to the RTL representation to generate a definition for use in manufacturing a device embodying the invention. Alternatively or additionally, one or more logic synthesis processes may generate a bitstream from the computer readable code that is loaded into a Field Programmable Gate Array (FPGA) to configure the FPGA to embody the concepts described. The FPGA may be deployed for concept validation and testing purposes prior to manufacturing in an integrated circuit, or the FPGA may be deployed directly into a product.

[0028] The computer readable code may include a mixture of code representations for fabrication of a device, including, for example, a mixture of one or more of an RTL representation, a netlist representation, or another computer readable definition used in a semiconductor design and manufacturing process to fabricate a device embodying the invention. Alternatively or additionally, a concept may be defined in a combination of a computer readable definition used in a semiconductor design and manufacturing process to fabricate a device and computer readable code that defines instructions to be executed by the defined device once fabricated.

[0029] Such computer readable code may be disposed on any known transitory computer readable medium (such as wired or wireless transmission of code over a network) or on a non-transitory computer readable medium such as a semiconductor, magnetic disk, or optical disk. Integrated circuits manufactured using the computer readable code may include components such as one or more central processing units, graphic processing units, neural processing units, digital signal processors, or other components that individually or collectively embody the concepts.

[0030] Specific example configurations will now be described with reference to the accompanying drawings.

[0031] 1 illustrates generally an example of a data processing apparatus 2 utilizing address translation circuitry 40 according to various configurations of the present technique. The data processing apparatus 2 includes a number of stages including a fetch stage 6, a decode stage 10, a rename stage 12, an issue stage 16, an execute stage 18, and a writeback stage 20. Instructions move from stage to stage through a pipeline, with some instructions being in one stage of the pipeline and other instructions pending in another stage. It will be appreciated that this is merely an example of a possible pipeline configuration and other examples may have different stages or combinations of stages as desired.

[0032] The fetch stage 6 fetches instructions, for example from an instruction cache. A branch predictor 4 may be provided to predict the outcome of branch instructions. The fetched instructions are passed to a decode stage 10, which decodes the instructions to generate decoded instructions that may provide control signals to trigger an execution stage 18 to perform corresponding processing operations. For some instructions fetched by the fetch stage 6, the decode stage 10 may map the instruction to two or more decoded instructions, such that the "instruction" seen by later stages of the pipeline may be in a different form than the instruction fetched from the cache 8. The decoded instructions are passed to a register renaming stage 12 for mapping architectural register specifiers specified by the instruction to physical register specifiers that identify corresponding physical registers 14 to be accessed in response to the instruction. The issue stage 16 queues instructions awaiting issue for execution. The execution stage 18 executes the instructions issued by the issue stage 16 and, in response to the instructions, performs various data processing operations such as arithmetic or logical operations or load / store operations to a data cache 30 or a further level cache 32 or a memory 34. The execution units 18 may have several execution units 22, 24, 21, 25 including a load store unit 26 for queuing any pending load / store operations. The execution units may be capable of speculative execution of one or more instructions and a speculation control unit 35 may be provided to track the execution of speculatively executed instructions. The writeback stage 20 writes the results of instructions executed by the execution stage 18 to the physical register file 14, which includes a predicate register 44 and a condition status register 42.

[0033] The pipeline also includes an address translation circuit 40 for performing a translation between a first address and a second address. The address translation circuit 40 performs a translation of a first address received from the load / store unit 26 and the fetch stage 6 and returns a second address to the load / store unit 26 or the fetch stage 6 from which the first address was received. The address translation circuit 40 performs the address translation by performing a predetermined maximum number of sequential lookups in a page table level stored in the L2 cache 32 or memory 34.

[0034] 2 provides further details of the address translation circuit 40 according to some exemplary configurations. The address translation circuit 40 is configured to perform an address translation to determine a second address 46 in response to receiving a first address 42 and an identifier 44. The address translation circuit 40 determines the second address 46 by performing a translation table walk using a plurality of translation tables 50. In particular, the address translation circuit 40 performs a series of lookups in the translation tables 50. The series of lookups includes a series of intermediate lookups in the translation tables 50 and a final lookup in one of the translation tables 50. Each intermediate lookup is indexed based on a portion of the first address 42 to determine an address used in a subsequent lookup in one of the translation tables 50. The final lookup is performed by the address translation circuit 40 at an address in one of the translation tables 50 defined based on a portion of the first address 42 to determine the second address 46. In addition, the address translation circuit 40 performs a corresponding series of lookups in a plurality of metadata lookup tables 52 to determine metadata 48. In particular, the address translation circuit 40 performs a series of lookups in the metadata lookup tables 52. The series of lookups includes a series of intermediate lookups in the metadata lookup tables 52 and a final lookup in one of the metadata lookup tables 52. Each intermediate lookup is indexed based on the same portion of the first address 42 used in the corresponding lookup in the translation table 50 to determine an address to be used in a subsequent lookup in one of the metadata lookup tables 50. The final metadata table lookup is performed by using the address translation circuit 40 at an address in one of the metadata lookup tables 52 defined based on the same portion of the first address 42 used in the final lookup in the translation table 50. The address translation circuit 40 is configured to determine the metadata 48 based on the final lookup of the metadata table walk and the identifier 44.

[0035] FIG. 3 provides further details of the address translation 40 circuit according to some exemplary configurations. The address translation circuit 40 includes several features common to the address translation circuit 40 as shown in FIG. 2. These features are described above in connection with FIG. 2. The address translation circuit 40 includes a storage circuit 56 for storing a base translation address for performing a first translation lookup in one of a plurality of translation tables 50 and for storing a base metadata lookup table address for a first metadata table lookup in one of a plurality of metadata lookup tables 52. The address translation circuit 40 further includes a translation lookaside buffer 58 for storing a plurality of entries defining a correspondence between the first address 42, the second address 46, and the metadata 48. The address translation circuit 40 is configured to perform a lookup in the translation lookaside buffer 58 in response to receiving the first address 42 to determine whether the first address 42 is cached therein. If the address translation circuit 40 determines that the first address 42 is cached in the translation lookaside buffer 58, the address translation circuit determines the second address 46 and the metadata 48 based on the entry hit in the translation lookaside buffer 58. On the other hand, if the address translation circuit 40 determines that the first address 42 is not cached in the translation lookaside buffer 58, the address translation circuit 40 performs a translation table walk using the translation table 50 and a metadata table walk using the metadata lookup table 52 to determine the second address 46 and the metadata 48. Once the address translation circuit 40 has performed the translation table walk and the metadata table walk, the address translation circuit 40 may generate a new entry in the translation lookaside buffer 58 that associates the first address 42 with the second address 46 and the metadata 48. The generation of the new entry in the translation lookaside buffer 58 may require that an existing entry in the translation lookaside buffer 58 be evicted. In such a case, the address translation circuit 40 may evict one of the existing entries in the translation lookaside buffer 58 in accordance with a standard cache replacement policy.The address translation circuitry 40 further comprises circuitry for determining a failure indication 54. The address translation circuitry 40 is configured to output the failure indication 54 when the metadata 48 associated with the identifier 44 is determined to be absent.

[0036] 4a and 4b generally illustrate different configurations of the address translation circuit 40 according to various exemplary configurations. Figure 4a generally illustrates an arrangement in which the address translation circuit 40 comprises a single sequential translation circuit 60 configured to perform both a translation table walk based on the first address 42 to determine the second address 46, and a metadata table walk based on the first address 42 and the identifier 44 to determine metadata 48 associated with the second address.

[0037] 4b illustrates generally an arrangement in which the address translation circuit 40 comprises a translation circuit 62 that performs a translation table walk to generate the second address 46 based on the first address 42. The address translation circuit 40 also comprises a second translation circuit 64 configured to perform a metadata table walk based on the first address 42 and the identifier 44 to determine the metadata 48. By providing the address translation circuit 40 with the first translation circuit 62 and the second translation circuit 64, the address translation circuit 40 can perform a translation table walk to determine the second address 46 in parallel with the metadata table walk to determine the metadata 48.

[0038] 5a-5c show schematic arrangements of translation tables and metadata lookup tables in physical memory. FIG. 5a shows schematic arrangements of a host processing device 74 in which separate translation tables are provided for a first virtual machine 70 and a second virtual machine 72 hosted by the host processing device 74. This arrangement corresponds to a typical approach to storing translation tables. The host processing device 74 is configured to access a memory 76 to store data at a first physical address 82 associated with the first virtual machine 70 and a second physical address 84 associated with the second virtual machine 72. In order for the host processing device 74 to perform a translation between an intermediate physical address associated with the first virtual machine 70 and the first physical address 82 associated with the first virtual machine 70, the host processing device 74 stores a first translation table 78. In addition, in order for the host processing device 74 to perform a translation between an intermediate physical address associated with the second virtual machine 72 and the second physical address 84 associated with the second virtual machine 72, the host processing device 74 stores a second translation table 80. In such a configuration, the first physical memory 82 associated with the first virtual machine 70 and the second physical memory 84 associated with the second virtual machine 72 are separate from each other. Thus, each requires their own translation table. In such a configuration, metadata associated with the translation is typically stored in the translation table itself. In this case, the first translation table 78 determines the physical address within the first physical address space 82 associated with the first virtual machine 70 and the metadata associated with the first physical address space 82. In addition, the second translation table 78 determines the physical address within the second physical address space 82 associated with the second virtual machine 70 and the metadata associated with the second physical address space 84.

[0039] 5b shows a schematic diagram of an alternative configuration of physical memory associated with a first virtual machine and a second virtual machine according to a typical approach for storing translation tables. In this configuration, the first virtual machine 70 and the second virtual machine 72 are configured to share the same set of physical addresses 86. If the first virtual machine and the second virtual machine each have access to the same set of physical addresses 86 and further have the same access permissions associated with each set of physical addresses 86, the same set of translation tables can be provided to each of the first virtual machine 70 and the second virtual machine 72. However, a typical usage requirement is that one of the first virtual machine 70 and the second virtual machine 72 may have a higher privilege level than the other of the first virtual machine 70 and the second virtual machine 72. Therefore, it may be desirable for a virtual machine with a higher privilege level to have an elevated set of access permissions when accessing the physical address space 86. To ensure that these access permissions are respected, in a typical configuration, a first set of translation tables 81 is provided for address translations for the first virtual machine 70, the first set of translation tables 81 defining intermediate physical address-to-physical address translations associated with the first virtual machine 70, and the first set of translation tables 81 defining authorization metadata associated with each physical address for which a translation is provided. Additionally, in a typical configuration, a second set of translation tables 83 is provided for address translations for the second virtual machine 72, the second set of translation tables 83 defining intermediate physical address-to-physical address translations associated with the second virtual machine 70, and the second set of translation tables 83 defining authorization metadata associated with each physical address for which a translation is provided. In such a configuration, when the host processing unit 74 modifies the physical addresses 86 associated with the first virtual machine 70 and the second virtual machine 72, both the first translation table 81 and the second translation table 83 require rewriting, resulting in a large processing overhead for the host processing unit 74.

[0040] In contrast, FIG. 5c illustrates a schematic of a host processing unit 94 that includes an address translation circuit 40 according to the present technique. In particular, the host processing unit 94 hosts a first virtual machine 90 and a second virtual machine 92. The first virtual machine 90 and the second virtual machine 92 are configured to access the same set of physical addresses 102 stored in a memory 96 associated with the host processing unit 94. As described in relation to FIG. 5b, when the first virtual machine 90 and the second virtual machine 92 share the same set of physical addresses 102, it is typically required that the permission metadata associated with the first virtual machine 90 and the second virtual machine 92 be different. According to the present technique, the host processing unit 94 stores a set of translation tables that define the translation between the intermediate physical addresses used by each of the first virtual machine 90 and the second virtual machine 92 and the corresponding physical addresses 102 shared between the first virtual machine 90 and the second virtual machine 92. The host processing unit 94 also stores in the memory 96 a set of metadata lookup tables 98 that define the permissions associated with each of the first virtual machine 90 and the second virtual machine 92. When the host processing unit 94 modifies the physical addresses 102 associated with the first virtual machine 90 and the second virtual machine 92, only one set of translation tables, the translation table 100, needs to be modified. Thus, processing overhead is reduced. The host processing unit 94 includes an address translation circuit 40 according to the present technique. In response to receiving an intermediate physical address (first address) associated with one of the first virtual machine 90 and the second virtual machine 92, the address translation circuit 40 performs a translation table walk using the translation table 100 stored in the memory 96. Furthermore, the address translation circuit 40 uses the intermediate physical address in combination with an identifier specifying whether the intermediate physical address originated from the first virtual machine 90 or the second virtual machine 92 to perform a metadata table lookup in the metadata lookup table 98 to determine the authorization metadata associated with the physical address determined from the translation table walk.In this way the same functionality as shown in FIG. 5b is provided, but with the advantage that when physical addresses 102 are remapped, only a single set of translation tables, namely translation tables 100, need to be rewritten.

[0041] FIG. 6 illustrates a schematic of a translation between a first address and a second address, and between a first address and metadata associated with that second address, according to various exemplary configurations. The address translation circuit 40 receives a first address 116. The address translation circuit 40 performs a translation table walk based on a series of lookups in the translation table 110 to determine a second address 132. In particular, the address translation circuit 40 determines a base translation address from a base translation register 120. The base translation address is the address of a sequentially first lookup (L0 lookup) in the translation table 110(A). The lookup in the translation table 110(A) is performed using bits 47:39 (bits 47 through 39) of the first address 116. The result of the lookup in the translation table 110(A) provides an address of a second translation table 110(B) for use in a sequentially second lookup (L1 lookup). The L1 lookup in translation table 110(B) is indexed using bits 38:30 of the first address 116. The result of the lookup in translation table 110(B) in turn provides the address of a third translation table 110(C) that is used in a third lookup (L2 lookup). The L2 lookup in translation table 110(C) is indexed using bits 29:21 of the first address 116. The result of the lookup in translation table 110(C) in turn provides the address of a fourth translation table 110(D) that is used in a fourth lookup (L3 lookup). The L3 lookup in translation table 110(D) is indexed using bits 20:12 of the first address 116. The result of the lookup in translation table 110 (D) is combined with bits 11:0 of ​​the first address 116 using combination unit 118 to generate a second address 132 .

[0042] In addition, the address translation circuit 40 performs a metadata table walk based on a series of metadata lookups in the metadata table 112 to determine the metadata 124. In particular, the address translation circuit 40 determines a base metadata address from the base metadata register 122. The base metadata address is the address of a sequential first lookup (L0 lookup) in the metadata table 112(A). The lookup in the metadata table 112(A) is performed using bits 47:39 of the first address 116. The result of the lookup in the metadata table 112(A) provides an address of a second metadata table 112(B) that is used in a sequential second lookup (L1 lookup). The L1 lookup in the metadata table 112(B) is indexed using bits 38:30 of the first address 116. The result of the lookup in metadata table 112(B) provides an address of a third metadata table 112(C) that is used in a subsequent third lookup (L2 lookup). The L2 lookup in metadata table 112(C) is indexed using bits 29:21 of the first address 116. The result of the lookup in metadata table 112(C) provides an address of a fourth metadata table 112(D) that is used in a subsequent fourth lookup (L3 lookup). The L3 lookup in metadata table 112(D) is indexed using bits 20:12 of the first address 116. The result of the lookup in metadata table 112(D) is combined with bits 11:0 of ​​the first address 116 using a combination unit 130 to generate metadata 124. The metadata 124 is provided to a lookup unit 126 that performs a lookup based on the identifier 114 to determine identifier specific metadata 128 associated with the second address 132. The identifier specific metadata 128 and the second address 132 are returned by the address translation circuit 40.

[0043] In an alternative configuration, the portion of the first address used for each level lookup uses a different number of bits. For example, an L0 lookup may use a different number of bits than an L1 lookup. However, both the L0 lookup in the translation table and the L0 lookup in the metadata table use the same set of bits, resulting in the same structure of the translation table hierarchy and the metadata table hierarchy.

[0044] 7a and 7b show schematic layouts of a translation table (TT) and a metadata table (MT). FIG. 7a shows schematic layouts of translation tables associated with the present technique. Each of the translation tables is associated with a different level of lookup performed by the address translation circuit 40. A level 0 (L0) translation table 142 is determined based on an address stored in a base translation register 140. As described in relation to FIG. 6, the address translation circuit 40 performs a lookup in the L0 translation table 142 to determine which of a plurality of level 1 (L1) translation tables 144 should be used for the L1 lookup. The address translation circuit then performs an L1 lookup in the L1 translation table to determine which of a plurality of level 2 (L2) translation tables 146 should be used for the L2 lookup. The address translation circuit then performs an L2 lookup to determine which of a plurality of level 3 (L3) translation tables 148 should be used for the L3 lookup. Finally, the L3 lookup returns an address portion from which the second address is determined, and a set of default read, write, and execute bits that are combined with the permission bits determined from the metadata lookup.

[0045] FIG. 7b shows a schematic layout of metadata tables corresponding to the translation table layout shown in FIG. 7a. Each of the metadata tables is associated with a different level of lookup performed by the address translation circuit 40. The level 0 (L0) metadata table 152 is determined based on the address stored in the base metadata register 150. As described in connection with FIG. 6, the address translation circuit 40 performs a lookup in the L0 metadata table 152 to determine which of a plurality of level 1 (L1) metadata tables 154 should be used for the L1 lookup. The address translation circuit then performs an L1 lookup in the L1 metadata table to determine which of a plurality of level 2 (L2) metadata tables 156 should be used for the L2 lookup. The address translation circuit then performs an L2 lookup to determine which of a level 3 (L3) metadata table 158 should be used for the L3 lookup. Finally, the L3 lookup returns a set of permission bits associated with a set of possible identifiers. The address translation circuit performs a lookup based on an identifier received with the first address to determine permission bits associated with the identifier, and the address translation circuit determines permissions based on a combination of the permission bits associated with the identifier and default permission bits.

[0046] FIG. 8 illustrates generally how the permission data associated with an identifier is determined from the default permission data and the permission metadata returned from a sequential final metadata lookup for the cases where the permission data is determined additively (default permissions define a minimum set of permissions and the permission metadata defines an increase on the minimum set of permissions), subtractively (default permissions define a maximum set of permissions and the permission metadata defines a limit on the maximum set of permissions) and deterministically (the permission metadata is determined independently of the default permissions).

[0047] When the permission data is determined additively, the permission metadata is defined for each permission bit by increasing the default permission if the permission metadata from the sequential final metadata lookup is more permissive than the default permission metadata. There are two possibilities in this case. First, if the default permission metadata is 1 (indicating that the particular permission is permitted), the resulting permission metadata is 1 regardless of the permission metadata returned from the sequential final metadata lookup. Second, if the default permission metadata is 0 (indicating that the particular permission is not permitted), the resulting permission metadata is determined by the permission metadata from the sequential final metadata lookup. Thus, if the permission metadata from the sequential final metadata lookup is X (where X=1 or X=0), the permission metadata is also equal to X (i.e., the same value of X=1 or X=0). A first example of determining the permission metadata in the additive case has the default permission metadata RWX=100 and the permission metadata from the sequential final metadata lookup of RWX=XXX. In this situation, when the default permission data is 1, the permission metadata is equal to 1, and when the default permission metadata is 0, the permission metadata is determined by the permission metadata from the sequential final metadata lookup, so the permission metadata is RWX=1XX. Similarly, if the default permission metadata is RWX=XX0 and the permission metadata from the sequential final metadata lookup is RWX=101, then the permission metadata is RWX=1X1.

[0048] When the permission data is determined subtractively, if the permission metadata from the sequential final metadata lookup is more restrictive than the default permission metadata, the permission metadata is defined for each permission bit by restricting the default permission. In this case, there are two possibilities. First, if the default permission metadata is 0 (indicating that the particular permission is not permitted), the resulting permission metadata is 0, regardless of the permission metadata returned from the sequential final metadata lookup. Second, if the default permission metadata is 1 (indicating that the particular permission is permitted), the resulting permission metadata is determined by the permission metadata from the sequential final metadata lookup. Thus, if the permission metadata from the sequential final metadata lookup is X (where X=1 or X=0), the permission metadata is also equal to X (i.e., the same value of X=0 or X=1). A first example of determining the permission metadata in the subtractive case has the default permission metadata RWX=100 and the permission metadata from the sequential final metadata lookup of RWX=XXX. In this situation, when the default permission data is 0, the permission metadata is equal to 0, and when the default permission metadata is 1, the permission metadata is determined by the permission metadata from the sequential final metadata lookup, so the permission metadata is RWX=X00. Similarly, if the default permission metadata is RWX=XX0 and the permission metadata from the sequential final metadata lookup is RWX=101, then the permission metadata is RWX=X00.

[0049] When the permission data is determined absolutely, the permission metadata is defined for each permission bit by the permission metadata from the sequential final metadata lookup independent of the default permission data. A first example of determining the permission metadata in the absolute case has the default permission metadata RWX=100 and the permission metadata from the sequential final metadata lookup of RWX=XXX. In this situation, the permission metadata is RWX=XXX. Similarly, if the default permission metadata is RWX=XX0 and the permission metadata from the sequential final metadata lookup is RWX=101, the permission metadata is RWX=101.

[0050] In the illustrated embodiment, permission is defined by a logical 1 indicating that permission is allowed and a logical 0 indicating that permission is not allowed. In an alternative configuration, permission is encoded using a logical 0 indicating that permission is allowed and a logical 1 indicating that permission is not allowed. It will be readily apparent to one skilled in the art that other alternatives for encoding permission may be provided.

[0051] FIG. 9 illustrates a schematic of a translation lookaside buffer according to various configurations of the present technique. The translation lookaside buffer includes a number of rows in which a portion of an intermediate physical address is associated with a portion of a physical address, and a set of permission bits for a particular identifier. In the illustrated embodiment, permission bits are provided for two identifiers (identifier 00 and identifier 01). In particular, a portion of intermediate physical address IPA0 is associated with a portion of physical address PA0, permission bit RWX=111 is associated with identifier 00, and permission bit RWX=111 is associated with identifier 01. Thus, physical address PA0 can be accessed by the virtual machine associated with identifier 00, and can be accessed by the virtual machine associated with identifier 01 for read, write, and execute access. In addition, a portion of intermediate physical address IPA1 is associated with a portion of physical address PA1, permission bit RWX=111 is associated with identifier 00, and permission bit RWX=100 is associated with identifier 01. Thus, physical address PA1 can be accessed by the virtual machine associated with identifier 00 for read, write, and execute access, and can be accessed by the virtual machine associated with identifier 01 for read access only. Finally, a portion of intermediate physical address IPAN is associated with a portion of physical address PAN, with permission bit RWX=110 associated with identifier 00 and permission bit RWX=000 associated with identifier 01. Thus, physical address PAN can be accessed by the virtual machine associated with identifier 00 for read and write access, and cannot be accessed by the virtual machine associated with identifier 01 for any type of access.

[0052] FIG. 10 illustrates a schematic of a series of steps performed by the address translation circuit 40 according to various configurations of the present technique. Flow begins at step S2, where it is determined whether a first address and an identifier associated with the first address have been received. If no, flow remains at step S2. If it is determined in step S2 that a first address and an identifier have been received, flow proceeds to step S4. In step S4, the address translation circuit 30 performs a translation table walk in a series of translation tables to determine a second address corresponding to the first address. The translation table walk is indexed based on the first address. Flow then proceeds to step S6, where a metadata table walk is performed to determine metadata associated with the address translation specific to the identifier. The metadata table walk is performed using a series of translation lookups indexed based on the same portion of the first address as the translation lookup. In some configurations, steps S4 and S6 are performed in parallel.

[0053] FIG. 11 illustrates a schematic of the fabrication of an address translation circuit 40 according to various configurations of the present technique. The fabrication is performed based on computer readable code 1002 stored on a non-transitory computer readable medium 1000. The computer readable code can be used at one or more stages of a semiconductor design and manufacturing process, including an electronic design automation (EDA) stage, to fabricate an integrated circuit with a device embodying the concept. The fabrication process includes applying the computer readable code 1002 directly to one or more programmable hardware units, such as a field programmable gate array (FPGA), to configure the FPGA to embody the configurations described above, or to facilitate the fabrication of a device implemented as one or more integrated circuits or embodying the configurations described above. The fabricated design 1004 includes the address translation circuit 40, which can be fabricated as the whole or part of an integrated circuit.

[0054] In summary, the present invention relates to an address translation circuit and method for performing an address translation. In response to receiving a first address and an identifier, the address translation circuit performs an address translation from the first address to a second address by performing a translation table walk including one or more translation lookups in a plurality of translation tables indexed based on corresponding portions of the first address. The address translation circuit is further configured to perform a metadata table walk to determine metadata specific to the identifier and associated with the address translation. The metadata table walk includes one or more metadata lookups in a plurality of metadata lookup tables, each of the one or more metadata lookups corresponding to one of the one or more translation lookups and indexed based on the same portion of the first address as the translation lookup.

[0055] In this application, the term "configured to..." is used to mean that an element of an apparatus has a configuration capable of performing a defined operation. In this context, "configuration" refers to a method of arrangement or interconnection of hardware or software. For example, an apparatus may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not imply that an apparatus element needs to be modified in any way to provide the defined operation.

[0056] Although illustrative embodiments have been described in detail herein with reference to the accompanying drawings, it will be understood that the invention is not limited to exact embodiments thereof, and various changes, additions and modifications may be made by those skilled in the art without departing from the scope and spirit of the invention as defined in the appended claims. For example, various combinations of the features of the following dependent claims may be made with the features of the independent claims without departing from the scope of the invention.

Claims

1. In response to receiving the first address and the identifier, an address translation from the first address to a second address by performing a translation table walk including one or more translation lookups in a plurality of translation tables indexed based on a corresponding portion of the first address; and performing a metadata table walk to determine metadata specific to the identifier and associated with the address translation, the metadata table walk including one or more metadata lookups in a plurality of metadata lookup tables, each of the one or more metadata lookups corresponding to one of the one or more translation lookups and indexed based on the same portion of the first address as the translation lookup.

2. 2. The address translation circuit of claim 1, configured to perform the translation table walk and the metadata table walk in parallel.

3. 2. The address translation circuit of claim 1, configured to perform the translation table walk and the metadata table walk sequentially, wherein the translation table walk and the metadata table walk are each performed using the same functional circuitry.

4. the one or more transformation lookups are a plurality of sequential transformation lookups; The address translation circuit of claim 1 , wherein the one or more metadata lookups are multiple sequential metadata lookups.

5. 5. The address translation circuit of claim 4, configured to determine the metadata specific to the identifier based on data returned from a sequential final metadata lookup of the sequential metadata lookups, the data returned from the sequential final metadata lookup associating multiple identifiers with corresponding metadata.

6. 6. The address translation circuit of claim 5, wherein the metadata specific to the identifier is permission metadata.

7. determining default authorization metadata from the address translation; responsive to obtaining the data returned from the sequential final metadata lookup, determining the authorization metadata by combining the default authorization metadata with the data returned from the sequential final metadata lookup.

7. The address conversion circuit according to claim 6, configured as follows:

8. 8. The address translation circuit of claim 7, wherein the default permission metadata defines a set of maximum permissions associated with the address translation, and the data returned from the sequential final metadata lookup defines a limit on the set of maximum permissions.

9. 8. The address translation circuit of claim 7, wherein the default permission metadata defines a set of minimum permissions associated with the address translation, and the data returned from the sequential final metadata lookup defines an extension of the set of minimum permissions.

10. 6. The address translation circuit of claim 5, configured to, in response to an indication returned from one of the sequential metadata lookups that a remainder of the sequential metadata lookup is undefined, set the metadata specific to the identifier based on the default permission metadata.

11. 6. The address translation circuit of claim 5, configured to trigger a fault indication in response to determining that the identifier is different from each of the plurality of identifiers.

12. 4. The address translation circuit of claim 1, further comprising a translation lookaside buffer for storing address translations between the first address and the second address and corresponding metadata associated with the address translations.

13. 13. The address translation circuit of claim 12, wherein the identifier is one of a predetermined number of identifiers, and the translation lookaside buffer is configured to store, as the corresponding metadata, metadata specific to each of the predetermined number of identifiers.

14. 4. The address translation circuit according to claim 1, wherein the first address is an intermediate physical address and the second address is a physical address.

15. 4. The address translation circuit of claim 1, wherein the identifier identifies one virtual machine among a plurality of virtual machines hosted on a data processing circuit associated with the address translation circuit, the plurality of virtual machines sharing the same set of second addresses.

16. a base conversion table address sequentially indicating a first conversion table among the plurality of conversion tables; a base metadata lookup table address indicating a sequentially first metadata lookup table among the plurality of metadata lookup tables; 5. The address translation circuit according to claim 4, further comprising a storage circuit for storing:

17. 17. The address translation circuit of claim 16, wherein the storage circuit comprises: a base translation register that stores the base translation table address; and a base metadata register that stores the base metadata lookup table address.

18. A computer readable medium storing computer readable code for manufacturing the address translation circuit of any one of claims 1 to 3.

19. 1. A method for performing address translation using address translation circuitry in response to receiving a first address and an identifier, comprising: performing the address translation from the first address to a second address by performing a translation table walk including one or more translation lookups in a plurality of translation tables indexed based on corresponding portions of the first address; performing a metadata table walk to determine metadata specific to the identifier and associated with the address translation, the metadata table walk including one or more metadata lookups in a plurality of metadata lookup tables, each of the one or more metadata lookups corresponding to one of the one or more translation lookups and indexed based on the same portion of the first address as the translation lookup.

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