Edge ring for improved edge uniformity in semiconductor processing operations - Patents.com

Abstract

An improved edge ring having flow conductance features is disclosed. Edge ring flow conductance features are features added to the edge ring to adjust the flow conductance of gases flowing through localized areas of the edge ring. The flow conductance features can adjust the flow conductance to account for features that may affect the flow of gases in localized areas on the semiconductor wafer, on the edge ring, and in the chamber. The flow conductance may be increased, decreased, or adjusted depending on the desired effect.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] A PCT application is being filed contemporaneously herewith as a part of this application. Each application identified in the contemporaneously filed PCT application to which this application claims benefit or priority is hereby incorporated by reference in its entirety for all purposes. [Background technology]

[0002] It is often desirable to protect the edge of a semiconductor wafer during processing operations to prevent unwanted deposition or etching on the edge and / or underside of the semiconductor wafer. One technique used to provide such edge protection is commonly referred to in the industry as an "exclusion ring" or "edge ring." A typical edge ring features a ring structure with a central opening that is sized slightly smaller than the diameter of the semiconductor wafer with which the edge ring is used, such that when the edge ring is placed over and centered on the semiconductor wafer, the inner edge of the edge ring slightly overlaps the outer edge of the semiconductor wafer. Summary of the Invention

[0003] In some implementations, an edge ring for a wafer having a diameter D and a thickness T may be provided, the edge ring including an outer portion having an outer bottom surface and an inner portion having a top surface, an inner bottom surface, and an inner edge. The outer bottom surface may define a first reference plane that is coplanar with at least a portion of the outer bottom surface. The inner bottom surface may define a second reference plane that is parallel to the first reference plane and coincides with at least a portion of the inner bottom surface. The inner bottom surface may be between the first reference plane and the top surface. The inner bottom surface may be spaced at least a distance T from the first reference plane. The inner edge may have a nominal inner diameter smaller than D. The edge ring may include one of: (a) a raised section in the inner portion, the raised section having a raised section bottom surface between the first reference plane and the second reference plane; (b) an overhanging section having material in a circular region centered within the edge ring, the overhanging section having a diameter equal to the nominal inner diameter; or (c) both (a) and (b).

[0004] In some implementations of the edge ring, the inner portion may have one or more concave sections, each of the one or more concave sections having a concave bottom surface between the second reference plane and the top surface.

[0005] In some implementations of the edge ring, the inner portion has three concave sections.

[0006] In some implementations of the edge ring, each of the one or more concave sections may originate at an inner edge of the inner portion and extend toward an outer edge of the inner portion.

[0007] In some implementations of the edge ring, a concave bottom surface of each of the one or more concave sections may be at least 10 um away from the second reference plane.

[0008] In some implementations of the edge ring, each of the one or more concave sections may have an arcuate outer edge.

[0009] In some implementations of the edge ring, each of the one or more recessed sections may have a straight outer edge.

[0010] In some implementations of an edge ring, the inner portion may have one or more angular sectors in which an inner edge lies between the circular region and the outer edge of the inner portion.

[0011] In some implementations of the edge ring, the inner portion may have three angular sectors.

[0012] In some implementations of the edge ring, the inner edge in each of the one or more angular sectors may be between the circular region and a reference circle concentric with the circular region and the diameter D.

[0013] In some implementations of the edge ring, the inner edge in each of the one or more angular sectors may be arched.

[0014] In some implementations of the edge ring, the inner edge in each of the one or more angular sectors may be straight.

[0015] In some implementations of the edge ring, the raised section bottom surface may be at least 300 um above the first reference plane.

[0016] In some implementations of the edge ring, the flared section may have an flared inner edge that is a chord of a circular area.

[0017] In some implementations of the edge ring, the overhanging section may be sector shaped.

[0018] In some implementations of the edge ring, the overhanging section may be U-shaped.

[0019] In some implementations of the edge ring, the overhanging section may have an overhanging section bottom surface between the first reference plane and the second reference plane.

[0020] In some implementations of the edge ring, the inner edge may have a nominal inner diameter that is greater than or equal to 95% and less than or equal to 99.9% of D.

[0021] In some implementations of the edge ring, the edge ring may be made from a ceramic material.

[0022] In some implementations of the edge ring, the edge ring may further include a plurality of fingers, each of the fingers having a base, a radially inwardly extending portion supported by the base, and a roller configured to rotate relative to the inwardly extending portion, the base of each finger being connected to the outer bottom surface.

[0023] In some implementations of the edge ring, D may be about 300 mm.

[0024] In some implementations of the edge ring, T may be about 775 um. [Brief description of the drawings]

[0025] [Figure 1] FIG. 1 is a plan view of an exemplary edge ring.

[0026] [Figure 2-1] FIG. 2-1 is a perspective view of an example edge ring with example fingers at different locations above an example pedestal. [Figure 2-2] FIG. 2-2 is a perspective view of an example edge ring with example fingers at different locations above an example pedestal.

[0027] [Figure 2-3] FIG. 2-3 is a detailed view of the finger in the area circled in FIG. 2-1.

[0028] [Diagram 3] FIG. 3 is a cross-sectional view of an exemplary edge ring overlying a semiconductor wafer on an exemplary pedestal.

[0029] [Figure 4] FIG. 4 illustrates the flow conductance of an exemplary edge ring covering an exemplary semiconductor wafer.

[0030] [Figure 5-1] FIG. 5-1 is a plan view of an exemplary edge ring having an exemplary overhanging section. [Figure 5-2] FIG. 5-2 is a plan view of an example edge ring having an example overhanging section.

[0031] [Figure 6-1] FIG. 6-1 is a cross-sectional view of an exemplary edge ring having an exemplary overhanging section.

[0032] [Figure 6-2] FIG. 6-2 is a cross-sectional view of an example edge ring having an example overhang section and an example raised section. [Figure 6-3] FIG. 6-3 is a cross-sectional view of an exemplary edge ring having an exemplary overhang section and an exemplary raised section.

[0033] [Figure 6-4] FIG. 6-4 is a cross-sectional view of an exemplary edge ring having an exemplary raised section. [Figure 6-5] FIG. 6-5 is a cross-sectional view of an exemplary edge ring having an exemplary raised section.

[0034] [Figure 7] FIG. 7 is a plan view of an exemplary edge ring, including example feature section locations.

[0035] [Figure 8-1] FIG. 8-1 is a cross-sectional view of an exemplary edge ring having an exemplary recessed section. [Figure 8-2] FIG. 8-2 is a cross-sectional view of an exemplary edge ring having an exemplary recessed section. [Figure 8-3] FIG. 8-3 is a cross-sectional view of an exemplary edge ring having an exemplary recessed section.

[0036] [Figure 9] FIG. 9 is a top view of an example edge ring, including example cutout sections.

[0037] [Figure 10-1] FIG. 10-1 is a cross-sectional view of an exemplary edge ring, including an example of a cutout section.

[0038] [Figure 10-2] FIG. 10-2 is a cross-sectional view of an exemplary edge ring, including an exemplary cutout section and an exemplary recessed section.

[0039] [Figure 11] FIG. 11 illustrates an exemplary concave section and an exemplary raised section.

[0040] [Figure 12] FIG. 12 illustrates an exemplary wafer processing chamber. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0041] In the following description, numerous specific details are set forth to provide a thorough understanding of each presented embodiment. The embodiments disclosed herein may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. Furthermore, while the disclosed embodiments are described in conjunction with specific embodiments, it will be understood that the specific embodiments are not intended to limit the disclosed embodiments.

[0042] In some semiconductor processing operations, an edge ring may be used to help control gas flow near the outer edge of a semiconductor wafer during processing. As mentioned above, such an edge ring may have an internal opening sized slightly smaller than the diameter of the wafer so that when the edge ring is centered on the semiconductor wafer and placed over the semiconductor wafer, it overlaps the wafer by a small amount, e.g., a millimeter or less. The edge ring may be supported, for example, by a pedestal that supports the wafer so that the edge ring does not rest directly on the semiconductor wafer. An inert purge gas (e.g., argon, nitrogen, or other noble gas, or gas that is non-reactive with semiconductor processing gases) may be introduced through an orifice in the pedestal that supports the edge ring to flow into a gap between the edge ring and the pedestal. The purge gas may then flow through this gap, past the edge of the semiconductor wafer, and then be directed radially inward toward the center of the semiconductor wafer via a gap between the bottom surface of the edge ring and the top of the semiconductor wafer.

[0043] Some edge rings may also function as carrier rings that may support a semiconductor wafer during wafer loading and / or transfer operations. In some such edge rings, multiple (e.g., three) fingers may extend radially inward from positions along the edge ring's outer periphery. The fingers are located on the underside of the edge ring and are spaced from a surface of the edge ring that rests on a pedestal that supports the edge ring during processing operations. The fingers extend inward to a point that is located within a circular area of ​​the same diameter as the wafer supported thereby. Thus, when a wafer is centered under the edge ring and the tips of the fingers are located under the wafer, raising the edge ring will cause the tips of the fingers to contact the underside of the wafer and support it from below, so that the wafer can be lifted by moving the edge ring further upward. The pedestal may also have a recess or receptacle on the upper surface sized to allow the fingers (and any associated support structures) to be lowered into it when the edge ring and semiconductor wafer are placed on the pedestal. The recesses or receptacles allow the fingers and their support structures to be lowered below the surface of the pedestal that supports the semiconductor wafer, thereby allowing the edge ring to be lowered to the surface of the pedestal that normally supports the semiconductor wafer and rest on or near the surface of the pedestal.

[0044] The inventors have determined that in certain semiconductor processes, features such as recesses or receptacles for receiving fingers that may be part of an edge ring (or other similar pockets or voids that are in fluid communication with the underside of the wafer or edge ring when the wafer and edge ring are placed on the pedestal) may be able to trap small amounts of process gas from one stage of a semiconductor processing operation, which may then be unnecessarily released during a subsequent stage of the semiconductor processing operation. Such retained and later released process gas may, in some cases, locally disturb or interfere with (or, depending on the particular process in question, unnecessarily enhance) a deposition or etching process performed in a subsequent stage of the semiconductor processing operation, thereby causing increased non-uniformity near the edge of the wafer overlying the recesses or receptacles.

[0045] The inventors have also found that features that may be located on the wafer itself may also cause local edge non-uniformities. For example, semiconductor wafers typically have a notch or flat edge along their periphery that serves as a frame of reference that allows the rotational orientation of the semiconductor wafer to be reliably determined by different tools. Such indexing features allow the rotational orientation of the semiconductor wafer relative to a particular frame of reference / coordinate system to be determined. Once this information is obtained, the semiconductor wafer may be rotated a calculated amount to align it to the desired frame of reference / coordinate system. However, the notch often extends a millimeter or two inward from the edge of the semiconductor wafer, and in effect interacts with the edge ring to provide a small localized region where the flow conductance between the edge ring and the semiconductor wafer is higher than the flow conductance between most or all other locations around the edge ring. This, in turn, has led the inventors to find that this results in a localized increase in the radially inward flow rate of purge gas from the region between the edge ring and the pedestal. Thus, the flow rate of purge gas across the edge of the semiconductor wafer toward the center of the wafer may be elevated at a location(s) along the edge of the semiconductor wafer that covers any notch(es) that may be present on the wafer. A similar effect may be observed with wafers that have flats instead of notches (although potentially extending along a larger portion of the wafer's circumference).

[0046] The inventors have recognized that such issues contribute to potential wafer non-uniformities, and have determined that such non-uniformities can be mitigated or even eliminated by modifying the edge ring structure such that the lower surface of the edge ring that overlies the wafer in use has areas or regions that are raised and / or recessed relative to a surface that forms the nominal lower surface of the edge ring that radially overlies the wafer when the wafer is present. Such areas or regions can locally adjust the flow conductance in the gap between the lower surface of the edge ring and the top of the wafer, increasing or decreasing the amount of purge gas flowing radially inward at that location. The inventors have also determined that such non-uniformities can alternatively or additionally be mitigated or even eliminated by modifying the circular inner edge of the edge ring to have areas where the inner edge moves radially inward or outward relative to the circle along which the inner edge of the edge ring follows (e.g., positioned to align with features such as wafer notches and / or recesses or receptacles in the pedestal). Further details of such implementations are described in more detail below with respect to the figures.

[0047] FIG. 1 is a plan view of an exemplary edge ring 100 according to the present disclosure. The edge ring 100 has an outer portion 106 and an inner portion 104. The inner portion 104 has an inner edge 108. The inner edge 108 may define a substantially circular opening 110 centered about a ring central axis 112. The circular opening 110 has a diameter 114. The diameter 114 is slightly less than the diameter of the semiconductor wafer 102. In the illustrated example, the outline of the exemplary semiconductor wafer 102 is shown. For example, the semiconductor wafer 102 may have a diameter of about 300 mm. In this example, the diameter 114 of the circular opening 110 is less than 300 mm. The diameter 114 may be 297-299.5 mm when used to process 300 mm semiconductor wafers (FIG. 1 is not drawn to scale, as will be appreciated).

[0048] The edge ring 100 may have flow conductance features. The flow conductance features may be used to adjust the flow conductance of the gap between the semiconductor wafer 102 and the overlapping inner portion 104 of the edge ring 100. The flow conductance features may be placed at specific locations to modify the flow conductance at corresponding areas around the circumference of the semiconductor wafer 102. In the example shown in FIG. 1, the edge ring 100 has four locations with flow conductance features placed thereon. Each of the first three locations is in a corresponding section 122, and the fourth location is in the notch section 118. Each section 122 may have a first type of flow conductance feature, while the notch section 118 may have a second type of flow conductance feature, allowing the radial flow conductance of the edge ring to be adjusted to accommodate different purge gas flow rate requirements at different locations. Notch section 118 may be positioned to align with a notch 120 in a semiconductor wafer 102 with which edge ring 100 is to be used. Section 122 may also generally reside above a recess or receptacle in a pedestal (not shown) designed to receive fingers or similar structures attached to edge ring 100. Fingers (not shown, but see FIGS. 2-1 and 2-3) and similar structures may be attached to edge ring 100 by mounting screws 116.

[0049] FIG. 2-1 is a perspective view of an edge ring 100 holding a semiconductor wafer 102 in a raised position above a pedestal 124. The semiconductor wafer 102 is held by edge ring features 156 attached to the edge ring 100 by mounting screws. In this embodiment, the edge ring features 156 are fingers 158 with rollers 164. In this embodiment, there are three edge ring features 156. In some embodiments, there may be a single edge ring feature 156. In some embodiments, there may be two or more edge ring features 156 attached to the edge ring 100. The pedestal 124 may have one or more receptacles 162. The pedestal 124 has receptacles 162 to match the number of edge ring features 156. In the illustrated example, the edge ring 100 has three edge ring features 156 and the pedestal 125 has three receptacles 162. As mentioned above, the receptacles 162 may be capable of trapping small amounts of process gas during semiconductor processing operations. This trapped gas may be undesirably released during subsequent stages of the semiconductor processing operations and may become a source of wafer non-uniformity. The pedestal 124 may also have a number of ports 164. The ports 164 may be used to deliver gas, such as a purge gas, to the underside of the edge ring during wafer processing.

[0050] FIG 2-2 is a perspective view of the edge ring 100 in a lowered position over the pedestal 124. As shown in FIG 2-1, when the edge ring 100 is lowered from the raised position, the edge ring features 156 are lowered into corresponding receptacles 162 on the pedestal 124. By having a receptacle 162 for each edge ring feature 156, the edge ring 100 can lower the semiconductor wafer 102 onto the pedestal 124 and then continue to lower so that it eventually rests on the pedestal as well while remaining slightly above the semiconductor wafer 102.

[0051] 2-3 is a close-up view of an example edge ring feature 156, i.e., a finger 158 having a roller 164. The finger 158 has a base 160. The base 160 supports an elongated structure 162 that extends radially inward from the base. The roller 164 is supported by the elongated structure 162 such that the roller can rotate relative to the elongated structure. In the illustrated example, the roller 164 is attached to the elongated structure 162 by a pin 166. The finger 158 is configured to fit within the receptacle 162 when the edge ring 100 is lowered toward the pedestal 124.

[0052] FIG. 3 is a cross-sectional view of an edge ring 100. The cross-sectional view shows the edge ring overlying the outer edge 136 of a semiconductor wafer 102. The semiconductor wafer 102 rests on a pedestal 124. The edge ring 100 has an inner portion 104, an outer portion 106, and a top surface 142. The inner portion 104 has an inner edge 108. Typically, the inner edge 108 of the edge ring 100 is inboard relative to the semiconductor wafer outer edge 136. That is, the inner edge 108 of the edge ring 100 is within a circle defined by the semiconductor wafer outer edge 136. There may be exceptions to this. For example, in a wafer notch (not shown), the outer edge of the semiconductor wafer may be inboard relative to the inner edge 108 of the edge ring 100. As previously mentioned, the diameter of the circular opening defined by the inner edge 108 has a nominal diameter that is smaller than the diameter of the semiconductor wafer 102 being processed. The inner portion 104 has an inner bottom surface 130 and the outer portion 106 has an outer bottom surface 128. The inner bottom surface 130 is at a higher elevation than the outer bottom surface 128. In some embodiments, the difference in elevation between the inner bottom surface 130 and the outer bottom surface 128 is the thickness of the semiconductor wafer 102. In some embodiments, the elevation of the inner bottom surface 130 may be a distance greater than the thickness of the semiconductor wafer 102 that is higher than the elevation of the outer bottom surface 128. In still other embodiments, the difference in elevation between the inner bottom surface 130 and the outer bottom surface 128 may be less than the thickness of the semiconductor wafer 102. The wafer thickness may be, for example, about 750 um for a 300 mm diameter wafer.

[0053] 3 shows a first reference plane 132, a second reference plane 134, and an upper reference plane 144. The first reference plane 132 is coplanar with at least a majority of the outer bottom surface 128. The second reference plane 134 is parallel to the first reference plane 132 and coincides with at least a majority of the inner bottom surface 130. The upper reference plane 144 coincides with the highest portion of the top surface 142 and is parallel to the first reference plane 132.

[0054] 5-1, 5-2, and 6-1-6-6 show examples of flow conductance features on an edge ring 500 covering a notch 520 of a wafer 502. When an edge ring is used during semiconductor wafer processing, the notch area of ​​the semiconductor wafer is minimally covered by the edge ring. That is, the outer edge of the wafer at the notch is radially closer to the inner edge of the edge ring than the outer edge of the wafer at other portions of the wafer. Thus, during a purge operation, the area around the notch typically has less obstruction and higher flow conductance than other locations around the inner circumference of the edge ring. The higher flow conductance may allow more purge gas to flow radially inward in the area around the notch compared to other areas around the circumference of the semiconductor wafer.

[0055] 4 shows the flow conductance at an area around the notch of a semiconductor wafer compared to other areas around the circumference of the semiconductor wafer. Each figure shows a cross-sectional view of an edge ring 500 covering a semiconductor wafer 502 on a pedestal 524. The top figure shows a cross-sectional view of the semiconductor wafer 502 under the edge ring 500 at a non-notch location along the wafer circumference, and the bottom figure shows a cross-sectional view of the semiconductor wafer 502 under the edge ring 500 at the notch 520. Each figure shows a high conductance region 570 and a low conductance region 572. Around the circumference, the radial distance between the inner edge 508 of the edge ring 500 and the outer edge 536 of the semiconductor wafer 502 is greater, resulting in a smaller high conductance region 570 compared to the high conductance region 570 at the notch 520 where the radial distance between the inner edge 5008 of the edge ring 500 and the outer edge 536 of the semiconductor wafer 502 is smaller. Because the high conductance region 570 is larger at the notch 520, there is typically a higher flow conductance in this area that allows more purge gas to flow radially inward compared to other areas around the circumference of the semiconductor wafer. Flow conductance features in the edge ring may be used to reduce the flow conductance in areas around the notch of the semiconductor wafer. By using flow conductance features to reduce the flow conductance, the flow conductance around the wafer notch may be tailored so that the amount of gas remaining in the notch area after purging matches the amount of gas remaining in other areas around the circumference of the semiconductor wafer.

[0056] One example of a flow conductance feature that may be used to reduce flow conductance in the vicinity of where the wafer notch would be is a flared section. As used herein, the term flared section refers to a portion of the edge ring that extends radially inward from a circle that is generally concentric and coaxial with the inner edge of the edge ring. The flared section thus moves the inner edge of the edge ring at the notch section closer to the wafer central axis than the inner edge that would normally be around most or all of the rest of the inner edge, thereby increasing the length of the shortest flow path that purge gas flowing from the wafer notch feature can take before reaching the inner edge of the edge ring. By increasing the length of this flow path, the flow conductance of the flow path may be reduced, thereby offsetting the increased flow conductance that occurs in the wafer notch area.

[0057] 5-1 and 5-2 are plan views of two examples of edge rings 500 with flow conductance features. The flow conductance feature in each figure is an overhanging section 538. The edge ring 500 in FIGS. 5-1 and 5-2 has an inner portion 504 and an outer portion 506. Also shown is the outline of a semiconductor wafer 502 with a notch 520. The overhanging feature 538 in each figure moves the inner edge 508 in the notch section 518 of the edge ring 500 closer to the center of the wafer 502 in that region compared to the nominal distance of the inner edge to the center of the semiconductor wafer 502. This extends the radial flow path that the purge gas follows as it flows radially inward from the notch area of ​​the wafer toward the inner edge of the edge ring, thereby reducing the flow conductance in that area to offset the increased flow conductance that occurs in the notch area of ​​the wafer and helping to equalize the purge gas flow rate in the notch area to the nominal purge gas flow rate around the circumference of the edge ring.

[0058] FIG. 5-1 shows a first example of an overhanging section 538 of an edge ring 500. The overhanging section 538 in FIG. 5-1 is a portion of the edge ring between a reference circle that is generally coaxial and concentric with the inner edge of the edge ring and a chord of the reference circle. The overhanging section 538 in FIG. 5-1 may therefore be described as chordal. Although such an overhanging feature may be larger than necessary, it may be less susceptible to damage, less likely to be a source of non-uniformity itself, and more tolerant of angular misalignment of the notch features in the wafer relative to the edge ring. In the illustrated embodiment, the chord is just radially inside the notch 520 of the semiconductor wafer 502. The inner edge 508 of the edge ring 500 at the notch section 518 is a straight line that is perpendicular to the edge ring radius that passes through the notch 520 and is also inside the entire notch 520 of the semiconductor wafer. However, it will be understood that similar overhang features that do not feature straight lines may be used, for example, the straight lines may be replaced with constant or variable radius curves that transition slowly between the arcuate edges of the edge ring on either side of the overhang feature to a portion of the inner edge of the overhang feature. Such overhang features may be quite delicate in some implementations - for example, a chord-shaped overhang feature with a chord width (measured from the inner edge of the overhang feature to the circle nominally defined by the inner edge of the edge ring) of less than 1 mm (e.g., 0.8 mm, 0.75 mm, 0.7 mm, 0.65 mm, etc.) may be sufficient in some cases to provide sufficient flow conductance to offset the increased flow conductance resulting from the wafer notch.

[0059] FIG. 5-2 shows a second example of the overhang section 538 of the edge ring 500. The overhang section 538 of FIG. 5-2 follows the shape of the wafer notch 520 and is generally sector or triangular in shape. As with the example of FIG. 5-1, the inner edge 508 of the edge ring 500 is radially inward of a reference circle that is generally coaxial and concentric with the inner edge of the edge ring. However, compared to the chord of FIG. 5-1, the sector shape generally follows the shape of the notch 520 of the semiconductor wafer 502, but is offset outward from the notch 520 such that a zone of the edge ring extending around the notch area overlaps the wafer by a minimal amount (e.g., on the order of 1 millimeter). The sector-shaped overhang section 538 provides a more localized method of flow conductance adjustment compared to the chord-shaped overhang section, since the effect on flow conductance may be more limited compared to the chord-shaped overhang section in FIG. 5-1. In some embodiments, the flared section 538 may be U-shaped, with the curved bottom of the U positioned radially inward toward the center of the edge ring.

[0060] Another exemplary flow conductance feature that may be used to subtract out the increased flow conductance present near the wafer notch is a raised section, which is an area of ​​the bottom surface of the inner portion of the edge ring that is "raised" relative to a majority of the bottom surface of the inner portion of the edge ring. As a result, the gap between the bottom surface of the edge ring where such a raised section is located and the wafer is smaller than the gap between the wafer and most of the remainder of the bottom surface of the inner portion of the edge ring. The flow conductance between the raised section and the wafer is therefore lower than the flow conductance between the wafer and most of the remainder of the bottom surface of the inner portion. Such raised sections may be used alone or in combination with overhanging features. Examples of raised sections are described below with respect to some of the figures.

[0061] 6-1-6-5 are cross-sectional views of an edge ring 500 having flow conductance features positioned over a notch 520 of a semiconductor wafer 502. In each illustrated example, the semiconductor wafer 502 rests on a substrate 524. Shown in each figure is a first reference plane 532 that is coplanar with a majority of the outer bottom surface 528, a second reference plane 534, and a top reference plane 544. As discussed above, the second reference plane 534 coincides with a majority of the inner bottom surface and is parallel to the first reference plane 532. The top reference plane 544 coincides with the highest portion of the top surface 542 and is parallel to the first reference plane 532.

[0062] 6-1 illustrates an edge ring 500 having a flared section 538. In the illustrated embodiment, the flared section 538 locally extends the inner portion 504 of the edge ring 504 radially inward, moving the inner edge 508 inward such that the inner edge at the flared section is closer to the center of the edge ring than the inner edge is around most or all of the rest of the edge ring 500. The flared section 538 may be lengthened or shortened depending on the desired flow conductance.

[0063] FIG. 6-2 illustrates an edge ring 500 having a protruding section 538 and a raised section 546. The raised section 546 in FIG. 6-2 is shown as a darker shaded area than the rest of the edge ring 500. The raised section 546 has a raised section bottom surface 548. The bottom surface 548 is between the first reference plane 532 and the second reference plane 534, so that a portion of the bottom surface of the edge ring 500 is positioned closer to the top surface 526 of the semiconductor wafer 502. The raised section bottom surface 548 may be located anywhere between the top surface 526 of the semiconductor wafer 502 and the second reference plane 534. Having the raised section 546 reduces the gap between the edge ring 500 and the semiconductor wafer 502, thereby reducing the flow conductance in that area. The closer the raised section bottom surface 548 is to the wafer 502, the smaller the gap between the raised section bottom surface 548 and the semiconductor wafer 502. The smaller the gap between raised section bottom surface 548 and semiconductor wafer 502, the lower the flow conductance in that region. In the illustrated embodiment, raised section 546 extends from overhanging section 538 through inner portion 504 to a boundary 507 between inner portion 504 and outer portion 506. Boundary 507 may also be referred to as the outer edge of inner portion 504 or the inner edge of outer portion 506.

[0064] FIG. 6-3 illustrates another embodiment of an edge ring 500 having both a flared section 538 and a raised section 546. In this embodiment, the raised section 546 extends from the flared section 538 into the inner portion 504. Unlike the previous embodiment, the raised section 538 is interrupted partway through its passage into the inner portion 504. In some embodiments, the raised section 538 may be only a segment of the inner portion 504 between the inner edge 508 and the boundary 507. In some embodiments, the raised section may not extend all the way to the inner edge 508 of the inner portion 504. In these embodiments, the raised section begins radially outward of the inner edge 508.

[0065] FIG. 6-4 shows yet another example of an edge ring 500 having a flow conductance feature that is a raised section 546 for use over a notch 520 of a semiconductor wafer 502. The raised section 546 extends outward from a nominal bottom surface of the edge ring 500 such that a bottom surface 548 of the raised section 546 is between a top surface 536 of the semiconductor wafer 502 and a second reference plane 534. The raised section 546 extends from an outer edge 508 through an inner portion 504 to a boundary 507 between the inner portion 504 and the outer portion 506. In the illustrated example, the edge ring 500 does not have an overhanging section as shown in the previous example. Thus, the flow conductance is modified only by the reduced clearance between the bottom surface 548 of the raised section 546 and the top surface 526 of the semiconductor wafer 502.

[0066] FIG. 6-5 illustrates another example of an edge ring 500 having a flow conductance feature that is a raised section 546 over a notch 520 of a semiconductor wafer 502. Similar to the example of FIG. 6-4, in this example, the raised section extends outward such that a bottom surface 548 of the raised section 546 is between the top surface 526 of the semiconductor wafer 502 and the second reference plane 534. In this example, the raised section 546 extends from the outer edge 508 through the inner portion 504 toward the outer portion 506. The raised section 546 terminates at a portion of its passage into the inner portion 504 before extending to a boundary 507 between the inner portion and the outer portion 506. In some embodiments, the raised section 546 may be a segment of the inner portion 504 between the inner edge 508 and the boundary 507. The segment of the raised section 546 may be designed to produce a desired flow conductance in an area above the notch 520 of the wafer 502.

[0067] The flow conductance features described above may be used to reduce flow conductance in localized areas of the edge ring, for example to offset increased flow conductance that may be present due to features such as a wafer notch, while a second type of flow conductance feature may be used to locally increase flow conductance to increase purge gas flow rate in a particular area around the circumference of the edge ring. Broadly speaking, such flow conductance features may be used where features (e.g., fingers) are located on the edge ring that may require the presence of a recess or receptacle in the pedestal. Such recesses or receptacles may trap gas that may resist being purged through the standard purge gas flow that may be provided by the edge ring. A second type of flow conductance feature may increase the flow conductance in these areas, allowing for a locally increased purge gas flow that can act to more efficiently remove trapped gas, thereby preventing such trapped gas from slowly escaping over a longer period of time and potentially interfering with subsequent processing operations. Examples of the second type of flow conductance feature include a recessed section in the bottom surface of the inner portion of the edge ring, a cutout section along the inner edge of the edge ring, or a combination thereof.

[0068] 7 is a plan view of an example edge ring 700 having three feature sections 722. In some embodiments, there may be a single feature section. In some embodiments, there may be two or more feature sections. Such implementations may be used, for example, in situations where there are other than three recesses or receptacles in the pedestal.

[0069] The edge ring 700 has an outer portion 706 and an inner portion 704. The inner portion 704 has an inner edge 708. The inner edge 708 may define a substantially circular opening 710 centered on the ring central axis 712. A semiconductor wafer 702 is shown having an outer edge 736. The inner edge 708 of the inner portion 704 is inside the outer edge 736 of the semiconductor wafer 702. As described in FIG. 1, the section 722 may have features below the edge ring 700, requiring that there be recesses or receptacles in the pedestal to accommodate such features when the edge ring is placed on top of the pedestal. Such recesses or receptacles may trap or contain process gases that may later slowly leak out and potentially interfere with subsequent processing operations that use other gases. It may therefore be desirable to provide a high flow conductance to localized areas of the edge ring to increase the purge rate of such areas. Leaving the purge rate at the "default" purge rate in such areas may result in process gas escaping from the recesses or receptacles increasing local process non-uniformities on the semiconductor wafer 702 around the sections 722. Placing flow conductance features as described above in these sections may improve the purge gas flow rate in these areas, thereby allowing trapped process gas to be removed more quickly.

[0070] As mentioned above, one type of flow conductance feature that may be used is a concave section (not shown). Such flow conductance features are typically cut from the bottom surface of the inner portion 704. Section 722 highlights an area of ​​the edge ring 700 that may be modified to incorporate a flow conductance feature. In the illustrated embodiment, section 722, and thus the flow conductance feature (i.e., the concave section), has an arcuate outer edge. In this embodiment, the arcuate edge follows the arc of a circle concentric with the edge ring 700. In some embodiments, the concave section may have a straight outer edge. In some embodiments, the concave section may extend from the inner edge 708 through the inner portion 704 to a boundary 707 between the inner portion 704 and the outer portion 706. The boundary 707 is where the inner portion outer edge meets the outer portion inner edge, and may be referred to as the inner portion outer edge or the outer portion inner edge. In some embodiments, the concave section may cover only a segment of the inner portion 704 that extends radially outward. In these embodiments, the concave section may extend to either or both of the boundary 707 and the inner edge 708 of the inner portion 704.

[0071] 8-1-8-3 show three cross-sectional areas of an edge ring 700, each having an exemplary concave section 750. Each figure shows an edge ring 700 having an outer portion 706, an inner portion 704, and a top surface 742. The inner portion 704 meets the outer portion 706 at a boundary 707. The inner portion 704 has an inner bottom surface 730 and an inner edge 708. The outer portion 706 has an outer bottom surface 728. A first reference plane 732 is coplanar with a majority of the outer bottom surface 728. A second reference plane 734 coincides with a majority of the inner bottom surface 730 and is parallel to the first reference plane 732. A top reference plane 744 coincides with the highest portion of the top surface 742 and is parallel to the first reference plane 732. The second reference plane 734 is between the first reference plane 732 and the top reference plane 744. Shown in each figure is a semiconductor wafer 702 on a pedestal 724. Semiconductor wafer 702 has an outer edge 736 and a top surface 726. In each figure, wafer outer edge 736 is radially outward of inner edge 708 of inner portion 704. That is, inner edge 708 of inner portion 704 is within a circle defined by wafer outer edge 736.

[0072] FIG. 8-1 illustrates a first example of a recessed section 750. The recessed section 750 is an area where material has been removed from the inner portion 704 of the edge ring 700, thereby forming a recessed section bottom surface 752. The recessed section bottom surface 752 may be anywhere between the second reference plane 734 and the upper reference plane 744. In some implementations, the recessed section bottom surface 752 may be at least 10 um away from the second reference plane 734. In some implementations, the recessed section bottom surface 752 may be at most 200 um away from the second reference plane 734. The recessed section 750 raises the bottom surface in a localized area of ​​the edge ring 700, creating a larger gap between a portion of the bottom surface of the edge ring 700 and the wafer top surface 726. The increased gap may increase the flow conductance in that area, which in turn may encourage a higher purge gas flow rate to more effectively purge process gas in the area around the recessed section 750. Generally, the closer the concave section bottom surface 752 is to the upper reference plane 744, the higher the flow conductance. As shown in FIG. 8-1, the concave section may extend from the outer edge 708 to the boundary 707.

[0073] FIG. 8-2 illustrates a second example of a concave section 750 on the edge ring 700. As in FIG. 8-1, the concave section bottom surface 752 is elevated so that it is between the second reference plane 734 and the upper reference plane 744. In the illustrated example, the concave section 750 extends from the outer edge 708 toward the outer portion 706. However, unlike the example of FIG. 8-1, the concave section ends before the boundary 707 between the inner portion 704 and the outer portion 706. In the illustrated embodiment, the concave section 750 ends before the boundary 707, but the concave section 750 also extends beyond the wafer outer edge 736. In some embodiments, the concave section 750 may be shorter such that the wafer outer edge 736 is radially outward relative to the entire concave section 750, i.e., the wafer outer edge 736 is farther from the center of the edge ring 700 than the outer edge of the concave section. Typically, the greater the radial distance that the recessed section extends, the higher the flow conductance, and therefore, the flow conductance produced in this embodiment may be less than that produced in the embodiment shown in FIG.

[0074] FIG. 8-3 illustrates a third example of a concave section 750 on an edge ring 700. As with the previous example, the concave section 750 has a concave section bottom surface 752. The concave section bottom surface 752 raises the bottom surface of the edge ring 700 in a localized area and is between the second reference plane 734 and the upper reference plane 744. In the illustrated embodiment, the concave section 750 is contained radially within the inner portion 704 of the edge ring 700 and does not extend to the boundary 707 or the outer edge 708. In some embodiments, the concave section 750 may extend radially all the way to the boundary 707 but not all the way to the inner edge 708 of the inner portion 704. The concave section 750 may span any radial segment of the inner portion 704 between the inner edge 708 and the boundary 707.

[0075] The recessed section is one example of a flow conductance feature that may be used to increase the flow conductance in certain areas of the edge ring. Another example of a flow conductance feature is a cut-out section. A cut-out section is a section in an inner portion of the edge ring where material has been removed. Roughly speaking, a cut-out section has an inner edge that is outside a reference circle that is usually coaxial and concentric with the inner edge of the edge ring. In some embodiments, the inner edge of the cut-out section remains inside the outer edge of the semiconductor wafer. The cut-out section reduces the distance that gas must travel between the edge ring and the semiconductor wafer, thereby increasing the flow conductance in these areas compared to areas of the edge ring without the flow conductance feature.

[0076] 9 is a plan view of another example edge ring 900 having three cutout sections 954. In some embodiments, there may be a single cutout section. In some embodiments, there may be two or more cutout sections. Such implementations may be used, for example, in situations where there are other than three recesses or receptacles in the pedestal.

[0077] Shown in this figure is a semiconductor wafer 902. The edge ring 900 has an outer portion 906 and an inner portion 904. The inner portion 904 has an inner edge 908. The semiconductor wafer 902 has a reference circle 960 that is generally coaxial and concentric with the inner edge 908 of the edge ring 900 centered on the ring central axis 912. That is, the reference circle 960 is concentric with the inner edge 908 that is not part of each of the three cutout sections 954. In each of the three cutout sections 954, the inner edge 908 of the inner portion 904 moves radially outward such that the inner edge is between the reference circle 960 and the boundary 907 between the inner portion 904 and the outer portion 906. As explained in the previous figures, the boundary 907 is where the inner portion outer edge meets the outer portion inner edge. In the illustrated embodiment, the cutout sections 954 are angular sectors from the ring central axis 912. The inner edge 908 of the cutout section 954 is arcuate. In some embodiments, the inner edge 908 of the cutout section 954 may be straight. As described in FIG. 1, the arcuate shape may be less than 5 degrees. In some embodiments, the arcuate shape may be between 5 and 10 degrees. In yet some other embodiments, the arcuate shape may be greater than 10 degrees. In some embodiments, the cutout section may be rectangular (not shown).

[0078] As shown in FIG. 9 , the inner edge 908 of the cutout section 954 moves radially outward toward the outer portion 906 relative to the non-cutout section area. In the illustrated embodiment, the inner edge 908 of each cutout section 954 is approximately halfway between the reference circle 960 and the boundary 907. In this embodiment, the inner edge 908 of the cutout section 954 remains radially inward relative to the wafer outer edge 936. That is, the inner edge 908 of each cutout section is in a circle that is concentric and coaxial with the wafer outer edge. It is noted that the illustrated example is exaggerated in size for clarity, and such cutouts and wafer overlaps may be much smaller than those illustrated (e.g., the radial depth of the cutouts may be on the order of 1 millimeter). In some implementations, the radial depth of such cutouts may be less than 1 millimeter (e.g., less than 0.9 mm, less than 0.8 mm, less than 0.7 mm, less than 0.6 mm, less than 0.5 mm, less than 0.4 mm, less than 0.3 mm, etc.). In some embodiments, the cutout section 954 may bring the inner edge 908 closer to the reference circle 960 such that the inner edge at the cutout section is closer to the reference circle 960 than the wafer outer edge 936. In other embodiments, the cutout section 954 may bring the inner edge 908 closer to the boundary 907 such that the inner edge 908 is above or slightly radially inward of the wafer outer edge 936.

[0079] 10-1 and 10-2 are cross-sectional views of an example cutout section 954 on an edge ring 900. In FIG. 10-1, the edge ring 900 has a single flow conductance feature, i.e., a cutout section. In the example of FIG. 10-2, there are two flow conductance features on the edge ring 900, i.e., a cutout section 954 and a recessed section 950. In both figures, the edge ring 900 has an outer portion 906, an inner portion 904, and a top surface 942. The inner portion 904 meets the outer portion 906 at a boundary 907. The boundary 907 may be referred to as the outer edge of the inner portion 904 or the inner edge of the outer portion 906. The inner portion 904 has an inner bottom surface 930 and an inner edge 908. The outer portion 906 has an outer bottom surface 928. A first reference plane 932 is coplanar with a majority of the outer bottom surface 928. The second reference plane 934 coincides with a majority of the inner bottom surface 930 and is parallel to the first reference plane 932. The top reference plane 944 coincides with the highest portion of the top surface 942 and is parallel to the first reference plane 932. Shown in each figure is a semiconductor wafer 902 on a pedestal 924. The semiconductor wafer 902 has an outer edge 936. In each figure, the outer edge 936 is radially outward of the inner edge 908 of the inner portion 904.

[0080] The cross-sectional view in FIG. 10-1 shows a cutout section 954 of the edge ring 900. Behind the cutout section 954 is the edge ring 900 without flow conductance features, i.e., a normal edge ring without a cutout section, shown as a dark shaded area. The cutout section 954 has an inner edge 908 closer to the outer portion 906 of the edge ring 900, reducing overhang of the edge ring 900 over the semiconductor wafer 902 in a localized area. As described in FIG. 9, the cutout section 954 may extend radially inward to remove less material, or may extend radially outward to remove more material. For example, the cutout section 954 may exclude the inner portion 904 in its area, leaving the inner edge 908 above or slightly inside the outer edge of the wafer.

[0081] In the illustrated embodiment, the inner bottom surface 930 is not altered and remains flush with the remainder of the edge ring 900. Thus, in this embodiment, the flow conductance in this range is altered by reducing the overhang of the edge ring 900 with the cutout sections 954, and not by altering the gap between the inner bottom surface 930 and the top surface 926 of the semiconductor wafer 902.

[0082] In the embodiment of FIG. 10-2, the edge ring 900 has both a cutout section 954 and a recessed section 950. Unlike the previous embodiment, both the amount of overhang of the edge ring 900 over the semiconductor wafer 902 and the gap between the bottom surface of the edge ring 900 and the top surface 926 of the semiconductor wafer 902 are modified to change the flow conductance in that area. The cutout section 954 may be formed such that the inner edge 908 of the inner portion 904 of the cutout section 954 is approximately halfway between the inner edge of the unmodified inner portion and the boundary 907. In the illustrated embodiment, the inner edge 908 of the cutout section 954 is radially inward relative to the wafer outer edge 936. The cutout section 954 may be deeper, e.g., the inner edge of the cutout section may be closer to the inner portion 906, or shallower, e.g., the inner edge of the cutout section may be further away from the inner portion 906, depending on the desired flow conductance. In some embodiments, the cutout section 954 may be deeper toward the outer portion 906. In some embodiments, the cutout section 954 may be shallower such that the inner edge 908 is closer to the center (not shown) of the semiconductor wafer 902. The recessed section 950 raises the recessed section bottom surface 952 away from the wafer top surface 926. The recessed section bottom surface 952 is between the upper reference plane 944 and the second reference plane 934. The recessed section 950 may be modified as described with reference to FIGS. 8-1-8-3.

[0083] To further aid in understanding and provide further insight, various exemplary concave and raised sections are shown in FIG. K. In FIG. K, four exemplary concave and four raised sections are provided on the inner portion 1104 of the edge ring 1100, with the flow conductance features all placed side-by-side for comparison. The first concave section 1180 is an example of the embodiment described with respect to FIG. 8-3. The second concave section 1182 is a perspective view of an example of the concave section 650 shown in FIG. 8-1. The third concave section 1184 is a perspective view of an example of the concave section 650 shown in FIG. 8-3. The fourth concave section 1186 is a perspective view of an example of the concave section 650 shown in FIG. 8-2. The first raised section 1190 is an example of the embodiment described with respect to FIG. 6-5. The second raised section 1192 is a perspective view of an example of the raised section 646 shown in FIG. 6-4. The third raised section 1194 is another example of the embodiment described with respect to Figure 6-5. The fourth raised section 1196 is a perspective view of the exemplary raised section 646 shown in Figure 6-5.

[0084] Returning to FIG. 1, each section 122 may be disposed above a corresponding feature, such as feature 156 shown in FIG. 2. Sections 122 may extend through a sector of a circumferential region or arc that may vary depending on the particular flow conductance characteristics desired, as illustrated, for example, by the three different sized feature sections. In the illustrated example, sections 122 are annular sectors of an inner portion of edge ring 100. In some embodiments, sections 122 may be rectangular extending to inner edge 108.

[0085] Similarly, notch section 118 is disposed above a notch 120 in semiconductor wafer 102. Notch section 118 may extend through a sector of a circumferential region or arc that may vary depending on the particular flow conductance characteristics desired, as illustrated, for example, by the two different sized feature sections. In the illustrated example, notch section 122 is an annular sector of an inner portion of edge ring 100. In some embodiments, section 122 may be a rectangle that extends to inner edge 108.

[0086] Edge rings having the features discussed herein may be made from ceramics (e.g., aluminum oxide, aluminum nitride, silicon oxide, silicon nitride, quartz, or other materials that are chemically resistant or otherwise suitable for use in a semiconductor processing environment), and the like.

[0087] In some implementations, the edge rings discussed herein may be used in or be part of a system that includes a controller. FIG. 12 shows an exemplary wafer processing chamber 1201. The illustrated chamber 1201 has multiple wafer processing stations 1221, each having a showerhead 1223 and a pedestal 1224. Within each wafer processing station 1221 is a corresponding edge ring 1200 and semiconductor wafer 1202. The wafer processing chamber 1201 has a wafer handler 1273 (e.g., a rotary indexer, carousel, or wafer handling robot) that may be used to transport wafers between stations. Connected to the wafer processing chamber is an exemplary controller 1274. The controller 1274 has one or more processors 1278 and memory 1276, which may be integrated with electronics for controlling the operation of the edge ring 1200 and / or the wafer handler to place and / or align a wafer on the edge ring. Depending on the processing requirements and / or type of system, the controller 1274 may be programmed to control any of the processes disclosed herein, such as processes for controlling the placement and alignment of a wafer on an edge ring, as well as other processes or parameters not discussed herein, such as delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow settings, fluid delivery settings, position and operation settings, loading and unloading of wafers into and out of chambers, and loading and unloading of wafers into and out of other transport tools and / or load locks connected or interfaced with a particular system.

[0088] Broadly speaking, a controller may be defined as electronic equipment having various integrated circuits, logic, memory, and / or software that, for example, receive instructions, issue instructions, control operations, enable cleaning operations, enable end-point measurements, and the like. Integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various personalizations (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. The operational parameters may, in some embodiments, be part of a recipe defined by a process engineer to accomplish one or more processing processes in the manufacture of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer types.

[0089] The controller may in some implementations be part of or coupled to a computer that is integrated with, coupled to, or otherwise networked to the system, or a combination thereof. For example, the controller may be all or part of a host computer system in the "cloud" or in a fab that allows remote access of wafer processing. The computer may allow remote access to the system to monitor the current progress of a manufacturing operation, review the history of past manufacturing operations, review trends or performance criteria from multiple manufacturing operations, modify parameters of a current process, set up processing steps following a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system over a network that may include a local network or the Internet. The remote computer may include a user interface that allows for input or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data that defines parameters for each processing step that is performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed or the type of tool that the controller is configured to interface with or control. Thus, as discussed above, the controller may be distributed, such as by including one or more separate controllers networked together and working toward a common purpose, such as the process and control described herein. An example of a controller distributed for such a purpose includes one or more integrated circuits on the chamber that are combined to control a process on the chamber and communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer).

[0090] Without limitation, exemplary edge rings according to the present disclosure may be mounted on or be a part of a semiconductor processing tool having a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system that may be associated with or used in the manufacturing and / or production of semiconductor wafers.

[0091] As described above, depending on the process step or steps being performed by the tool, the controller may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, other controllers, or one or more of tools used in material transport to and from containers of wafers to and from tool locations and / or load ports within a semiconductor manufacturing factory.

[0092] As used herein, phrases such as "for each <item> of one or more <items>," "for each <item> of one or more <items>," and the like, are to be understood to encompass both single and multiple items; i.e., "for each" is used in the sense that it is used in programming languages ​​to refer to each item, whatever the collection of items referred to. For example, if the collection of items referred to is a single item, then "each" refers only to that single item (even though dictionary definitions of "each" often define "each" as a term that refers to "one and only one of two or more things") and does not mean that there must be at least two of that item. Similarly, the terms "set" or "subset," in and of themselves, should not be considered as necessarily inclusive of multiple items--it will be understood that a set or subset can contain only one member, or multiple members (unless the context suggests otherwise). conclusion

[0093] Although the foregoing embodiments have been described in some detail for clarity of understanding, it will be apparent that certain changes and modifications may be implemented within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Thus, the present embodiments are considered to be illustrative and not restrictive, and the present embodiments are not limited to the details shown herein.

Claims

1. 1. An edge ring for a wafer having a diameter D and a thickness T, comprising: an outer portion having an outer bottom surface; an inner portion having a top surface, an inner bottom surface, and an inner edge; the outer bottom surface defines a first reference plane that is coplanar with at least a portion of the outer bottom surface; the inner bottom surface defines a second reference plane parallel to the first reference plane and coincident with at least a portion of the inner bottom surface; the inner bottom surface is between the first reference plane and the top surface; the inner bottom surface is spaced from the first reference plane by at least a distance T; the inner edge has a nominal inner diameter less than D; The edge ring includes a raised section in the inner portion, the raised section having a raised section base between the first and second reference planes.

2. 2. The edge ring of claim 1, wherein the inner portion has one or more concave sections, each of the one or more concave sections having a concave bottom surface between the second reference plane and the top surface.

3. The edge ring of claim 2 , wherein the inner portion has three concave sections.

4. The edge ring of claim 2 , wherein each of the one or more recessed sections originates at the inner edge of the inner portion and extends toward an outer edge of the inner portion.

5. 3. The edge ring of claim 2, wherein the concave bottom surface of each of the one or more concave sections is at least 10 um away from the second reference plane.

6. The edge ring of claim 2 , wherein each of the one or more recessed sections has an arcuate outer edge.

7. The edge ring of claim 2 , wherein each of the one or more recessed sections has a straight outer edge.

8. 10. The edge ring of claim 1, wherein the inner portion has one or more angular sectors in which the inner edge lies between a circular area centered within the edge ring and an outer edge of the inner portion.

9. 9. The edge ring of claim 8, wherein the inner portion has three angular sectors.

10. 9. The edge ring of claim 8, wherein the inner edge in each of the one or more angular sectors is between the circular region and a reference circle concentric with the circular region and a diameter D.

11. The edge ring of claim 8 , wherein the inner edge in each of the one or more angular sectors is arcuate.

12. The edge ring of claim 8 , wherein the inner edge in each of the one or more angular sectors is linear.

13. 2. The edge ring of claim 1, wherein the raised section bottom surface is at least 300 um above the first reference plane.

14. 10. The edge ring of claim 1 further comprising an overhanging section having material within a circular area centered within the edge ring, the overhanging section having a diameter equal to the nominal inner diameter, the overhanging section having an overhanging inner edge that is a chord of the circular area.

15. 10. The edge ring of claim 1 further comprising an overhanging section having material within a circular area centered within the edge ring, the overhanging section having a diameter equal to the nominal inner diameter, the overhanging section being sector-shaped.

16. 10. The edge ring of claim 1 further comprising an overhanging section having material within a circular area centered within the edge ring, the overhanging section having a diameter equal to the nominal inner diameter, the overhanging section being U-shaped.

17. 10. The edge ring of claim 1 further comprising an overhang section having material within a circular region centered within the edge ring, the overhang section having a diameter equal to the nominal inner diameter, the overhang section having an overhang section base surface between the first reference plane and the second reference plane.

18. 2. The edge ring of claim 1, wherein the inner edge has a nominal inner diameter that is 95% to 99.9% of D.

19. 10. The edge ring of claim 1, wherein the edge ring is made from a ceramic material.

20. 10. The edge ring of claim 1, further comprising a plurality of fingers; Each of the plurality of fingers has a base, a radially inwardly extending portion supported by the base, and a roller configured to rotate relative to the inwardly extending portion. an edge ring, wherein the base of each of the plurality of fingers is connected to the outer bottom surface;

21. 2. The edge ring of claim 1, wherein D is about 300 mm.

22. 2. The edge ring of claim 1, wherein T is about 775 um.

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