Scrambling circuit, communication system, and scrambling method

Abstract

To provide a scrambling circuit, a communication system, and a scrambling method capable of reducing scrambling processing time.SOLUTION: K (K and k are the same natural number) temporary scrambling circuits TS1 to TSk divide a series of data into L (L is a natural number) pieces and, for each set of k, perform scrambling processing in parallel in k sequences, with L×k pieces of data being treated as one data set. K pattern generating circuits PG1 to PGk do not input the series of data, but generate output data from only initial values. K EXOR circuits EX1 to EXk calculate exclusive OR for outputs of the k temporary scrambling circuits TS1 to TSk and outputs of the k pattern generating circuits PG1 to PGk for each piece of data in the same order, and output continuous scrambled data for the L×k pieces of data. As an initial value for the ith (i is a natural number of 2 or more and k or less) pattern generating circuit PGi of the k pattern generating circuits PG1 to PGk, part of the output of the (i-1)th EXOR circuit PGi-1 is set.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present disclosure relates to a scrambling circuit, a communication system, and a scrambling method. [Background technology]

[0002] A scramble circuit is used in a communication system (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2006-324921 A Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, there has been a problem in that the operation of conventional scrambling circuits is unable to keep up with the increasing data speeds.

[0005] The present disclosure has been made to solve the above-mentioned problems, and has as its object to provide a scrambling circuit, a communication system, and a scrambling method that can reduce the scrambling processing time. [Means for solving the problem]

[0006] The scramble circuit according to the present disclosure is a scramble circuit that continuously scrambles a series of data, and includes k temporary scramble circuits that divide the series of data into L (L is a natural number) pieces and perform scrambling processing in parallel in k sequences, with L x k pieces of data as one data set, k pattern generation circuits that generate output data from only initial values ​​without inputting the series of data, and k EXOR circuits that perform exclusive OR for each piece of data in the same order for the outputs of the k temporary scramble circuits and the outputs of the k pattern generation circuits, and output continuous scrambled data for the L x k pieces of data, and is characterized in that a portion of the output of the (i-1)th EXOR circuit is set as the initial value of the ith (i is a natural number between 2 and k) pattern generation circuit among the k pattern generation circuits. Effect of the Invention

[0007] In the present disclosure, the number of serial processing stages can be reduced because the scrambling process is performed in parallel, which reduces the scrambling process time and makes it possible to handle high-speed data. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing a communication system according to a first embodiment. [Diagram 2] FIG. 2 is a diagram showing a general-purpose scrambling circuit. [Diagram 3] FIG. 1 is a diagram illustrating a general-purpose scramble circuit decomposed into a provisional scramble circuit and a pattern generation circuit. [Figure 4] FIG. 4 is a diagram showing the output of a general-purpose scrambling circuit and the output of the scrambling circuit of FIG. [Diagram 5] 4 is a diagram showing the output of the scramble circuit of FIG. 3 when the initial value of the temporary scramble circuit is set to zero. [Figure 6] This is a diagram in which the scramble circuit in FIG. 3 is modified to have a two-parallel processing configuration. [Figure 7] FIG. 7 is a diagram showing the output of the scrambling circuit of FIG. [Figure 8] FIG. 2 is a diagram illustrating a scramble circuit according to the first embodiment. [Figure 9] FIG. 2 is a diagram showing a scheme for performing two-parallel processing of a first set of data by the scramble circuit according to the first embodiment. [Figure 10] FIG. 13 is a diagram showing a scheme for performing two-parallel processing of a second set of data by the scramble circuit according to the first embodiment. [Figure 11] FIG. 2 is a diagram showing a scheme for performing k-parallel processing on the m-th set of data by the scramble circuit according to the first embodiment. [Figure 12] 1 is a diagram showing a scheme for performing k-parallel processing of the (m+1)th set of data by the scramble circuit according to the first embodiment. FIG. [Figure 13] FIG. 11 is a diagram illustrating a scramble circuit according to a second embodiment. [Figure 14] FIG. 11 is a diagram illustrating an example in which a three-stage linear feedback shift register is applied to the subscramble circuit of the second embodiment. [Figure 15] FIG. 15 is a diagram showing the output of the scrambling circuit of FIG. [Figure 16] FIG. 13 is a diagram illustrating a scramble circuit according to a comparative example. [Figure 17] FIG. 11 is a diagram illustrating an example in which a 58-stage linear feedback shift register is applied to the subscramble circuit of the second embodiment. [Figure 18] FIG. 18 is a diagram showing the output of the scrambling circuit of FIG. [Figure 19] FIG. 18 is a diagram showing the output of the scrambling circuit of FIG. [Figure 20] FIG. 13 is a diagram showing an example in which a 58-stage linear feedback shift register is applied to the subscramble circuit of the second embodiment, and the number of subscramble stages is set to 8. [Figure 21] FIG. 21 illustrates the operations performed by the scrambling circuit of FIG. 20. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] A scrambling circuit, a communication system, and a scrambling method according to the embodiments will be described with reference to the drawings. The same or corresponding components are designated by the same reference numerals, and the description will not be repeated. Embodiment 1

[0010] FIG. 1 is a diagram showing a communication system according to a first embodiment. If the same data is transmitted continuously, it becomes difficult for the receiving side to acquire the timing of the bits. To solve this problem, a scrambling circuit 100 on the transmitting side continuously scrambles a series of data. A transmitter 200 transmits the scrambled data output from the scrambling circuit 100 to a communication path 300 such as an optical fiber. A receiver 400 receives the scrambled data from the communication path 300 and decodes it. A descrambling circuit 500 descrambles the scrambled data output by the receiver 400 to restore the original data.

[0011] Next, before explaining the scramble circuit according to this embodiment, it will be explained that the general-purpose scramble circuit can be decomposed into a provisional scramble circuit and a pattern generation circuit.

[0012] Figure 2 shows the general-purpose scramble circuit. The general-purpose scramble circuit is a linear feedback shift register, and has three stages of shift registers D0, D1, and D2 and EXOR circuits EXa and EXb. S(n) is the initial value of each register (n=0, 1, 2). The general-purpose scramble circuit inputs serial data I(0), I(1), and I(2) in that order, scrambles them, and outputs O(0), O(1), and O(2) in that order.

[0013] The exclusive OR of the output of the first-stage shift register D0 and the output of the third-stage shift register D2 is calculated, and the result of the calculation and the exclusive OR of the input data is fed back to the input of the first-stage shift register D0. The feedback polynomial of the above general-purpose scramble circuit can be expressed as 1+X+X^3.

[0014] Figure 3 shows the general-purpose scramble circuit decomposed into a provisional scramble circuit and a pattern generation circuit. The general-purpose scramble circuit in Figure 2 can be decomposed into a provisional scramble circuit TS that receives data and performs scrambling processing, and a pattern generation circuit PG that does not receive data but generates output data only from initial values. The pattern generation circuit PG is a linear feedback shift register with the same number of stages as the provisional scramble circuit TS. The output A of the provisional scramble circuit TS is held in a flip-flop circuit FF. The EXOR circuit EX calculates the exclusive OR of the output A of the provisional scramble circuit TS and the output B of the pattern generation circuit PG, and outputs the result as the scrambled output.

[0015] c(n) is the initial value of each register of the temporary scramble circuit TS (n=0,1,2). d(n) is the initial value of each register of the pattern generation circuit PG (n=0,1,2). In this specification, "*" indicates an exclusive OR, and the initial value S(n) of each register of the general-purpose scramble circuit is S(n)=c(n)*d(n).

[0016] FIG. 4 is a diagram showing the output of the general-purpose scramble circuit and the output of the scramble circuit in FIG. 3. At time t=0, if the input is I(0), the output of the shift register D0 is S(2), D1 is S(1), and the output of the shift register D2 is S(0), the output O(0) of the general-purpose scramble circuit is expressed as "I(0)*S(2)*S(0)". If the general-purpose scramble circuit is decomposed into a temporary scramble circuit TS and a pattern generation circuit PG, S(2)=c(2)*d(2) and S(0)=c(0)*d(0), so the output O(0) is expressed as I(0)*c(2)*d(2)*c(0)*d(0)=(I(0)*c(2)*c(0))*(d(2)*d(0)). The same is true for time t=N. Therefore, the scramble output O(0) of the general-purpose scramble circuit in Fig. 2 can be expressed as the exclusive OR of the output A of the provisional scramble circuit TS and the output B of the pattern generation circuit PG in Fig. 3. Therefore, the general-purpose scramble circuit can be decomposed into the provisional scramble circuit TS and the pattern generation circuit PG.

[0017] Fig. 5 is a diagram showing the output of the scramble circuit in Fig. 3 when the initial value of the temporary scramble circuit TS is set to zero. When the initial value of the temporary scramble circuit TS is set to zero (c(2) = c(1) = c(0) = 0), the output A of the temporary scramble circuit TS can be obtained only from the input data I(n). Therefore, calculations of the temporary scramble circuit TS can be performed easily. The output B of the pattern generation circuit PG can be obtained only from the initial values ​​d(0) to d(2).

[0018] Next, it will be explained that the scramble circuit decomposed into a provisional scramble circuit and a pattern generation circuit can be changed to a parallel processing configuration. FIG. 6 is a diagram in which the scramble circuit in FIG. 3 is changed to a two-parallel processing configuration. Two sets of provisional scramble circuits and pattern generation circuits are prepared. A divider DIV divides input data into two, each with a predetermined number L=10 pieces. Of the input data I(0)-I(19), the first 10 pieces of data I(0)-I(9) are input to the provisional scramble circuit TS1 in the upper stage, and the next 10 pieces of data I(10)-I(19) are input to the provisional scramble circuit TS2 in the lower stage. The EXOR circuit EX1 in the upper stage calculates the exclusive OR of the provisional output A1 of the provisional scramble circuit TS1 and the output B1 of the pattern generation circuit PG1. The EXOR circuit EX2 in the lower stage calculates the exclusive OR of the provisional output A2 of the provisional scramble circuit TS2 and the output B2 of the pattern generation circuit PG2. A combiner SYN combines the output of the upper EXOR circuit EX1 and the output of the lower EXOR circuit EX2 to output scrambled outputs O(17) to O(19).

[0019] The final output O(7)-O(9) of the EXOR circuit EX1 in the upper stage is set as the initial value of the pattern generating circuit PG2 in the lower stage. This allows the scrambled output in the lower stage to be the result of continuously scrambling the result of the scrambled output in the upper stage.

[0020] Similarly, for the next data set I(20)-I(39), the first 10 pieces of data I(20)-I(29) are input to the upper circuit, and the next 10 pieces of data I(30)-I(39) are input to the lower circuit. However, the initial value of the upper pattern generation circuit PG1 is set to the final output O(17)-O(19) of the lower EXOR circuit EX2 in the previous set. The initial value of the lower pattern generation circuit PG2 is set to the final output O(27)-O(29) of the upper EXOR circuit EX1.

[0021] As described above, the scramble circuit in Fig. 6 scrambles 2L=20 pieces at a time using a two-parallel processing configuration, which makes it possible to reduce the processing time compared to the scramble circuit in Fig. 3.

[0022] Fig. 7 is a diagram showing the output of the scramble circuit of Fig. 6. Twenty pieces of data I(0) to I(19) are input as input data to the scramble circuit of Fig. 6. The outputs O(0) to O(9) corresponding to the inputs I(0) to I(9) can be expressed as the exclusive OR of the output A1 of the upper temporary scramble circuit TS1, which is calculated using only the inputs I(0) to I(9), and the output B1 of the upper pattern generation circuit PG1, which is calculated using only the initial values ​​S(0) to S(2).

[0023] Also, the outputs O(10) to O(19) for the inputs I(10) to I(19) can be expressed as the exclusive OR of the output A2 of the temporary scrambling circuit TS2 in the lower stage, which is calculated only from the inputs I(10) to I(19), and the output B2 of the pattern generating circuit PG2 in the lower stage, which is calculated only from the outputs O(7) to O(9) of the EXOR circuit EX1 in the upper stage. Note that B2 is the output of the pattern generating circuit PG2 when the initial values ​​are set to O(7) to O(9).

[0024] The above A1 and A2 can be calculated simultaneously in parallel for the inputs I(0) to I(9) and I(10) to I(19). B1 can be calculated instantly using only S(0) to S(2) that are preset as the initial values ​​of the upper pattern generation circuit PG1. B2 can be calculated instantly when the outputs O(7) to O(9) are calculated in the upper circuit. Therefore, the scrambled outputs O(0) to O(19) for the 20 input data I(0) to I(19) can be calculated in parallel. This makes it possible to reduce the scrambling processing time. The following scrambled outputs O(20) to O(39) for I(20) to I(39) can be calculated in a similar manner.

[0025] Fig. 8 is a diagram showing a scramble circuit according to the first embodiment. Input data is a series of serial data. This series of data is divided into L (natural number) pieces to form one set. Each set of L x k pieces of data is k (natural number) sets. For example, L is 512 pieces. Although not shown in Fig. 8, the divider DIV in Fig. 6 is used to divide the input data.

[0026] The scramble circuit 100 includes k temporary scramble circuits TS1 to TS k and k pattern generation circuits PG1 to PG k and k EXOR circuits EX1 to EX k The temporary scramble circuits TS1 to TS k Each of the pattern generating circuits PG1 to PG k Each of the temporary scrambling circuits TS1 to TS k Although not shown in FIG. 8, the temporary scrambling circuits TS1 to TS k and the corresponding EXOR circuits EX1 to EX k As shown in FIG. 3, a flip-flop circuit FF is inserted between these.

[0027] k temporary scrambling circuits TS1 to TS kEach of the temporary scrambling circuits TS1 to TS2 performs parallel scrambling processing on L×k pieces of data as one data set in k sequences, and outputs L×k pieces of scrambled data. k The pattern generating circuits PG1 to PG perform scrambling processing on L pieces of data and output L pieces of scrambled data. k does not input the above series of data, but generates output data only from initial values.

[0028] k EXOR circuits EX1 to EX k are k temporary scrambling circuits TS1 to TS k and k pattern generators PG1 to PG k For example, the first EXOR circuit EX1 calculates an exclusive OR for each data in the same order for the output of the first temporary scramble circuit TS1 and the output of the first pattern generation circuit PG1. k The scrambled data output from are synthesized and the scrambled output is output. Although not shown in Fig. 8, the synthesizer SYN in Fig. 6 is used to synthesize the scrambled data.

[0029] k temporary scrambling circuits TS1 to TS k The initial values ​​of k pattern generating circuits PG1 to PG k The i-th (i is a natural number between 2 and k) pattern generator PG i As the initial value of the i-1th EXOR circuit EX i-1 Sets part of the output of the pattern generation circuits PG1 to PG k When the number of stages of each of the patterns is N (N is a natural number), the i-th pattern generating circuit PG i As the initial value of the i-1th EXOR circuit EX i-1 The initial value of the first pattern generating circuit PG1 is set to the kth temporary scrambling circuit TS for the previous data set, if there is a previous data set.k Sets a part of the output, and sets all zeros if there is no previous data set.

[0030] Specifically, the first L pieces of data in the first (m=1) set are scrambled by the first provisional scramble circuit TS1, and the output of that circuit is exclusive-ORed with the output of the first pattern generation circuit PG1. The initial value of the first pattern generation circuit PG1 is zero. The next L pieces of data in the first set are scrambled by the second provisional scramble circuit TS2, and the output of that circuit is exclusive-ORed with the output of the second pattern generation circuit PG2. The final portion of the output of the first EXOR circuit EX1 is set as the initial value of the second pattern generation circuit PG2. Similarly, the kth L pieces of data in the first set are scrambled by the kth provisional scramble circuit TS k Then, the output is scrambled with the kth pattern generator PG k The kth pattern generator PG k The initial value of the k-1th EXOR circuit EX k-1 The final part of the output of all the temporary scrambling circuits TS1 to TS k The initial value of is zero.

[0031] Next, the first L data of the 2nd (m=2) set is scrambled by the first temporary scrambling circuit TS1, and the exclusive OR of the output of the scrambling circuit TS1 and the output of the first pattern generating circuit PG1 is obtained. k The next L pieces of data in the second set are scrambled by the second temporary scrambler circuit TS2, and the exclusive OR of that output and the output of the second pattern generator circuit PG2 is calculated. The final part of the output of the first EXOR circuit EX1 is set as the initial value of the second pattern generator circuit PG2. The process is then the same as for the first set.

[0032] The result of k sets of L pieces of data being processed in parallel in one data set by the above scramble circuit is the same as the result of consecutively scrambling serial data obtained by serializing L pieces x k sets of data. Similarly, L pieces of data are processed in k parallel for the next data set. The result is the same as the result of consecutively scrambling serial data obtained by serializing L pieces x k sets of data in the previous set and L pieces x k sets of data in the current set.

[0033] Next, a scheme for continuously scrambling input data in two parallel processes using the scramble circuit according to the first embodiment will be described. FIG. 9 is a diagram showing a scheme for performing two-parallel processing of the first set of data using the scramble circuit according to the first embodiment. 20 pieces of input data are considered as one data set. The first ten pieces of data I(0) to I(9) of the first set of data are input to the first provisional scramble circuit TS1, and the last ten pieces of data I(10) to I(19) are simultaneously input to the second provisional scramble circuit TS2. The initial values ​​of the provisional scramble circuits TS1 and TS2 are all zero, the initial value of the first pattern generation circuit PG1 is all zero, and the final part of the output of the first EXOR circuit EX1 is set as the initial value of the second pattern generation circuit PG2.

[0034] FIG. 10 is a diagram showing a scheme for performing two-parallel processing of the second set of data by the scramble circuit according to the first embodiment. The first ten pieces of the twenty pieces of data in the second set, I(20) to I(29), are input to the first provisional scramble circuit TS1 of the same scramble circuit 100, and the last ten pieces, I(30) to I(39), are simultaneously input to the second provisional scramble circuit TS2. The initial values ​​of the provisional scramble circuits TS1 and TS2 are all zero. The final part of the output of the second EXOR circuit EX2 in the first set is set as the initial value of the first pattern generation circuit PG1. The final part of the output of the first EXOR circuit EX1 is set as the initial value of the second pattern generation circuit PG2. Calculations are performed for the following sets using a similar scheme.

[0035] A scheme for 2-parallel processing has been described using Figures 9 and 10, but a scheme generalized to k-parallel processing will be described below. Figure 11 is a diagram showing a scheme for k-parallel processing of the m-th set of data by the scramble circuit according to the first embodiment. The scramble circuit 100 performs k-parallel processing of L items x k combinations of data in the m-th set.

[0036] 12 is a diagram showing a scheme for performing k-parallel processing of the (m+1)th set of data by the scramble circuit according to the first embodiment. The scramble circuit 100 performs k-parallel processing of the (m+1)th set of data following the mth set of data. The kth EXOR circuit EXOR in the mth set is used as the initial value of the first pattern generation circuit PG1. k By performing k-parallel processing in this way, the scrambling time for input data can be reduced to 1 / k.

[0037] Next, the effect of this embodiment will be explained in comparison with a general-purpose scramble circuit. In a general-purpose scramble circuit, the first output O(0) is output when the first input I(0) is input. Therefore, when scrambling a predetermined number of data, a processing time proportional to the predetermined number is required. For this reason, the operation of the scramble circuit cannot keep up with increased data speed. In contrast, in this embodiment, the scramble process is performed in parallel, so the number of serial processing stages can be reduced. This reduces the scramble process time, making it possible to keep up with increased data speeds.

[0038] Embodiment 2 13 is a diagram showing a scrambling circuit according to the second embodiment. In this embodiment, k temporary scrambling circuits TS1 to TS k Each of the sub-scrambling circuits SS1 to SS2 is a linear feedback shift register (M is a natural number). M The provisional scramble circuit of the first embodiment is equivalent to the provisional scramble circuit of the second embodiment having one sub-scramble circuit.

[0039] Temporary scramble circuit TS1~TS k The data of a predetermined number L input to each of the sub-scrambling circuits SS1 to SS2 is divided into M pieces of data each of which is P pieces (L=P×M). M The M sub-scrambling circuits SS1 to SS M The jth (j is a natural number between 2 and M) sub-scrambling circuit SS j As the initial value of the j-1th subscrambling circuit SS j-1 This allows continuous scrambling. The rest of the configuration is the same as in the first embodiment.

[0040] Generally, input data is recorded in a memory divided into a predetermined range. Therefore, by dividing the data into a plurality of linear feedback shift registers and processing each range, efficient processing can be achieved. k For example, if L=512-bit input data is divided into M=8 memory stacks, the divided data (P=64 bits) is processed by M sub-scrambling circuits SS1 to SS M This allows efficient input / output supply processing.

[0041] 14 is a diagram showing an example in which a three-stage linear feedback shift register is applied to the sub-scramble circuit of the second embodiment. The feedback polynomial of the three-stage linear feedback shift register can be expressed as 1+X+X^3. The number of data in one data set is 20, the number of parallel processes k is 2, and the number M of sub-scramble circuits included in the provisional scramble circuit is 2.

[0042] The provisional scramble circuits TS1 and TS2 process input data I(0) to I(9) and input data I(10) to I(19) in parallel. Each of the provisional scramble circuits TS1 and TS2 performs processing sequentially using two sub-scramble circuits SS1 and SS2. Specifically, in the provisional scramble circuit TS1, the sub-scramble circuit SS1 scrambles I(0) to I(4), and the sub-scramble circuit SS2 scrambles I(5) to I(9). In the provisional scramble circuit TS2, the sub-scramble circuit SS1 scrambles I(10) to I(14), and the sub-scramble circuit SS2 scrambles I(15) to I(19).

[0043] The initial values ​​S(0) to S(2) of the sub-scramble circuit SS1 in the provisional scramble circuit TS1 are all zero, and the final data O(4) to O(2) of the sub-scramble circuit SS1 are set as the initial values ​​of the sub-scramble circuit SS2 in the provisional scramble circuit TS1. For the initial data, all zeros are set as the initial values ​​S(0) to S(2) of the first pattern generation circuit PG1.

[0044] The initial values ​​O(9) to O(7) of the sub-scramble circuit SS1 of the provisional scramble circuit TS2 are all zero, and the initial values ​​of the sub-scramble circuit SS2 of the provisional scramble circuit TS2 are set to the final data O(14) to O(12) as the sub-scramble circuit SS1. The final data O(9) to O(7) of the EXOR circuit EX1 is set as the initial value of the second pattern generation circuit PG2. From this point onwards, the scramble process is similarly performed for 10 data x 2 each. However, the final three data of the EXOR circuit EX2 in the previous data set are set as the initial value of the first pattern generation circuit PG1.

[0045] FIG. 15 is a diagram showing the output of the scramble circuit of FIG. 14. I(0) to I(9) of the first data set are input to the provisional scramble circuit TS1. The sub-scramble circuit SS1 of the provisional scramble circuit TS1 calculates the output A11 with initial values ​​S(0) to S(2)=0. The sub-scramble circuit SS2 of the provisional scramble circuit TS1 sets O(2) to O(4) as initial values ​​and calculates the output A12. (A11+A12) becomes the provisional output A1 of the provisional scramble circuit TS1. The pattern generation circuit PG1 calculates the output B1 with initial values ​​S(0) to S(2)=0. The EXOR circuit EX1 calculates the exclusive OR (A1*B1) of the provisional output A1 and the output B1 to obtain the outputs O(0) to O(9).

[0046] I(10) to I(19) of the first data set are input to the provisional scramble circuit TS2. The sub-scramble circuit SS1 of the provisional scramble circuit TS2 sets O(7) to O(9) = 0 as the initial value and calculates the output A21. The sub-scramble circuit SS2 of the provisional scramble circuit TS2 sets O(12) to O(14) as the initial value and calculates the output A22. (A21 + A22) becomes the provisional output A2 of the provisional scramble circuit TS2. The pattern generation circuit PG2 sets O(7) to O(9) as the initial value and calculates the output B2. The EXOR circuit EX2 calculates the exclusive OR (A2 * B2) of the provisional output A2 and the output B2, and the outputs O(10) to O(19) are obtained.

[0047] As a result, for the input of the first data set I(0) to I(19), the scrambled outputs O(0) to O(19) are obtained by two parallel processes. The same scramble process is performed for the input of the second data set I(20) to I(39), but O(17) to O(19) are set as the initial values ​​of the pattern generation circuit PG1.

[0048] Next, a case where a 58-stage linear feedback shift register is applied to the sub-scramble circuit of the second embodiment will be described in comparison with a comparative example. Fig. 16 is a diagram showing a scramble circuit according to the comparative example. In the comparative example, 16 stages of 58-stage scramble circuits Scr_core[0] to Scr_core

[15] are connected between flip-flop circuits FF1 and FF2 to perform serial processing. The feedback polynomial of each scramble circuit can be expressed as 1+x^39+x^58.

[0049] In the comparative example, each scramble circuit inputs input data idat1 and initial value idat2, and outputs output data odat. In the first cycle, all 0 is set as the initial value of the scramble circuit Scr_core[0]. From the second cycle, the output [65:8] of the scramble circuit Scr_core

[15] in the previous cycle is set. s0 to s57 of the output calculated by the scramble circuit Scr_core[n] (0≦n≦14) for 66 bits are set as the initial value of the scramble circuit Scr_core[n+1]. The outputs [65:0], [131:66]···[1055:990] of the scramble circuits Scr_core[0] to Scr_core

[15] are input to the flip-flop circuit FF1, and the final output is obtained as [1055:0].

[0050] In the 16-stage serial processing by the scramble circuit according to the comparative example, the number of logic circuits between the flip-flop circuits FF1 and FF2 increases, and when the input signal speed increases (for example, from 400 Gbps to 800 Gbps), the timing cannot be met by logic synthesis.

[0051] 17 is a diagram showing an example in which a 58-stage linear feedback shift register is applied to the subscramble circuit of the second embodiment. The number of data in one data set is 264 (only the first data set has 262). The number of parallel processes k is 2, and the number of subscrambles M is 2. Of the input data I(0) to I(263), I(0) and I(1) are not scrambled and are fixed, and scramble processing is performed on I(2) to I(263).

[0052] The final 58 pieces of data of the EXOR circuit EX2 in the previous data set are set as the initial values ​​of the pattern generation circuit PG1. However, only for the first data set, the initial values ​​of the pattern generation circuit PG1 are set to all zeros. The initial values ​​of the pattern generation circuit PG2 are set to outputs 0 (74) to 0 (131). The final 58 pieces of data of the EXOR circuit EX2 are set as the initial values ​​of the pattern generation circuit PG1 in the next data set.

[0053] The provisional scrambling circuits TS1 and TS2 process the input data I(2) to I(131) and the input data I(132) to I(263) in parallel. Similarly, the second and subsequent data sets are scrambled in parallel in groups of 132 data. By performing scrambling in parallel in this way, the number of serial processing stages can be reduced, and the scrambling time can be reduced compared to the comparative example.

[0054] 18 and 19 are diagrams showing the output of the scramble circuit of FIG. 17. I(2) to I(131) of the first data set are input to the provisional scramble circuit TS1. The sub-scramble circuit SS1 of the provisional scramble circuit TS1 calculates the output A11 with initial values ​​S(0) to S(57)=0. The sub-scramble circuit SS2 of the provisional scramble circuit TS1 sets O(8) to O(65) as initial values ​​and calculates the output A12. (A11+A12) becomes the provisional output A1 of the provisional scramble circuit TS1. The pattern generation circuit PG1 calculates the output B1 with initial values ​​S(0) to S(57)=0. The EXOR circuit EX1 calculates the exclusive OR (A1*B1) of the provisional output A1 and the output B1 to obtain the outputs O(2) to O(131).

[0055] I(132) to I(263) of the first data set are input to the provisional scramble circuit TS2. The sub-scramble circuit SS1 of the provisional scramble circuit TS2 sets O(74) to O(131) = 0 as the initial value and calculates the output A21. The sub-scramble circuit SS2 of the provisional scramble circuit TS2 sets O(140) to O(197) as the initial value and calculates the output A22. (A21 + A22) becomes the provisional output A2 of the provisional scramble circuit TS2. The pattern generation circuit PG2 sets O(74) to O(131) as the initial value and calculates the output B2. The EXOR circuit EX2 calculates the exclusive OR (A2 * B2) of the provisional output A2 and the output B2, and the output O(132) to O(263) is obtained.

[0056] As described above, the inputs of the first data set I(2) to I(263) are scrambled in two parallel processes to obtain scrambled outputs O(2) to O(263). The inputs of the second data set I(264) to I(527) are scrambled in a similar manner, but O(206) to O(263) are set as the initial values ​​of the pattern generation circuit PG1.

[0057] FIG. 20 is a diagram showing an example in which a 58-stage linear feedback shift register is applied to the sub-scramble circuit of the second embodiment, and the number of sub-scrambles is 8. The number of data in one data set is 1056, the number of parallel processes k is 2, and the number of sub-scrambles M is 8. The sub-scramble circuits SS0 to SS7 of the provisional scramble circuits TS1 and TS2 are 58-stage linear feedback shift registers. Each sub-scramble circuit inputs input data idat1[65:0] in parallel and outputs output data wa_dat[65:0] in parallel. The initial value idat2 of the first sub-scramble circuit SS0 is all zero. The output [57:0] of the sub-scramble circuit SS1 is set as the initial value idat2 of the sub-scramble circuit SS1. The pattern generation circuit PG1 generates patterns for the lower 66B×8 data from [527:462], which corresponds to the 66B data in the final stage. The pattern generation circuit PG2 generates patterns for the upper 66B x 8 data from [1055:990], which corresponds to the final 66B data.

[0058] FIG. 21 is a diagram showing the operation executed by the scramble circuit in FIG. 20. This operation is the expansion of the polynomial G(x)=1+x^39+x^58 for 66-bit parallel data. The first 2 bits of the 66 bits are header data, so they are not scrambled. Therefore, bits 0 and 1 of the output data wa_dat are wa_dat[0]=idat1[0] and wa_dat[1]=idat1[1], respectively. Bits 2-65 of the output data wa_dat are the exclusive OR of the operation on the input data and the operation on the initial value, as shown in FIG. 21.

[0059] The sub-scrambler circuits SS0 to SS7 of the provisional scrambler circuits TS1 and TS2 in FIG. 20 perform calculations on the input data in FIG. 21, and the pattern generators PG1 and PG2 perform calculations of initial values.

[0060] First, the sub-scramble circuits SS0 to SS7 of the provisional scramble circuits TS1 and TS2 perform calculations on the input data with a fixed initial value (all 0 in this case). When the calculation result of the EXOR circuit EX2 is finalized, the pattern generation circuit PG1 performs a calculation and calculates the exclusive OR of the calculation result and the calculation result of the provisional scramble circuit TS1. When the calculation result of the EXOR circuit EX1 is finalized, the pattern generation circuit PG2 performs a calculation and calculates the exclusive OR of the calculation result and the calculation result of the provisional scramble circuit TS2. Because the provisional scramble circuits TS1 and TS2 in the previous stage perform calculations with a fixed initial value, the exclusive OR of the calculation result of the subsequent pattern generation circuits PG1 and PG2 is calculated to correct this.

[0061] As described above, in this embodiment, the temporary scrambling circuits TS1 to TS kEach of the sub-scrambling circuits includes a plurality of sub-scrambling circuits. This allows input data recorded in a memory divided into predetermined ranges to be processed for each range, making it possible to perform efficient processing. Also, as in the first embodiment, the number of serial processing stages can be reduced because the scrambling processing is performed in parallel. This allows the scrambling processing time to be reduced, making it possible to handle cases where data speeds have increased. [Explanation of symbols]

[0062] 100 scrambling circuit, 200 transmitter, 300 communication path, 400 receiver, 500 descrambling circuit, EX1~EX k EXOR circuit, FF2 flip-flop circuit, PG1~PG k Pattern generation circuit, TS1~TS k Temporary scramble circuit, SS0~~SS M Sub-scrambling circuit

Claims

1. A scrambling circuit for continuously scrambling a series of data, comprising: k temporary scrambling circuits which divide the series of data into L (L is a natural number) sets and perform a scrambling process in parallel in k series for each set of L×k data sets as one data set; k pattern generation circuits that generate output data from only initial values ​​without inputting the series of data; k EXOR circuits for calculating exclusive ORs of the outputs of the k temporary scrambling circuits and the outputs of the k pattern generating circuits for each data of the same order, and outputting continuous scrambled data for the L×k data; A scramble circuit characterized in that a part of the output of an (i-1)th EXOR circuit is set as an initial value of an ith pattern generation circuit (i is a natural number of 2 or more and k or less) among the k pattern generation circuits.

2. Each of the k provisional scrambling circuits is a linear feedback shift register; Each of the k pattern generating circuits is a linear feedback shift register having the same number of stages as the provisional scrambling circuit; 2. The scramble circuit according to claim 1, wherein the initial values ​​of said k provisional scramble circuits are fixed.

3. The number of stages of the linear feedback shift register of the pattern generation circuit is N (N is a natural number), 3. The scramble circuit according to claim 2, wherein N pieces of data are set from the final data of the output of the (i-1)th EXOR circuit as the initial value of the i-th pattern generating circuit.

4. The scramble circuit according to any one of claims 1 to 3, characterized in that the initial value of the first pattern generating circuit is set to a part of the output of the kth temporary scramble circuit for a previous data set if there is a previous data set, and is set to all zero if there is no previous data set.

5. Each of the k provisional scrambling circuits includes M (M is a natural number) sub-scrambling circuits which are linear feedback shift registers; The scramble circuit according to any one of claims 1 to 3, characterized in that a part of the output of a j-1th subscramble circuit is set as an initial value of a jth subscramble circuit (j is a natural number between 2 and M) among the M subscramble circuits.

6. 4. The scramble circuit according to claim 1, further comprising a flip-flop circuit inserted between said provisional scramble circuit and said EXOR circuit.

7. A scramble circuit according to any one of claims 1 to 3; a transmitter for transmitting the scrambled data output from the scrambling circuit to a communication path; a receiver for receiving the scrambled data from the communication path; a descrambling circuit for descrambling the scrambled data output from the receiver.

8. 1. A method for continuously scrambling a sequence of data, comprising: a step of dividing the series of data into L (L is a natural number) sets of data, each set consisting of L×k sets of data, and scrambling the data in k sequences in parallel by k temporary scrambling circuits; a step of calculating exclusive ORs of outputs of k pattern generating circuits which generate output data only from initial values ​​without inputting the series of data and outputs of the k temporary scrambling circuits by k EXOR circuits for each data of the same order, and outputting continuous scrambled data for the L×k data; A scrambling method comprising the steps of: setting a part of an output of an (i-1)th EXOR circuit as an initial value of an ith pattern generating circuit (i is a natural number between 2 and k) among said k pattern generating circuits.

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