Transmitting module for transmitting / receiving mechanism of subscriber station of serial bus system and method for transmitting messages by differential signals in serial bus system

Abstract

To provide a transmitting module, a transmitting / receiving mechanism, a subscriber station and a method for creating / generating a low emission bus signal.SOLUTION: In a serial bus system, a message transmission method is formed for transmitting a digital transmit signal (TXD_INT) as an analog differential signal (CAN_H, CAN_L) to a bus 40, the bits of a digital transmit signal having a larger bit duration in a second communication phase of the transmit signal. A transmitting module generates the bus state set by the digital transmit signal over time (t) by modifying the bus voltage and / or the bus impedance and changes through a predefined sequence of intermediate states for the bus voltage and / or the bus impedance. Furthermore, when the signaling changes during the transition between two set bus states, the transition is again successively reversed from the intermediate state previously reached in a sequence of reverse intermediate states.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The present invention relates to a transmission module for a transmission / reception mechanism of a subscriber station of a serial bus system and to a method for transmitting messages by differential signals in a serial bus system, in particular a CAN XL bus system. [Background technology]

[0002] In technical installations, like production facilities, vehicles etc., serial bus systems are often used for transmitting messages or data between e.g. sensors, actuators and control devices as subscriber stations. In the subscriber stations, a transmitting / receiving device, also called a transceiver, is connected to the bus of the bus system and transmits messages to the bus and / or receives messages from the bus.

[0003] With regard to CAN bus systems, CAN SIC or CAN XL are increasingly being used in addition to or instead of transmitting messages using the CAN protocol and / or CAN FD protocol as described in the standard ISO-11898-1:2015 CAN protocol specification with CAN FD. In CAN FD and its successors, such as CAN-SIC and CAN XL, the transmission on the bus alternates between a slower operating mode in the first communication phase (arbitration phase) and a faster operating mode in the second communication phase (data phase). CAN FD is used by most manufacturers in vehicles, for example with an arbitration bit rate of 500 kbit / s and a data bit rate of 2 Mbit / s.

[0004] Successor bus systems to CAN FD are compatible with CAN FD and are conceived for even greater data rates in the second communication phase. For CAN-SIC, based on the standard CiA601-4 from the organization CAN in Automation (CiA), data rates of approximately 5 to 8 Mbit / s are achieved in the second communication phase. For CAN XL, based on the standard CiA601-3, data rates of >10 Mbit / s are required in the second communication phase.

[0005] In the case of the bus systems CAN XL, CAN FD and CAN SIC, data is therefore transmitted to the bus in the second communication phase at a higher data rate than in the first communication phase. In the case of CAN XL, for this, not only do the bits of the transmission signal in the second communication phase have shorter bit durations or bit times or time lengths than in the first communication phase, but also usually must be transmitted to the bus at a different physical layer than in the first communication phase and must be received at a different reception threshold. As a result, in the case of CAN XL, the bus level of the bus signals CAN_H, CAN_L for the first communication phase can differ from the bus level of the second communication phase. This results in at least four different bus levels on the bus. In the case of CAN XL, the communication method in the second communication phase is also called FAST MODE. The physical layer corresponds to the bit transmission layer or layer 1 of the known OSI model (Open Systems Interconnection Model).

[0006] CAN XL communication therefore distinguishes at least four different voltages VCAN of the bus, which are given by the voltage difference of both CAN outputs (VCANH and VCANL) of the transmitting / receiving mechanism. In this respect, VCAN:=VCANH-VCANL applies. In addition to this, three to four different bus impedances R_IN are possible. R_IN is given by the impedance between both CAN outputs or the Z parameter. In total, five different bus output states are provided, characterized by VCAN and R_IN. These output states of the bus 40 are called dom, rec for the arbitration phase, Level1 and Level0 or LV1 and LV0 for the data phase 452 and sic. The sic state is an impedance-adapted recessive state, which corresponds to the rec state in terms of the bus voltage, but is generated with an output impedance of 100 Ω and is transmitted at the beginning of each rec state. The sic state reduces the occurrence and propagation of reflections in the bus network (wave conductor), which occur in classical CAN systems at high data rates. Switching between states is effected by signals transmitted from the subscriber station's communication control mechanism, which is connected to the transmit / receive mechanism.

[0007] However, a problem with the transmit / receive mechanism is that the transmit signaling a change of state is unpredictable, so at any time, even during the exact transition between two different bus states, external signaling may change such that a different final state is desired.

[0008] In addition to this, there is the problem that according to the CAN-XL standard, not all transitions between the listed states are allowed, so that in order to switch from a first to a second predefined state, the send / receive mechanism must sometimes perform so-called loops, if a direct transition between this first and second predefined state is not allowed.

[0009] Furthermore, each (allowed) transition is precisely defined in time. In this respect, abrupt bus state changes with abrupt changes in differential voltage or output impedance must not appear, because they would cause strong emissions and additional reflections that are contrary to the requirements for emissions and bus integrity.

[0010] What is needed is a CAN XL transmit / receive mechanism (transceiver) that avoids abrupt transitions on the bus during all operational phases of bus communication, to minimize emissions and reflections and ensure communication as error-free as possible. Summary of the Invention

[0011] It is therefore an object of the present invention to provide a transmitting module for a transmitting / receiving mechanism of a subscriber station of a serial bus system and a method for transmitting messages by differential signals in a serial bus system, which solves the problems listed above. In particular, a transmitting module for a transmitting / receiving mechanism of a subscriber station of a serial bus system and a method for transmitting messages by differential signals in a serial bus system should be provided, which allows for the creation / generation of a reliable, as error-free as possible and low-emission bus signal as inexpensively as possible, even if the external signaling changes during the just-occurring transition between two different bus states and therefore a different final state is desired than before the just-occurring transition began.

[0012] This problem is solved by a transmitting module for a transmission / reception mechanism of a subscriber station of a serial bus system having the features of claim 1, in which the transmitting module is configured for transmitting a digital transmission signal as an analog differential signal to a bus of the bus system in order to transmit a message to at least one other subscriber station of the bus system, whereby bits of the digital transmission signal in a first communication phase have a larger bit duration than in a second communication phase of the transmission signal, the transmitting module is configured for generating a bus state set over time by the digital transmission signal by changing the bus voltage and / or the bus impedance, the transmitting module is configured for changing the set bus state through a predefined sequence of intermediate states for the bus voltage and / or the bus impedance in the direction of the desired bus state, and the transmitting module is configured for successively returning the transition again from the intermediate state previously achieved in a sequence of intermediate states going backwards if the signaling changes during the transition between two set bus states.

[0013] With the described transmission module data rates clearly exceeding 40 MBps can be achieved without any problems. The described transmission module is designed in such a way that the topology of possible bus states is simplified. This is realized because loops no longer have to be implemented and any transition can be inverted. All transitions that can be represented by the transmission signal TXD_INT, FAST can be implemented with continuous differential voltages and output impedances.

[0014] Furthermore, the described transmission module can ensure that the final state of the bus is reached in the right time. For this purpose, each trigger, for example the signal TXD_INT, F_TM or the lapse of the time t_sic, individually initiates a fixed time sequence between a start time and an end time for the rising and falling edges of the bus state. This sequence may be called a delay chain or "delay chain". The sequence changes the bus state continuously and in the right time through defined intermediate states defined by the differential voltage and the bus impedance in the direction of the desired state. If the signaling changes during the transition between two bus states, the intermediate state then reached continues to exist, i.e. the current sequence is interrupted and then returned continuously in the right time by the reverse sequence.

[0015] In this way, the described transmit module ensures that the bus has no abrupt transitions in the differential voltages VBUS or VCAN and / or impedances, so that the transmit / receive mechanism generates little to no emissions and reflections within the bus system.

[0016] Another advantage is that the described transmission module allows very easy control between states, so that the transmission / reception mechanism can cover a large number of possibilities in time and in succession, thus guaranteeing a time-correct switching to the final state without abrupt transitions.

[0017] It is therefore highly advantageous that the described transmission module can guarantee compliance with the time window of the final valid transition, thereby not violating, inter alia, the CAN XL specification. In summary, the described transmission / reception mechanism ensures that communication within the bus system with other subscriber stations is not only possible at the high bit rates required for CAN XL, but also that the transmittable bit rate is not reduced by errors in the communication.

[0018] Advantageous further configurations of the transmission module are set out in the dependent claims. In one exemplary embodiment, the transmit module has synchronization logic for generating a predetermined sequence of intermediate states for bus voltage and / or bus impedance in the direction of a desired bus state.

[0019] In another exemplary embodiment, a transmit module is configured to generate different states of a digital transmit signal as dominant and recessive states on a bus, the transmit module being configured to generate transitions from the dominant state to the recessive state via impedance-matched recessive states that correspond to the recessive state in terms of bus voltage but are generated with a bus impedance different from the recessive state and transmitted at the start of each recessive state.

[0020] In another exemplary embodiment as mentioned above, the transmission module comprises, for example, a first switching chain for gradually changing the amplitude of the bus voltage and / or the value of the bus impedance in response to at least one edge of the transmission signal, a second switching chain for gradually changing the amplitude of the bus voltage and / or the value of the bus impedance in response to at least one edge of the inverted transmission signal, and a logic circuit connected to the first and second switching chains.

[0021] In one embodiment, each delay element in the first switching chain delays an edge of the inverted transmit signal by a predetermined amount, and each delay element in the second switching chain delays an edge of the transmit signal by a predetermined amount.

[0022] The first switching chain may have, inter alia, delay elements with switchable capacitors alternating with AND gates, these delay elements and the AND gates being connected in series, and the second switching chain may have, inter alia, delay elements with switchable capacitors alternating with AND gates, these delay elements and the AND gates being connected in series, and both the first switching chain and the second switching chain have delay elements at their beginning and end.

[0023] At least two of the delay elements of one switching chain may have switchable capacitors of different sizes. In the first and second switching chains, the outlet of each AND gate may be connected to the inlet of one of the delay elements.

[0024] In one form, the logic circuit has a predetermined number of logic elements. One of the logic elements may have one input connected to the output of the first delay element of the first delay chain, and one of the logic elements may have one input connected to the output of the first delay element of the second delay chain. In this regard, the logic element may be a flip-flop, a first input of the flip-flop being connected to a first input of one AND gate of the first switching chain, and a second input of the flip-flop being connected to a first input of one AND gate of the second switching chain.

[0025] The second input of the AND gate of the second switching chain may be connected to a terminal for inputting the digital transmit signal, and the second input of the AND gate of the first switching chain is connected to a terminal for inputting the inverted digital transmit signal.

[0026] Optionally, the transmitting module further comprises an edge detector for capturing a falling edge of the transmit signal, an edge detector for capturing a falling edge of an operating mode switching signal which signals to the transmitting module which operating mode the transmitting module should switch to instead of the current communication phase, an edge detector for capturing a rising edge of the transmit signal, and an edge detector for capturing a rising edge of the operating mode switching signal, and the logic circuit is formed to generate a predetermined sequence of intermediate states for the bus voltage and / or bus impedance in the direction of a desired bus state based on at least one capturing result of the edge detector.

[0027] The transmit module described above may be part of a transmit / receive mechanism that additionally has a receive module for receiving signals from the bus and for generating a digital receive signal from the analog differential signal.

[0028] In some cases, the transmit module may be configured to generate analog differential signals for a first communication phase of a message at a different physical layer than for a second communication phase.

[0029] The above-described transmission / reception mechanism may be part of a subscriber station for a serial bus system. The subscriber station may additionally have a communication control mechanism for controlling communication within the bus system and for generating the first transmission signal. The subscriber station may be configured for communication within the bus system in which at least temporarily exclusive and collision-free access of one subscriber station to the bus of the bus system is guaranteed.

[0030] The above-mentioned problem is further solved by a method for transmitting messages by differential signals in a serial bus system having the features of claim 17. The method is performed by a transmitting module of a transmitting / receiving arrangement, the transmitting module being configured for transmitting a digital transmit signal as an analog differential signal to a bus of the bus system in order to transmit a message to at least one other subscriber station of the bus system, whereby bits of the digital transmit signal in a first communication phase have a larger bit duration than in a second communication phase of the transmit signal, and the method comprises the step of generating a bus state set over time by the digital transmit signal by changing the bus voltage and / or the bus impedance, the transmitting module being configured for changing the set bus state through a predefined sequence of intermediate states for the bus voltage and / or the bus impedance in the direction of the desired bus state, and the transmitting module being configured for successively returning the transition again from the intermediate state previously achieved in a sequence of intermediate states going backwards if the signaling changes during the transition between two set bus states.

[0031] This method offers the same advantages as those listed above in connection with the transmission module. Further possible implementations of the present invention also include not explicitly mentioned combinations of the features or embodiments described above or below in relation to the exemplary embodiments, in which case the skilled person will also add individual aspects as improvements or supplements to the respective basic form of the invention.

[0032] The invention will now be explained in more detail with reference to the accompanying drawings and on the basis of exemplary embodiments. [Brief description of the drawings]

[0033] [Figure 1] FIG. 1 is a simplified block diagram of a bus system according to a first exemplary embodiment; [Diagram 2]FIG. 2 is a schematic diagram for illustrating the structure of a message that can be transmitted from a subscriber station of the bus system according to the first exemplary embodiment; [Diagram 3] 3 is a diagram showing an example of an ideal progression over time of bus signals CAN_H, CAN_L transmitted from a subscriber station of the bus system to a bus of the bus system for the message of FIG. 2; [Figure 4] 4 shows the course over time of a differential voltage VDIFF which is identical to the bus voltage VBUS, in particular to VCAN, and which is generated on the bus of the bus system as a result of the bus signals of FIG. [Diagram 5] 2 is a diagram showing an example of a time progression of a digital transmission signal to be converted into bus signals CAN_H, CAN_L for the bus of the bus system of FIG. 1 in an arbitration phase (SIC operation mode). FIG. [Figure 6] FIG. 6 is a diagram showing the transition over time of the bus signals CAN_H and CAN_L transmitted to the bus based on the transmission signal of FIG. 5 during the arbitration phase (SIC operation method) as they change from a recessive bus state to a dominant bus state and then back to the recessive bus state. [Figure 7] 2 is a diagram showing an example of a time progression of a digital transmission signal to be converted into bus signals CAN_H, CAN_L for the bus of the bus system of FIG. 1 in a data phase. [Figure 8] 8 is a diagram showing the transition over time of bus signals CAN_H and CAN_L transmitted to the bus based on the transmission signal of FIG. 7 in the data phase. [Figure 9] 2 is a block diagram of a transmission / reception mechanism for a subscriber station of a bus system according to a first exemplary embodiment; [Figure 10]9. (A) is a diagram showing signal progression over time in the transmission / reception mechanism of FIG. 9. (B) is a diagram showing signal progression over time in the transmission / reception mechanism of FIG. 9. (C) is a diagram showing signal progression over time in the transmission / reception mechanism of FIG. 9. (D) is a diagram showing the progression over time of bus signals CAN_H, CAN_L transmitted from the transmission / reception mechanism of FIG. 9 to the bus of the bus system as a result of the signals (A) to (C). (E) is a diagram showing the required bus states of the bus signals CAN_H, CAN_L of (D) and the value of the bus voltage VBUS attributed thereto, which are directed or generated by the transmission / reception mechanism of FIG. 9 over time t. (F) is a diagram showing the progression over time of the impedance R_IN adjusted by the transmission / reception mechanism of FIG. 9 to generate the state of the bus signals CAN_H, CAN_L of (D) or (E). [Figure 11] 10 is a block diagram of a transmission module according to a first exemplary embodiment for the transmission / reception arrangement of FIG. 9; [Figure 12] FIG. 12 is an electrical circuit diagram of a delay element of the transmission module of FIG. [Figure 13] 12 is a graph illustrating the progression of the bus voltage generated by the transmit module of FIG. 11 over time t to transition from a first state to a second state. [Figure 14] FIG. 2 is a schematic diagram for illustrating a switching sequence of a transmission module based on a first exemplary embodiment. [Figure 15] FIG. 2 is a schematic diagram for illustrating a switching sequence of a transmission module based on a first exemplary embodiment. [Figure 16] FIG. 11 is a schematic diagram for illustrating a switching sequence of a conventional transmission module of a bus system according to a second exemplary embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] In the figures, identical elements or elements with identical functions are provided with the same reference numbers unless otherwise stated. 1 shows a bus system 1 which may for example be at least partly a CAN bus system, a CAN-FD bus system, etc. The bus system 1 may be used in vehicles, especially automobiles, airplanes, etc. or in hospitals, etc.

[0035] 1, a bus system 1 comprises a number of subscriber stations 10, 20, 30, which are respectively connected to a bus 40 or bus line having a first bus conductor 41 and a second bus conductor 42. The bus conductors 41, 42 may also be referred to as CAN_H and CAN_L for signals on the bus 40. Via the bus 40, messages 45, 46, 47 can be transmitted in the form of signals between the individual subscriber stations 10, 20, 30. The subscriber stations 10, 20, 30 are, for example, controls or displays of a motor vehicle.

[0036] 1, each of the subscriber stations 10, 30 includes a communication control mechanism 11 and a transmission / reception mechanism 12. The transmission / reception mechanism 12 includes a transmission module 121 and a reception module 122.

[0037] The subscriber station 20 includes a communication control mechanism 21 and a transmission / reception mechanism 22. The transmission / reception mechanism 22 includes a transmission module 221 and a reception module 222. The transmit / receive mechanism 12 of the subscriber stations 10, 30 and the transmit / receive mechanism 22 of the subscriber station 20 are each directly connected to the bus 40, even though it is not represented in FIG.

[0038] The communication control mechanisms 11 , 21 are used to control the communication of a respective subscriber station 10 , 20 , 30 via the bus 40 with at least one other of the subscriber stations 10 , 20 , 30 connected to the bus 40 .

[0039] The communication control mechanism 11 creates and reads first messages 45, 47, which are for example modified CAN messages 45, 47. In this regard, the modified CAN messages 45, 47 are for example built on the basis of the CAN XL format. The transmission / reception mechanism 12 is used for transmitting and receiving the messages 45, 47 on the bus 40. The transmission module 121 receives a digital transmission signal TxD created by the communication control mechanism 11 for one of the messages 45, 47 and converts this digital transmission signal TxD into a signal for the bus 40. The digital transmission signal TxD can be, at least temporarily or partially, a pulse width modulated signal. The reception module 122 receives signals corresponding to the messages 45-47 transmitted on the bus 40 and generates a digital reception signal RxD on the basis of them. The reception module 122 transmits the reception signal RxD to the communication control mechanism 11.

[0040] In addition to this, the communication control mechanism 11 may be configured for creating and reading a second message 46, for example a CAN SIC message 46. The send / receive mechanism 12 may be configured accordingly.

[0041] The communication control mechanism 21 may be manufactured like a conventional CAN controller based on ISO 11898-1:2015, that is, like a CAN FD-tolerant classical CAN controller, CAN FD controller, or CAN SIC controller. The communication control mechanism 21 creates and reads a second message 46, for example, a CAN FD message or a CAN SIC message. The transmission / reception mechanism 22 is used to transmit and receive the message 46 on the bus 40. The transmission module 221 receives a digital transmission signal TxD created by the communication control mechanism 21 and converts the digital transmission signal TxD into a signal for the message 46 to the bus 40. The reception module 222 receives signals corresponding to the messages 45 to 47 transmitted on the bus 40, and generates a digital reception signal RxD based on the signals. The transmission / reception mechanism 22 may be manufactured like a conventional CAN FD transceiver or CAN SIC transceiver in some cases.

[0042] The transmission of messages 45, 46, 47 using CAN SIC or CAN XL retains the well-established properties that make CAN and CAN FD robust and easy to use, in particular the frame structure with identifiers and arbitration based on the known CSMA / CR method, in which so-called recessive states must exist on the bus 40, which can be overwritten by other subscriber stations 10, 20, 30 with a dominant level or state on the bus 40.

[0043] Both subscriber stations 10, 30 allow the formation and subsequent transmission of messages 45, 47 having different CAN formats, in particular the CAN FD format or the CAN SIC format or the CAN XL format, as well as the reception of such messages 45, 47. This will be explained more precisely with respect to the message 45 below.

[0044] 2 shows a frame 450, notably a CAN XL frame, as provided by the communication control mechanism 11 to the transmit / receive mechanism 12 for transmission to the bus 40 for the message 45. In this regard, the communication control mechanism 11 creates the frame 450 as being compatible with CAN FD in this exemplary embodiment. Alternatively, the frame 450 is compatible with any successor standard of CAN FD.

[0045] 2, a frame 450 for CAN communication on the bus 40 is partitioned into different communication phases 451, 452, in particular an arbitration phase 451 (first communication phase) and a data phase 452 (second communication phase). After a start bit SOF, the frame 450 has an arbitration field 453, a control field 454, a first switching field 455, a data field 456, a checksum field 457, a second switching field 458, and an end of frame field 459. The checksum field 457, the second switching field 458, and the end of frame field 459 constitute the frame end phases 457, 458, 459 of the frame 450.

[0046] In the arbitration phase 451, it is decided bit by bit between the subscriber stations 10, 20, 30, using an identifier (ID) in the arbitration field 453, which subscriber station wants to transmit a message 45, 46 with the highest priority and therefore has exclusive access to the bus 40 of the bus system 1 at the next time for transmission in the subsequent data phase 452. In the arbitration phase 451, a physical layer is used, as in CAN and CAN-FD, which corresponds to the bit transmission layer or layer 1 of the known OSI model (Open Systems Interconnection Modell).

[0047] During phase 451 the known CSMA / CR method is used, which allows simultaneous access of subscriber stations 10, 20, 30 to the bus 40 without higher priority messages 45, 46 being corrupted. This allows further bus subscriber stations 10, 20, 30 to be added to the bus system 1 relatively easily, which is highly advantageous.

[0048] In the CSMA / CR method, so-called recessive states must exist on the bus 40, which can be overwritten by other subscriber stations 10, 20, 30 with dominant levels or states on the bus 40. In the recessive states, a high resistance situation prevails in the individual subscriber stations 10, 20, 30, which in combination with the parasitics of the bus wiring results in longer time constants. This limits the maximum bit rate of today's CAN-FD physical layer to about 2 Mbit / s for real-world in-vehicle use today.

[0049] At the end of the arbitration phase 451 , a first switch field 455 switches to the data phase 452 . In the data phase 452, the payload of the CAN-XL frame 450 or message 45 consisting of a data field 456 is transmitted together with a portion of a first switch field 455, as well as a checksum field 457 and a portion of a second switch field 458. At the end of the data phase 452, the second switch field 458 switches back to the arbitration phase 451 again.

[0050] Only if the subscriber station 10 wins the arbitration as the sender, thereby giving the subscriber station 10 as the sender exclusive access to the bus 40 of the bus system 1 for transmission, does the sender of the message 45 start transmitting the bits of the data phase 452 onto the bus 40.

[0051] Thus, in the first communication phase, the arbitration phase 451, the subscriber station 10, 30 uses a format based on ISO 11898-1:2015 known from CAN / CAN-FD, in particular up to the FDF bit, but in the second communication phase, the data phase 452, the net data transmission rate can be increased, in particular to more than 10 Mbit / s, compared to CAN or CAN FD, and the payload size per frame can be increased, in particular to about 2 Kbytes or any other value.

[0052] As shown in Fig. 3, the transmit / receive mechanism 12 uses, in the arbitration phase 451, a first physical layer 451_P in order to transmit the transmit signal TxD (Fig. 1) as signals CAN_H, CAN_L along the time t to the bus 40. The same applies to the transmit / receive mechanism 22. In contrast to this, as already explained above, the transmit / receive mechanism 12 may use, in the data phase 452, a second physical layer 452_P, different from the first physical layer 451_P, in order to transmit the transmit signal TxD (Fig. 1) as signals CAN_H, CAN_L to the bus 40. With regard to the physical layer 452_P, there are two operating modes, in particular FAST_TX and FAST_RX, as will be explained more precisely later.

[0053] 3 shows on the left side that the subscriber stations 10, 20, 30 transmit signals CAN_H, CAN_L, respectively, having a first bit duration t_bt1, to the bus 40 along time t in an arbitration phase 451. The signals CAN_H, CAN_L are serial signals and alternately have at least one dominant state 401, in which VCAN_H=3.5V and VCAN_L=1.5V apply, or at least one recessive state 402, in which VCAN_H=VCAN_L=2.5 apply. The dominant state 401 (dom) is driven if, in the case of NRZ coding of the transmission signal TXD in phase 451, TXD=0 or LW (LOW=low). The recessive state 402 (rec) is generated or arises if, in the case of NRZ coding of the transmission signal TXD in phase 451, TXD=1 or HI (HIGH) applies. After arbitration in arbitration phase 451, one of the subscriber stations 10, 20, 30 is determined to be the winner.

[0054] 2 for switching from the first to the second communication phase 451, 452, the associated transmit / receive mechanism 12 switches its physical layer 451_P to the physical layer 452_P of the data phase 452 at the end of the arbitration phase 451 of the first operating mode (SLOW) (which may alternatively be implemented as a SIC operating mode). In this regard, the operating mode of the data phase 452 is turned on as follows:

[0055] Assume that the first subscriber station 10 wins the arbitration. In this case, since the subscriber station 10 is the sender of the message 45 in the data phase 452, the transmission / reception mechanism 12 of the subscriber station 10 switches its physical layer 451_P to the physical layer 452_P of the data phase 452 for the second operation mode (FAST_TX) of the transmission / reception mechanism 12 at the end of the arbitration phase 451 of the first operation mode (SLOW) based on the signaling in particular in the first switching field 455 of Fig. 2. As shown in Fig. 3, the transmission module 121 in this case generates the state LV0 or LV1 by the physical layer 452_P for the signals CAN_H, CAN_L on the bus 40 in the data phase 452 or in the second operation mode (FAST_TX) sequentially, thus serially, depending on the transmission signal TxD. State LV0 (VCAN_H=3.0V, VCAN_L=2.0V) is driven for a first PWM symbol in the transmit signal TXD in case of pulse width modulation (PWM coding) of the transmit signal TXD. State LV1 (VCAN_H=2.0V and VCAN_L=3.0V) is driven for a second PWM symbol, different from the first PWM symbol, in the transmit signal TXD in case of pulse width modulation (PWM coding) of the transmit signal TXD.

[0056] The frequency of signals CAN_H, CAN_L may be increased in data phase 452. In this regard, in the example of Fig. 3, the bit time or bit duration t_bt2 in data phase 452 is shorter or less than the bit time or bit duration t_bt1 in arbitration phase 451. Thus, the net data transmission rate in data phase 452 is increased compared to arbitration phase 451 in the example of Fig. 3.

[0057] In contrast, for example, since the subscriber station 30 is merely a receiver of the frame 450 in the data phase 452, i.e., not a sender, the transmit / receive mechanism 12 of the subscriber station 30 switches its physical layer 451_P to a physical layer 452_P in the data phase 452 for the third operating mode (FAST_RX) of the transmit / receive mechanism 12 at the end of the arbitration phase 451 of the first operating mode (SLOW or SIC).

[0058] When the transmitting / receiving mechanism 12 recognizes, notably by signaling in the second switching field 458 of Fig. 2, that a switch from the data phase 452 back to the arbitration phase 451 should be made, the transmitting / receiving mechanism 12 switches from transmitting (operating scheme FAST_TX) (and) or receiving (operating scheme FAST_RX) signals by the physical layer 452_P to transmitting and / or receiving signals by the physical layer 451_P. This causes all transmitting / receiving mechanisms 12 to switch their operating scheme to the first operating scheme (SLOW or SIC) after the end of the data phase 452. Thus, as explained above, all transmitting / receiving mechanisms 12 may not only switch their bit durations t_bt1, t_bt2, but also their physical layer.

[0059] The corresponding signal transitions in the transmission / reception mechanism 12 when switching from phase 451 to phase 452, during the data phase 452, and when switching from phase 452 back to phase 451 will be explained more precisely later on the basis of FIGS. 10(A-F).

[0060] According to Fig. 4, in the ideal case, during arbitration phase 451, along time t, a differential signal VDIFF=CAN_H-CAN_L is generated on bus 40 with a value of VDIFF=2V for dominant state 401 (dom) and VDIFF=0V for recessive state 402 (rec). The progression of VDIFF during phase 451 is shown on the left side of Fig. 4. In contrast, during data phase 452, as shown on the right side of Fig. 4, along time t, a differential signal VDIFF=CAN_H-CAN_L is generated on bus 40 corresponding to states LV0 and LV1 of Fig. 4. State LV0 has a value of VDIFF=1V. State LV1 has a value of VDIFF=-1V.

[0061] The receiving module 122 can distinguish between the states 401, 402 by two receiving thresholds T1, T2, T3, respectively, which are in the ranges TH_T1, TH_T2, TH_T3. In this regard, the receiving module 122 samples the signal of FIG. 3 or FIG. 4 at the time t_A as shown in FIG. 4. To evaluate the sampling result, the receiving module 122 uses a receiving threshold T1, for example 0.7V, and a receiving threshold T2, for example −0.35V, in the arbitration phase 451. In contrast, the receiving module 122 uses only the signal evaluated at the receiving threshold T3 in the data phase 452. When switching between the first to third operating modes (SLOW or SIC, FAST_TX, FAST_RX) described above in connection with FIG. 3, the receiving module 122 switches between the receiving thresholds T2, T3, respectively.

[0062] The reception threshold T2 is useful for recognizing whether the bus 40 is free when a subscriber station 10 is newly connected to and attempts to be incorporated into communication on the bus 40. 1, each transmit / receive mechanism 12 generates an associated receive signal RxD upon receiving a corresponding signal from the bus 40. The receive signal RxD ideally has no time offset with respect to the transmit signal TxD.

[0063] Fig. 5 shows an example of a portion of the digital transmit signal TxD, which the transmit module 121 receives from the communication control mechanism 11 during the arbitration phase 451 and uses as a basis to generate the signals CAN_H and CAN_L for the bus 40. In Fig. 5, the transmit signal TxD transitions from a state HI (high) to a state LW (low), and then returns to a state HI (high).

[0064] As shown more precisely in Fig. 6, the transmitting module 121 generates the signals CAN_H, CAN_L for the bus conductors 41, 42 for the transmit signal TxD of Fig. 5, in which there is additionally a state 403(sic). The state 403(sic) may be of different duration, as shown by the state 403_0(sic) at the transition from state 402(rec) to state 401(dom) and the state 403_1(sic) at the transition from state 401(dom) to state 402(rec). The state 403_0(sic) is shorter in time than the state 403_1(sic). To generate the signals according to Fig. 6, the transmitting module 121 is switched to a SIC mode of operation (SIC mode).

[0065] The implementation of the short sic state 403_0 is not required by CiA 610-3 and this state is implementation type dependent. The duration of the "long" state 403_1 (sic) is t_sic<530ns starting from the rising edge of the transmit signal TxD in FIG. 5 for CAN-SIC and also for the SIC operation method in case of CAN-XL.

[0066] In the "long" state 403_1 (sic), the transmitting module 121 should match the impedance between the bus conductors 41 (CANH) and 42 (CANL) as closely as possible to the characteristic impedance Zw of the bus line used. In this respect, Zw=100 ohms or 120 ohms. This matching prevents reflections and therefore allows operation at higher bit rates. For simplicity, in the following it is always referred to as state 403 (sic) or sic state 403.

[0067] The transmitting module 121 can be used to generate signals for the bus 40 for the following CAN types: CAN-FD, CAN-SIC, and CAN-XL.

[0068] [Table 1]

[0069] Thus, the state 403(sic) of the transmitting module can not only be generated in the case of CAN-SIC or CAN-XL (xl_sic), but can also be generated in the case of CAN-FD, where the time of the state 403(sic) of the transmitting module can be shorter than in the case of CAN-SIC or CAN-XL.

[0070] Fig. 7 shows an example of another part of the digital transmission signal TxD, which the transmission module 121 receives from the communication control mechanism 11 in the data phase 452 and generates signals CAN_H and CAN_L for the bus 40 based on the digital transmission signal TxD. In Fig. 7, the transmission signal TxD changes several times, from a state HI (high = High) to a state LW (low = Low), then back to a state HI (high = High), and then again.

[0071] As shown more precisely in Fig. 8, the transmission module 121 generates, for a transmission signal TxD of Fig. 7, the signals CAN_H, CAN_L for the bus conductors 41, 42, such that for a state LW (Low=Low) a state LV0 is formed and in addition for a state HI (High=High) a state LV1 is formed.

[0072] Fig. 9 shows the basic structure of the subscriber station 10 with the communication control mechanism 11 and the transmission / reception mechanism 12. To explain its function, Fig. 10(A) shows the transmission signal TXD generated by the communication control mechanism 11 and transmitted to the transmission / reception mechanism 12 along the time t. In this regard, along the time t and in the upper part of Fig. 10(A), the division of the signal TXD into two communication phases 451, 452 and switching fields 455, 458 is also presented. In addition, in Fig. 10(A), the individual bits of the two communication phases 451, 452 are also named. Fig. 10(B) and Fig. 10(C) show the signals TXD_INT and F_TM generated by the transmission / reception mechanism 12 from the signal TXD along the time t. Fig. 10(D) shows the signals CAN_H, CAN_L transmitted by the transmission / reception mechanism 12 to the bus 40 as a result.

[0073] According to Fig. 9, the subscriber station 10 also comprises a microcontroller 13 and a system ASIC (ASIC = Application Specific Integrated Circuit) 14. The system ASIC may be independent of the transmit / receive mechanism 12, which is thus an independent device, also called a stand-alone transceiver. The system ASIC 14 comprises digital components 141, 142, 143, which receive signals from the transmit / receive mechanism 12 and may evaluate or further process them, inter alia, for diagnostic purposes.

[0074] The microcontroller 13 generates or processes data which must be converted by the communication control mechanism 11 into the appropriate frame format for transmission of messages 45 , 47 over the bus 40 .

[0075] The communication control mechanism 11 may be formed as a protocol controller for transmitting and / or receiving CAN XL messages 45, 47. Optionally, the communication control mechanism 11 is formed for transmitting and / or receiving CAN FD or CAN SIC messages 46. To transmit data to the bus 40, the communication control mechanism 11 generates a transmit signal TXD according to the corresponding standard for CAN FD, CAN SIC or CAN XL messages 45, 47. The mechanism 11 outputs the transmit signal TXD at a terminal TxD to a terminal TxD of the transmit / receive mechanism 12. The mechanism 12 and the system ASIC 14 each have a terminal TxD and RxD.

[0076] The system ASIC 14 of the subscriber station 10 of Fig. 9 may instead be a system base chip (SBC) in which several functions necessary for the electronics assembly of the subscriber station 10 are integrated. In addition to the transmitting / receiving mechanism 12, an energy supply mechanism (not shown) may be fitted in the system ASIC 14, which supplies the transmitting / receiving mechanism 12 with electrical energy at a terminal 43. The energy supply mechanism provides a voltage CAN_Supply, typically 5V. However, the energy supply mechanism may provide other voltages of other values ​​if required. Additionally or alternatively, the energy supply mechanism is formed as a current source. A terminal 44 is used for connection to ground, also called CAN-GND.

[0077] In the example of Fig. 9, the transmitting / receiving mechanism 12 further comprises a protection module 120, a transmission signal buffer module 123, an oscillation module 124, a transmission signal evaluation module 125, a reception signal buffer module 126, and a recovery module 127 in addition to the transmission module 121 and the reception module 122. In Fig. 9, the modules 121 to 127 are only represented in a simplified manner. The transmission module 121 comprises a logic 1210 and may optionally use parameters stored in a memory block 1219. The transmission signal evaluation module 125 is also referred to as the evaluation module 125 below.

[0078] The protection module 120 is connected to the bus conductors 41, 42 and is used to protect the transmitting / receiving mechanism 12 against electrostatic discharge (ESD).

[0079] The transmission signal TXD received from the mechanism 11 is temporarily stored in the transmission signal buffer module 123. As mentioned above in relation to Fig. 3 and shown by way of example in Fig. 10(A), the transmission signal TXD at the terminal TxD of the mechanism 11 is a transmission signal that is at least temporarily or partially pulse width modulated in the case of a CAN XL. The transmission signal buffer module 123 outputs the transmission signal TXD_EXT to the digital component 141 and the transmission signal TXD_B to the evaluation module 125. The evaluation module 125 additionally receives an oscillation signal OSC having a predetermined frequency f from the oscillation module 124.

[0080] The evaluation module 125 is configured to forward and / or process the transmission signal TXD_B using the oscillation signal OSC. In a first communication phase 451 of the message 45, in which the transmission signal TXD is not pulse-width modulated (PWM), as shown in FIG. 10(A) for the data states D1, D2, D3, the resXL bit, and the bits AH1, AL1, the evaluation module 125 forwards the transmission signal TXD_B as is to the transmission module 121. In a second communication phase 452 of the message 45, in which the transmission signal TXD is pulse-width modulated (PWM), as also shown in FIG. 10(A) for the bits B1, B2, B3, FCP1, FCP0, DAH, the evaluation module 125 performs a pulse-width demodulation of the transmission signal TXD_B. The transmission signal TXD_INT output from the evaluation module 125 to the transmission module 121 is thus a decoded or pulse-width demodulated transmission signal, as shown in FIG. 10(B).

[0081] According to Fig. 10(B), in the fast operating scheme FAST, a distinction is made between both TXD symbols LL0 or Level0 (PWM duty cycle < 50%) and LL1 or Level1 (PWM duty cycle > 50%). The symbol Level0 of TXD_INT is represented by LL0 in Fig. 10(B) and corresponds to state LV0 in Fig. 10(D) and state L0 in Fig. 10(E). The symbol Level1 of TXD_INT is represented by LL1 in Fig. 10(B) and corresponds to state LV1 in Fig. 10(D) and state L1 in Fig. 10(E). The evaluation module 125 signals the transmission module 121 to switch back to the operating scheme SLOW or SIC with the signal F_TM as soon as the PWM coding according to CiA610-3 is transitioned to NRZ coding, in which there are not two successive edges of the same direction within a set time window. The transmitting module 121 thereby converts the signal TXD_INT back to a recessive or dominant bus voltage or state sic as explained above in relation to Figures 3 to 8. The signal F_TM is an operating mode switching signal that can signal the transmitting module 121 to switch to a given operating mode for the communication phases (451, 452) in order to generate the analog differential signals CAN_H, CAN_L for the bus 40.

[0082] According to Fig. 9, the evaluation module 125 additionally outputs a signal F_TM to the transmitting module 121 and a signal F_RC to the receiving module 122. The signal F_TM is shown, for example, in Fig. 10(C). The signals F_TM, F_RC signal or indicate which physical layers the modules 121, 122 should turn on, in particular whether or not the physical layer 452_P (Fig. 3) for the data phase 452 should be turned on.

[0083] The transmitting module 121 is configured to convert the transmission signal TXD_INT of the evaluation module 125, as explained above in relation to Figures 3 to 8, into signals CAN_H, CAN_L according to Figure 10(D) for the bus 40. The transmitting module 121 is directly connected to the bus 40 via the terminals CANH, CANL for the bus conductors 41, 42 in order to transmit to the bus 40 analog signals CAN_H, CAN_L based on the transmission signal TXD_INT.

[0084] In this regard, as illustrated in Fig. 10(E) and Fig. 10(F) to be viewed together with Fig. 10(B)-(D), the transmitting module 121 is formed as follows: the transmitting module 121 generates a state 401 (dom) represented by the letter D in Fig. 10(E) or a state 402 (rec) represented by the letter R in Fig. 10(E) or a state 403 (sic) represented by the letter S in Fig. 10(E) or a state L0 or a state L1 in response to the signaling by the transmitting signal TXD or TXD_INT and the signal F_TM. To this end, the transmitting module 121 selects a voltage value of the bus voltage VBUS as shown in Fig. 10(E) and / or a value of the impedance R_IN as shown in Fig. 10(F), where ND stands for undefined and ∞ stands for infinity, in response to the signaling by the transmitting signal TXD or TXD_INT and the signal F_TM. The form and function of the transmission module 121 for this purpose will be explained more precisely below on the basis of FIGS. 10(E) to 15 and also on the basis of FIG.

[0085] According to Fig. 9, the receiving module 122 is also directly connected to the bus 40 via the terminals CANH, CANL for the bus conductors 41, 42. The receiving module 122 is formed to generate a digital receiving signal RXD from the signals CAN_H, CAN_L received at the terminals CANH, CANL from the bus 40. The receiving module 122 transmits or forwards the receiving signal RXD to a receiving signal buffer module 126. The receiving module 122 further forwards the signals CAN_H, CAN_L to a wake-up module 127. The wake-up module 127 can also use the digital component 143 to determine whether the communication control mechanism 11 should be woken up again after it has gone to sleep, for example to save energy.

[0086] The receive signal buffer module 126 outputs the receive signal RXD to a terminal RxD of the microcontroller 13 or the communication control mechanism 11 via a terminal RxD of the system ASIC 14 or the transmit / receive mechanism 12. In addition, the receive signal buffer module 126 transfers the receive signal RXD to the digital component 142.

[0087] 11 shows more precisely the transmission module 121 of FIG. 9. FIG. 12 shows the electrical circuit of the delay element of the transmission module 121. According to FIG. 11, the transmission module 121 receives the transmission signal TXD of FIG. 10(A), more precisely the signal TXD_INT and the inverted signal TXD_INT of FIG. 10(B).

[0088]

number

[0089] 10D on the bus 40. The signal amplitude stages or intermediate states S1, S2 to SN-1, SN are used to generate the signals CAN_H, CAN_L on the bus 40 according to FIG. 10D. The signal amplitude stages or intermediate states S1, S2 to SN-1, SN are used to generate the signal TXD, the signal TXD_INT derived therefrom, and its inverted signal TXD_INT.

[0090]

number

[0091] 13 for the example of N=27, with the number N not necessarily being 27, but being any natural number that can be chosen.

[0092] According to FIG. 11, the transmission module 121 for this purpose comprises a first switching chain 1211 in the forward direction, a second switching chain 1212 in the reverse direction and N logic elements LG1, LG2, . . . , SN-1, SN, which generate signal steps or states S1, S2, . . . , SN-1, SN. 1 ...LG N The logic 1210 includes a logic circuit 1213 having a logic circuit 1214, an edge evaluation unit 1214 having edge detectors 1215, 1216, and an inverter 1217. 1 ~LG N For example, as shown in FIG. 11, the inlets S and R and the outlet Q,

[0093]

number

[0094] A flip-flop with N>0, specifically a D flip-flop.

[0095]

number

[0096] is the inverted exit Q. The inverter 1217 inverts the signal TXD_INT, i.e., the inverted signal

[0097]

number

[0098] Generate. The edge evaluation unit 1214 evaluates the signal F_TM and the transmission signal TXD_INT using edge detectors 1215, 1216. The edge detector 1215 detects whether a rising edge occurs in the signal being observed. The edge detector 1216 detects whether a falling edge occurs in the signal being observed.

[0099] Each of the first switching chains 1211 includes N delay elements D FWD1 , D FWD2 , D FWD3 , ...D FWDN There are N delay elements D FWD1 , D FWD2 , ...D FWDN Each of the N logic elements LG 1 ~LG N The delay elements D FWD1 , D FWD2 , D FWD3 , ...D FWDN Each of the delay elements D FWD1 , D FWD2 , ...D FWDN-1 In FIG. 11, an AND gate is placed after the N-th delay element D FWDN does not have a trailing AND gate. Each delay element D FWD1 , D FWD2 , D FWD3 , ...D FWDN The delay elements t_D1 to t_DN delay the edges of the signals input from the AND gates to the inputs of the delay elements associated with them. The edge delay times t_D1 to t_DN can be stored as parameters in the memory block 1219. One input of each AND gate receives an inverted signal

[0100]

number

[0101] The other inlet of each AND gate is connected to the terminal for the preceding delay element D FWD1 , D FWD2 , D FWD3 , ...D FWDN-1 At the exit of, and assigned logic element LG 1 ...LG N It is connected to one of the inlets S.

[0102] The second switching chains 1212 each include N delay elements D BWD1 , D BWD2 , ...D BWDN There are N delay elements D BWD1 , D BWD2 , D BWD3 , ...D BWDN Each of the N logic elements LG 1 ...LG N The delay elements D BWD1 , D BWD2 , D BWD3 , ...D BWDN Each of the delay elements D BWD1 , D BWD2 , D BWD3 , ...D BWDN-1 In FIG. 11, the Nth delay element D BWDN does not have a trailing AND gate. Each delay element D BWD1 , D BWD2 , D BWD3 , ...D BWDN delays in time the edge of the signal coming from the AND gate to the input of the delay element associated with it. The delay time t_D of the edge can be stored as a parameter in the memory block 1219. The same applies here as explained above for the first switching chain 1211. One input of each AND gate is connected to a terminal for the signal TXD_INT. The other input of each AND gate is connected to a terminal for the preceding delay element D, as shown in FIG. BWD1 , D BWD2 , D BWD3 , ...D BWDN-1At the exit of, and assigned logic element LG 1 ...LG N is connected to one of the inlets R.

[0103] Each individual delay element D FWD1 , D FWD2 , ...D FWDN The delay times t_D1, t_D2, t_D3 to t_DN correspond to individual time slices. FWD1 , D FWD2 , ...D FWDN The delay times t_D1, t_D2, t_D3 to t_DN are summed together to produce the total sequence or delay t_S as shown in FIG. 13. The same applies to the N delay elements D BWD1 , D BWD2 , D BWD3 , ...D BWDN This applies to:

[0104] In one embodiment, the individual time slices, more precisely the delay times t_D1, t_D2, t_D3 to t_DN, relative to the length of the entire sequence / delay t_S are so to speak "hardwired". This is realized according to Fig. 12 by a predefined size of an electrical capacitor 1211C, which is selected for one time slice or the delay element belonging thereto and is chargeable with a switchable reference current I. In this regard, the N delay elements D FWD1 , D FWD2 , D FWD3 , ...D FWDN Each of the delay elements D FWD1 In addition, N delay elements D BWD1 , D BWD2 , D BWD3 , ...D BWDN Each of them is constructed accordingly.

[0105] According to FIG. 12, the electric capacitor 1211C is connected in parallel to the switch 1211S and is charged to the voltage U_C or discharged again by the current I. The current I is connected to the delay element D of FIG. FWD1In the case of , the input is fed into the junction between switch 1211S and capacitor 1211C, which is connected to the input of inverter 1211J. Switch 1211S is connected to element D FWD1 Now, the inverted signal

[0106]

number

[0107] The switch 1211S is controlled by an input signal S_I, which is: The switch 1211S is for example a semiconductor switch, in particular an NMOS switch (NMOS=n-type doped metal oxide semiconductor).

[0108] Delay element D FWD1 If the switch 1211S in is an NMOS switch, the following applies: As soon as the input signal S_I has a low or 0 (=Low) value, the switch 1211S cuts off and the capacitor 1211C is charged with a current I to a voltage U_C. As soon as the threshold voltage U_TH of the inverter 1211J is reached, i.e. U_C=U_TH, the signal S_O at the output of the inverter 1211J changes to a low or 0 (=Low) value. The output signal S_O is input to the following AND gate (FIG. 11) and the inverted signal

[0109]

number

[0110] After evaluating the delay element D FWD2 This controls the switch 1211S of the switching chain 1211 in sequence. N delay elements D FWD1 , D FWD2 , ...D FWDN When the input signal S_I at one of the delay elements transitions to a high or 1 (=High) value, the capacitor 1211C in this delay element is discharged again via the switch 1211S, proceeding backwards through the switching chain 1211 described above.

[0111] The magnitude of the electrical capacitor 1211C may be different for at least two time slices, i.e. for at least two delay elements of the switching chain 1211. The magnitudes of the at least two delay elements of the switching chain 1212 are selected accordingly.

[0112] 13, each time slice, or more precisely each delay t_D1, t_D2, t_D3 to t_DN, has a length that is a set percentage of the length of the entire sequence or delay t_S. The size of each capacitor 1211C and especially its order within each switching chain 1211, 1212 are selected accordingly. This in turn results in a predefined rise time Δt_R of the edge between both states of the bus 40.

[0113] As illustrated in FIG. 13, the order of the length of the respective delay times t_D1, t_D2, t_D3 to t_DN of the individual time slices along the length of the overall sequence t_S sets a fixed "transition shape" for the signal transition between two of the states 401, 402, 403, LV0, LV1. In this regard, the length of time of the overall sequence or delay t_S is controlled by a reference current I. The reason is that the delay element D BWD1 , D BWD2 , ...D BWDN and D. FWD1 , D FWD2 , ...D FWDN The same reference current I is applied to the various sized capacitors 1211C. This results in various speeds of voltage rise across the capacitors 1211C, and therefore various lengths of time t, until the inverter 1211J changes the state of the output signal S_O, as shown in FIG. 13 for delay times t_D1, t_D2, t_D3 to t_DN (N=27).

[0114] This at least one adjustment to the reference current I is stored in memory block 1219. The progression of a transition between two of the states 401, 402, 403, LV0, LV1 may be freely selectably adjusted or may be adjusted, with longer delay times t_D1, t_D2, t_D3 to t_DN at the beginning and end of the transition or sequence than in the middle, to approximate a spectrally optimal "smooth" overall transition from one state to the other.

[0115] If greater flexibility is required with regard to the individual time slices, more precisely the delay times t_D1, t_D2, t_D3 to t_DN of at least one respective delay element of the switching chains 1211, 1212, according to an alternative embodiment, the length of each individual time slice can be or may be stored in the memory block 1219. At least one of the switching chains 1211, 1212 has at least two parallel-connected capacitors 1211C for at least one of the time slices. Thereby, the length of such an individual time slice can be achieved by turning on or off at least one parallel-connected capacitor 1211C. Instead, a separate current I can be stored for each time slice in order to vary the delay times t_D1, t_D2, t_D3 to t_DN of at least one delay element of at least one of the switching chains 1211, 1212. However, this increased flexibility requires a higher circuit complexity than the "hardwired" time slices described above.

[0116] Two independent forward and reverse switching chains 1211, 1212 are responsible for reaching the desired final state (dom, rec, sic, LV0, LV1) on the bus 40 at the appropriate time based on the setting of the transmit signal TXD or TXD_INT.

[0117] 11 shows possible implementations for bus voltage sequences between states 403 (sic) and 401 (dom) or LV0 and LV1. 1 ...LG N, in particular each signal swing stage or intermediate state S1, S2...SN-1, SN of the flip-flop uniquely defines the state of the corresponding intermediate state, in particular the bus voltage and impedance as shown in Figures 10(E) and 10(F).

[0118] When the transition from state 403 to 401 (sic→dom) is made, all the logic elements LG 1 ...LG N , in particular the static state (S1 to SN=0) of the flip-flop means that the transmitting module 121 is in the sic state 403.

[0119]

number

[0120] 11 to 1 (S1 to SN=1) until all flip-flops are set. This state corresponds to the dom state 401 in the chosen example. A rising edge at the terminal for the signal TXD_INT activates the first switching chain 1211 in the forward direction, which with a defined delay sets the flip-flops of FIG. 11 to 1 in turn (S1 to SN=1) until all flip-flops are set. This state corresponds to the dom state 401 in the chosen example. 1 ...LG N , inter alia, enables the flip-flops and initiates a sequential reset in the opposite direction, for a defined time, of the second switching chain in the opposite direction 1212. At a defined time, the second switching chain 1212 reaches a final state, which in the described example is the sic state 403.

[0121] The described form of the transmission module 121 allows reversible switching at any time between all possible states of the state transition diagram of FIG. 14 with continuous behavior of the bus voltage VBUS and / or the bus impedance R_IN at any time.

[0122] As a result, the first switching chain 1211 outputs the transmit signal TXD_INT or the inverted signal

[0123]

number

[0124] In response to at least one edge of the signal TXD_INT, the second switching chain 1212 may stepwise change the amplitude of the bus voltage VBUS, in particular the amplitude of VCAN, and / or the value of the bus impedance R_IN.

[0125]

number

[0126] In response to at least one edge of V, the amplitude of the bus voltage VBUS, in particular VCAN, and / or the value of the bus impedance R_IN may be changed stepwise. FIG. 14 shows, in a three-dimensional diagram of state transitions, the states to which the transmitting module 121 may move by the permitted transitions between states (sequences). The vertical axis of FIG. 14 shows the transition from the arbitration phase 451 to the data phase 452. The horizontal axis of FIG. 14 shows the transition of the bus voltage VBUS between the states 401 (dom), 402 (rec), 403 (sic) or between the states LV0 and LV1. The axis that goes into the drawing plane of FIG. 14 and is perpendicular to the horizontal and vertical axes in FIG. 14 shows the bus impedance R_IN. In this regard, the values ​​of Table 2 below apply to the states generated by the transmitting module 121. That is, the axes of FIG. 14 do not show the quantitative magnitude of the bus impedance R_IN and the bus voltage VBUS, since the states 403 (sic) and 401 (dom) do not have the same bus impedance R_IN or the states 403 (sic) and LV1 do not have the same bus voltage as presented in Table 2.

[0127] [Table 2]

[0128] According to Fig. 14, there are five states, specifically 401 (dom), 403 (sic), 402 (rec), LV1, and LV0. Therefore, three is the minimum number of sequences for transitions between these five states, specifically the impedance sequence, the bus voltage sequence, and the FAST operating mode sequence. Two sequences can represent up to four static states on the bus 40.

[0129] At least one of the sequences in Fig. 14 is constructed as shown in Fig. 11 and Fig. 12 and explained above based on their switching chains 1211, 1212. The three dimensions of the "cube" in Fig. 14 visualize the states 401 (dom), 403 (sic), 402 (rec), LV1, LV0 of the three sequences.

[0130] In principle, there are many different possibilities for forming these three sequences. Each of the three sequences can be formed differently. Examples of this are described above in connection with Figures 11 and 12.

[0131] To achieve the desired state of the bus 40 or the final state of Table 2 and Figure 14, the transmit module 121 operates as follows with respect to the impedance sequence, the bus voltage sequence, and the FAST operating mode sequence along the aforementioned axes of Figure 14. In this regard, the transmit module 121 uses various triggers, which are illustrated in Figure 15.

[0132] Regarding the implementation, an edge on each of the three triggers, specifically on the signals TXD_INT, F_TM, and the time t-sic (FIG. 6), initiates a well-defined sequence in time of intermediate states of the (defined) bus voltage VBUS and impedance R_IN. The sequence proceeds in one or the other direction depending on the edge of the trigger. The sequences described below define three independent coordinate directions in the space of static CAN-XL states and therefore can also start and proceed independently of each other. In FIG. 14, all CAN-XL states 401, 402, 403, LV0, LV1 are represented as the end points of three independent sequences of all allowed states. Possible but not allowed paths are not shown in this figure for simplicity.

[0133] For the impedance sequence, the transmitting module 121 switches the bus impedance R_IN from the rec state 402 (60 kΩ) through the defined intermediate impedance to the bus impedance of the sic state 403, specifically 100Ω. The bus voltage VBUS in the final state and all intermediate states remains unchanged, specifically VBUS=0V. The trigger for performing the sequence in the rec→sic direction is the falling edge of TXD_INT while F_TM=0 is applied to the signal F_TM. The trigger for performing the sic→rec direction is the expiration / end of the time t_sic while the transmitting module 121 is in the normal operating mode SLOW or SIC, i.e. while F_TM=0 is applied.

[0134] For bus voltage sequencing, the transmit module 121 switches from a starting state bus voltage and bus impedance through defined intermediate states to a final state bus voltage and bus impedance. In a normal operating regime SLOW or SIC, i.e. F_TM=0, the end with TXD_INT=1 defines a sic state with VBUS=0V and R_IN=100Ω. The sic state changes to a dom state 401 with VBUS=2V and R_IN approximately 30Ω, as defined, by a falling edge of TXD_INT. A rising edge of TXD_INT triggers an inverted transition from state 401 (dom) to state 403 (sic). If the transmit module 121 is in a FAST operating regime (F_TM=1), the starting state with TXD_INT=1 is the LV1 state with VBUS=-1V and R_IN=100Ω. The LV1 state is triggered by a falling edge at the terminal for the signal TXD_INT, which changes stepwise and by definition to the LV0 state with VBUS=1V. Throughout this transition the impedance R_IN remains constant at R_IN=100Ω. A rising TXD_INT edge during the FAST operating regime causes the reversed sequence.

[0135] The FAST operating method sequence defines the transition from the classical CAN states dom, sic, rec to the CAN-XL specific states LV0, LV1 for a static TXD_INT signal.

[0136] In this regard, as shown more precisely in figure 15, the rising edge at the terminal for the signal F_TM and the falling edge at the terminal for the signal F_TM, respectively, must be considered in combination with the value of the transmit signal TXD_INT. The transmit module 121 is, for example, configured as follows.

[0137] A rising edge at the terminal for the signal F_TM triggers a sequence of transitions from the sic state 403 to the LV1 state in the case of a static or constant TXD_INT=1. In the sic state 403, VBUS=0V and R_IN=100Ω apply, and in the LV1 state, VBUS=-1V and R_IN=100Ω apply. A falling edge at the terminal for the signal F_TM in the case of a constant signal TXD_INT triggers the inverted transition, i.e., from the LV1 state to the sic state 403. Both of these transitions are not allowed according to the CAN XL specification, but are possible without problems due to the above-described configuration of the transmitting module 121, and are performed continuously and with the impedance R_IN kept constant.

[0138] A rising edge at the terminal for the signal F_TM triggers the allowed transition dom→LV0 in the case of a static or constant TXD_INT=0. To this end, the transmitting module 121 changes the bus voltage VBUS and the bus impedance R_IN from the dom state 401 with VBUS=2V and R_IN approx. 30Ω to the LV0 state with VBUS=1V and R_IN=100Ω continuously in a defined sequence. A falling edge at the terminal for the signal F_TM in the case of TXD_INT=0 triggers the inverted transition, i.e. from the LV0 state to the dom state 401. This transition is likewise not allowed according to the CAN XL specification, but is possible without problems due to the above-described configuration of the transmitting module 121. The allowed transition LV0→sic (403) is achieved by the simultaneous triggering of the FAST operating method sequence and the bus voltage sequence, where the triggering by the falling edge of F_TM is performed simultaneously with the rising edge of TXD_INT. A transition from bus voltage VBUS=+1 to VBUS=0 for a constant bus impedance R_IN=100 is effected by simultaneous implementation of the bus voltage sequence and the FAST operating regime sequence.

[0139] As shown in the three-dimensional state transition diagram of FIG. 14 and the two-dimensional diagram of FIG. 15, the sending module 121 can transition between the above-described states 401 (dom) and 403 (sic) in both directions in the first communication phase (arbitration phase) 451. Furthermore, the sending module 121 can transition between the above-described states 402 (rec) and 403 (sic) in both directions in the first phase 451. Furthermore, the sending module 121 can transition between the above-described states LV0 and LV1 in both directions in the second communication phase (data phase) 452. In other words, in the case of the above-mentioned state transitions, the transitions or transitions between states are reversible. In this case, the current states 401, 402, 403, LV0, and LV1 can immediately go to the new controlled states 401, 402, 403, LV0, and LV1, respectively, according to the control by the above-mentioned signals.

[0140] Due to the linear topology of the first communication phase (arbitration phase) 451, there is only one route from state 402(rec) via state 403(sic) to state (dom). This route can be interrupted and reversed at any point. The fast transition from state 402(rec) to state 403(sic) ensures that the transition times from state 402(rec) to state 403(sic) and to each intermediate state are determined only by the sic→dom sequence or transition, and therefore the dom state 401 is reached in the right time. Moreover, the reversibility at any point ensures the continuity of the bus voltage VBUS, especially VCAN, and the bus impedance R_IN.

[0141] According to FIG. 14, the transitions allowed by the transmission module 121 form a state tetrahedron consisting of only reversible transitions, as also shown in FIG. In contrast to this, according to FIG. 16, in the case of a conventional CAN-FD and / or CAN-XL transmit module 221, only one-way transitions are permitted between states 403(sic) and 402(rec). Moreover, only one-way transitions are permitted between states 402(rec) and 403(dom). This requires a loop to be implemented, which is undesirable due to the emissions and reflections that it generates, as explained above. For example, an edge of the transmit signal TXD will cause a transition depending on the current state, while the signal F_TM remains statically unchanged F_TM=0. The passage of time t_sic will likewise trigger an autonomous transition sic→rec or from state 403 to state 402. Due to the loop in the diagram of FIG. 16, an interrupted sic→rec transition or from state 403 to state 402 cannot be easily reversed without the above-mentioned drawbacks.

[0142] Based on Fig. 14 and Fig. 15, in a first exemplary embodiment using the transmit / receive mechanism 12 of Fig. 9 and the transmit module 121 of Fig. 11, such a loop is avoided by the fact that the sic state 403 is always positioned between 402 (rec) and 401 (dom) as shown in Fig. 14 and Fig. 15. A falling TXD edge in state 402 (rec) initiates the rec → sic transition, i.e. the transition from 402 to 403. As a result, the low resistance switching of state VBUS = 0V occurs in a very short time, always immediately followed by the sic → dom transition, i.e. the transition from 403 to 401, i.e. the defined controlled raising of the bus voltage to VBUS = 2V, simultaneously with a continuous drop of the impedance to R_IN = low = low. In this context, "very short time" should be understood as a gradual drop of the bus impedance through defined intermediate states according to the gate speed of the logic circuit 1213 of Fig. 11, as shown in Fig. 13.

[0143] The transmitting module 121 thus avoids discontinuities on the bus 40 and reaches the dom state 401 in time. In case of a rising edge of TXD, an inverted sequence is started, passing through defined states until the sic state 403 is reached, which relaxes autonomously and stepwise through defined states to the state of high resistance 402 (rec) after the time t_sic has elapsed.

[0144] Therefore, a clear image emerges by using a simplified topology of a 402 (rec) to 401 (dom) to 403 (sic) transition (rec / dom / sic transition) that is linearized based on Figures 14 and 15. This topology has a great advantage over the many possible transitions, allowed and not allowed, in a conventional CAN-FD transmit module 221 of a subscriber station 20, or in a conventional CAN-XL transmit module that is configured and operated based on Figure 16.

[0145] As a result, the transmit module 121 ideally eliminates the occurrence of discontinuities in the bus voltage VBUS and the bus impedance R_IN, and therefore has the great advantage that no wasteful emissions and reflections are generated.

[0146] The transmission module 121 may realize robust, continuous and timely switching of the bus voltage VBUS or VCAN and the bus impedance R_IN even in the case of erroneous signaling of switching transitions between any of the states 401 (dom), 402 (rec), 403 (sic), LV0, LV1 of the bus 40.

[0147] According to one variant of the first exemplary embodiment, a complete independence of the three coordinate axes of Fig. 14 is realized: in this case, the transmission module 121 may achieve all possible states within the pyramid defined by the CAN-XL states 401 (dom), 402 (rec), 403 (sic), LV0, LV1 as corner vertices.

[0148] According to the second exemplary embodiment, the transmitting module 121 does not only have a first stepping switching mechanism with a first forward switching chain 1211, a second reverse switching chain 1212, and a logic circuit 1213 as shown in FIG. 11.

[0149] Instead, the transmission module 121 additionally includes a second stepping switch mechanism, which also includes a first forward switch chain 1211, a second reverse switch chain 1212, and a logic circuit 1213, as shown in FIG. 11. The second stepping switch mechanism includes up to N time delay elements D FWDN and D. BWDN In particular, the time delay elements D for the first stepping switch mechanism may have a different number and / or size. FWDN and D. BWDN The number N of time delay elements D of the first stepping switch mechanism is different from that of the second stepping switch mechanism. In addition or instead of that, it is possible to use a maximum of N time delay elements D of the first stepping switch mechanism, as already explained above in connection with Figs. 11 to 13. FWDN and D. BWDN At least one of the other time delay elements D FWDN and D. BWDN It has a different size.

[0150] The third stepping switch mechanism can be formed like the first or second stepping switch mechanism. Alternatively, the third stepping switch mechanism also includes at least up to N time delay elements D FWDN and D. BWDN are formed to be different in number and / or size from the first and / or second stepping switching mechanisms.

[0151] In this case, the transmitting module 121 may execute the impedance sequence, for example, by a first stepping switching mechanism, the transmitting module 121 may further execute the bus voltage sequence, for example, by a second stepping switching mechanism, and the transmitting module 121 may further execute the FAST operation method sequence, for example, by a third stepping switching mechanism.

[0152] The advantage of the above described asynchronous delay chains 1211, 1212 for the transmission module 121 lies among other things in the fact that the states and all defined states have to be defined only once based on the desired signal shape. In this case, the speed of the delay chains 1211, 1212 defines how long the transitions between states take place. If the delay chains 1211, 1212 are made adaptive, for example, by an adjustable current I to a defined capacitance value, the transition times can be adjusted with the signal shape remaining the same, which provides an edge slew-rate control. The speed of the transitions 401, 402, 403, LV0, LV1 is limited only by the maximum switching speed of the delay chains 1211, 1212 used.

[0153] Otherwise, the same applies to the second exemplary embodiment as described above in relation to FIGS. 10(E)-15 and further with respect to FIG. According to a third exemplary embodiment, the transmission module 121 does not comprise delay chains 1211, 1212 but rather a logic 1210 formed as a synchronization logic 1210 for generating the switching sequence.

[0154] In the case of a synchronous system, the clock frequency of the synchronous system is typically defined, i.e. the change of the edge slew rate is only possible by means of a predefined intermediate state. The predefined intermediate state can be stored as a parameter, for example in a memory, in particular in a memory block of the transmitting / receiving arrangement 12 and / or in the memory block 1219 of the transmitting module 121 as shown in FIG. 9.

[0155] A further essential drawback of synchronous systems is the fact that with increasing data rates of the bus (currently up to 20 MBps) and limiting frequencies due to technological constraints for reliable implementation of the synchronous logic (e.g. maximum clock frequency 1 GHz), the number of intermediate states necessarily decreases, so that the transitions of the bus voltage and the bus impedance, which are desirable and necessary for emission and reflection reasons, become increasingly coarse-grained as the data rate increases and therefore spectrally worse.

[0156] The transmission module 121 according to FIG. 11 with the delay chains 1211, 1212 does not exhibit this limitation and can easily achieve data rates well above 40 MBps.

[0157] All above-described aspects of the transmitting module 121, of the transmitting / receiving arrangement 12, of the subscriber stations 10, 20, 30, of the bus system 1 and of the methods implemented therein, based on the exemplary embodiment and their variants, may be used alone or in all possible combinations. In addition, the following variants, among others, are conceivable:

[0158] The above-described bus system 1 according to at least one of the exemplary embodiments has been described on the basis of a bus system based on the CAN protocol. However, the bus system 1 according to at least one of the exemplary embodiments may instead be another kind of communication network in which signals are transmitted as differential signals. However, it is advantageous, but not necessarily a prerequisite, that the bus system 1 guarantees exclusive and collision-free access of one subscriber station 10, 20, 30 to the bus 40 at least for a certain period of time.

[0159] The bus system 1 according to the exemplary embodiment and at least one of its variants is, inter alia, a bus system in which communication can be performed between at least two subscriber stations 10, 20, 30 according to two different CAN standards, for example CAN-HS or CAN FD or CAN SIC or CAN XL. However, the bus system 1 may also be another communication network in which signals are transmitted as differential signals and serially via a bus 40. The functions of the exemplary embodiment described above can thus be used, for example, in a transmission / reception arrangement 12, 22 which can operate within such a bus system.

[0160] The number and arrangement of subscriber stations 10, 20, 30 in a bus system 1 according to the exemplary embodiment and / or its variants is optional. The number of stepping switching mechanisms can be selected arbitrarily. [Explanation of symbols]

[0161] 1 Serial Bus System 10, 20, 30 subscriber stations 11, 21 Communication control mechanism 12, 22 Transmission / reception mechanism 40 Bus 41 First bus conductor 42 Second bus conductor 45, 46, 47 Messages 121, 221 Transmitting Module 122, 222 receiving module 401, 402, 403, LV0, LV1 Status 451 First communication phase 452 Second Communication Phase 451_P 1st Physical Layer 452_P Second physical layer 1210 Logic, Synchronous Logic 1211 First Switch Chain 1211C Capacitor 1211S Switch 1211J Inverter 1212 Second Switch Chain 1213 Logic Circuit 1214 Edge Evaluation Unit 1215 Edge Detector 1216 Edge Detector 1217 Inverter CAN_H, CAN_L Analog differential signal D FWD1 , ...D FWDN Delay Element D BWD1 , ...D BWDN Delay Element F_TM Operation method switching signal LG 1 ...LG N Logic Elements RXD Digital receive signal R_IN bus impedance S1, S2...SN intermediate states TXD, TXD_INT Digital transmit signal t_bt1, t_bt2 bit duration t_D1...t_DN Delay time VBUS bus voltage

Claims

1. A transmission module (121) for a transmission and reception mechanism (12) of a subscriber station (10; 30) of a serial bus system (1), in which the transmission module (121) is configured for transmitting a digital transmission signal (TXD_INT) as an analog differential signal (CAN_H, CAN_L) to a bus (40) of the bus system (1) in order to transmit a message (45) to at least one further subscriber station (10; 20; 30) of the bus system (1), wherein bits of the digital transmission signal (TXD_INT) in a first communication phase (451) have a larger bit duration (t_bt1) than in a second communication phase (452) of the transmission signal (TXD_INT), the transmitting module (121) is configured to generate bus (40) states (401; 402; 403; LV0; LV1) set over time (t) by the digital transmit signal (TXD_INT) by changing a bus voltage (VBUS) and / or a bus impedance (R_IN); the transmission module (121) is configured to change the set bus (40) state (401; 402; 403; LV0; LV1) through a predefined sequence of intermediate states (S1, S2...SN) for the bus voltage (VBUS) and / or the bus impedance (R_IN) in the direction of the desired bus (40) state (401; 402; 403; LV0; LV1); and The transmission module (121) is configured such that, if signaling changes during a transition between two set bus (40) states (401; 402; 403; LV0; LV1), the transmission module (121) is configured to sequentially return the transition again from the intermediate state (S1; S2; SN-1; SN) achieved so far to a sequence of the intermediate states (S1, S2...SN) going backwards.

2. 2. The transmission module (121) of claim 1, further comprising a synchronization logic (1210) for generating a predetermined sequence of the intermediate states (S1, S2...SN) for the bus voltage (VBUS) and / or the bus impedance (R_IN) in the direction of the desired bus (40) state (401; 402; 403; LV0; LV1).

3. configured to generate different states of said digital transmit signal (TXD_INT) as dominant states (401) and recessive states (402) on said bus (40); and 3. A transmitting module (121) according to claim 1 or 2, which is configured to generate a transition from a dominant state (401) to a recessive state (402) via an impedance-matched recessive state (403), which corresponds to the recessive state (402) with respect to the bus voltage (VBUS) but is generated with a bus impedance (R_IN) different from that of the recessive state (402) and is transmitted at the beginning of each recessive state (402).

4. a first switching chain (1211) for gradually varying the amplitude of said bus voltage (VBUS) and / or the value of said bus impedance (R_IN) in response to at least one edge of a transmission signal (TXD_INT); Inverted transmit signal [0010] a second switching chain (1212) for gradually varying the amplitude of the bus voltage (VBUS) and / or the value of the bus impedance (R_IN) in response to at least one edge of 4. A transmission module (121) according to claim 1 or 3, comprising a logic circuit (1213) connected to said first switching chain (1211) and to said second switching chain (1212).

5. The delay element (D ＦＷＤ１ , . . . D ＦＷＤＮ ) each of the inverted transmit signals [0025] by a predetermined time (t_D1 . . . t_DN), and The delay element (D ＢＷＤ１ , . . . D ＢＷＤＮ 5. The transmission module (121) of claim 4, wherein each of said first and second delays (t_D1 . . . t_DN) delays said edge of said transmission signal (TXD_INT) by said predetermined time (t_D1 . . . t_DN).

6. The first switching chain (1211) comprises a delay element (D) having, inter alia, a switchable capacitor (1211C). ＦＷＤ１ , . . . D ＦＷＤＮ ) and an AND gate alternately, and the delay element (D ＦＷＤ１ , . . . D ＦＷＤＮ ) and the AND gate are connected in series, The second switching chain (1212) comprises a delay element (D) having, inter alia, a switchable capacitor (1211C). ＢＷＤ１ , . . . D ＢＷＤＮ ) and an AND gate alternately, and the delay element (D ＢＷＤ１ , . . . D ＢＷＤＮ ) and the AND gate are connected in series, and Both the first switching chain (1211) and the second switching chain (1212) have delay elements (D ＦＷＤ１ , D ＦＷＤＮ ;D ＢＷＤ１ , D ＢＷＤＮ 6. The transmission module (121) according to claim 4 or 5, comprising:

7. The delay element (D ＦＷＤ１ , . . . D ＦＷＤＮ ;D ＢＷＤ１ , . . . D ＢＷＤＮ 7. A transmission module according to claim 4, wherein at least two of the first and second inputs have switchable capacitors (1211C) of different sizes.

8. In the first and second switching chains (1211; 1212), the output of each AND gate is connected to one of the delay elements (D ＦＷＤ１ , . . . D ＦＷＤＮ ;D ＢＷＤ１ , . . . D ＢＷＤＮ 8. The transmission module (121) according to any one of claims 4 to 7, wherein the transmission module (121) is connected to an inlet of a gas turbine.

9. The logic circuit (1213) has a predetermined number of logic elements (LG １ . . . LG Ｎ 9. The transmission module (121) according to any one of claims 4 to 8, comprising a first input / output (122) and a second input / output (124).

10. One of the logic elements (LG １ ) at its one input (S) to the delay element (D ＦＷＤ１ ) and One of the logic elements (LG Ｎ ) at its one input (R) to the delay element (D) located at the beginning of the second delay chain (1212). ＢＷＤ１ 10. The transmitting module (121) according to claim 9 when dependent on claim 8, wherein the transmitting module (121) is connected to an outlet of the

11. The logic element (LG １ . . . LG Ｎ 11. A transmission module (121) according to claim 9 or 10, characterized in that said first input (S) of said flip-flop is connected to a first input of an AND gate of said first switching chain (1211) and said second input (R) of said flip-flop is connected to a first input of an AND gate of said second switching chain (1212).

12. A second input of the AND gate of the second switching chain (1212) is connected to a terminal for inputting the digital transmit signal (TXD_INT); and A second input of the AND gate of the first switching chain (1211) receives the inverted digital transmit signal [0030] The transmission module (121) according to claim 11, in communication with a terminal for inputting:

13. In addition to this, an edge detector (1215) for capturing the falling edge of said transmit signal (TXD_INT); an edge detector (1215) for capturing the falling edge of an operating mode switching signal (F_TM) which signals to the transmitting module (121) the operating mode to which the transmitting module (121) should switch in place of the current communication phase (451, 452); an edge detector (1216) for capturing the rising edge of the transmit signal (TXD_INT); An edge detector (1216) for capturing a rising edge of the operation mode switching signal (F_TM), 13. The transmitting module (121) according to claim 3, wherein the logic circuit (1213) is configured to generate a predetermined sequence of the intermediate states (S1, S2...SN) for the bus voltage (VBUS) and / or the bus impedance (R_IN) in the direction of the desired bus (40) state (401; 402; 403; LV0; LV1) based on the capture result of at least one of the edge detectors (1215; 1216).

14. A transmission module (121) according to any one of claims 1 to 13, and a receiving module (122) for receiving signals (CAN_H, CAN_L) from said bus (40) and for generating a digital receiving signal (RXD) from said analog differential signals (CAN_H, CAN_L); A transmit / receive mechanism (12) having:

15. The transmitting / receiving mechanism (12) of claim 14, wherein the transmitting module (121) is configured to generate the analog differential signal (CAN_H, CAN_L) in the first communication phase (451) of the message (45) at a different physical layer (451_P) than in the second communication phase (452).

16. A subscriber station (20) for a serial bus system (1), comprising: A transmitting / receiving arrangement (12) according to claim 14 or 15, a communication control mechanism (11) for controlling communication within the bus system (1) and for generating the first transmission signal (TXD), The subscriber station (20) is configured for communication within the bus system (1) in which exclusive and collision-free access of one subscriber station (10, 20, 30) to the bus (40) of the bus system (1) is guaranteed at least temporarily.

17. A method for transmitting a message (45) by differential signals (CAN_H, CAN_L) in a serial bus system (1), the method being performed by a transmitting module (121) of a transmitting / receiving arrangement (12), the transmitting module (121) being arranged for transmitting a digital transmit signal (TXD_INT) as an analog differential signal (CAN_H, CAN_L) to a bus (40) of the bus system (1) in order to transmit a message (45) to at least one further subscriber station (10; 20; 30) of the bus system (1), wherein bits of the digital transmit signal (TXD_INT) in a first communication phase (451) have a larger bit duration (t_bt1) than in a second communication phase (452) of the transmit signal (TXD_INT), generating bus (40) states (401; 402; 403; LV0; LV1) set over time (t) by said digital transmit signal (TXD_INT) by varying a bus voltage (VBUS) and / or a bus impedance (R_IN); the transmission module (121) is configured to change the set bus (40) state (401; 402; 403; LV0; LV1) through a predefined sequence of intermediate states (S1, S2...SN) for the bus voltage (VBUS) and / or the bus impedance (R_IN) in the direction of the desired bus (40) state (401; 402; 403; LV0; LV1); and the transmitting module (121) being configured, if the signalling changes during a transition between two set bus (40) states (401; 402; 403; LV0; LV1), to successively return said transition again from the intermediate state (S1; S2; SN-1; SN) reached so far to a sequence of intermediate states (S1, S2...SN) going backwards.

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