Imaging element and imaging device

Abstract

To increase a time from the transfer of charges to the reading of pixel signals as the number of pixels increase, and increase or decrease the charges to easily add noise to the pixel signals.SOLUTION: An imaging element includes a plurality of imaging units in which a plurality of unit blocks in which multiple pixels are arranged in a matrix are arranged in a matrix, at least one A / D conversion unit provided for each of the unit blocks, and converting a pixel signal from a pixel included in the corresponding unit block into a digital signal, and a reading unit that sequentially reads digital signals of pixels included in the imaging unit across the plurality of unit blocks.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to an imaging element and an imaging apparatus. [Background technology]

[0002] In an image sensor having pixels arranged in a matrix, a global shutter is electronically realized by transferring electric charges all at once using a memory circuit consisting of transistors and storage capacitors (see, for example, Patent Document 1). Patent Document 1: JP2011-119950 Summary of the Invention [Problem to be solved by the invention]

[0003] However, after the charges are transferred all at once, the pixel signals based on the charges are read out one by one. Therefore, as the number of pixels increases, the time from when the charges are transferred until the pixel signals are read out becomes longer, and the charges increase or decrease, making it easier for noise to be introduced into the pixel signals. [Means for solving the problem]

[0004] In a first aspect of the present invention, a first block has a first photoelectric conversion unit that converts light into an electric charge, a second photoelectric conversion unit that converts light into an electric charge and is arranged alongside the first photoelectric conversion unit in the column direction, and a third photoelectric conversion unit that converts light into an electric charge and is arranged alongside the first photoelectric conversion unit in the row direction; a fourth photoelectric conversion unit that converts light into an electric charge, which is a block arranged alongside the first block in the column direction, and a fifth photoelectric conversion unit that converts light into an electric charge and is arranged alongside the fourth photoelectric conversion unit in the column direction; a first semiconductor chip including a second block having a sixth photoelectric conversion unit that converts light into electric charges and that is arranged alongside the fourth photoelectric conversion unit in the row direction; a third block that is arranged alongside the first block in the row direction and that has a seventh photoelectric conversion unit that converts light into electric charges, an eighth photoelectric conversion unit that converts light into electric charges and that is arranged alongside the seventh photoelectric conversion unit in the column direction, and a ninth photoelectric conversion unit that converts light into electric charges and that is arranged alongside the seventh photoelectric conversion unit in the row direction; a first circuit disposed so as to overlap with a first block in a stacking direction in which the first semiconductor chip and the second semiconductor chip are stacked; a first signal processing unit that performs signal processing on a first signal based on the charges converted by the first photoelectric conversion unit and a second signal based on the charges converted by the second photoelectric conversion unit; and a second signal processing unit that performs signal processing on a third signal based on the charges converted by the third photoelectric conversion unit, the first circuit being arranged so as to overlap with a first block in a stacking direction in which the first semiconductor chip and the second semiconductor chip are stacked; and a third signal processing unit that performs signal processing on a fourth signal based on the charges converted by the fourth photoelectric conversion unit and a fifth signal based on the charges converted by the fifth photoelectric conversion unit. and a fourth signal processing unit that performs signal processing on a sixth signal based on the charges converted in the sixth photoelectric conversion unit and an eighth signal based on the charges converted in the eighth photoelectric conversion unit, and a sixth signal processing unit that performs signal processing on a ninth signal based on the charges converted in the ninth photoelectric conversion unit and a second circuit that is arranged to overlap with the second block in the stacking direction.

[0005] The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view of a back-illuminated imaging element according to an embodiment of the present invention. [Diagram 2] 2 is a diagram illustrating a pixel array and unit blocks of an imaging chip. FIG. [Diagram 3] FIG. 2 is a circuit diagram corresponding to a pixel. [Figure 4] 1 shows an outline of a unit block, its peripheral circuits, and their connections. [Diagram 5] 2 shows an outline of the connections of peripheral circuits, etc. [Figure 6] 1 is a block diagram showing a configuration of an imaging device according to an embodiment of the present invention. [Figure 7] FIG. 4 is a block diagram showing a specific configuration of a drive unit. [Figure 8] 4 shows a timing chart of operations such as pixel charge accumulation and transfer. [Figure 9] 4 shows a timing chart of an operation for reading out a pixel signal from a pixel. [Figure 10] 4 is a timing chart showing readout timings of a plurality of pixels included in the imaging unit. [Figure 11] 13 shows another example of the connection relationship of peripheral circuits and the like. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0008] 1 is a cross-sectional view of a back-illuminated image sensor 100 according to this embodiment. The image sensor 100 includes an image sensor chip 113 that outputs pixel signals corresponding to incident light, a signal processing chip 111 that processes the pixel signals, and a memory chip 112 that stores the pixel signals. The image sensor chip 113, the signal processing chip 111, and the memory chip 112 are stacked and electrically connected to each other by conductive bumps 109 made of Cu or the like.

[0009] As shown in the figure, the incident light is mainly incident in the Z-axis positive direction indicated by the white arrow. In this embodiment, the surface of the imaging chip 113 on which the incident light is incident is referred to as the back surface. As shown in the coordinate axes, the right direction on the paper surface perpendicular to the Z-axis is the X-axis positive direction, and the front direction on the paper surface perpendicular to the Z-axis and the X-axis is the Y-axis positive direction. In the following figures, the coordinate axes are displayed so that the orientation of each figure can be understood based on the coordinate axes in FIG. 1.

[0010] An example of the imaging chip 113 is a back-illuminated MOS image sensor. The PD layer is disposed on the back side of the wiring layer 108. The PD layer 106 has a plurality of PDs (photodiodes) 104 arranged two-dimensionally and transistors 105 provided corresponding to the PDs 104.

[0011] A color filter 102 is provided on the incident side of the PD layer 106 where the incident light is incident, with a passivation film 103 interposed therebetween. The color filters 102 are of a plurality of types that transmit different wavelength regions, and have a specific arrangement corresponding to each of the PDs 104. The arrangement of the color filters 102 will be described later. A set of the color filter 102, the PD 104, and the transistor 105 forms one pixel.

[0012] A microlens 101 is provided corresponding to each pixel on the incident light side of the color filter 102. The microlens 101 condenses the incident light toward the corresponding PD 104.

[0013] The wiring layer 108 has wiring 107 that transmits pixel signals from the PD layer 106 to the signal processing chip 111. The wiring 107 may be multi-layered, and may include passive and active elements.

[0014] A plurality of bumps 109 are arranged on the surface of the wiring layer 108. The plurality of bumps 109 are aligned with a plurality of bumps 109 provided on the opposing surface of the signal processing chip 111, and the imaging chip 113 and the signal processing chip 111 are pressed, etc., so that the aligned bumps 109 are joined and electrically connected to each other.

[0015] Similarly, a plurality of bumps 109 are arranged on the opposing surfaces of the signal processing chip 111 and the memory chip 112. These bumps 109 are aligned with each other, and the signal processing chip 111 and the memory chip 112 are pressed together, etc., so that the aligned bumps 109 are bonded to each other and electrically connected.

[0016] The bonding between the bumps 109 is not limited to Cu bump bonding by solid-phase diffusion, and micro-bump bonding by solder melting may be used. Also, it is sufficient to provide one bump 109 for each output wiring, which will be described later. Therefore, the size of the bump 109 may be larger than the pitch of the PD 104. Also, in a peripheral region other than the pixel region where the pixels are arranged, a bump larger than the bump 109 corresponding to the pixel region may be provided.

[0017] The signal processing chip 111 has TSVs (Through Silicon Vias) 110 that connect the circuits provided on the front and back surfaces of the chip to each other. The TSVs 110 are preferably provided in the peripheral region. The TSVs 110 may also be provided in the peripheral region of the imaging chip 113 and the memory chip 112.

[0018] 2 is a diagram illustrating the pixel array of the imaging chip 113 and the unit block 131. In particular, the imaging chip 113 is shown as observed from the back side. The imaging chip 113 has an imaging section in which more than 20 million pixels are arranged in a matrix. In the example of FIG. 2, adjacent 4 pixels x 4 pixels, or 16 pixels, form one unit block 131. The grid lines in the figure show the concept of forming the unit block 131 by grouping adjacent pixels.

[0019] As shown in the partially enlarged view of the imaging section, the unit block 131 includes four so-called Bayer arrays, each consisting of four pixels: green pixels Gb, Gr, blue pixel B, and red pixel R, arranged vertically and horizontally. The green pixels Gb and Gr have a green filter as the color filter 102 and receive light in the green wavelength band of the incident light. Similarly, the blue pixel B has a blue filter as the color filter 102 and receives light in the blue wavelength band, and the red pixel R has a red filter as the color filter 102 and receives light in the red wavelength band.

[0020] In Fig. 2, for the sake of simplicity, an example is described in which the unit block 131 is made up of 16 pixels, 4 pixels x 4 pixels. Hereinafter, an example is described in which the unit block 131 has pixels arranged in L rows and P columns, totaling (L x P). There is no particular limit to the number of rows and columns, but when the total number of pixels in the imaging section is about 20 million pixels, for example, it may have 64 rows and 32 columns. Also, an example is described in which the imaging section is formed by arranging the unit blocks 131 in m rows and n columns, totaling (m x n).

[0021] Fig. 3 is a circuit diagram corresponding to a pixel 150. In Fig. 3, a rectangle surrounded by a dotted line representatively represents a circuit corresponding to one pixel 150. Note that at least a part of each transistor described below corresponds to the transistor 105 in Fig. 1.

[0022] The PD 104 is connected to a transfer transistor 154, and a gate of the transfer transistor 154 is connected to a wiring Tx_i_j to which a transfer pulse is supplied. Note that the subscript i is a serial number in the entire imaging section that identifies the unit block 131. The subscript j is a serial number in the unit block 131 that identifies a row number in the unit block 131.

[0023] The drain of the transfer transistor 154 is connected to the source of the reset transistor 152. This forms a so-called FD (floating diffusion) 156 between the drain of the transfer transistor 154 and the source of the reset transistor 152. The drain of the reset transistor 152 is connected to a wiring Vdd to which a power supply voltage is supplied, and the gate of the reset transistor 152 is connected to a wiring Rst_i_j to which a reset pulse is supplied.

[0024] One end of the FD 156 is further connected to the source of a pass transistor 158. The gate of the pass transistor 158 is connected to a wiring Wrt_i_j to which a pass pulse is supplied, and the drain is connected to one end of a storage capacitor 160. The pass transistor 158 and the storage capacitor 160 form a so-called memory circuit.

[0025] The one end of the storage capacitance 160 is further connected to the gate of the amplification transistor 162. The drain of the amplification transistor 162 is connected to a wiring Vdd to which a power supply voltage is supplied. The source of the amplification transistor 162 is connected to the drain of the corresponding selection transistor 164. The gate of the selection transistor 164 is connected to a wiring Sel_i_j to which a selection pulse is supplied.

[0026] The source of the selection transistor 164 is connected to a column transmission line 170. A load current source 166 supplies a current to the column transmission line 170. That is, the column transmission line 170 for the selection transistor 164 is formed by a source follower.

[0027] Fig. 4 shows an outline of a unit block 131, its peripheral circuit 133, and their connections. In the unit block 131 of Fig. 4, a total of (P x L) pixels 150 are arranged in L rows and P columns.

[0028] The wiring Rst_i_l (where l is an integer from 1 to L) is connected to the row control unit 200, and is also connected in common to P pixels 150 in the lth row in the unit block 131. Similarly, the wiring Tx_i_l, the wiring Wrt_i_l, and the wiring Sel_i_l are also connected to the row control unit 200, and are also connected in common to P pixels 150 in the lth row in the unit block 131.

[0029] The row control unit 200 may also be called a row selection unit, a vertical scanning circuit, etc. The row control unit 200 is provided for each unit block 131. The row control unit 200 may be provided on the signal processing chip 111 side.

[0030] The column transmission paths 170 are provided for each pixel 150 in the same column. These column transmission paths 170_p (where p is an integer from 1 to P) are commonly connected to L pixels 150 in the p-th column in the unit block 131. As a result, the column transmission path 170 is shared by the pixels 150 in the same column in the unit block 131, and transmits signals from the pixels 150 included in that column.

[0031] These column transmission paths 170_p are connected from the imaging chip 113 side to the peripheral circuits 133 provided on the signal processing chip 111 side via bumps 109. The peripheral circuits 133 are provided for each unit block 131, and are arranged so as to overlap the unit blocks 131 in the imaging chip 113 when viewed from the stacking direction.

[0032] The peripheral circuit 133 has a CDS circuit 202 and an A / D conversion circuit 204 connected in series for each column transmission line 170_p. In the example shown in Fig. 4, P pairs of the CDS circuit 202 and the A / D conversion circuit 204 are provided for each unit block 131.

[0033] The peripheral circuit 133 further includes a shift register 206 arranged on the output side of the P A / D conversion circuits 204. In the example of Fig. 4, one shift register 206 is arranged for each unit block 131. The output of the shift register 206 is connected to a shift register 210 via a column bus line 172.

[0034] 5 shows an outline of the connection relationship of the peripheral circuits 133 etc. The unit blocks 131 are arranged in m rows and n columns, and correspondingly, the peripheral circuits 133 are also arranged in m rows and n columns.

[0035] A column bus line 172 is provided for each peripheral circuit 133 in the same column. This column bus line 172_u (where u is an integer from 1 to n) is commonly connected to m peripheral circuits 133 in the u-th column. As a result, the column bus line 172 is shared by the unit blocks 131 in the same column and transmits signals from the unit blocks 131 included in that column.

[0036] In addition, since the column bus line 172 is shared by the peripheral circuits 133 in the same column, the output of each peripheral circuit 133 is configured to be controlled by an output selection circuit (not shown). For example, the output of 172 in Fig. 4 is enabled or disabled. When it is disabled, it is controlled by setting it to high impedance, etc.

[0037] A shift register 210 is disposed on the output side of the n column bus lines 172. In the example of Fig. 5, one shift register 210 is disposed for the entire image sensor 100. The shift register 210 holds signals transmitted from the n column bus lines 172 and outputs them sequentially. The shift registers 206 and 210 may also be called horizontal scanning circuits, multiplexers, etc.

[0038] 6 is a block diagram showing the configuration of an image capturing apparatus according to this embodiment. The image capturing apparatus 500 includes a photographing lens 520 as an image capturing optical system, which guides a subject light flux incident along an optical axis OA to the image capturing element 100. The photographing lens 520 may be an interchangeable lens that can be attached to and detached from the image capturing apparatus 500. The image capturing apparatus 500 mainly includes the image capturing element 100, a system control unit 501, a driving unit 502, a photometry unit 503, a work memory 504, a recording unit 505, and a display unit 506.

[0039] The photographing lens 520 is composed of a group of optical lenses, and focuses the subject light beam from the scene near its focal plane. Note that in Fig. 6, it is represented by a virtual single lens arranged near the pupil. The driving unit 502 executes charge accumulation control of the image sensor 100, pixel signal readout control, etc. according to instructions from the system control unit 501.

[0040] The image sensor 100 passes the pixel signal to an image processor 511 in the system controller 501. The image processor 511 performs various image processes using the work memory 504 as a workspace to generate image data. For example, when generating image data in a JPEG file format, compression is performed after white balance processing, gamma processing, etc. The generated image data is recorded in a recording unit 505 and is also converted into a display signal and displayed on a display unit 506 for a preset time.

[0041] The photometry unit 503 detects the luminance distribution of a scene prior to a series of shooting sequences for generating image data. The photometry unit 503 includes an AE sensor with, for example, about one million pixels. The calculation unit 512 of the system control unit 501 receives the output of the photometry unit 503 and calculates the luminance of each area of ​​the scene. The calculation unit 512 determines the shutter speed, the aperture value, and the ISO sensitivity according to the calculated luminance distribution. Note that the pixels used for the AE sensor may be provided within the image sensor 100, and in this case, it is not necessary to provide a photometry unit 503 separate from the image sensor 100.

[0042] 7 is a block diagram showing a specific configuration of the driving unit 502. The driving unit 502 includes a sensor control unit 441, a block control unit 442, a synchronization control unit 443, a signal control unit 444, a pixel memory 414, and an arithmetic circuit 415 as distributed control functions, and a driving control unit 420 that controls these control units. The driving unit 502 further includes an I / F circuit 418 between the driving control unit 420 and a system control unit 501 of the imaging device 500 main body.

[0043] The drive control section 420 converts instructions from the system control section 501 into control signals executable by each control section, and passes them on to each control section, with reference to the timing memory 430. The timing memory 430 is formed of a flash RAM or the like.

[0044] The sensor control unit 441 is responsible for controlling the transmission of control pulses related to charge accumulation and charge readout of each pixel, which are sent to the imaging chip 113. Specifically, the sensor control unit 441 controls the start and end of charge accumulation of the target pixel by sending a reset pulse, a transfer pulse, and a pass pulse to the row control unit 200 of each unit block 131, and outputs a pixel signal to the column transmission path 170 by sending a selection pulse to the readout pixel.

[0045] The block control unit 442 executes transmission of specific pulses that identify the unit blocks 131 to be controlled and are transmitted to the imaging chip 113. The transfer pulses and the like that each pixel receives via the wiring Tx_i_j and the like are the logical product of each pulse transmitted by the sensor control unit 441 and the specific pulse transmitted by the block control unit 442. In this way, each region can be controlled as a block independent of each other. Note that when using pulses synchronized with each other in a plurality of unit blocks 131, and when performing an operation across a plurality of unit blocks 131, the block control unit 442 simultaneously transmits specific pulses that identify each of the plurality of unit blocks.

[0046] The synchronization control unit 443 sends a synchronization signal to the imaging chip 113. Each pulse becomes active in the imaging chip 113 in synchronization with the synchronization signal. For example, by adjusting the synchronization signal, random control, thinning control, and the like that control only specific pixels belonging to the same unit block 131 are realized. In addition, the signal control unit 444 is responsible for timing control of the CDS circuit 202, the A / D conversion circuit 204, and the shift registers 206 and 210.

[0047] The arithmetic circuit 415 calculates an AE evaluation value and the like based on the pixel values ​​stored in the pixel memory 414. The arithmetic circuit 415 outputs the calculation results to the drive control unit 420.

[0048] The pixel memory 414 has a memory space capable of storing pixel values ​​from the pixels 150 of the imaging unit, and stores each pixel value that has been read out from each pixel and digitized. The pixel memory 414 is provided with a data transfer interface that transmits pixel signals in accordance with a transfer request. The data transfer interface is connected to a data transfer line that is connected to the image processing unit 511. The data transfer line is formed, for example, by a data bus among bus lines. In this case, a transfer request from the system control unit 501 to the drive control unit 420 is executed by address designation using the address bus.

[0049] The transmission of pixel signals by the data transfer interface is not limited to the addressing method, and various other methods may be adopted. For example, a double data rate method may be adopted, which uses both the rising and falling edges of the clock signal used to synchronize each circuit when transferring data. A burst transfer method may also be adopted, which transfers data all at once by omitting some steps such as addressing, thereby increasing speed. A bus method using lines that connect the control unit, memory unit, and input / output unit in parallel, and a serial method that transfers data one bit at a time in series may also be adopted in combination.

[0050] With this configuration, the image processing unit 511 can receive only the necessary pixel values, and therefore can complete image processing at high speed, especially when forming an image with low resolution. The driving unit 502, the row control unit 200 in Fig. 4, the peripheral circuit 133, and the shift register 210 in Fig. 5 function as a readout unit that sequentially reads out pixel signals of the pixels 150 included in the imaging unit across multiple unit blocks 131.

[0051] 8 shows a timing chart of operations such as charge accumulation and transfer in the pixel 150. Hereinafter, the charge accumulation and transfer operations in the pixel 150 in FIG. 3 will be described with reference to FIG.

[0052] As an initial state, at time t0, the driving unit 502 turns on the reset transistor 152, the transfer transistor 154, and the pass transistor 158 by setting the voltages of the wirings Rst_i_j, Tx_i_j, and Wrt_i_j to high via the row control unit 200. This resets the PD 104, the FD 156, and the storage capacitance 160.

[0053] At time t1 when an input is made to start imaging by pressing the release button, etc., the driving unit 502 sets the wiring Tx_i_j to low, thereby turning off the transfer transistor 154. As a result, light incident on the PD 104 is photoelectrically converted and starts to be stored as electric charge.

[0054] At time t2 immediately before the end time t3 of the set charge accumulation, the driving unit 502 sets the voltage of the wirings Rst_i_j and Wrt_i_j to low to turn off the reset transistor 152 and the pass transistor 158, and then sends a transfer pulse that sets the wiring Tx_i_j to high from the end time t3 to time t4. As a result, the charge photoelectrically converted by the PD 104 is accumulated in the FD 156.

[0055] After time t4, the driving unit 502 sends a transfer pulse that sets the line Wrt_i_j high from time t5 to time t6. This transfers the charge stored in the FD 156 to the storage capacitor 160, and the charge is isolated from subsequent charge storage in the PD 104 and held there. Thereafter, at time t7, the line Rst_i_j is set high, thereby completing the charge storage and transfer operations.

[0056] The operation of one pixel 150 in Fig. 3 has been described above. However, as shown in Fig. 4, in a unit block 131, the wirings Rst_i_j etc. are commonly connected to P pixels 150 in the same row. Therefore, the operation in Fig. 8 above is simultaneously executed at least in the pixels 150 in the same row in the unit block 131.

[0057] Furthermore, during global shuttering, the operation of FIG. 8 is executed simultaneously for the pixels 150 in L rows in the unit block 131 with m rows and n columns. That is, wirings such as wiring Rst_i_j, whose subscript i ranges from 1 to m×n and whose subscript j ranges from 1 to L, are switched between high and low at the same time according to FIG. 8. This makes it possible to photoelectrically convert image light incident on each pixel 150 at the same time and hold an electric charge. Unless otherwise specified, the following description will be given assuming that the global shutter has been executed.

[0058] 9 shows a timing chart of the operation of reading out the pixel signal of the pixel 150. Hereinafter, the operation of reading out the pixel signal of the pixel 150 to the column transmission path 170 will be described with reference to FIG.

[0059] At time t8, which is later than the time t7, the driving unit 502 turns on the selection transistor 164 by turning on the line Sel_i_j. As a result, a voltage serving as a pixel signal corresponding to the voltage generated by the charge stored in the storage capacitance 160 is output to the column transmission path 170. Furthermore, the driving unit 502 sends a pass pulse to turn on the line Wrt_i_j with the line Sel_i_j being kept high. As a result, a voltage serving as a reset signal at the node between the storage capacitance 160 and the amplification transistor 162 is output to the column transmission path 170. Thereafter, at time t9, the driving unit 502 turns on the line Sel_i_j low, thereby completing the readout for the pixel 150.

[0060] The CDS circuit 202 removes noise based on the pixel signal and the reset signal. The A / D conversion circuit 204 converts the pixel signal from which noise has been removed by the CDS circuit 202 into a digital signal and outputs it.

[0061] Fig. 10 is a timing chart showing the readout timing of a plurality of pixels 150 included in the imaging unit. As explained in Fig. 9, the pass pulse for the wiring Wrt_i_j is sent with the wiring Sel_i_j set to high, so for the purpose of simplifying the explanation, only the timing chart for the wiring Sel_i_j is shown in Fig. 9.

[0062] In reading out the entire imaging section, first, the pixels 150 in the first row in the entire imaging section are selected. That is, the pixels 150 in the first row in the unit block 131 in the first row are selected. In the example of FIG. 5, the subscript i of the unit block 131 in the first row corresponds to 1 to n. Therefore, the driving unit 502 sends a selection pulse that simultaneously sets the wirings Sel_i_1 (where i is 1 to n) to high to the row control unit 200 of the corresponding unit block 131.

[0063] As described above, the wiring Sel_i_1 is commonly connected to the pixels 150 in the first row in the unit block 131. Furthermore, a selection pulse is sent to the unit block 131 in the first row. Therefore, pixel signals of the pixels 150 in the first row are read out to the respective column transmission paths 170 across the multiple unit blocks 131.

[0064] Each of the column transmission paths 170 transmits a pixel signal from the pixel 150 selected by the row control unit 200 to the CDS circuit 202 of the corresponding column in the unit block 131. The pixel signal has noise removed by the CDS circuit 202, is converted into a digital signal by the A / D conversion circuit 204, and is input to the shift register 206. The shift register 206 receives the P digital signals of the first row in the unit block 131 through each of the column transmission paths 170 by the readout operation, and temporarily holds them.

[0065] The shift register 206 sequentially outputs P digital signals to the shift register 210 via the column bus line 172. In this case, it is preferable that the unit blocks 131 in the first row are synchronously transmitted to each other. The shift register 210 receives the pixels 150 in the first row of the entire imaging unit, i.e., P×n digital signals, by the readout operation.

[0066] The shift register 210 sequentially outputs P×n digital signals to the pixel memory 414, and the pixel memory 414 stores the digital signals as pixel values. In this case, it is preferable that the shift register 210 outputs the digital signals in the arrangement order of the pixels 150 in the entire imaging section. In the example shown in Figures 4 and 5, P digital signals of the pixels 150 in the first row in the first (i=1) unit block 131 are output from left to right, and then P digital signals of the pixels 150 in the first row in the second (i=2) unit block 131 are output from left to right, and so on.

[0067] With the above, the readout of the pixels 150 in the first row of the entire imaging section is completed. Next, the pixels 150 in the second row of the entire imaging section are selected. That is, the pixels 150 in the second row in the unit block 131 in the first row are selected. The driving unit 502 sends a selection pulse that simultaneously sets the wirings Sel_i_2 (where i is 1 to n) to high to the row control unit 200 of the corresponding unit block 131. As a result, the pixel signals of the pixels 150 in the second row are read out in the same way as the pixels 150 in the first row, and are output to the pixel memory 414 as pixel values.

[0068] Thereafter, the above operation is repeated from the third row to the Lth row, which is the last row in the unit block 131. This completes the readout of the pixels 150 included in the unit block 131 in the first row.

[0069] Next, the pixel 150 in the (L+1)th row in the entire imaging section is selected. That is, the pixel 150 in the first row in the unit block 131 in the second row is selected. The driving unit 502 sends a selection pulse that simultaneously sets the wiring Sel_i_1 (where i is from (n+1) to 2n) to high to the row control unit 200 of the corresponding unit block 131. As a result, similar to the case of the unit block 131 in the first row, the pixel signal of the pixel 150 in the first row of the unit block 131 in the second row is read out and output as a pixel value to the pixel memory 414. Similarly, the pixels in the (L+2)th row to the 2Lth row in the entire imaging section, that is, the second row to the Lth row of the unit block 131 in the second row are sequentially read out. As a result, the reading of the pixel 150 included in the unit block 131 in the second row is completed.

[0070] Thereafter, the (2L+1)th to L×mth rows in the entire imaging section, i.e., the 1st row of the 3rd unit block 131 to the Lth row of the mth unit block 131, are sequentially read out. This completes the readout of the (L×P)×(n×m) pixels 150 included in the entire imaging section, i.e., the unit blocks 131 with m rows and n columns.

[0071] In the above embodiment, the pixel signals are converted into digital signals by the peripheral circuit 133 before being input to the shift register 210, which sequentially outputs pixels to the pixel memory 414. This makes it possible to suppress noise being superimposed on the pixel signals while they are held in the shift register 210. Furthermore, since the pixel signals are converted into digital signals before being input to the shift register 206 of the peripheral circuit 133, it is possible to suppress noise being superimposed on the pixel signals while they are held in the shift register 206.

[0072] Also, by dividing the imaging section into a plurality of unit blocks 131 and arranging the peripheral circuits 133 corresponding to the unit blocks 131 on the signal processing chip 111 side, A / D conversion can be performed before input to the shift registers 206, 210 without reducing the area of ​​the PD 104. Furthermore, even if the unit blocks 131 are arranged in a matrix and the pixels 150 in the unit blocks 131 are also arranged in a matrix, pixel signals corresponding to the matrix arrangement of the pixels 150 in the entire imaging section can be output. As a result, in the pixel memory 414, image processing section 511, etc., additional circuits, processing, etc. due to the imaging section being divided into unit blocks 131 are not required.

[0073] Fig. 11 shows another example of the connection relationship of the peripheral circuit 133 etc. In Fig. 11, the same components as those in Fig. 5 are given the same reference numbers and the description thereof will be omitted.

[0074] A matrix switch 220 is connected to the output sides of the n column bus lines 172. The output side of the matrix switch 220 is connected to the shift registers 206_1 to 206_k.

[0075] The matrix switch 220 inputs the digital signals transmitted to the column bus lines 172 to any one of the multiple shift registers 206 for each unit block 131 included in the corresponding column. For example, the digital signals from the column bus lines 172_1 and 172_2 are input to the shift register 206_1, and the digital signals from the column bus lines 172_3 and 172_4 are input to the shift register 206_2.

[0076] Furthermore, the matrix switch 220 may dynamically change the combination of the column bus line 172 and the shift register 206_1, etc. For example, when reading from some of the unit blocks 131 in the imaging section in moving image shooting, live view (also called through image display, etc.), crop shooting, etc., a combination of the column bus line 172 of the unit block 131 to be read and the shift register 206_1, etc. may be set. For example, when reading out n / 2 unit blocks 131, these unit blocks 131 may be allocated as evenly as possible to the shift registers 206_1 to 206_k. This makes it possible to transmit pixel signals at a preset maximum transmission frequency whether pixel signals are output from unit blocks 131 in m rows and n columns or from a smaller number of unit blocks 131.

[0077] Although an example in which a global shutter is used has been described in the above embodiment, instead, a global shutter may not be used. In this case, the accumulation and transfer of charges may be performed simultaneously in the unit block 131, and may be performed in a time-varying manner between the multiple unit blocks 131. Alternatively, the accumulation and transfer of charges may be performed in a time-varying manner between the pixels 150 in the unit block 131. Whether or not to use a global shutter may be selected by the user, or may be automatically set based on the shooting conditions.

[0078] 3 uses a memory circuit, the memory circuit may not be used. In that case, a mechanical shutter, for example, may be used as the global shutter.

[0079] 4 has a CDS circuit 202 and an A / D conversion circuit 204 for each column. The number of pairs of the CDS circuit 202 and the A / D conversion circuit 204 may be more or less than this. For example, a pair of the CDS circuit 202 and the A / D conversion circuit 204 may be provided for one pixel 150. In this case, the pair of the CDS circuit 202 and the A / D conversion circuit 204 may be provided on the signal processing chip 111 side, and the output line for each pixel 150 may be connected via the bump 109, and a column transmission path that transmits the output of the A / D conversion circuit 204 for each column may be provided on the signal processing chip 111 side.

[0080] 4 uses a shift register 206 to sequentially input P digital signals for one row to a shift register 210. Alternatively, P systems of column bus lines 172 may be provided for each column, and the peripheral circuit 133 may simultaneously input P digital data to the shift register 210 via the column bus lines 172. Alternatively, the number of column bus lines 172 provided for each column may be the same as the number of bits, and digital signals may be transmitted simultaneously in relation to the number of bits, or fewer than the number of bits may be provided for each column, and digital signals may be transmitted sequentially in relation to the number of bits.

[0081] 10, a selection pulse is sent sequentially to each row of the unit blocks 131. Alternatively, a selection pulse may be sent simultaneously to the unit blocks 131 in m rows and n columns. That is, a transfer pulse may be sent simultaneously to the wirings Sel_i_j where i ranges from 1 to m×n. In this case, the driving unit 502 controls the timing for each shift register 206 of the unit blocks 131 in the same column so that after P digital signals are sent from the shift register 206 corresponding to one unit block 131, P digital signals are sent from the shift register 206 corresponding to the next unit block 131 according to the order of the columns.

[0082] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0083] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0084] 100 imaging element, 101 microlens, 102 color filter, 103 passivation film, 104 PD, 105 transistor, 106 PD layer, 107 wiring, 108 wiring layer, 109 bump, 110 TSV, 111 signal processing chip, 112 memory chip, 113 imaging chip, 131 unit block, 133 peripheral circuit, 150 pixel, 152 reset transistor, 154 transfer transistor, 156 FD, 158 pass transistor, 160 storage capacitance, 162 amplification transistor, 164 selection transistor, 166 load current source, 170 column transmission path, 172 column bus line, 200 row control unit, 202 CDS circuit, 204 A / D conversion circuit, 206 shift register, 210 shift register, 220 matrix switch, 414 pixel memory, 415 Arithmetic circuit, 418 I / F circuit, 420 drive control unit, 430 timing memory, 441 sensor control unit, 442 block control unit, 443 synchronization control unit, 444 signal control unit, 500 imaging device, 520 photographing lens, 501 system control unit, 502 drive unit, 503 photometry unit, 504 work memory, 505 recording unit, 506 display unit, 511 image processing unit, 512 arithmetic unit

Claims

1. a first block including a first photoelectric conversion unit that converts light into electric charges, a second photoelectric conversion unit that converts light into electric charges and that is arranged alongside the first photoelectric conversion unit in the column direction, and a third photoelectric conversion unit that converts light into electric charges and that is arranged alongside the first photoelectric conversion unit in the row direction; a second block arranged alongside the first block in the column direction, the second block including a fourth photoelectric conversion unit that converts light into electric charges, a fifth photoelectric conversion unit that converts light into electric charges and that is arranged alongside the fourth photoelectric conversion unit in the column direction, and a sixth photoelectric conversion unit that converts light into electric charges and that is arranged alongside the fourth photoelectric conversion unit in the row direction; a third block which is arranged alongside the first block in the row direction and includes a seventh photoelectric conversion unit which converts light into an electric charge, an eighth photoelectric conversion unit which converts light into an electric charge and which is arranged alongside the seventh photoelectric conversion unit in the column direction, and a ninth photoelectric conversion unit which converts light into an electric charge and which is arranged alongside the seventh photoelectric conversion unit in the row direction; A first semiconductor chip having A semiconductor chip stacked on the first semiconductor chip, a first circuit including a first signal processing unit that performs signal processing on a first signal based on the charges converted by the first photoelectric conversion unit and a second signal based on the charges converted by the second photoelectric conversion unit, and a second signal processing unit that performs signal processing on a third signal based on the charges converted by the third photoelectric conversion unit, the first circuit being arranged to overlap with the first block in a stacking direction in which the first semiconductor chip and the second semiconductor chip are stacked; a second circuit including a third signal processing unit that performs signal processing on a fourth signal based on the charges converted by the fourth photoelectric conversion unit and a fifth signal based on the charges converted by the fifth photoelectric conversion unit, and a fourth signal processing unit that performs signal processing on a sixth signal based on the charges converted by the sixth photoelectric conversion unit, the second circuit being disposed so as to overlap with the second block in the stacking direction; a fifth signal processing unit that performs signal processing on a seventh signal based on the charges converted by the seventh photoelectric conversion unit and an eighth signal based on the charges converted by the eighth photoelectric conversion unit, and a sixth signal processing unit that performs signal processing on a ninth signal based on the charges converted by the ninth photoelectric conversion unit, and a third circuit that is arranged to overlap with the third block in the stacking direction; A second semiconductor chip having An imaging element comprising:

2. 2. The imaging device according to claim 1, The first semiconductor chip is a semiconductor layer in which the first photoelectric conversion unit, the second photoelectric conversion unit, the third photoelectric conversion unit, the fourth photoelectric conversion unit, the fifth photoelectric conversion unit, the sixth photoelectric conversion unit, the seventh photoelectric conversion unit, the eighth photoelectric conversion unit, and the ninth photoelectric conversion unit are arranged; a wiring layer in which a first signal line through which the first signal and the second signal are output, a second signal line through which the third signal is output, a third signal line through which the fourth signal and the fifth signal are output, a fourth signal line through which the sixth signal is output, a fifth signal line through which the seventh signal and the eighth signal are output, and a sixth signal line through which the ninth signal is output are disposed; having the wiring layer is disposed between the semiconductor layer and the second semiconductor chip in the stacking direction. Image sensor.

3. 3. The imaging device according to claim 1, the first signal processing unit has a first conversion unit that converts the first signal and the second signal into a digital signal; the second signal processing unit has a second conversion unit that converts the third signal into a digital signal; the third signal processing unit has a third conversion unit that converts the fourth signal and the fifth signal into digital signals; the fourth signal processing unit has a fourth conversion unit that converts the sixth signal into a digital signal; the fifth signal processing unit includes a fifth conversion unit that converts the seventh signal and the eighth signal into digital signals; The sixth signal processing unit has a sixth conversion unit that converts the ninth signal into a digital signal. Image sensor.

4. 4. The imaging device according to claim 3, the second conversion unit is arranged alongside the first conversion unit in the row direction, the fourth conversion unit is arranged alongside the third conversion unit in the row direction; The sixth conversion unit is arranged alongside the fifth conversion unit in the row direction. Image sensor.

5. 5. The imaging device according to claim 3, the first circuit has a first transmission unit that transmits a first digital signal obtained by converting the first signal into a digital signal in the first conversion unit, a second digital signal obtained by converting the second signal into a digital signal in the first conversion unit, and a third digital signal obtained by converting the third signal into a digital signal in the second conversion unit, the second circuit has a second transmission unit that transmits a fourth digital signal converted from the fourth signal to a digital signal by the third conversion unit, a fifth digital signal converted from the fifth signal to a digital signal by the third conversion unit, and a sixth digital signal converted from the sixth signal to a digital signal by the fourth conversion unit; the third circuit has a third transmission unit that transmits a seventh digital signal converted from the seventh signal to a digital signal by the fifth conversion unit, an eighth digital signal converted from the eighth signal to a digital signal by the fifth conversion unit, and a ninth digital signal converted from the ninth signal to a digital signal by the sixth conversion unit; Image sensor.

6. 6. The imaging device according to claim 5, the first transmission unit transmits the first digital signal, the second digital signal, and the third digital signal using a shift register; the second transmission unit transmits the fourth digital signal, the fifth digital signal, and the sixth digital signal by a shift register; the third transmission unit transmits the seventh digital signal, the eighth digital signal, and the ninth digital signal by a shift register; Image sensor.

7. 7. The imaging device according to claim 1, the first signal processing unit includes a first noise removal unit for removing noise included in the first signal and noise included in the second signal, and a second noise removal unit for removing noise included in the third signal; the second signal processing unit includes a third noise removal unit for removing noise included in the fourth signal and noise included in the fifth signal, and a fourth noise removal unit for removing noise included in the sixth signal; the third signal processing unit has a fifth noise removal unit for removing noise included in the seventh signal and noise included in the eighth signal, and a sixth noise removal unit for removing noise included in the ninth signal; Image sensor.

8. 8. The imaging device according to claim 7, the second noise removal unit is arranged alongside the first noise removal unit in the row direction, the fourth noise removal unit is arranged alongside the third noise removal unit in the row direction, the sixth noise removal unit is disposed alongside the fifth noise removal unit in the row direction; Image sensor.

9. 3. The imaging device according to claim 1, a first joint portion that electrically joins the first signal line and the second semiconductor chip; a second joint portion that electrically joins the second signal line and the second semiconductor chip; a third joint portion that electrically joins the third signal line and the second semiconductor chip; a fourth joint portion that electrically joins the fourth signal line and the second semiconductor chip; a fifth joint portion that electrically joins the fifth signal line and the second semiconductor chip; a sixth joint portion that electrically joins the sixth signal line and the second semiconductor chip; An imaging element comprising:

10. 10. The imaging device according to claim 9, the first joint portion has first metal members arranged to face each other in the stacking direction, the second joint portion has second metal members arranged to face each other in the stacking direction, The third joint portion is an imaging element having third metal members arranged to face each other in the stacking direction.

11. The imaging device according to claim 10, the first metal member is made of copper, the second metal member is made of copper, The third metal member is made of copper. Image sensor.

12. The imaging device according to any one of claims 9 to 11, The first signal processing unit performs signal processing on the first signal output via the first joint unit and the second signal output via the first joint unit, The second signal processing unit performs signal processing on the third signal output via the second joint unit, The third signal processing unit performs signal processing on the fourth signal output via the third joint unit and the fifth signal output via the third joint unit; The fourth signal processing unit performs signal processing on the sixth signal output via the fourth joint unit, The fifth signal processing unit performs signal processing on the seventh signal output via the fifth joint unit and the eighth signal output via the fifth joint unit; The sixth signal processing unit performs signal processing on the ninth signal output via the sixth joint unit. Image sensor.

13. 13. The imaging device according to claim 12, The first signal processing unit has a first conversion unit that converts the first signal output via the first joint unit and the second signal output via the first joint unit into a digital signal, the second signal processing unit has a second conversion unit that converts the third signal output via the second joint unit into a digital signal, The third signal processing unit has a third conversion unit that converts the fourth signal output via the third joint unit and the fifth signal output via the third joint unit into digital signals, the fourth signal processing unit has a fourth conversion unit that converts the sixth signal output via the fourth joint unit into a digital signal, The fifth signal processing unit has a fifth conversion unit that converts the seventh signal output via the fifth joint unit and the eighth signal output via the fifth joint unit into digital signals, The sixth signal processing unit has a sixth conversion unit that converts the ninth signal output via the sixth joint unit into a digital signal. Image sensor.

14. 14. The imaging device according to claim 13, the second conversion unit is arranged alongside the first conversion unit in the row direction, the fourth conversion unit is arranged alongside the third conversion unit in the row direction; The sixth conversion unit is arranged alongside the fifth conversion unit in the row direction. Image sensor.

15. 15. The imaging device according to claim 13, the first circuit has a first transmission unit that transmits a first digital signal obtained by converting the first signal into a digital signal in the first conversion unit, a second digital signal obtained by converting the second signal into a digital signal in the first conversion unit, and a third digital signal obtained by converting the third signal into a digital signal in the second conversion unit, the second circuit has a second transmission unit that transmits a fourth digital signal converted from the fourth signal to a digital signal by the third conversion unit, a fifth digital signal converted from the fifth signal to a digital signal by the third conversion unit, and a sixth digital signal converted from the sixth signal to a digital signal by the fourth conversion unit; the third circuit has a third transmission unit that transmits a seventh digital signal converted from the seventh signal to a digital signal by the fifth conversion unit, an eighth digital signal converted from the eighth signal to a digital signal by the fifth conversion unit, and a ninth digital signal converted from the ninth signal to a digital signal by the sixth conversion unit; Image sensor.

16. 16. The imaging device according to claim 15, the first transmission unit transmits the first digital signal, the second digital signal, and the third digital signal using a shift register; the second transmission unit transmits the fourth digital signal, the fifth digital signal, and the sixth digital signal by a shift register; the third transmission unit transmits the seventh digital signal, the eighth digital signal, and the ninth digital signal by a shift register; Image sensor.

17. The imaging device according to any one of claims 12 to 16, the first signal processing unit has a first noise removal unit for removing noise included in the first signal outputted through the first joint unit and noise included in the second signal outputted through the first joint unit, and a second noise removal unit for removing noise included in the third signal outputted through the second joint unit; the second signal processing unit has a third noise removal unit for removing noise included in the fourth signal output through the third joint unit and noise included in the fifth signal output through the third joint unit, and a fourth noise removal unit for removing noise included in the sixth signal output through the fourth joint unit, The third signal processing unit has a fifth noise removal unit for removing noise included in the seventh signal output through the fifth joint unit and noise included in the eighth signal output through the fifth joint unit, and a sixth noise removal unit for removing noise included in the ninth signal output through the sixth joint unit. Image sensor.

18. 18. The imaging device according to claim 17, the second noise removal unit is arranged alongside the first noise removal unit in the row direction, the fourth noise removal unit is arranged alongside the third noise removal unit in the row direction, the sixth noise removal unit is disposed alongside the fifth noise removal unit in the row direction; Image sensor.

19. 19. The imaging device according to claim 1, a first control unit that controls accumulation of the electric charge converted by the first photoelectric conversion unit, accumulation of the electric charge converted by the second photoelectric conversion unit, and accumulation of the electric charge converted by the third photoelectric conversion unit; a second control unit that controls accumulation of the electric charge converted by the fourth photoelectric conversion unit, accumulation of the electric charge converted by the fifth photoelectric conversion unit, and accumulation of the electric charge converted by the sixth photoelectric conversion unit; a third control unit that controls accumulation of the electric charge converted by the seventh photoelectric conversion unit, accumulation of the electric charge converted by the eighth photoelectric conversion unit, and accumulation of the electric charge converted by the ninth photoelectric conversion unit; An imaging element comprising:

20. 20. The imaging device according to claim 19, the first control unit, the second control unit, and the third control unit are disposed on the second semiconductor chip; Image sensor.

21. 19. The imaging device according to claim 1, the first block includes a first transfer unit that transfers charges converted by the first photoelectric conversion unit, a second transfer unit that transfers charges converted by the second photoelectric conversion unit, and a third transfer unit that transfers charges converted by the third photoelectric conversion unit; the second block includes a fourth transfer unit that transfers the charges converted by the fourth photoelectric conversion unit, a fifth transfer unit that transfers the charges converted by the fifth photoelectric conversion unit, and a sixth transfer unit that transfers the charges converted by the sixth photoelectric conversion unit, the third block includes a seventh transfer unit that transfers the charges converted by the seventh photoelectric conversion unit, an eighth transfer unit that transfers the charges converted by the eighth photoelectric conversion unit, and a ninth transfer unit that transfers the charges converted by the ninth photoelectric conversion unit. Image sensor.

22. 22. The imaging device according to claim 21, a first control unit that controls a timing at which the first transfer unit transfers electric charges from the first photoelectric conversion unit, a timing at which the second transfer unit transfers electric charges from the second photoelectric conversion unit, and a timing at which the third transfer unit transfers electric charges from the third photoelectric conversion unit; a second control unit that controls a timing at which the fourth transfer unit transfers the electric charge from the fourth photoelectric conversion unit, a timing at which the fifth transfer unit transfers the electric charge from the fifth photoelectric conversion unit, and a timing at which the sixth transfer unit transfers the electric charge from the sixth photoelectric conversion unit; a third control unit that controls a timing at which the seventh transfer unit transfers the electric charge from the seventh photoelectric conversion unit, a timing at which the eighth transfer unit transfers the electric charge from the eighth photoelectric conversion unit, and a timing at which the ninth transfer unit transfers the electric charge from the ninth photoelectric conversion unit; An imaging element comprising:

23. 23. The imaging device according to claim 22, the first control unit, the second control unit, and the third control unit are disposed on the second semiconductor chip; Image sensor.

24. 24. The imaging device according to claim 1, the second photoelectric conversion unit is disposed adjacent to the first photoelectric conversion unit in the column direction, the fifth photoelectric conversion unit is disposed adjacent to the fourth photoelectric conversion unit in the column direction, the eighth photoelectric conversion unit is disposed adjacent to the seventh photoelectric conversion unit in the column direction; Image sensor.

25. 25. The imaging device according to claim 1, the third photoelectric conversion unit is disposed adjacent to the first photoelectric conversion unit in the row direction, the sixth photoelectric conversion unit is disposed adjacent to the fourth photoelectric conversion unit in the row direction, the ninth photoelectric conversion unit is disposed adjacent to the seventh photoelectric conversion unit in the row direction. Image sensor.

26. 26. The imaging device according to claim 1, The second block is disposed adjacent to the first block in the column direction. Image sensor.

27. 27. The imaging device according to claim 1, the third block is disposed adjacent to the first block in the row direction; Image sensor.

28. 28. The imaging device according to claim 1, the first block includes a tenth photoelectric conversion unit that converts light into electric charges and is arranged alongside the third photoelectric conversion unit in the column direction; the second block includes an eleventh photoelectric conversion unit that converts light into an electric charge and is arranged alongside the sixth photoelectric conversion unit in the column direction; the third block includes a twelfth photoelectric conversion unit that converts light into an electric charge and is arranged alongside the ninth photoelectric conversion unit in the column direction; The second signal processing unit performs signal processing on a tenth signal based on the charge converted by the tenth photoelectric conversion unit; The fourth signal processing unit performs signal processing on an eleventh signal based on the charge converted by the eleventh photoelectric conversion unit; The sixth signal processing unit performs signal processing on a twelfth signal based on the charge converted by the twelfth photoelectric conversion unit. Image sensor.

29. 29. The imaging device according to claim 28, the tenth photoelectric conversion unit is disposed adjacent to the third photoelectric conversion unit in the column direction, the eleventh photoelectric conversion unit is disposed adjacent to the sixth photoelectric conversion unit in the column direction, the twelfth photoelectric conversion unit is disposed adjacent to the ninth photoelectric conversion unit in the column direction; Image sensor.

30. 30. The imaging device according to claim 29, the tenth photoelectric conversion unit is disposed adjacent to the second photoelectric conversion unit in the row direction, the eleventh photoelectric conversion unit is disposed adjacent to the fifth photoelectric conversion unit in the row direction, the twelfth photoelectric conversion unit is disposed adjacent to the eighth photoelectric conversion unit in the row direction; Image sensor.

31. 31. The imaging device according to claim 1 , An imaging element comprising a third semiconductor chip stacked on the first semiconductor chip.

32. An imaging device comprising the imaging element according to any one of claims 1 to 31.

33. 33. The imaging device according to claim 32, The imaging element receives light from a photographing lens having a plurality of optical lenses. Imaging device.

34. 34. The imaging device according to claim 32 or 33, an image capturing apparatus comprising an image processing unit electrically connected to the image capturing element and configured to generate image data;

Images