Semiconductor circuit device, integrated circuit device and inspection method

Abstract

To provide a semiconductor circuit device and the like that can suitably perform a screening test of a gate-source breakdown voltage of a transistor.SOLUTION: A semiconductor circuit device 10 includes a driver circuit 100, a pre-driver circuit 200, a first pad (pad PD1), first wiring L1, a second pad (pad PD2), second wiring L2, and a voltage clamp circuit 300. The driver circuit 100 includes a first transistor TR1 on a high side. The pre-driver circuit 200 includes a first pre-driver 210 that drives a gate of the first transistor TR1. The first wiring L1 connects the first pad (pad PD1) and a source of the first transistor TR1. The second wiring L2 connects the second pad (pad PD2) and a power supply node of the first pre-driver 210. The voltage clamp circuit 300 clamps power supplies of the first pre-driver 210.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor circuit device, an integrated circuit device, an inspection method, and the like. [Background technology]

[0002] Conventionally, there is known a metal-oxide-semiconductor field effect transistor (MOSFET) used in a power device, etc. Patent Document 1 discloses a method in which a pad connected to a gate of a MOSFET and a pad connected to an ESD protection circuit are separated and can be inspected individually. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2006-513585 Summary of the Invention [Problem to be solved by the invention]

[0004] In some cases, the gate of a MOSFET is driven by a pre-driver, and the pre-driver is protected by a voltage clamp circuit. Even in such cases, a method is required for performing a suitable gate-source voltage screening test of the MOSFET. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a semiconductor circuit device including a driver circuit including a first transistor on a high side, a pre-driver circuit including a first pre-driver that drives a gate of the first transistor, a first pad, a first wiring that connects the first pad and a source of the first transistor, a second pad, a second wiring that connects the second pad and a power supply node of the first pre-driver, and a voltage clamp circuit that clamps between the power supplies of the first pre-driver.

[0006] Another aspect of the present disclosure relates to an integrated circuit device that includes the above-mentioned semiconductor circuit device and a package that houses the semiconductor circuit device, and a power terminal of the package is electrically connected to the first pad and the second pad.

[0007] Another aspect of the present disclosure relates to a method for testing a semiconductor circuit device including a driver circuit including a first transistor on a high side, a pre-driver circuit including a first pre-driver that drives a gate of the first transistor, a first pad, a first wiring that connects the first pad and a source of the first transistor, a second pad, a second wiring that connects the second pad and a power supply node of the first pre-driver, and a voltage clamp circuit that clamps between the first pre-driver and a power supply, the method comprising: applying a first test voltage to the first pad to set the source of the first transistor to the first test voltage; applying a second test voltage different from the first test voltage to the second pad to set the gate of the first transistor to the second test voltage; and measuring a current flowing through the first pad, thereby performing a screening test of a gate-source withstand voltage of the first transistor. [Brief description of the drawings]

[0008] [Figure 1] 1 is a diagram for explaining a configuration example of a semiconductor circuit device according to an embodiment of the present invention; [Diagram 2] 1A to 1C are diagrams illustrating a screening test of a first transistor. [Diagram 3] FIG. 2 is a diagram illustrating an example of a half-bridge circuit according to the embodiment. [Figure 4] 3A and 3B are diagrams for explaining examples of connections between pads of a semiconductor circuit device and terminals of a package. [Diagram 5] 1A and 1B are diagrams for explaining an example of the layout of an IC chip in a semiconductor circuit device. [Figure 6] FIG. 2 is a diagram for explaining an example of an H-bridge circuit according to the embodiment; [Figure 7]11A and 11B are diagrams illustrating modified examples of a semiconductor circuit device. [Figure 8] 10A to 10C are diagrams illustrating a screening test of a first transistor in a modified example. [Figure 9] 13A to 13C are diagrams illustrating a screening test of a second transistor in a modified example. [Figure 10] FIG. 13 is a diagram illustrating an example of an H-bridge circuit according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] A preferred embodiment of the present disclosure will be described in detail below. Note that the embodiment described below does not unduly limit the contents described in the claims, and all of the configurations described in the embodiment are not necessarily essential configurations.

[0010] 1 shows a configuration example of a semiconductor circuit device 10 according to the present embodiment. In the following description, an external load M described below is a motor, and the semiconductor circuit device 10 functioning as a motor control device is exemplified, but for example, the external load M may be an LED, and the semiconductor circuit device 10 may function as an LED control device, and the use of the semiconductor circuit device 10 is not particularly limited. In the following description, operating the semiconductor circuit device 10 to drive the external load M will be referred to as normal operation.

[0011] A plurality of semiconductor circuit devices 10 are formed on a predetermined substrate having a predetermined shape by a wafer process. A substrate including the semiconductor circuit devices 10 thus formed is called a semiconductor wafer. The predetermined shape is, for example, a circle, but may be another shape such as a square. The predetermined substrate is, for example, a single crystal silicon substrate, but may be a sapphire substrate, a glass substrate, or the like. The wafer process refers to a method of forming a device by a patterning method that combines photolithography, CVD (Chemical Vapor Deposition), sputtering, etching, and the like. Then, the formed semiconductor wafer is subjected to a wafer level test process to determine whether the semiconductor circuit devices 10 formed on the semiconductor wafer are non-defective or not. The wafer level test process is specifically, for example, a probe test process, but may also include other stress tests. The probe test process is, for example, a test in which a semiconductor wafer including the semiconductor circuit devices 10 is set in an inspection device (not shown), the tips of probe needles arranged in a predetermined pattern are brought into contact with the pads of the semiconductor circuit devices 10, and a voltage is applied to each pad according to a predetermined test program. As a result, IC chips including semiconductor circuit devices 10 that do not meet the predetermined criteria are judged to be defective products that are likely to malfunction in a period shorter than the target period. Then, information on whether each IC chip included in the semiconductor wafer is good or bad is recorded, and after the IC chips are separated into individual IC chips through a subsequent dicing process, etc., only IC chips judged to be good are selected based on the information recorded in the wafer level test process. This allows IC chips judged to be defective to be screened out.

[0012] Thereafter, the individual IC chips are accommodated in a package 3, which will be described later, by an assembly process, and modularized as the integrated circuit device 1. In other words, the package 3 refers to each configuration of the integrated circuit device 1 excluding the IC chip. The form of the package 3 is DIP, QFP, etc., but a form such as BGA may also be adopted, and is appropriately determined at the time of designing the integrated circuit device 1. Thereby, each configuration of the package 3 and details of the assembly process are appropriately determined. For example, when the package 3 is DIP or QFP, the package 3 includes, for example, a lead frame, a bonding wire, a molding resin, a die bond material, etc., and the assembly process includes a wire bonding process, a resin sealing process, etc. Note that while FIG. 1 illustrates one semiconductor circuit device 10, the IC chip may include multiple semiconductor circuit devices 10, or may further include a circuit device other than the semiconductor circuit device 10. Also, the integrated circuit device 1 may be a multi-chip package including an IC chip other than the IC chip including the semiconductor circuit device 10.

[0013] The semiconductor circuit device 10 includes a driver circuit 100, a pre-driver circuit 200, a pad PD1 as a first pad, a first wiring L1, a pad PD2 as a second pad, a second wiring L2, and a voltage clamp circuit 300. That is, the pad PD1 in FIG. 1 corresponds to the first pad according to the method of the present embodiment, and the pad PD2 in FIG. 1 corresponds to the second pad according to the method of the present embodiment. In normal operation, a first voltage V1 is supplied to the pads PD1 and PD2 from a first power supply device (not shown). The first voltage V1 is a high-potential power supply voltage that is higher than a low-potential power supply voltage such as a ground voltage.

[0014] The driver circuit 100 controls an external load M not shown in FIG. 1. The driver circuit 100 includes a first transistor TR1. The first transistor TR1 in FIG. 1 is a P-type transistor, more specifically, a P-type MOSFET. The source of the first transistor TR1 is connected to a pad PD1 via a first wiring L1. The drain of the first transistor TR1 is connected to a node NM1. The node NM1 is connected to an external load M not shown via a pad PD3. That is, the driver circuit 100 in FIG. 1 includes a first transistor TR1 on the high side. When the semiconductor circuit device 10 functions as a motor control device, the first transistor TR1 can be realized by, for example, a transistor having a DMOS (Double-diffused Metal Oxide Semiconductor) structure. For example, when the first transistor TR1 is turned on, a voltage of 42 V is supplied as a first voltage V1 to the external load M via the pad PD3.

[0015] For ease of understanding, the first voltage V1 will be specifically described as 42V in the following description, but this is merely an example and does not limit the value of the first voltage V1. The same applies to the second voltage V2, third voltage V3, fourth voltage V4, first inspection voltage TV1, and second inspection voltage TV2, which will be described later.

[0016] The probe inspection process for the semiconductor circuit device 10 includes a process of inspecting whether the gate oxide film included in the first transistor TR1 is properly manufactured. The gate oxide film being properly manufactured means, for example, that the thickness of the manufactured gate oxide film is within a target range in design, that the manufactured gate oxide film does not contain any fatal defects, and the like. In this inspection, for example, a voltage higher than a first withstand voltage, which is the withstand voltage of the first transistor TR1, is applied between the source and gate of the first transistor TR1 for a short period of time, and the generated leakage current is measured. If there is a first transistor TR1 whose measured leakage current is higher than a predetermined reference value, the semiconductor circuit device 10 including the first transistor TR1 is determined to be defective, and the IC chip including the semiconductor circuit device 10 is excluded from the assembly process. For example, the first withstand voltage is about 5.5V to 6V when the first transistor TR1 is a P-type transistor with a DMOS structure.

[0017] By carrying out such an inspection, defective products resulting from manufacturing defects in the gate oxide film included in the first transistor TR1 are screened out. In other words, the probe inspection process for the first transistor TR1, etc. can also be said to be a screening test between the gate and source of the first transistor TR1, etc. Hereinafter, the withstand voltage screening test between the gate and source of the first transistor TR1, etc. may be simply referred to as the withstand voltage screening test of the first transistor TR1, etc.

[0018] The pre-driver circuit 200 includes a first pre-driver 210. The first pre-driver 210 drives the first transistor TR1 based on a control signal from a control circuit (not shown). The first pre-driver 210 drives the gate of the first transistor TR1. The second wiring L2 connects the pad PD2 to a node N1, which is a power supply node of the first pre-driver 210. The control circuit (not shown) is configured with a logic circuit or the like made of transistors having a complementary metal oxide semiconductor (CMOS) structure, and operates at a voltage of, for example, about 1.8V to 3.3V. In this way, the control circuit can control the driver circuit 100 via the pre-driver circuit 200. This allows the drive control of an external load M such as a motor.

[0019] The first pre-driver 210 includes, for example, an inverter circuit in which a P-type transistor and an N-type transistor are connected in series. The transistors included in the inverter circuit are configured, for example, with a CMOS structure. In this way, the size of the semiconductor circuit device 10 can be reduced. Since the transistors are CMOS structure transistors, if the withstand voltage of each transistor included in the first pre-driver 210 is a second withstand voltage, the second withstand voltage is about 5V, which is lower than the above-mentioned first withstand voltage.

[0020] One end of the first pre-driver 210 is connected to the node N1. The second wiring L2 connects the node N1 and the pad PD2. On the other hand, the power supply line indicated by D1 is a power supply line to which a third voltage V3 is supplied. The third voltage V3 is higher than the low potential side power supply voltage and lower than the first voltage V1. For example, the power supply line indicated by D1 is supplied with a third voltage V3 obtained by subtracting the second voltage V2 from the first voltage V1 by a regulator (not shown) based on the first voltage V1 and a second voltage V2 (described later). More specifically, when the first voltage V1 is 42V and the second voltage V2 is 5V as described above, the third voltage V3 is 37V. That is, the node N1 is a power supply node on the high potential side of the first pre-driver 210. The second voltage V2 is supplied from a second power supply device (not shown) via a pad PD4 (not shown in FIG. 1).

[0021] In this way, the first pre-driver 210 can operate the transistors included in the first pre-driver 210 in the range of the second withstand voltage (5V) by connecting to the 42V power line and the 37V power line. In addition, a control signal from a control circuit (not shown) is converted to a voltage of 42V or 37V through a level shifter (not shown) and input to the first pre-driver 210. As a result, in normal operation, the first pre-driver 210 outputs a voltage of 42V as a high level and a voltage of 37V as a low level. In this way, when a voltage of 37V is output from the first pre-driver 210 as a low level voltage, a voltage of 5V is applied between the source and gate since the first voltage V1 of 42V is supplied to the source of the first transistor TR1, which is a P-type transistor, as described above, and the first transistor TR1 is turned on.

[0022] By configuring the driver circuit 100 and the pre-driver circuit 200 in this manner, regardless of the magnitude of the voltage applied to the pads PD1 and PD2, the third voltage V3 (5V) is applied as a constant voltage between the source and gate of the first transistor TR1 when it is on. In other words, even if the value of the first voltage V1 is set to be equal to or greater than 42V or less than 42V, the voltage applied between the source and gate of the first transistor TR1 when it is on is the third voltage V3 (5V) as a constant voltage.

[0023] The voltage clamp circuit 300 clamps the voltage between the power supplies of the first pre-driver 210. That is, the voltage clamp circuit 300 prevents the first pre-driver 210 from being destroyed by a surge voltage such as static electricity. The voltage clamp circuit 300 includes, for example, a Zener diode ZD shown in FIG. 2. The Zener diode ZD has a withstand voltage of about 5.7V. Although the voltage clamp circuit 300 illustrates one Zener diode ZD in FIG. 2, it may include, for example, two Zener diodes ZD connected in series and in the opposite direction to each other, or may further include a resistor. In this way, the surge voltage can be clamped to a desired voltage whether it is positive or negative.

[0024] Next, an inspection method for a withstand voltage screening test of the first transistor TR1 in the semiconductor circuit device 10 of this embodiment will be described. In the inspection method of this embodiment, a first inspection voltage TV1 is applied to the pad PD1. As a result, the source of the first transistor TR1 is set to the first inspection voltage TV1. In addition, a second inspection voltage TV2 is applied to the pad PD2. The voltage value of the second inspection voltage TV2 is a voltage value different from that of the first inspection voltage TV1. The voltage value of the second inspection voltage TV2 may be 0V. In the following, taking into consideration that the first withstand voltage is about 5.5 to 6V as described above, the first inspection voltage TV1 is exemplified as 7V and the second inspection voltage TV2 is exemplified as 0V.

[0025] Specifically, for example, in Fig. 2, from an inspection device shown in E, a first inspection voltage TV1 (7V) is supplied to pads PD1 and PD3, and a second inspection voltage TV2 (0V) is supplied to pad PD2. Although not shown in Fig. 2, a second inspection voltage TV2 (0V) is supplied to pad PD4 from the inspection device. As a result, the voltages of the power supply nodes connected to the first pre-driver 210 are all 0V. Note that the inspection device is not shown in the following figures.

[0026] Then, a voltage of 0V is output from the first pre-driver 210 as a low level, and the gate of the first transistor TR1 is set to 0V, which is the second inspection voltage TV2. As a result, the source of the first transistor TR1 connected to the pad PD1 is set to the first inspection voltage TV1 (7V), and therefore a voltage of 7V is applied between the gate and source of the first transistor TR1. As a result, if a leakage current flows from the source to the gate of the first transistor TR1, the value of the current flowing through the pad PD1 increases. Therefore, by measuring the value of the current flowing through the pad PD1, a withstand voltage screening test of the first transistor TR1 can be performed.

[0027] Since the first inspection voltage TV1 (7V) is applied between the gate and source of the first transistor TR1, the first transistor TR1 is turned on. At this time, since the first inspection voltage TV1 (7V) is supplied to the pad PD3 as described above, the voltage of the node NM1 connected to the drain of the first transistor TR1 is 7V, and there is no potential difference between the source and drain of the first transistor TR1. In this way, when the first transistor TR1 has a DMOS structure, it is possible to prevent an excessive current from flowing between the source and drain of the first transistor TR1 when a screening test of the first transistor TR1 is performed.

[0028] From the above, the semiconductor circuit device 10 of this embodiment includes a driver circuit 100, a pre-driver circuit 200, a first pad (pad PD1), a first wiring L1, a second pad (pad PD2), a second wiring L2, and a voltage clamp circuit 300. The driver circuit 100 includes a first transistor TR1 on the high side. The pre-driver circuit 200 includes a first pre-driver 210 that drives the gate of the first transistor TR1. The first wiring L1 connects the first pad (pad PD1) and the source of the first transistor TR1. The second wiring L2 connects the second pad (pad PD2) and the power supply node of the first pre-driver 210. The voltage clamp circuit 300 clamps between the power supplies of the first pre-driver 210.

[0029] In this manner, the semiconductor circuit device 10 of this embodiment includes the driver circuit 100 and the pre-driver circuit 200, and therefore can control the driver circuit 100, which cannot be directly controlled by a control circuit (not shown). This allows the semiconductor circuit device 10 to be applied to power devices, for example. This allows the range of application of the semiconductor circuit device 10 to be broadened. In addition, the semiconductor circuit device 10 of this embodiment further includes the voltage clamp circuit 300, and therefore can protect the first pre-driver 210.

[0030] In the semiconductor circuit device 10 including the driver circuit 100, the pre-driver circuit 200, and the voltage clamp circuit 300, the withstand voltage screening test of the first transistor TR1 in the wafer level test process may not be performed properly. As described above, the semiconductor circuit device 10 may be configured such that only a constant voltage is applied between the gate and source of the first transistor TR1 in normal operation regardless of the value of the first voltage V1. In such a case, even if a voltage higher than the first withstand voltage is applied to the pad connected to the external terminal that supplies the first voltage V1 in the screening test of the first transistor TR1, only a voltage equal to or lower than the first withstand voltage is applied between the gate and source of the first transistor TR1. In addition, since the on / off of the first transistor TR1 is controlled by the control of the pre-driver circuit 200, the withstand voltage screening test of the first transistor TR1 cannot be performed by simply providing a pad connected to the gate of the first transistor TR1 as in the method of Patent Document 1.

[0031] In this regard, in the semiconductor circuit device 10 of this embodiment, the first wiring L1 is configured to connect the first pad (pad PD1) and the source of the first transistor TR1, and the second wiring L2 is configured to connect the second pad (pad PD2) and the power supply node (node ​​N1) of the first pre-driver 210. In this way, the voltage output from the first pre-driver 210 to the gate of the first transistor TR1 can be made different from the voltage supplied to the gate of the first transistor TR1. As a result, when the same voltage is supplied to the first wiring L1 and the second wiring L2, the difference between the voltage of the source of the first transistor TR1 and the voltage of the gate of the first transistor TR1 can be set to a desired value. As a result, a withstand voltage screening test of the first transistor TR1 can be performed.

[0032] Also, as described above, since a voltage (7V) exceeding 5.7V, which is the withstand voltage of the Zener diode ZD, can be applied to the first transistor TR1, a withstand voltage screening test of the first transistor TR1 can be performed using a desired voltage. Also, for example, the pads PD1 and PD2 are treated as one pad, the first inspection voltage TV1 is set to 5.5V, the second inspection voltage TV2 is set to 0V, and a voltage of 0V is output from the first pre-driver 210 as a low-level voltage, so that a withstand voltage screening test of the first transistor TR1 can be performed. However, in this case, the first inspection voltage TV1 of 5.5V is applied to both the first pre-driver 210 and the first transistor TR1, and it becomes impossible to distinguish between the leakage current of the first pre-driver 210 and the leakage current of the first transistor TR1. In this respect, by applying the method of this embodiment, only the leakage current of the first transistor TR1 can be measured. As a result, only the first transistor TR1 can be subject to the withstand voltage screening test without being affected by the first pre-driver 210.

[0033] The technique of this embodiment may be realized as an inspection method. That is, the inspection method of this embodiment is a method for inspecting a semiconductor circuit device 10 including a driver circuit 100, a pre-driver circuit 200, a first pad (pad PD1), a first wiring L1, a second pad (pad PD2), a second wiring L2, and a voltage clamp circuit 300. The driver circuit 100 includes a first transistor TR1 on the high side. The pre-driver circuit 200 includes a first pre-driver 210 that drives the gate of the first transistor TR1. The first wiring L1 connects the first pad (pad PD1) and the source of the first transistor TR1. The second wiring L2 connects the second pad (pad PD2) and the power supply node of the first pre-driver 210. The voltage clamp circuit 300 clamps between the power supplies of the first pre-driver 210. In the inspection method of this embodiment, the source of the first transistor TR1 is set to the first inspection voltage TV1 (7V) by applying a first inspection voltage TV1 (7V) to the first pad (pad PD1), and the gate of the first transistor TR1 is set to the second inspection voltage TV2 (0V) different from the first inspection voltage TV1 (7V) by applying a second inspection voltage TV2 (0V) to the second pad (pad PD2). In the inspection method of this embodiment, a screening test of the gate-source breakdown voltage of the first transistor TR1 is performed by measuring the current flowing through the first pad (pad PD1). In this way, the same effect as above can be obtained.

[0034] In the semiconductor circuit device 10 of this embodiment, the first transistor TR1 is a P-type transistor, and the power supply node (node ​​N1) of the first pre-driver 210 is a high-potential power supply node of the first pre-driver 210. In this manner, the difference between the voltage on the source side and the voltage on the gate side of the first transistor TR1, which is a P-type transistor, can be adjusted. This makes it possible to perform a screening test of the gate-source withstand voltage of the P-type transistor.

[0035] In the semiconductor circuit device 10 of this embodiment, the first transistor TR1 has a source supplied with a first voltage V1 (42V). The first pre-driver 210 supplies the first voltage V1 (42V) to the gate of the first transistor TR1 as a high-level voltage, and supplies a third voltage V3 (37V) obtained by subtracting a second voltage V2 (5V) lower than the first voltage V1 (42V) from the first voltage V1 (42V) to the gate of the first transistor TR1 as a low-level voltage. In this way, the first pre-driver 210 can control the supply of the third voltage V3 (37V) lower than the first voltage V1 (42V) supplied to the source of the first transistor TR1 to the gate of the first transistor TR1. This allows the gate-source voltage of the first transistor TR1 to be a desired voltage.

[0036] In the semiconductor circuit device 10 of this embodiment, the withstand voltage of the transistor included in the first pre-driver 210 is a second withstand voltage (5V) lower than the first withstand voltage (6V) of the first transistor TR1, and the voltage clamp circuit 300 protects the first pre-driver 210 by receiving the power supply voltage and clamping it to a voltage corresponding to the second withstand voltage or lower. In this way, a semiconductor circuit device 10 using the first pre-driver 210 composed of a transistor with a second withstand voltage lower than the first withstand voltage can be constructed, and a withstand voltage screening test of the first transistor TR1 can be performed. This allows the semiconductor circuit device 10 to be miniaturized, and allows a withstand voltage screening test of the first transistor TR1 to be performed.

[0037] Furthermore, in the inspection method of this embodiment, the voltage difference (7 V) between the first inspection voltage TV1 (7 V) and the second inspection voltage TV2 (0 V) is larger than the clamp voltage (5 V) of the voltage clamp circuit 300. In this way, a withstand voltage screening test of the first transistor TR1 can be performed using a voltage difference larger than the clamp voltage.

[0038] The method of this embodiment is not limited to the above, and various modifications such as adding other configurations are possible. For example, Fig. 1 shows a configuration example of a semiconductor circuit device 10 including a first transistor TR1 on the high side, but as shown in Fig. 3, a configuration example may be used in which a second transistor TR2 is further included on the low side to form a half-bridge circuit. Specifically, for example, the second transistor TR2 may be included in the driver circuit 100, and a second pre-driver 220 that drives the gate of the second transistor TR2 may be included in the pre-driver circuit 200.

[0039] The second transistor TR2 is, for example, an N-type MOSFET. The source of the second transistor TR2 is connected to the node NM1, and the drain is connected to the node NG1. The drain of the first transistor TR1 is connected to the aforementioned node NM1, and the source of the second transistor TR2 is connected to the node NG1. In normal operation, the pad PDG functions as a ground pad. That is, the node NG1 is a ground node.

[0040] The second pre-driver 220 can be realized by an inverter circuit similar to that of the first pre-driver 210. One end of the second pre-driver 220 is connected to a power supply line indicated by D2. In normal operation, a second voltage V2 is applied to the pad PD4 from a second power supply device (not shown). That is, the second pre-driver 220 is connected to the power supply line of the second voltage V2. The other end of the second pre-driver 220 is connected to a node NG11. The node NG11 is connected to a node NG1. That is, the second pre-driver 220 is connected to the node NG11, which is a ground node. In this way, the second pre-driver 220 outputs the second voltage V2 (5V) as a high level and a voltage of 0V as a low level. As a result, when a high level signal is output from the second pre-driver 220, the second transistor TR2 is turned on.

[0041] In addition, in certain cases, it is not necessary to provide a protection circuit for protecting the second pre-driver 220 between the pad PD4 and the second pre-driver 220. The certain cases include, for example, cases where sufficient electrostatic countermeasures are taken on the second power supply device side.

[0042] When the above-mentioned screening test of the first transistor TR1 is performed in the semiconductor circuit device 10 shown in Fig. 3, in addition to the above-mentioned method, a low-level signal may be output from the second pre-driver 220 to turn off the second transistor TR2. This provides insulation between the second transistor TR2 and the node NG, equivalent to Fig. 2. Alternatively, a probe needle may be brought into contact with the pad PDG to apply the second test voltage TV2 (0V).

[0043] From the above, in the semiconductor circuit device 10 of this embodiment, the driver circuit 100 includes the second transistor TR2 on the low side, and the pre-driver circuit 200 includes the second pre-driver 220 that drives the gate of the second transistor TR2. In this way, a half-bridge circuit consisting of the first transistor TR1 and the second transistor TR2 is configured, and a withstand voltage screening test of the first transistor TR1 can be suitably performed.

[0044] Also, each pad included in the semiconductor circuit device 10 of this embodiment may be connected to each external terminal of the package 3 as shown in FIG. 4. Here, the connection means that each pad included in the semiconductor circuit device 10 is electrically connected to each external terminal provided on the lead frame by a wire bonding process using a bonding wire. Note that FIG. 4 merely conceptually illustrates the features described below, and does not specifically specify the shapes of the semiconductor circuit device 10 and the package 3, nor does it specifically specify the positional relationship between the pads and the external terminals. For example, in FIG. 4, the external terminals are illustrated as being located to the right of the pads, but the external terminals may be located below the pads, and there is no particular limitation.

[0045] 4, the pad PD1 is connected to the terminal TM1 by a bonding wire indicated by A1. The pad PD2 is connected to the terminal TM1 by a bonding wire indicated by A2. The pad PD3 is connected to the terminal TM2, and the pad PDG is connected to the terminal TM3.

[0046] Terminal TM1 is connected to a first power supply device (not shown) via a wiring board or the like. That is, terminal TM1 functions as a power supply terminal, is arranged at a predetermined position on the wiring board so as to be electrically connected to the first power supply device, and is mounted on the wiring board using solder or the like. Similarly, terminal TM2 is connected to an external load M via the wiring board. Similarly, terminal TM3 functions as a ground terminal, and is connected to a ground pad of the wiring board.

[0047] Also, as shown in FIG. 4, the diameter of the bonding wire indicated by A1 may be larger than the diameter of the bonding wire indicated by A2. When the semiconductor circuit device 10 is used as a power device, the first transistor TR1 is turned on, and the amount of current flowing from the pad PD1 to the external load M via the first wiring L1 and the first transistor TR1 is larger than the amount of current flowing to the pad PD2 through the second wiring L2. In this regard, by applying the method of this embodiment, the cross-sectional area of ​​the bonding wire connected to the pad PD1 can be increased. This makes it possible to reduce the resistance of the bonding wire connected to the pad PD1. This makes it possible to construct the semiconductor circuit device 10 based on a wiring design that corresponds to the magnitude of the current flowing.

[0048] From the above, the integrated circuit device 1 of this embodiment includes the semiconductor circuit device 10 and the package 3 that houses the semiconductor circuit device 10, and the power supply terminal (terminal TM1) of the package 3 is electrically connected to the first pad (pad PD1) and the second pad (pad PD2). In this way, the specifications of the package 3 can be made common. For example, suppose that the method of this embodiment is applied to an IC chip that does not have a pad corresponding to the pad PD2 in FIG. 1, and the specifications of the IC chip are changed. In this case, for a certain reason, the manufacturer may have to manage both the integrated circuit device 1 that houses the IC chip before the specification change and the integrated circuit device 1 that houses the IC chip after the specification change. The certain reason may be that the user of the integrated circuit device 1 continues to use the integrated circuit device 1 using the IC chip before the specification change. In this regard, by applying the method of this embodiment, the manufacturer of the integrated circuit device 1 can manufacture the integrated circuit device 1 using a common package 3 for both the IC chip before the specification change and the IC chip after the specification change. This reduces the manufacturer's burden of managing the package 3.

[0049] Although not specifically shown, the width of the wiring of the first wiring L1 and the width of the wiring of the second wiring L2 may be different from each other for the same reason as above. This is because, as the wiring width becomes wider, the cross-sectional area of ​​the wiring increases, and the same effect as above can be expected. That is, in the semiconductor circuit device 10 of this embodiment, the wiring width of the first wiring L1 is wider than the wiring width of the second wiring L2. In this way, the wiring resistance of the first wiring L1 can be made lower than the wiring resistance of the second wiring L2. This allows the semiconductor circuit device 10 to be constructed based on a wiring design that corresponds to the magnitude of the current flowing.

[0050] Although not specifically illustrated, the width of the first wiring L1 and the width of the third wiring L3 may be different from each other. The current flowing through the third wiring L3 is a current for driving the gate of the first transistor TR1 or a leakage current in a screening test of the first transistor TR1 to which the method of this embodiment is applied, and the amount of current flowing through the third wiring L3 is smaller than the current for driving the external load M through the first wiring L1. For this reason, the semiconductor circuit device 10 of this embodiment includes a third wiring L3 that connects the output node of the first pre-driver 210 and the gate of the first transistor TR1, and the wiring width of the first wiring L1 is wider than the wiring width of the third wiring L3. In this way, the wiring resistance of the first wiring L1 can be made lower than the wiring resistance of the third wiring L3. This allows the semiconductor circuit device 10 to be constructed based on a wiring design that corresponds to the magnitude of the current that can flow.

[0051] The semiconductor circuit device 10 of this embodiment may be arranged as shown in FIG. 5. FIG. 5 is a plan view of an IC chip related to the semiconductor circuit device 10 as viewed from above. FIG. 5 illustrates a case in which one IC chip includes two channels of the semiconductor circuit device 10. In FIG. 5, the first transistor TR1 and the second transistor TR2 in one semiconductor circuit device 10 are shown as the first transistor TR1-1 and the second transistor TR2-1, and the first transistor TR1 and the second transistor TR2 in the other semiconductor circuit device 10 are shown as the first transistor TR1-2 and the second transistor TR2-2. In FIG. 5, configurations that are not directly related to the characteristics described below (such as the pre-driver circuit 200 and the voltage clamp circuit 300) are omitted from the illustration.

[0052] Since the pad PD3 is connected to both the first transistor TR1 and the second transistor TR2, in FIG. 5, the pad PD3 is disposed between the first transistor TR1 and the second transistor TR2. The pads PD1 and PD2 are disposed so that the distance indicated by C1 is shorter than the distance indicated by C2. In other words, the semiconductor circuit device 10 of this embodiment includes a third pad (pad PD3) electrically connected to the drain of the first transistor TR1, and the distance between the first pad (pad PD1) and the third pad (pad PD3) is shorter than the distance between the second pad (pad PD2) and the third pad (pad PD3). In this way, the wiring resistance between the first pad (pad PD1) and the third pad (pad PD3) can be further reduced. This allows the semiconductor circuit device 10 to be constructed based on a wiring design that corresponds to the magnitude of the current that can flow.

[0053] The semiconductor circuit device 10 of this embodiment may also configure an H-bridge circuit as shown in B1 of FIG. 6. The H-bridge circuit shown in B1 includes driver circuits 100-1 and 100-2 and pads PD1, PD2, PD3-1, PD3-2, and PDG. The driver circuit 100-1 and pads PD1, PD2, PD3-1, and PDG correspond to the driver circuit 100 and pads PD1, PD2, PD3, and PDG in FIG. 3, respectively. The gate of the first transistor TR1 is driven and controlled by a first pre-driver 210-1 included in the pre-driver circuit 200-1. That is, the first pre-driver 210-1 included in the pre-driver circuit 200-1 in FIG. 6 corresponds to the first pre-driver 210 included in the pre-driver circuit 200 in FIG. 3. Similarly, the gate of the second transistor TR2 is driven and controlled by a second pre-driver 220-1 included in the pre-driver circuit 200-1. 3. That is, the second pre-driver 220-2 included in the pre-driver circuit 200-1 in FIG. 6 corresponds to the second pre-driver 220 included in the pre-driver circuit 200 in FIG.

[0054] The driver circuit 100-2 is a circuit similar to the driver circuit 100-1, and includes a third transistor TR3 and a fourth transistor TR4. The third transistor TR3 is a P-type transistor similar to the first transistor TR1 in FIG. 1 and the like, and the fourth transistor TR4 is an N-type transistor similar to the second transistor TR2 in FIG. 3. The gate of the third transistor TR3 is driven and controlled by a first pre-driver 210-2 included in the pre-driver circuit 200-2. The first pre-driver 210-2 is a pre-driver similar to the first pre-driver 210-1. The gate of the fourth transistor TR4 is driven and controlled by a second pre-driver 220-2 included in the pre-driver circuit 200-2. The second pre-driver 220-2 is a pre-driver similar to the second pre-driver 220-1.

[0055] The pad PD1 is connected to the gate of the first transistor TR1 and the gate of the third transistor TR3. The pad PD2 is connected to the high potential side power supply node of the first pre-driver 210-1 and the high potential side power supply node of the first pre-driver 210-2. The pad PDG is connected to the source of the second transistor TR2 and the source of the fourth transistor TR4, respectively, and functions as a ground pad as in FIG. 3. The pad PD3-2 is connected to the external load M as in FIG. 3, and the pad PD3-2 is connected to the drain of the third transistor TR3 and the drain of the fourth transistor TR4, respectively.

[0056] 4, the pads PD1 and PD2 shown in the dotted frame of B11 are connected to one external terminal of the package 3 by bonding wires or the like. Similarly, the pad PD3-1 shown in the dotted frame of B12 is connected to one external terminal of the package 3, the pad PDG shown in the dotted frame of B13 is connected to one external terminal of the package 3, and the pad PD3-2 shown in the dotted frame of B14 is connected to one external terminal of the package 3. In other words, the number of pads constituting the H-bridge circuit shown in B1 is five, but the number of external terminals of the package 3 connected to the pads is four.

[0057] By configuring such an H-bridge circuit, for example, when the external load M is a motor, the semiconductor circuit device 10 can function as a motor driver. Note that many known control methods for the motor driver have been proposed, and a detailed description thereof will be omitted since it is only necessary to select an appropriate method.

[0058] The method of this embodiment can also be applied to the case where the first transistor TR1 on the high side is an N-type transistor. It can also be applied to the second transistor TR2 on the low side. As a modification of this embodiment, a semiconductor circuit device 10 including the first transistor TR1 and the second transistor TR2, which are N-type transistors, will be described with reference to Figures 7, 8, and 9.

[0059] FIG. 7 differs from FIG. 3 in that the pad connected to the external load M is divided into two, the pad PD3A and the pad PD3B. FIG. 7 also differs from FIG. 3 in that the pad that supplies the voltage for driving the external load M is a single pad, the pad PD1. FIG. 7 also differs from FIG. 3 in that the pad connected to the ground line is divided into two, the pad PDGA and the pad PDGB. In the modified example, for convenience of explanation, the voltage applied to the pad PD1 in FIG. 7 is the fourth voltage V4, and the voltage value of the fourth voltage V4 is 42V, which is the same as the voltage value of the first voltage V1. In other words, the fourth voltage V4 in FIG. 7 is substantially the same as the first voltage V1 in FIG. 1 and the like.

[0060] In FIG. 7, the drain of the first N-type transistor TR1 is connected to a node NV. The node NV is connected to a pad PD1. That is, the voltage of the node NV is a fourth voltage V4 (42V). Also, the source of the first N-type transistor TR1 is connected to a node NM2. The node NM2 in FIG. 7 is connected to an external load M (not shown) via a pad PD3B. Also, in FIG. 7, the first pre-driver 210 is connected to a node N2. The node N2 is connected to an external load M (not shown) via a pad PD3A. That is, when the voltage at the node N2 is a fifth voltage V5, the fifth voltage V5 is adjusted to match the voltage at the pad PD3A. Also, since the fifth voltage V5 is influenced by the external load M, it may not be a constant value but may fluctuate. Therefore, a specific value of the fifth voltage V5 is not shown. Also, the first pre-driver 210 is connected to a power supply line indicated by D3. The power supply line indicated by D3 is a power supply line of a sixth voltage V6 as a high potential side voltage of the first pre-driver 210. The sixth voltage V6 is output from a regulator (not shown) so that the value of the sixth voltage V6 is a value obtained by adding the value of the second voltage V2 (5V) described above to the value of the fifth voltage V5. That is, the node N2 is a low potential side power supply node of the first pre-driver 210. In normal operation, the first pre-driver 210 outputs the sixth voltage V6 as a high level and outputs the fifth voltage V5 as a low level.

[0061] The drain of the second transistor TR2 is connected to the node NM2. The source of the second transistor TR2 is connected to the pad PDGB. Similarly to FIG. 3, in normal operation, the pad PDGB functions as a ground pad. One end of the second pre-driver 220 is connected to the node NG2. The pad PDGA is connected to the node NG2 and functions as a ground pad in normal operation. That is, one end of the second pre-driver 220 is connected to the node NG2 as a ground node. The other end of the second pre-driver 220 is also connected to the power supply line indicated by D4, and the second voltage V2 is applied from the pad PD4. In normal operation, the second pre-driver 220 outputs the second voltage V2 as a high level and outputs the ground voltage (0V) as a low level.

[0062] A withstand voltage screening test of the first transistor TR1 in the semiconductor circuit device 10 of the modified example will be described with reference to Fig. 8. A first inspection voltage TV1 (7V) is applied to the pad PD3A from an inspection device (not shown). On the other hand, a second inspection voltage TV2 (0V) is supplied to the pads PD1, PD3B, PDGA, PDGB, and PD4. That is, the value of the second voltage V2 is 0V in Fig. 8. As a result, the second transistor TR2 is turned off.

[0063] Since the first inspection voltage TV1 (7V) is supplied to the pad PD3A, the voltage of the node N2 is 7V. That is, the value of the fifth voltage V5 in this case is 7V. Therefore, the value of the sixth voltage V6 described above is 7V, which is the sum of the value of the second voltage V2 (0V) and the value of the fifth voltage V5 (7V). Then, a voltage of 7V is output from the first pre-driver 210, and the voltage of the gate of the first transistor TR1 becomes 7V. On the other hand, since the value of the second inspection voltage TV2 applied to the pad PD3B is 0V, the voltage of the source of the first transistor TR1 connected to the pad PD3B is 0V.

[0064] As a result, a voltage of 7 V is applied between the gate and source of the first transistor TR1, causing a leakage current from the gate to the source of the first transistor TR1, increasing the value of the current flowing through the pad PD3B. Therefore, by measuring the value of the current flowing through the pad PD3B, a withstand voltage screening test of the first transistor TR1 can be performed.

[0065] From the above, in the modified example, the pad PD3B corresponds to the first pad according to the method of the present embodiment, the pad PD3A corresponds to the second pad, the wiring connecting the source of the first transistor TR1 and the pad PD3B corresponds to the first wiring L1, and the wiring connecting the pad PD3A and the node N2 corresponds to the second wiring L2. Thus, in the semiconductor circuit device 10 of the present embodiment, the first transistor TR1 is an N-type transistor, and the power supply node (node ​​N2) of the first pre-driver 210 is the low-potential power supply node of the first pre-driver 210. In this way, it is possible to construct a first pre-driver 210 that includes the first pad and the second pad and adjusts the difference between the voltage on the source side and the voltage on the gate side of the first transistor TR1, which is an N-type transistor.

[0066] In the semiconductor circuit device 10 of this embodiment, the drain of the first transistor TR1 is supplied with the fourth voltage V4 (42V), and the first pre-driver 210 supplies the fifth voltage V5, which is the source voltage of the first transistor TR1, to the gate of the first transistor TR1 as a low-level voltage. The first pre-driver 210 also supplies the sixth voltage V6, which is the sum of the second voltage V2 (5V) lower than the fourth voltage V4 (42V) and the fifth voltage V5, to the gate of the first transistor TR1 as a high-level voltage. In this way, the first pre-driver 210 can be constructed to control the on / off of the gate of the first transistor TR1 based on the fifth voltage V5 and the sixth voltage V6 within the range of the second withstand voltage.

[0067] A breakdown voltage screening test of the second transistor TR2 in the semiconductor circuit device 10 of the modified example will be described with reference to FIG. 9. A first test voltage TV1 (7V) is applied to the pad PDGA from a test device (not shown). A second test voltage TV2 (0V) is supplied to the pads PD3A, PD3B, and PDGB. A voltage equal to or higher than the first test voltage TV1 (7V) is applied to the pad PD4 from a test device (not shown). A level-shifted control signal is input from a control circuit (not shown) to the second pre-driver 220, which outputs a low-level voltage of 7V, and the voltage of the gate of the second transistor TR2 becomes 7V. As a result, the source of the second transistor TR2 is connected to the pad PDGB and is therefore at 0V, so a voltage of 7V is applied between the gate and source of the second transistor TR2. As a result, a leakage current is generated from the gate to the source of the second transistor TR2, and the value of the current flowing through the pad PDGB increases. Therefore, by measuring the current value flowing through the pad PDGB, a withstand voltage screening test of the second transistor TR2 can be performed. Note that, as long as the first transistor TR1 on the high side can be turned off, the magnitude of the voltage applied to the pad PD1 does not matter.

[0068] In addition, when performing a withstand voltage screening test of the second transistor TR2, the semiconductor circuit device 10 may be configured as shown in FIG. 3, and the first inspection voltage TV1 (7V) may be applied directly to the gate of the second transistor TR2 by setting a second power supply device (not shown). In this case, leakage currents and the like caused by transistors included in the second pre-driver 220 and the like are also generated, and the leakage current value generated from the second transistor TR2 cannot be accurately measured. In this regard, by applying the method shown in FIG. 9, leakage currents caused only by the second transistor TR2 can be generated, and the reliability of the withstand voltage screening test of the second transistor TR2 can be improved. In addition, the same effect can be expected for the withstand voltage screening test of the first transistor TR1 described above.

[0069] Moreover, the semiconductor circuit device 10 of the modified example can configure an H-bridge circuit shown in B2 of FIG. 10. The H-bridge circuit shown in B2 includes driver circuits 100-1 and 100-2 and pads PD1, PD3A-1, PD3B-1, PDGA-1, PDGB-1, PD3A-2, PD3B-2, PDGA-2, and PDGB-2. The driver circuit 100-1 and pads PD1, PD3A-1, PD3B-1, PDGA-1, and PDGB-1 correspond to the driver circuit 100 and pads PD1, PD3A, PD3B, PDGA, and PDGB, respectively, of FIG. 7. The gate of the first transistor TR1 is driven and controlled by a first pre-driver 210-1 included in the pre-driver circuit 200-1. The first pre-driver 210-1 included in the pre-driver circuit 200-1 of FIG. 10 corresponds to the first pre-driver 210 included in the pre-driver circuit 200 of FIG. 7. 7. Similarly, the second pre-driver 220-1 included in the pre-driver circuit 200-1 in FIG. 10 corresponds to the second pre-driver 220 included in the pre-driver circuit 200 in FIG.

[0070] The driver circuit 100-2 in Fig. 10 is the same as the driver circuit 100-1. The third transistor TR3 in Fig. 10 is an N-type transistor similar to the first transistor TR1 in Fig. 7, and the fourth transistor TR4 is an N-type transistor similar to the second transistor TR2 in Fig. 7. Note that the first pre-driver 210-2 and the second pre-driver 220-2 included in the pre-driver circuit 200-2 are the same as those in Fig. 7, and therefore description thereof will be omitted.

[0071] The pad PD1 is connected to the gate of the first transistor TR1 and the gate of the third transistor TR3. The pad PD3A-1 connected to the low potential side power supply node of the first pre-driver 210-1 is connected to a node connecting the pad PD3B-1 and an external power supply. Similarly, the pad PD3A-2 connected to the low potential side power supply node of the first pre-driver 210-2 is connected to a node connecting the pad PD3B-2 and an external power supply. The pad PDGA is connected to a ground node to which the second pre-drivers 220-1 and 220-2 are connected. The pad PDGB is connected to the source of the second transistor TR2 and the source of the fourth transistor TR4.

[0072] Also, the pad PD1 shown in the dotted frame of B21 is connected to one external terminal of the package 3 by a bonding wire or the like. Also, the pads PD3A-1 and PD3B-1 shown in the dotted frame of B22 are connected to one external terminal of the package 3. That is, as described above, the pads PD3A-1 and PD3B-1 are connected to the same external terminal by wire bonding or the like. Similarly, the pads PDGA and PDGB shown in the dotted frame of B23 are connected to one external terminal of the package 3. Similarly, the pads PD3A-2 and PD3B-2 shown in the dotted frame of B24 are connected to one external terminal of the package 3. That is, in the modified example, the number of pads constituting the H-bridge circuit shown in B2 is seven, but the number of external terminals of the package 3 connected to the pads is four.

[0073] As described above, the semiconductor circuit device of this embodiment includes a driver circuit, a pre-driver circuit, a first pad, a first wiring, a second pad, a second wiring, and a voltage clamp circuit. The driver circuit includes a first transistor on the high side. The pre-driver circuit includes a first pre-driver that drives a gate of the first transistor. The first wiring connects the first pad and a source of the first transistor. The second wiring connects the second pad and a power supply node of the first pre-driver. The voltage clamp circuit clamps between the power supplies of the first pre-driver.

[0074] In this way, the voltage output from the first pre-driver to the gate of the first transistor can be made different from the voltage supplied to the gate of the first transistor. As a result, when the same voltage is supplied to the first wiring and the second wiring, the difference between the voltage of the source of the first transistor and the voltage of the gate of the first transistor can be set to a desired value. This makes it possible to perform a withstand voltage screening test of the first transistor.

[0075] The width of the first wiring may be wider than the width of the second wiring.

[0076] By doing so, the wiring resistance of the first wiring can be made lower than the wiring resistance of the second wiring.

[0077] The circuit may also include a third wiring that connects the output node of the first pre-driver and the gate of the first transistor, and the wiring width of the first wiring may be wider than the wiring width of the third wiring.

[0078] By doing so, the wiring resistance of the first wiring can be made lower than the wiring resistance of the third wiring.

[0079] In addition, the breakdown voltage of the transistor included in the first pre-driver may be a second breakdown voltage lower than a first breakdown voltage which is a breakdown voltage of the first transistor, and the voltage clamp circuit may receive the power supply voltage and protect the first pre-driver by clamping it to a voltage corresponding to the second breakdown voltage or lower.

[0080] In this way, it is possible to construct a semiconductor circuit device 10 using a first pre-driver made up of a transistor having a second withstand voltage lower than the first withstand voltage, and to perform a withstand voltage screening test on the first transistor.

[0081] Also, the first transistor may be a P-type transistor, and the power supply node of the first pre-driver may be a high potential side power supply node of the first pre-driver.

[0082] In this way, the difference between the voltage on the source side and the voltage on the gate side of the first transistor, which is a P-type transistor, can be adjusted.

[0083] In addition, a first voltage may be supplied to the source of the first transistor, and the first pre-driver may supply the first voltage as a high-level voltage to the gate of the first transistor, and supply a third voltage, obtained by subtracting a second voltage lower than the first voltage from the first voltage, to the gate of the first transistor as a low-level voltage.

[0084] In this way, the first pre-driver can control so as to supply a third voltage, which is lower than the first voltage supplied to the source of the first transistor, to the gate of the first transistor.

[0085] Moreover, the first transistor may be an N-type transistor, and the power supply node of the first pre-driver may be a low potential side power supply node of the first pre-driver.

[0086] In this way, a first pre-driver can be constructed that includes a first pad and a second pad and adjusts the difference between the voltage on the source side and the voltage on the gate side of the first transistor, which is an N-type transistor.

[0087] The first transistor may have a drain supplied with a fourth voltage, and the first pre-driver may supply a fifth voltage, which is a source voltage of the first transistor, to the gate of the first transistor as a low-level voltage. The first pre-driver may supply a sixth voltage, which is a sum of a second voltage lower than the fourth voltage and the fifth voltage, to the gate of the first transistor as a high-level voltage.

[0088] In this way, a first pre-driver can be constructed that controls the on / off of the gate of the first transistor based on the fifth voltage and the sixth voltage within the second withstand voltage range.

[0089] Moreover, the driver circuit may include a second transistor on the low side, and the pre-driver circuit may include a second pre-driver that drives the gate of the second transistor.

[0090] In this manner, a half-bridge circuit made up of the first transistor and the second transistor can be configured, and a withstand voltage screening test of the first transistor can be suitably performed.

[0091] The semiconductor device may also include a third pad electrically connected to the drain of the first transistor, and the distance between the first pad and the third pad may be shorter than the distance between the second pad and the third pad.

[0092] In this way, the wiring resistance between the first pad and the third pad can be further reduced.

[0093] Moreover, the integrated circuit device of the present embodiment includes the above-mentioned semiconductor circuit device and a package that houses the semiconductor circuit device, and a power supply terminal of the package is electrically connected to the first pad and the second pad.

[0094] The inspection method of the present embodiment is an inspection method for a semiconductor circuit device including a driver circuit, a pre-driver circuit, a first pad, a first wiring, a second pad, a second wiring, and a voltage clamp circuit. The driver circuit includes a first transistor on the high side. The pre-driver circuit includes a first pre-driver that drives the gate of the first transistor. The first wiring connects the first pad and the source of the first transistor. The second wiring connects the second pad and the power supply node of the first pre-driver. The voltage clamp circuit clamps between the power supplies of the first pre-driver. In the inspection method of the present embodiment, a first inspection voltage is applied to the first pad to set the source of the first transistor to the first inspection voltage, and a second inspection voltage different from the first inspection voltage is applied to the second pad to set the gate of the first transistor to the second inspection voltage. In the inspection method of the present embodiment, a screening test of the gate-source withstand voltage of the first transistor is performed by measuring the current flowing through the first pad.

[0095] Furthermore, the voltage difference between the first inspection voltage and the second inspection voltage may be larger than the clamp voltage of the voltage clamp circuit.

[0096] In this way, a withstand voltage screening test of the first transistor can be performed using a voltage difference larger than the clamp voltage.

[0097] Although the present embodiment has been described in detail as above, it will be easily understood by those skilled in the art that many modifications are possible without substantially departing from the novel matters and effects of the present disclosure. Therefore, all such modifications are intended to be included in the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader meaning or synonymy can be replaced with that different term anywhere in the specification or drawings. In addition, all combinations of the present embodiment and modifications are also included in the scope of the present disclosure. In addition, the configurations and operations of the semiconductor circuit device, integrated circuit device, inspection method, etc. are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0098] 1...integrated circuit device, 3...package, 10...semiconductor circuit device, 100, 100-1, 100-2...driver circuit, 200, 200-1, 200-2...pre-driver circuit, 210, 220-1, 220-2...first pre-driver, 220, 220-1, 220-2...second pre-driver, 300...voltage clamp circuit, L1...first wiring, L2...second wiring, L3...third wiring, M...external load, N1, N2, NM1, NM2, NG1, NG2, NV...node, PD1, PD2, PD3, PD3A, PD 3A-1, PD3A-2, PD3B, PD3B-1, PD3B-2, PD4, PDG, PDGA, PDGA-1, PDGA-2, PDGB, PDGB-1, PDGB-2...pad, TM1, TM2, TM3...terminal, TR1...first transistor, TR2...second transistor, TR3...third transistor, TR4...fourth transistor, TV1...first test voltage, TV2...second test voltage, V1...first voltage, V2...second voltage, V3...third voltage, V4...fourth voltage, V5...first voltage, V6...sixth voltage

Claims

1. a driver circuit including a first transistor on a high side; a pre-driver circuit including a first pre-driver for driving a gate of the first transistor; A first pad; a first wiring that connects the first pad and a source of the first transistor; A second pad; a second wiring that connects the second pad and a power supply node of the first pre-driver; a voltage clamp circuit that clamps a voltage between the power supplies of the first pre-driver; A semiconductor circuit device comprising:

2. 2. The semiconductor circuit device according to claim 1, A semiconductor circuit device, wherein the first wiring has a width wider than the second wiring.

3. 2. The semiconductor circuit device according to claim 1, a third wiring that connects an output node of the first pre-driver and a gate of the first transistor; A semiconductor circuit device, wherein a width of the first wiring is wider than a width of the third wiring.

4. 2. The semiconductor circuit device according to claim 1, a withstand voltage of a transistor included in the first pre-driver is a second withstand voltage that is lower than a first withstand voltage that is a withstand voltage of the first transistor; The voltage clamp circuit includes: a semiconductor circuit device that receives a power supply voltage and protects the first pre-driver by clamping the power supply voltage to a voltage equal to or lower than the second withstand voltage;

5. 2. The semiconductor circuit device according to claim 1, The first transistor is It is a P-type transistor, The power supply node of the first pre-driver is a high potential side power supply node of the first pre-driver.

6. 6. The semiconductor circuit device according to claim 5, The first transistor is A first voltage is provided to the source; The first pre-driver is a third voltage obtained by subtracting a second voltage lower than the first voltage from the first voltage is supplied to the gate of the first transistor as a low-level voltage.

7. 2. The semiconductor circuit device according to claim 1, The first transistor is It is an N-type transistor, The power supply node of the first pre-driver is a low potential side power supply node of the first pre-driver.

8. 8. The semiconductor circuit device according to claim 7, The first transistor is A fourth voltage is provided to the drain; The first pre-driver is supplying a fifth voltage, which is a source voltage of the first transistor, to a gate of the first transistor as a low-level voltage; a sixth voltage obtained by adding a second voltage lower than the fourth voltage and the fifth voltage is supplied as a high-level voltage to the gate of the first transistor.

9. 2. The semiconductor circuit device according to claim 1, The driver circuit includes: a second transistor on a low side; The pre-driver circuit includes: a second pre-driver that drives a gate of the second transistor.

10. 2. The semiconductor circuit device according to claim 1, a third pad electrically connected to a drain of the first transistor; A semiconductor circuit device, wherein a distance between the first pad and the third pad is shorter than a distance between the second pad and the third pad.

11. A semiconductor circuit device according to any one of claims 1 to 10, a package that houses the semiconductor circuit device; Including, a power supply terminal of the package electrically connected to the first pad and the second pad,

12. a driver circuit including a first transistor on a high side; a pre-driver circuit including a first pre-driver for driving a gate of the first transistor; A first pad; a first wiring that connects the first pad and a source of the first transistor; A second pad; a second wiring that connects the second pad and a power supply node of the first pre-driver; a voltage clamp circuit that clamps a voltage between the first pre-driver and a power supply; A method for testing a semiconductor circuit device, comprising: applying a first inspection voltage to the first pad to set the source of the first transistor to the first inspection voltage; applying a second inspection voltage different from the first inspection voltage to the second pad, thereby setting the gate of the first transistor to the second inspection voltage; a gate-source breakdown voltage of the first transistor is screened by measuring a current flowing through the first pad.

13. 13. The inspection method according to claim 12, A test method, comprising: a voltage difference between the first test voltage and the second test voltage that is greater than a clamp voltage of the voltage clamp circuit.

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