Circuit device and power conversion circuit

Abstract

To reduce the number of terminals in a power conversion circuit.SOLUTION: A circuit device includes a power conversion circuit and a control circuit that controls the power conversion circuit, the power conversion circuit includes a control terminal to which a control signal from the control circuit is input, an output terminal to which an output signal is output to the control circuit, and a data identification unit that identifies an input data signal input to the output terminal. A first superimposed signal in which the output signal and the input data signal are superimposed is input to the data identification unit, and the data identification unit may identify the input data signal on the basis of the first superimposed signal and the output signal.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a circuit device and a power conversion circuit. [Background technology]

[0002] 2. Description of the Related Art Conventionally, circuits such as power conversion circuits and control circuits for controlling the circuits are known (see, for example, Patent Documents 1 to 4). Patent Document 1: JP 2014-93903 A Patent Document 2: JP 2009-258016 A Patent Document 3: JP 2011-172336 A Patent Document 4: JP 2020-96436 A Summary of the Invention [Problem to be solved by the invention]

[0003] In a circuit such as a power conversion circuit, it is preferable to have a small number of terminals. [Means for solving the problem]

[0004] In order to solve the above problems, one aspect of the present invention provides a circuit device including a power conversion circuit and a control circuit that controls the power conversion circuit. In the above circuit device, the power conversion circuit may have a control terminal to which a control signal from the control circuit is input. In any of the above circuit devices, the power conversion circuit may have an output terminal that outputs an output signal to the control circuit. In any of the above circuit devices, the power conversion circuit may have a data identification unit that identifies an input data signal input to the output terminal.

[0005] In any of the circuit devices described above, a first superimposed signal in which the output signal and the input data signal are superimposed may be input to the data identification unit. In any of the circuit devices described above, the data identification unit may identify the input data signal based on the first superimposed signal and the output signal.

[0006] In any of the circuit devices described above, the data discrimination section may extract pulses other than pulses of the output signal from among pulses included in the first superimposed signal to generate the input data signal.

[0007] In any of the circuit devices described above, the output signal may include an alarm signal indicating whether or not the power conversion circuit has reached a preset state.

[0008] In any of the circuit devices described above, the output signal may include an output data signal output by the power conversion circuit.

[0009] Any of the above circuit devices may include a first transmission section provided between the output terminal and the control circuit and outputting a signal from the output terminal to the control circuit. Any of the above circuit devices may include a second transmission section superimposing the input data signal from the control circuit on a signal at the output terminal. In any of the above circuit devices, the data identification section may receive the signal at the output terminal.

[0010] In any of the circuit devices described above, the control circuit may receive the first superimposed signal, and identify the output signal based on the first superimposed signal and the input data signal.

[0011] In any of the circuit devices described above, the first transmission section may transmit to the control circuit a signal at the output terminal that is equal to or greater than a reference current value.In any of the circuit devices described above, the second transmission section may convert the input data signal into a signal having a current smaller than the reference current value and superimpose the converted signal on the signal at the output terminal.

[0012] In any of the circuit devices described above, the power conversion circuit may include a clock identification unit that separates a clock signal input to the control terminal from the control signal.

[0013] In any of the circuit devices described above, a second superimposed signal in which the control signal and the clock signal having an amplitude different from that of the control signal are superimposed on each other may be input to the control terminal. In any of the circuit devices described above, the clock identification unit may separate the control signal and the clock signal based on the amplitude of each pulse included in the second superimposed signal.

[0014] Any of the above circuit devices may include a third transmission section provided between the control circuit and the control terminal and configured to transmit the control signal to the control terminal. Any of the above circuit devices may include a fourth transmission section provided between the control circuit and the control terminal and configured to transmit the clock signal to the control terminal to generate the second superimposed signal. In any of the above circuit devices, at least one of the third transmission section and the fourth transmission section may have an amplitude conversion section that converts the amplitude of a signal.

[0015] In any of the circuit devices described above, the control circuit may arrange the pulses of the control signal and the pulses of the clock signal in different periods.

[0016] In any of the circuit devices described above, the control circuit may be capable of arranging a pulse of the control signal and a pulse of the clock signal in the same period.

[0017] Any of the above circuit devices may include an amplitude control unit that is provided between the control circuit and the control terminal and that generates a pulse having an amplitude different from both the amplitude of the pulse of the control signal and the amplitude of the pulse of the clock signal during a period when the pulse of the control signal and the pulse of the clock signal overlap.

[0018] In any of the above circuit devices, the amplitude control section may have a power supply wiring. In any of the above circuit devices, the amplitude control section may have a signal wiring to which the control signal is applied. In any of the above circuit devices, the amplitude control section may have a first resistor, a second resistor, and a third resistor connected in series between the power supply wiring and the signal wiring. In any of the above circuit devices, the clock signal may be applied to a connection point between the first resistor and the second resistor. In any of the above circuit devices, a connection point between the second resistor and the third resistor may be connected to the control terminal.

[0019] In a second aspect of the present invention, there is provided a power conversion circuit controlled by a control circuit. The power conversion circuit may include a control terminal to which a control signal from the control circuit is input. Any of the power conversion circuits may include an output terminal that outputs an output signal to the control circuit. Any of the power conversion circuits may include a data identification unit that identifies an input data signal input to the output terminal.

[0020] In any of the power conversion circuits described above, a first superimposed signal in which the output signal and the input data signal are superimposed may be input to the data discrimination unit. In any of the power conversion circuits described above, the data discrimination unit may discriminate the input data signal based on the first superimposed signal and the output signal.

[0021] In any of the power conversion circuits described above, the data discrimination section may extract pulses other than pulses of the output signal from pulses included in the first superimposed signal to generate the input data signal.

[0022] In any of the power conversion circuits described above, the output signal may include an alarm signal indicating whether or not the power conversion circuit has reached a preset state.

[0023] In any of the power conversion circuits described above, the output signal may include an output data signal output by the power conversion circuit.

[0024] Any of the power conversion circuits described above may include a clock identification unit that separates a clock signal input to the control terminal from the control signal.

[0025] In any of the power conversion circuits described above, a second superimposed signal in which the control signal and the clock signal having an amplitude different from that of the control signal are superimposed may be input to the control terminal. In any of the power conversion circuits described above, the clock identification unit may separate the control signal and the clock signal based on the amplitude of each pulse included in the second superimposed signal.

[0026] The above summary of the invention does not list all of the features of the present invention. In addition, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0027] [Figure 1] 1 is a diagram showing an example of a circuit device 10 according to an embodiment of the present invention. [Diagram 2] 2 is a diagram showing a specific circuit example of the circuit device 10. FIG. [Diagram 3] 11 is a timing chart illustrating an operation related to an input data signal SDAIu and an output signal OS. [Figure 4] 4 is a timing chart illustrating operations related to control signals and clock signals. [Diagram 5] 13 is a diagram illustrating another exemplary configuration of the third transmission section 330 and the power conversion circuit 200. FIG. [Figure 6] 4 is a timing chart illustrating the operations of the control circuit 100, the transmission device 300, and the signal identification unit 250. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The present invention will be described below through the embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. In this specification and drawings, elements having substantially the same functions and configurations are given the same reference numerals to avoid repeated explanations, and elements not directly related to the present invention are not shown. In addition, in one drawing, elements having the same functions and configurations may be given the same reference numerals as representative elements, and the reference numerals may be omitted for the others.

[0029] In this specification, when the term "same" or "equal" is used, it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0030] FIG. 1 is a diagram showing an example of a circuit device 10 according to an embodiment of the present invention. The circuit device 10 includes one or more power conversion circuits 200 and a control circuit 100. The power conversion circuit 200 may output power to another circuit of a target device in which the circuit device 10 is provided. As an example, the control circuit 100 is a computer provided in the target device. The control circuit 100 may control a circuit other than the power conversion circuit 200 of the target device. As an example, the target device is a car or an industrial robot, but is not limited thereto. The circuit device 10 may further include a transmission device 300 that transmits a signal between the power conversion circuit 200 and the control circuit 100. The transmission device 300 may be provided for each power conversion circuit 200.

[0031] The power conversion circuit 200 converts input power into a predetermined output power. As an example, the power conversion circuit 200 is an AC / DC converter that converts DC power into AC power, but the form of the power conversion circuit 200 is not limited to this. The power conversion circuit 200 may include a power semiconductor such as an IGBT. The power conversion circuit 200 may include an inverter. The power conversion circuit 200 may supply power to an electric motor such as a motor.

[0032] The control circuit 100 controls the power conversion circuit 200. The control circuit 100 may control the on and off of the operation of the power conversion circuit 200, and may control the amplitude or frequency of the power output by the power conversion circuit 200. The control circuit 100 of this example transmits a control signal to each power conversion circuit 200. The control signal may control the switching of a transistor inside the power conversion circuit 200.

[0033] The power conversion circuit 200 has a control terminal 202 and an output terminal 204. A control signal from the control circuit 100 is input to the control terminal 202 via the transmission device 300. The output terminal 204 outputs an output signal to the control circuit 100. The output signal is transmitted by the transmission device 300.

[0034] The output signal is, for example, a signal indicating the state of the power conversion circuit 200. The output signal may include an alarm signal indicating whether the power conversion circuit 200 is in any of the preset states. The state may be an abnormal state such as an overcurrent state in which a current of a predetermined value or more flows at a predetermined point of the power conversion circuit 200, an overvoltage state in which a voltage of a predetermined value or more is applied to a predetermined point of the power conversion circuit 200, or an overheat state in which the temperature at a predetermined point of the power conversion circuit 200 is equal to or higher than a predetermined value. The power conversion circuit 200 may change the pulse width of the alarm signal depending on the type of the abnormal state. This allows the control circuit 100 to detect the type of abnormality that has occurred in the power conversion circuit 200.

[0035] The output signal may include an output data signal generated by the power conversion circuit 200. The output signal may include one or both of an alarm signal and an output data signal. The output data signal may be a signal that numerically indicates an internal state of the power conversion circuit 200. The output data signal may indicate a numerical value of a parameter such as temperature, voltage, or current at a predetermined point of the power conversion circuit 200. The output data signal may be data generated in response to a request from the control circuit 100. Each signal in this specification may be a signal that indicates one or multiple bits of information by the arrangement pattern of pulses on the time axis.

[0036] The control circuit 100 of this example has a control output terminal 102, a clock output terminal 104, an input terminal 106, and a data output terminal 108. The control output terminal 102 outputs a control signal. The clock output terminal 104 outputs a clock signal. The input terminal 106 receives an output signal from the power conversion circuit 200. The data output terminal 108 outputs an input data signal.

[0037] The input data signal is a signal including data to be input to the power conversion circuit 200. The input data signal may include any data. The input data signal may include data specifying a destination of an output signal of the power conversion circuit 200, may include data to be recorded in a memory inside the power conversion circuit 200, or may include data for controlling the operation of the power conversion circuit 200.

[0038] The clock signal is used for communication between the control circuit 100 and the power conversion circuit 200. For example, the power conversion circuit 200 may sample the data value of an input data signal according to the period of the clock signal. The clock signal may be used as an operation clock for a circuit inside the power conversion circuit 200.

[0039] The period of the clock signal may be smaller than the pulse width of the alarm signal. The period of the clock signal may be equal to or smaller than half the pulse width of the alarm signal. The power conversion circuit 200 may generate an alarm signal having a pulse width that is an integer multiple of the period of the clock signal. The power conversion circuit 200 may generate an output data signal having the same period as the clock signal. The control circuit 100 may determine that an alarm signal is being output when the pulse width of the output signal is equal to or greater than a certain value. When the alarm signal and the output data signal should be output simultaneously, the power conversion circuit 200 may output one of the signals with priority. The power conversion circuit 200 may output the alarm signal with priority.

[0040] The transmission device 300 of this example inputs an input data signal from the control circuit 100 to an output terminal 204 of the power conversion circuit 200. The power conversion circuit 200 has a data identification unit that identifies the input data signal input to the output terminal 204. The output terminal 204 functions as a terminal for outputting an output signal and also functions as a terminal for inputting an input data signal, thereby making it possible to reduce the number of terminals of the power conversion circuit 200.

[0041] The transmission device 300 may input both the control signal and the clock signal to the control terminal 202. The power conversion circuit 200 may have a clock identification unit that separates the clock signal input to the control terminal 202 from the control signal. The control terminal 202 functions as a terminal for inputting the control signal and also functions as a terminal for inputting the clock signal, thereby further reducing the number of terminals of the power conversion circuit 200.

[0042] When a plurality of power conversion circuits 200 are connected to a common terminal of the control circuit 100, an identification code may be assigned to each of the power conversion circuits 200. At least one of the input data signal and the output data signal may include the identification code. When starting communication with any of the power conversion circuits 200, the control circuit 100 may transmit an input data signal including the identification code of the power conversion circuit 200. When each of the power conversion circuits 200 receives an input data signal including an identification code corresponding to itself, the control circuit 100 may operate according to the input data signal. The control circuit 100 may determine which of the power conversion circuits 200 the output data signal is from based on identification information included in the output data signal.

[0043] The control circuit 100 may notify the power conversion circuit 200 of the start of communication by transmitting a clock signal. In another example, the control circuit 100 may notify the power conversion circuit 200 of the start of communication in a manner similar to I2C communication. The control circuit 100 may notify the power conversion circuit 200 of the start of communication by using an input data signal.

[0044] 2 is a diagram showing a specific circuit example of the circuit device 10. First, a configuration relating to the output signal and the input data signal transmitted between the output terminal 204, the input terminal 106, and the data output terminal 108 will be described. Next, a configuration relating to the control signal and the clock signal transmitted between the control terminal 202, the control output terminal 102, and the clock output terminal 104 will be described.

[0045] (Configuration for output signals and input data signals) The power conversion circuit 200 of this example includes a signal output unit 210 and a data discrimination unit 220 connected to the output terminal 204. The signal output unit 210 outputs an output signal OS to be transmitted from the power conversion circuit 200 to the control circuit 100. The output signal OS may include at least one of an alarm signal ALMOm and an output data signal SDAOm. The output signal OS of this example is a logical OR signal of the alarm signal ALMOm and the output data signal SDAOm.

[0046] The signal output unit 210 of this example includes a NOR circuit 213, a buffer circuit 212, and a resistor 211. The NOR circuit 213 outputs an output signal OS indicating the NOR of the alarm signal ALMOm and the output data signal SDAOm. For example, the alarm signal ALMOm and the output data signal SDAOm may be signals indicating one or more bits of information by the arrangement pattern of pulses on the time axis. Each signal in this specification may be a signal in which an H-level voltage indicates a logical value of 1 and an L-level voltage indicates a logical value of 0. The NOR circuit 213 of this example may output an L-level voltage when at least one of the alarm signal ALMOm and the output data signal SDAOm indicates an H-level voltage, and may output an H-level voltage when both the alarm signal ALMOm and the output data signal SDAOm indicate an L-level voltage.

[0047] The buffer circuit 212 outputs a signal corresponding to the output signal OS. The output terminal of the buffer circuit 212 is connected to the output terminal 204 via a resistor 211. The input data signal SDAIu from the control circuit 100 is applied to the output terminal 204 in this example. Therefore, a first superimposed signal WAS1 in which the output signal OS and the input data signal SDAIu are superimposed is applied to the output terminal 204. The first superimposed signal WAS1 in this example contains a mixture of pulses of the output signal OS and pulses of the input data signal SDAIu.

[0048] The data discrimination unit 220 extracts the input data signal SDAIm from the first superimposed signal WAS1. In this specification, the symbol u or m may be added to the end of the code of each signal transmitted between the control circuit 100 and the power conversion circuit 200. A signal with the symbol u is a signal transmitted by the control circuit 100 or received by the control circuit 100. A signal with the symbol m is a signal transmitted by the power conversion circuit 200 or received by the power conversion circuit 200.

[0049] The data discrimination unit 220 of this example discriminates the input data signal SDAIm based on the first superimposed signal WAS1 and the output signal OS. For example, the input data signal SDAIm can be discriminated by extracting a pulse train that is not a pulse of the output signal OS from among the pulses included in the first superimposed signal WAS1. The data discrimination unit 220 of this example has a reference voltage generation unit 221, a comparator 222, and a logic circuit 223.

[0050] The reference voltage generating unit 221 generates a first reference voltage for extracting each pulse of the first superimposed signal WAS1. The first reference voltage in this example is higher than the L level voltages and lower than the H level voltages of all pulses included in the first superimposed signal WAS1.

[0051] The comparator 222 outputs a signal that indicates an L-level voltage when the voltage of the first superimposed signal WAS1 is equal to or lower than the first reference voltage, and indicates an H-level voltage when the voltage is higher than the first reference voltage. The signal includes all pulses of the first superimposed signal WAS1 (waveform indicating an L-level voltage).

[0052] The logic circuit 223 extracts pulses other than the pulses of the output signal OS from the pulses included in the first superimposed signal WAS1 to generate the input data signal SDAIm. The logic circuit 223 of this example outputs an input data signal SDAIm that is at L level when the output signal OS indicates a voltage of H level and the output of the comparator 222 indicates a voltage of L level, and is at H level in other periods. That is, the input data signal SDAIm has a pulse in a period when the output signal OS has no pulse and the first superimposed signal WAS1 has a pulse. The logic circuit 223 may output a signal obtained by inverting the logical product of the inverted signal of the output of the comparator 222 and the output signal OS. The logic circuit 223 may have other structures. For example, the logic circuit 223 may include a circuit that outputs the exclusive OR of the output signal OS and the first superimposed signal WAS1.

[0053] With this configuration, it is possible to extract the input data signal SDAIm input to the output terminal 204 from the first superimposed signal WAS1. Since there is no need to provide a new terminal for inputting the input data signal SDAIm, the number of terminals of the power conversion circuit 200 can be reduced.

[0054] The transmission device 300 of this example has a first transmission section 310 and a second transmission section 320 provided between the output terminal 204 and the control circuit 100. The first transmission section 310 outputs a signal at the output terminal 204 to the input terminal 106 of the control circuit 100. The second transmission section 320 superimposes an input data signal SDAIu from the data output terminal 108 of the control circuit 100 on the signal at the output terminal 204. As a result, a first superimposed signal WAS1 is applied to the output terminal 204.

[0055] The first transmission unit 310 of this example has a resistor 311, a photocoupler 313, and a resistor 316. The photocoupler 313 includes a light-emitting element 314 such as a light-emitting diode, and a light-receiving element 315 such as a phototransistor. By using the photocoupler 313, a signal can be transmitted while electrically insulating the transmitting side and the receiving side of the signal.

[0056] The light emitting element 314 emits light in response to a pulse of the first superimposed signal WAS1. In this example, the light emitting element 314 has a predetermined high voltage (e.g., 15 V) applied to its anode, and a predetermined high voltage (e.g., 15 V) also applied to its cathode via a resistor 316. The cathode of the light emitting element 314 is connected to the output terminal 204. As a result, the light emitting element 314 emits light when the first superimposed signal WAS1 becomes an L level voltage.

[0057] The light receiving element 315 converts the light from the light emitting element 314 into an electric signal. The light receiving element 315 may generate an electric signal having an amplitude different from that of the first superimposed signal WAS1, or may generate an electric signal having the same amplitude. A predetermined high voltage VDD is applied to the collector of the light receiving element 315 in this example via a resistor 311, and a predetermined reference potential GND1 is applied to the emitter. The collector of the light receiving element 315 is also connected to the input terminal 106. As a result, an input signal ALMu_SDAu having the same pulse pattern as the first superimposed signal WAS1 and an amplitude according to the high voltage VDD is applied to the input terminal 106. The high voltage VDD may be different from the high voltage (e.g., 15V) applied to the resistor 316. The high voltage VDD in this example is 5V. The reference potential GND1 is, for example, 0V.

[0058] The pulse pattern of the input signal ALMu_SDAu is the same as that of the first superimposed signal WAS1. Therefore, the input signal ALMu_SDAu includes pulses of both the output signal OS and the input data signal SDAIu. The control circuit 100 may extract the pulse pattern of the output signal OS from the input signal ALMu_SDAu based on the pulse pattern of the input data signal SDAIu generated by itself. The control circuit 100 may extract, as the pulse pattern of the output signal OS, pulses from the input signal ALMu_SDAu during a period in which the input data signal SDAIu has no pulses. This process may be performed by a logical operation process by a computer, or may be performed by a circuit similar to the data discrimination unit 220.

[0059] The second transmission section 320 of this example includes a buffer circuit 321, a resistor 322, a photocoupler 323, and a Zener diode 326. The photocoupler 323 includes a light emitting element 324 such as a light emitting diode, and a light receiving element 325 such as a phototransistor.

[0060] The light-emitting element 324 emits light in response to the pulse of the input data signal SDAIu. In this example, a high voltage VDD is applied to the anode of the light-emitting element 324. The cathode of the light-emitting element 324 is connected to the output of the buffer circuit 321 via a resistor 322. The input of the buffer circuit 321 is connected to the data output terminal 108. The buffer circuit 321 applies a voltage in response to the input data signal SDAIu to the cathode of the light-emitting element 324. This causes the light-emitting element 324 to emit light in response to the pulse (L-level voltage) in the input data signal SDAIu.

[0061] The light receiving element 325 converts the light from the light emitting element 324 into an electric signal. A predetermined high voltage (e.g., 15V) is applied to the collector of the light receiving element 325 in this example via the Zener diode 326 and the resistor 316, and a predetermined reference potential GND2 is applied to the emitter. The reference potential GND2 is, for example, 0V.

[0062] The anode of the Zener diode 326 is connected to the collector of the light receiving element 325, and a high voltage (for example, 15 V) is applied to the cathode via the resistor 316. The cathode of the Zener diode 326 is connected to the output terminal 204. The amplitude of the input data signal SDAIu superimposed on the output terminal 204 is determined according to the breakdown voltage of the Zener diode 326. In this example, the L-level voltage of the input data signal SDAIu superimposed on the output terminal 204 is equal to the breakdown voltage of the Zener diode 326. The breakdown voltage of the Zener diode 326 may be smaller than the high voltage (for example, 15 V) applied to the resistor 316. As an example, the breakdown voltage of the Zener diode 326 is 5 V.

[0063] As described above, a signal having the same pulse pattern as the first superimposed signal WAS1 may be input to the input terminal 106 of the control circuit 100. The control circuit 100 may identify the output signal OS based on the received first superimposed signal WAS1 and the input data signal SDAIu. The control circuit 100 may determine that a pulse of the first superimposed signal WAS1 that does not match a pulse of the input data signal SDAIu is a pulse of the output signal OS. When the control circuit 100 determines that a pulse of the output signal OS is present in the first superimposed signal WAS1, the control circuit 100 may stop outputting the input data signal SDAIu. This prevents the pulse of the input data signal SDAIu from overlapping with the pulse of the output signal OS in the first superimposed signal WAS1, and allows the pulse of the output signal OS to be preferentially communicated. When no pulse of the output signal OS is received for a set period, the control circuit 100 may resume outputting the input data signal SDAIu.

[0064] In another example, a signal having the same pulse pattern as the output signal OS may be input to the input terminal 106 of the control circuit 100. In this case, the control circuit 100 can process the pulse pattern of the signal input to the input terminal 106 as the pulse pattern of the output signal OS. The first transmission unit 310 transmits to the control circuit 100 a signal (a pulse in this example) that causes a current equal to or greater than a reference current value to flow, from among the first superimposed signal WAS1 at the output terminal 204. The reference current value is the lower limit current value at which the light-emitting element 314 can emit light.

[0065] The buffer circuit 212 and the resistor 211 of this example pass a current equal to or greater than a reference current value to the light-emitting element 314 in response to the pulse of the output signal OS. Meanwhile, the second transmission unit 320 converts the input data signal SDAIu into a signal of a current smaller than the reference current value and superimposes it on the signal at the output terminal 204. By adjusting the breakdown current of the Zener diode 326, the current flowing in response to the pulse of the input data signal SDAIu can be adjusted. The second transmission unit 320 may have an element such as a resistor that adjusts the breakdown current of the Zener diode 326 in series with the Zener diode 326. This allows the light-emitting element 314 to emit light in response to the pulse of the output signal OS, and the light-emitting element 314 to not emit light depending on the pulse of the input data signal SDAIu. Therefore, a signal having the same pulse pattern as the output signal OS can be input to the input terminal 106 of the control circuit 100.

[0066] (Configuration of control signals and clock signals) The power conversion circuit 200 of this example includes a control discrimination unit 230 and a clock discrimination unit 240 connected to a control terminal 202. A second superimposed signal WAS2 on which a control signal BRu and a clock signal SCLu are superimposed is input to the control terminal 202. The control discrimination unit 230 discriminates the control signal BRu included in the second superimposed signal WAS2. The clock discrimination unit 240 discriminates the clock signal SCLu included in the second superimposed signal WAS2.

[0067] The second superimposed signal WAS2 includes a pulse of the control signal BRu and a pulse of the clock signal SCLu. The pulse of the control signal BRu and the pulse of the clock signal SCLu included in the second superimposed signal WAS2 are pulses that can be distinguished from each other. In this example, the pulse of the control signal BRu and the pulse of the clock signal SCLu have different amplitudes from each other.

[0068] The control discrimination unit 230 separates and discriminates the control signal BRu included in the second superimposed signal WAS2 from the clock signal SCLu. The control discrimination unit 230 of this example discriminates the pulses of the control signal BRu based on the amplitude of each pulse included in the second superimposed signal WAS2. The control discrimination unit 230 of this example has a reference voltage generation unit 231 and a comparator 232.

[0069] The reference voltage generating unit 231 generates a second reference voltage according to the amplitude of the pulses of the control signal BRu and the clock signal SCLu. For example, when the voltage of the pulse of the control signal BRu (in this example, the voltage of the L level) is lower than the voltage of the pulse of the clock signal SCLu, the second reference voltage is a voltage between the voltage of the pulse of the control signal BRu and the voltage of the pulse of the clock signal SCLu.

[0070] The comparator 232 outputs a control signal BRm which indicates an L level voltage when the voltage of the second superimposed signal WAS2 is equal to or lower than the second reference voltage, and which indicates an H level voltage when the voltage is higher than the second reference voltage. In this example, the voltage of the pulse of the control signal BRu is lower than the second reference voltage, and the voltage of the pulse of the clock signal SCLu is higher than the second reference voltage. Therefore, by comparing the voltage of the second superimposed signal WAS2 with the second reference voltage, it is possible to generate the control signal BRm by extracting the pulse of the control signal BRu included in the second superimposed signal WAS2.

[0071] The clock discrimination unit 240 separates and discriminates the clock signal SCLu included in the second superimposed signal WAS2 from the control signal BRu. The clock discrimination unit 240 of this example discriminates the pulses of the clock signal SCLu based on the amplitude of each pulse included in the second superimposed signal WAS2. The control discrimination unit 230 of this example has a reference voltage generation unit 241, a comparator 242, and a logic circuit 243.

[0072] The reference voltage generating unit 241 generates a third reference voltage according to the amplitude of the pulses of the control signal BRu and the clock signal SCLu. The third reference voltage in this example is higher than the voltages (L-level voltages) of the pulses of the control signal BRu and the clock signal SCLu, and lower than the H-level voltages.

[0073] The comparator 242 outputs a signal indicating an L level voltage when the voltage of the second superimposed signal WAS2 is equal to or lower than the third reference voltage, and an H level voltage when the voltage is higher than the third reference voltage. In this example, the voltages of the pulses of the control signal BRu and the clock signal SCLu are lower than the third reference voltage. Therefore, the signal output by the comparator 242 includes all the pulses of the second superimposed signal WAS2.

[0074] The logic circuit 243 extracts pulses other than the pulses of the control signal BRm from the pulses included in the second superimposed signal WAS2 to generate a clock signal SCLm. The logic circuit 243 of this example outputs a clock signal SCLm that is at L level during a period when the control signal BRm indicates an H level voltage and the comparator 242 outputs an L level voltage, and is at H level during other periods. The logic circuit 243 may output a signal obtained by inverting the logical product of an inverted signal of the output of the comparator 242 and the control signal BRm. The logic circuit 243 may have another structure, as described for the logic circuit 223.

[0075] With this configuration, it is possible to separate and identify the control signal BRu and the clock signal SCLu input to the control terminal 202. Since there is no need to provide a new terminal for inputting the clock signal SCLu, the number of terminals of the power conversion circuit 200 can be reduced.

[0076] In this example, the case where the voltage of the pulse of the control signal BRu is lower than the voltage of the pulse of the clock signal SCLu has been described. In another example, the voltage of the pulse of the control signal BRu may be higher than the voltage of the pulse of the clock signal SCLu. When the second superimposed signal WAS2 including such a pulse is input to the control terminal 202 shown in FIG. 2, the output of the control discrimination unit 230 corresponds to the clock signal SCLm, and the output of the clock discrimination unit 240 corresponds to the control signal BRm.

[0077] The transmission device 300 of this example has a third transmission section 330 and a fourth transmission section 340 provided between the control terminal 202 and the control circuit 100. The third transmission section 330 outputs the control signal BRu from the control output terminal 102 to the control terminal 202. The fourth transmission section 340 superimposes the clock signal SCLu from the clock output terminal 104 on the signal at the control terminal 202. As a result, a second superimposed signal WAS2 is applied to the control terminal 202.

[0078] The third transmission section 330 of this example includes a buffer circuit 331, a resistor 332, a photocoupler 333, and a resistor 336. The photocoupler 333 includes a light emitting element 334 such as a light emitting diode, and a light receiving element 335 such as a phototransistor.

[0079] The light emitting element 334 emits light in response to the pulse of the control signal BRu. In the light emitting element 334 of this example, a high voltage VDD is applied to the anode. The cathode of the light emitting element 334 is connected to the output of the buffer circuit 331 via a resistor 332. The input of the buffer circuit 331 is connected to the control output terminal 102. The buffer circuit 331 applies a voltage in response to the control signal BRu to the cathode of the light emitting element 334. This causes the light emitting element 334 to emit light in response to the pulse (L level voltage) of the control signal BRu.

[0080] The light receiving element 335 converts the light from the light emitting element 334 into an electric signal. In this example, a predetermined high voltage (e.g., 15 V) is applied to the collector of the light receiving element 335 via a resistor 336, and a predetermined reference potential GND2 is applied to the emitter. As a result, a control signal BRu having an amplitude corresponding to the high voltage (e.g., 15 V) is applied to the control terminal 202.

[0081] The fourth transmission section 340 of this example has a buffer circuit 341, a resistor 342, a photocoupler 343, and a Zener diode 346. The photocoupler 343 includes a light emitting element 344 such as a light emitting diode, and a light receiving element 345 such as a phototransistor.

[0082] The light-emitting element 344 emits light in response to the pulse of the clock signal SCLu. In this example, a high voltage VDD is applied to the anode of the light-emitting element 344. The cathode of the light-emitting element 344 is connected to the output of the buffer circuit 341 via a resistor 342. The input of the buffer circuit 341 is connected to the clock output terminal 104. The buffer circuit 341 applies a voltage corresponding to the clock signal SCLu to the cathode of the light-emitting element 344. This causes the light-emitting element 344 to emit light in response to the pulse (L-level voltage) of the clock signal SCLu.

[0083] The light receiving element 345 converts the light from the light emitting element 344 into an electric signal. A predetermined high voltage (e.g., 15 V) is applied to the collector of the light receiving element 345 in this example via a Zener diode 346 and a resistor 336, and a predetermined reference potential GND2 is applied to the emitter.

[0084] The anode of the Zener diode 346 is connected to the collector of the light receiving element 345, and a high voltage (for example, 15 V) is applied to the cathode via the resistor 336. The cathode of the Zener diode 346 is connected to the control terminal 202. The amplitude of the clock signal SCLm superimposed on the control terminal 202 is determined according to the breakdown voltage of the Zener diode 346. The breakdown voltage of the Zener diode 346 may be smaller than the high voltage applied to the resistor 336. As an example, the breakdown voltage of the Zener diode 346 is 5 V.

[0085] As described above, the pulse of the control signal BRu and the pulse of the clock signal SCLu included in the second superimposed signal WAS2 in this example have different amplitudes. At least one of the third transmission section 330 and the fourth transmission section 340 may have an amplitude conversion section that converts the amplitude of the signal. In the example of FIG. 2, the Zener diode 346 of the fourth transmission section 340 functions as the amplitude conversion section. With this configuration, the pulse of the control signal BRu and the pulse of the clock signal SCLu included in the second superimposed signal WAS2 can be separated.

[0086] Fig. 3 is a timing chart for explaining the operation related to the input data signal SDAIu and the output signal OS. As explained in Fig. 2, the control circuit 100 outputs the input data signal SDAIu. The power conversion circuit 200 outputs the output signal OS.

[0087] 3, the first superimposed signal WAS1 at the output terminal 204 includes pulses of the input data signal SDAIu and the output signal OS. The pulses of the input data signal SDAIu included in the first superimposed signal WAS1 and the pulses of the output signal OS may have different amplitudes. In this example, the pulses corresponding to the input data signal SDAIu have an amplitude (15V to 5V) corresponding to the breakdown voltage (e.g., 5V) of the Zener diode 326. Moreover, the pulses corresponding to the output signal OS have an amplitude (15V to 0V) corresponding to the reference potential GND2 (0V). In another example, the pulses of the input data signal SDAIu included in the first superimposed signal WAS1 and the pulses of the output signal OS may have the same amplitude.

[0088] The first transmission unit 310 transmits the first superimposed signal WAS1 to the input terminal 106. The first transmission unit 310 of this example transmits the first superimposed signal WAS1 with the same amplitude for each pulse by the photocoupler 313. The control circuit 100 of this example receives an input signal ALMu_SDAu having the same pulse pattern as the first superimposed signal WAS1. As described above, the control circuit 100 can identify the output signal OS of the power conversion circuit 200 based on the input signal ALMu_SDAu and the input data signal SDAIu generated by the control circuit 100 itself.

[0089] The reference voltage generating unit 221 of the data discrimination unit 220 generates a first reference voltage capable of extracting all pulses contained in the first superimposed signal WAS1. In this example, the reference voltage generating unit 221 generates a voltage higher than 5V and lower than 15V. The comparator 222 compares the first reference voltage with the voltage of the first superimposed signal WAS1. The pulse pattern of the signal output by the comparator 222 is the same as the pulse pattern of the first superimposed signal WAS1. In this example, the pulse pattern of the signal output by the comparator 222 is omitted because it is the same as the pulse pattern of the signal ALMu_SDAu.

[0090] The logic circuit 223 generates the input data signal SDAIm based on the signal output by the comparator 222 and the output signal OS. As described above, the logic circuit 223 extracts pulses that do not overlap with pulses of the output signal OS from among the pulses included in the signal output by the comparator 222. This allows the input data signal SDAIm to be generated.

[0091] Fig. 4 is a timing chart for explaining the operation of the control signal and the clock signal. As explained in Fig. 2, the control circuit 100 outputs the control signal BRu and the clock signal SCLu. The control signal BRu and the clock signal SCLu output by the control circuit 100 are signals that are at a high voltage VDD during a period without a pulse and at a reference potential GND1 (0V) during a period with a pulse.

[0092] 4, the second superimposed signal WAS2 at the control terminal 202 includes pulses of the control signal BRu and the clock signal SCLu. In this example, the pulse of the control signal BRu included in the second superimposed signal WAS2 and the pulse of the clock signal SCLu have different amplitudes. In this example, the pulse corresponding to the clock signal SCLu has an amplitude (15V to 5V) corresponding to the breakdown voltage (e.g., 5V) of the Zener diode 346. In addition, the pulse corresponding to the control signal BRu has an amplitude (15V to 0V) corresponding to the reference potential GND2 (0V).

[0093] The reference voltage generating unit 231 of the control discriminator 230 generates a second reference voltage that can extract only the pulses corresponding to the control signal BRu from the pulses included in the second superimposed signal WAS2. The second reference voltage in this example is greater than 0V and less than 5V.

[0094] The comparator 232 of the control discriminator 230 compares the voltage of the second superimposed signal WAS2 with a second reference voltage. The pulse pattern of the control signal BRm output by the comparator 232 is the same as the pulse pattern of the control signal BRu.

[0095] The reference voltage generating section 241 of the clock discriminating section 240 generates a third reference voltage capable of extracting all pulses included in the second superimposed signal WAS2. In this example, the third reference voltage is higher than 5V and lower than 15V. The comparator 242 compares the third reference voltage with the voltage of the second superimposed signal WAS2. The pulse pattern of the signal output by the comparator 242 is the same as the pulse pattern of the second superimposed signal WAS2.

[0096] The logic circuit 243 generates the clock signal SCLm based on the signal output by the comparator 242 and the control signal BRm. As described above, the logic circuit 243 extracts pulses that do not overlap with pulses of the control signal BRm from among the pulses included in the signal output by the comparator 242. This allows the clock signal SCLm to be generated.

[0097] In the control circuit 100 of this example, the pulses of the control signal BRu and the pulses of the clock signal SCLu are arranged in different periods. In Fig. 4, the pulses of the control signal BRu are arranged in period A, and the pulses of the clock signal SCLu are arranged in period B. With this arrangement, the pulses of the control signal BRu and the pulses of the clock signal SCLu can be accurately distinguished from each other.

[0098] FIG. 5 is a diagram showing another example of the configuration of the third transmission unit 330 and the power conversion circuit 200. The control circuit 100 of this example can arrange the pulse of the control signal BRu and the pulse of the clock signal SCLu in the same period. When the pulse of the control signal BRu and the pulse of the clock signal SCLu overlap, the transmission device 300 of this example generates a pulse with an amplitude different from both the pulse of the control signal BRu and the pulse of the clock signal SCLu. This makes it possible to distinguish between a single pulse of the control signal BRu, a single pulse of the clock signal SCLu, and a pulse in which the control signal BRu and the clock signal SCLu overlap. The second superimposed signal includes these pulses. The power conversion circuit 200 determines whether each pulse is a single pulse of the control signal BRu, a single pulse of the clock signal SCLu, or a pulse in which the control signal BRu and the clock signal SCLu overlap, based on the amplitude of each pulse of the second superimposed signal.

[0099] The third transmission section 330 of this example has an amplitude control section 350 instead of the resistor 336. Other structures are similar to those of the example shown in Fig. 2. The amplitude control section 350 is provided between the control circuit 100 and the control terminal 202, and generates a pulse having an amplitude different from both the pulse of the control signal BRu and the pulse of the clock signal SCLu during a period in which the pulse of the control signal BRu and the pulse of the clock signal SCLu overlap.

[0100] The amplitude control section 350 of this example has a power supply wiring 354, a signal wiring 355, a first resistor 351, a second resistor 352, and a third resistor 353. The power supply wiring 354 is a wiring to which a predetermined high voltage (e.g., 15 V) is applied. The signal wiring 355 is a wiring to which a control signal BRu is applied. The signal wiring 355 of this example is connected to the collector of the light receiving element 335.

[0101] The first resistor 351, the second resistor 352, and the third resistor 353 are connected in series between a power supply wiring 354 and a signal wiring 355. The first resistor 351 is connected to the power supply wiring 354, and the third resistor 353 is connected to the signal wiring 355. The second resistor 352 is connected between the first resistor 351 and the third resistor 353.

[0102] A clock signal SCLu is applied to the connection point between the first resistor 351 and the second resistor 352. In this example, the cathode of the Zener diode 346 is connected to the connection point. In addition, the connection point between the second resistor 352 and the third resistor 353 is connected to the control terminal 202. The resistance values ​​of the first resistor 351, the second resistor 352, and the third resistor 353 may be the same as each other or may be different from each other.

[0103] During the period when the pulses of the control signal BRu and the clock signal SCLu overlap, the light receiving element 335 and the light receiving element 345 are turned on. The voltage at the connection point of the first resistor 351 and the second resistor 352 is clamped to the breakdown voltage (5V) of the Zener diode 346. In addition, a reference voltage GND2 (0V) is applied to the signal wiring 355. Therefore, the voltage of the second superimposed signal WAS2 is a voltage obtained by dividing 5V by the resistance ratio of the second resistor 352 and the third resistor 353. As an example, when the resistance values ​​of the second resistor 352 and the third resistor 353 are equal, the voltage of the second superimposed signal WAS2 is 2.5V.

[0104] The voltage of the second superimposed signal WAS2 when the pulse of the control signal BRu exists alone and when the pulse of the clock signal SCLu exists alone may be the same as the example of FIG. 4. The voltage of each signal is determined according to the resistance value of each resistor. The voltage of the second superimposed signal WAS2 when the pulse of the control signal BRu exists alone and when the pulse of the clock signal SCLu exists alone may be different from the example of FIG. 4. In this example, the voltage of the second superimposed signal WAS2 when the pulse of the control signal BRu exists alone is lower (for example, 0V) than the voltage of the second superimposed signal WAS2 during the period when the pulses of the control signal BRu and the clock signal SCLu overlap. Also, the voltage of the second superimposed signal WAS2 when the pulse of the clock signal SCLu exists alone is higher (for example, 5V) than the voltage of the second superimposed signal WAS2 during the period when the pulse of the control signal BRu and the clock signal SCLu overlap.

[0105] During the period when the pulse of the control signal BRu exists alone, the light receiving element 335 is turned on and the light receiving element 345 is turned off. The voltage at the connection point of the first resistor 351 and the second resistor 352 is not clamped by the Zener diode 346. In addition, the reference voltage GND2 (0V) is applied to the signal wiring 355. Therefore, the voltage of the second superimposed signal WAS2 is a voltage obtained by dividing 15V by the resistance ratio of the first resistor 351, the second resistor 352, and the third resistor 353. As an example, when the sum of the resistance values ​​of the first resistor 351 and the second resistor 352 is sufficiently larger than the resistance value of the third resistor 353, the voltage of the second superimposed signal WAS2 is approximately 0V. The resistance value of the first resistor 351 may be larger than the sum of the resistance values ​​of the second resistor 352 and the third resistor 353.

[0106] During a period when only a pulse of the clock signal SCLu exists, the light receiving element 335 is turned off and the light receiving element 345 is turned on. The voltage at the connection point between the first resistor 351 and the second resistor 352 is clamped to 5V by the Zener diode 346. In addition, the signal wiring 355 is disconnected from the reference voltage GND2 (0V). As a result, the voltage of the second superimposed signal WAS2 becomes 5V.

[0107] The power conversion circuit 200 of this example includes a signal identifier 250 that functions as a control identifier 230 and a clock identifier 240. The other structures are similar to those of the examples described with reference to FIGS.

[0108] The signal discrimination unit 250 separates and extracts the control signal BRu and the clock signal SCLu from the second superimposed signal WAS2. As described above, the second superimposed signal WAS2 has pulses with different amplitudes depending on whether the pulse of the control signal BRu exists alone, the pulse of the clock signal SCLu exists alone, or the pulses of the control signal BRu and the clock signal SCLu overlap. Based on the amplitude of each pulse of the second superimposed signal WAS2, the signal discrimination unit 250 discriminates whether each pulse is an independent pulse of either the control signal BRu or the clock signal SCLu, or a pulse in which the control signal BRu and the clock signal SCLu overlap. Based on the discrimination result, the signal discrimination unit 250 generates the control signal BRm and the clock signal SCLm.

[0109] The signal identifying section 250 of this example includes a reference voltage generating section 251, a comparator 261, a reference voltage generating section 252, a comparator 262, a reference voltage generating section 253, a comparator 263, and a logic circuit 270. The operation of the signal identifying section 250 will be described using a timing chart.

[0110] 6 is a timing chart for explaining the operations of the control circuit 100, the transmission device 300, and the signal identification unit 250. The control circuit 100 of this example outputs both a pulse of the control signal BRu and a pulse of the clock signal SCLu in period C. The operations in periods A and B are similar to those in the example of FIG.

[0111] When the pulse of the control signal BRu exists alone, the voltage of the second superimposed signal WAS2 becomes a first voltage (0V in this example). When the pulse of the control signal BRu and the pulse of the clock signal SCLu overlap, the voltage of the second superimposed signal WAS2 becomes a second voltage (2.5V in this example). When the pulse of the clock signal exists alone, the voltage of the second superimposed signal WAS2 becomes a third voltage (5V in this example).

[0112] The reference voltage generating unit 251 generates a fourth reference voltage that is higher than the first voltage (0 V) and lower than the second voltage (2.5 V). The comparator 261 outputs an L-level voltage when the voltage of the second superimposed signal WAS2 is equal to or lower than the fourth reference voltage, and outputs an H-level voltage when the voltage is higher than the fourth reference voltage. As a result, the comparator 261 outputs a signal that is at the L-level during a period when the pulse of the control signal BRu exists alone and at the H-level during other periods.

[0113] The reference voltage generating unit 252 generates a fifth reference voltage that is higher than the second voltage (2.5V) and lower than the third voltage (5V). The comparator 262 outputs an L-level voltage when the voltage of the second superimposed signal WAS2 is equal to or lower than the fifth reference voltage, and outputs an H-level voltage when the voltage is higher than the fifth reference voltage. As a result, the comparator 262 outputs a signal that is at L level during a period when a pulse of the control signal BRu exists and at H level during other periods, regardless of the presence or absence of a pulse of the clock signal SCLu. In the signal identifying unit 250 of this example, the signal output by the comparator 262 is the control signal BRm.

[0114] The reference voltage generating unit 253 generates a sixth reference voltage that is higher than the third voltage (5V) and lower than a predetermined high voltage (15V). The comparator 263 outputs an L-level voltage when the voltage of the second superimposed signal WAS2 is equal to or lower than the sixth reference voltage, and outputs an H-level voltage when the voltage is higher than the sixth reference voltage. As a result, the comparator 263 outputs a signal that is at L level during a period in which at least one of the pulses of the control signal BRu and the clock signal SCLu exists, and is at H level during other periods.

[0115] The logic circuit 270 generates a clock signal SCLm based on the signal output by the comparator 261 and the signal output by the comparator 263. The logic circuit 270 of this example outputs a voltage of L level during a period in which the signal output by the comparator 261 indicates an H level and the signal output by the comparator 263 indicates an L level. During other periods, the logic circuit 270 outputs a voltage of H level. The signal discrimination section 250 of this example sets the signal output by the logic circuit 270 as the clock signal SCLm. The logic circuit 270 may invert and output the logical AND of the inverted signal of the output of the comparator 263 and the output of the comparator 261.

[0116] According to this example, the control signal BRu and the clock signal SCLu can be transferred simultaneously using one control terminal 202. This makes it possible to reduce the number of terminals of the power conversion circuit 200 while improving the flexibility of the signal patterns of the control signal BRu and the clock signal SCLu.

[0117] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention. [Explanation of symbols]

[0118] 10 circuit device, 100 control circuit, 102 control output terminal, 104 clock output terminal, 106 input terminal, 108 data output terminal, 200 power conversion circuit, 202 control terminal, 204 output terminal, 210 signal output section, 211 resistor, 212 buffer circuit, 213 NOR circuit, 220 data discrimination section, 221 reference voltage generation section, 2 22 comparator, 223 logic circuit, 230 control discrimination unit, 231 reference voltage generation unit, 232 comparator, 240 clock discrimination unit, 241 reference voltage generation unit, 242 comparator, 243 logic circuit, 250 signal discrimination unit, 251, 252, 253 reference voltage generation units, 261, 262, 263 comparator, 270 logic circuit, 300 transmission device, 310 th 1. Transmission section, 311...resistor, 313...photocoupler, 314...light-emitting element, 315...light-receiving element, 316...resistor, 320...second transmission section, 321...buffer circuit, 322...resistor, 323...photocoupler, 324...light-emitting element, 325...light-receiving element, 326...Zener diode, 330...third transmission section, 331...buffer circuit, 332...resistor, 333...photocoupler Coupler, 334...light emitting element, 335...light receiving element, 336...resistor, 340...fourth transmission section, 341...buffer circuit, 342...resistor, 343...photocoupler, 344...light emitting element, 345...light receiving element, 346...zener diode, 350...amplitude control section, 351...first resistor, 352...second resistor, 353...third resistor, 354...power supply wiring, 355...signal wiring

Claims

1. A circuit device including a power conversion circuit and a control circuit that controls the power conversion circuit, The power conversion circuit includes: a control terminal to which a control signal from the control circuit is input; an output terminal for outputting an output signal to the control circuit; a data identification unit for identifying an input data signal input to the output terminal; A circuit device having the above configuration.

2. a first superimposed signal in which the output signal and the input data signal are superimposed is input to the data discrimination unit, The data identification unit identifies the input data signal based on the first superimposed signal and the output signal. The circuit device according to claim 1 .

3. The data discrimination unit extracts pulses other than the pulses of the output signal from among the pulses included in the first superimposed signal to generate the input data signal. The circuit device according to claim 2 .

4. The output signal includes an alarm signal indicating whether the power conversion circuit has reached a preset state. The circuit device according to claim 1 .

5. The output signal includes an output data signal output by the power conversion circuit. The circuit device according to claim 1 .

6. a first transmission unit provided between the output terminal and the control circuit and configured to output a signal from the output terminal to the control circuit; a second transmission section that superimposes the input data signal from the control circuit on a signal at the output terminal; Further comprising: The data identification unit receives a signal at the output terminal.

3. The circuit device according to claim 2.

7. The control circuit receives the first superimposed signal and identifies the output signal based on the first superimposed signal and the input data signal. The circuit device according to claim 2 .

8. the first transmission unit transmits a signal at the output terminal that is equal to or greater than a reference current value to the control circuit; The second transmission section converts the input data signal into a signal having a current smaller than the reference current value and superimposes the converted signal on the signal at the output terminal. The circuit arrangement according to claim 6.

9. The power conversion circuit further includes a clock identification unit that separates the clock signal input to the control terminal from the control signal. A circuit arrangement according to any one of claims 1 to 8.

10. a second superimposed signal in which the control signal and the clock signal having an amplitude different from that of the control signal are superimposed on each other is input to the control terminal; The clock identification unit separates the control signal and the clock signal based on the amplitude of each pulse included in the second superimposed signal. The circuit arrangement according to claim 9.

11. a third transmission unit provided between the control circuit and the control terminal and configured to transmit the control signal to the control terminal; a fourth transmission unit provided between the control circuit and the control terminal, the fourth transmission unit transmitting the clock signal to the control terminal to generate the second superimposed signal; Further comprising: The circuit device according to claim 10 , wherein at least one of the third transmission section and the fourth transmission section has an amplitude conversion section that converts the amplitude of a signal.

12. The control circuit arranges the pulses of the control signal and the pulses of the clock signal to have different periods. The circuit arrangement according to claim 10.

13. The control circuit can arrange a pulse of the control signal and a pulse of the clock signal in the same period. The circuit arrangement according to claim 10.

14. an amplitude control section that is provided between the control circuit and the control terminal and that generates a pulse having an amplitude different from both the pulse of the control signal and the pulse of the clock signal during a period in which the pulse of the control signal and the pulse of the clock signal overlap each other. The circuit arrangement according to claim 13.

15. The amplitude control unit is Power wiring, A signal wiring to which the control signal is applied; a first resistor, a second resistor and a third resistor connected in series between the power supply wiring and the signal wiring; having The clock signal is applied to a connection point between the first resistor and the second resistor; A connection point between the second resistor and the third resistor is connected to the control terminal.

15. A circuit arrangement according to claim 14.

16. A power conversion circuit controlled by a control circuit, a control terminal to which a control signal from the control circuit is input; an output terminal for outputting an output signal to the control circuit; a data identification unit for identifying an input data signal input to the output terminal; A power conversion circuit comprising:

17. a first superimposed signal in which the output signal and the input data signal are superimposed is input to the data discrimination unit, The data identification unit identifies the input data signal based on the first superimposed signal and the output signal.

17. The power conversion circuit of claim 16.

18. The data discrimination unit extracts pulses other than the pulses of the output signal from among the pulses included in the first superimposed signal to generate the input data signal.

20. The power conversion circuit of claim 17.

19. The output signal includes an alarm signal indicating whether the power conversion circuit has reached a preset state.

17. The power conversion circuit of claim 16.

20. The output signal includes an output data signal output by the power conversion circuit.

17. The power conversion circuit of claim 16.

21. The clock signal input to the control terminal is separated from the control signal by a clock identification unit.

21. A power conversion circuit according to any one of claims 16 to 20.

22. a second superimposed signal in which the control signal and the clock signal having an amplitude different from that of the control signal are superimposed on each other is input to the control terminal; The clock identification unit separates the control signal and the clock signal based on the amplitude of each pulse included in the second superimposed signal.

22. The power conversion circuit of claim 21.

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