Information processing device, information processing method, program, and circuit information

Abstract

To efficiently update a combination optimization problem.SOLUTION: An information processing device according to an embodiment performs processing for data. The information processing device comprises a solver device and an information processing circuit. The solver device stores a plurality of first weighted values and a plurality of second weighted values, and solves a combination optimization problem minimizing a cost function including a plurality of weighted values obtained by synthesizing the plurality of first weighted values and the plurality of second weighted values. The information processing circuit repeatedly acquires first data as data, and repeatedly acquires second data as data in asynchronization with the timing of acquiring the first data. The information processing device also updates the plurality of first weighted values stored in the solver device on the basis of the first data, and updates the plurality of second weighted values stored in the solver device on the basis of the second data.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present invention relates to an information processing device, an information processing method, a program, and circuit information. [Background technology]

[0002] In many application fields, such as control, finance, communication, logistics, and chemistry, system optimization is often mathematically reduced to a combinatorial optimization problem. Information processing systems have been proposed that realize various information processing functions, such as recognition, judgment, and planning, and improve the efficiency of such functions by solving combinatorial optimization problems.

[0003] A combinatorial optimization problem is a problem in which a cost function is defined with arguments being multiple decision variables (e.g., discrete variables) that represent the state of the system to be optimized, and the combination of values ​​of multiple decision variables that minimizes the defined cost function is solved. The state of the system represented by multiple decision variables is called a solution. In a combinatorial optimization problem, the number of states that can be taken as a solution increases exponentially as the number of decision variables increases. The increase in the number of states that can be taken as a solution is called combinatorial explosion. Combinatorial optimization, which involves selecting an optimal solution from all candidate solutions, is known to be a computationally difficult problem. Performing large-scale combinatorial optimization in a short period of time remains a challenging task.

[0004] In recent years, a special-purpose device called an Ising machine that searches for the ground state of an Ising spin model has been attracting attention. The problem of searching for the ground state of an Ising spin model is called the Ising problem. The Ising problem is a combinatorial optimization problem that minimizes a cost function given by a quadratic function of Ising spin, which is one of the binary variables. In the Ising problem, the cost function is called the Ising energy. Many practical combinatorial optimization problems can be converted into Ising problems. An Ising machine can solve an Ising problem quickly. Therefore, many practical combinatorial optimization problems can be solved quickly using an Ising machine.

[0005] However, when the situation is constantly changing, a new combinatorial optimization problem may be generated and solved in response to the change in the situation, and processing may be performed based on the obtained solution. For example, when applying a combinatorial optimization problem to a trading device that electronically trades stocks in a financial market, a new combinatorial optimization problem is generated in response to fluctuations in stock prices, and trading is performed based on the obtained solution. Also, when applying a combinatorial optimization problem to a control system that controls a moving object based on images of captured surrounding scenery, a new combinatorial optimization problem is generated in response to changes in the image, and the moving object is controlled based on the obtained solution.

[0006] In addition, such a system may generate a combinatorial optimization problem according to multiple types of situations, solve the generated combinatorial optimization problem, and perform processing based on the obtained solution. Furthermore, a first type of situation among the multiple types of situations may affect only a portion of the multiple weight values ​​included in the cost function of the combinatorial optimization problem, and may not affect the others. Even in such a case, such a system must generate a new combinatorial optimization problem that reflects all of the multiple types of situations in response to a change in only the first type of situation, and perform processing based on the obtained solution.

[0007] Furthermore, the speed of change may differ for each type, such as a first type of situation among the multiple types of situations changing once a day, while a second type of situation among the multiple types of situations changing once every few seconds, etc. In such a case, the system must generate a new combinatorial optimization problem that reflects all of the multiple types of situations by tracking the situation that changes the fastest, and perform processing based on the obtained solution. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Patent No. 6629864 [Patent Document 2] JP 2021-060864 A [Patent Document 3] JP 2019-145010 A [Patent Document 4] JP 2019-159566 A [Patent Document 5] Patent Publication No. 2021-043667 [Patent Document 6] JP 2021-043589 A [Non-patent literature]

[0009] [Non-Patent Document 1] Hayato Goto, Kosuke Tatsumura and Alexander R. Dixon, “Combinatorial optimization by simulating adiabatic bifurcations in nonlinear Hamiltonian systems,” Science Advances 5, eaav2372, 2019 [Non-Patent Document 2] Hayato Goto, Kotaro Endo, Masaru Suzuki, Yoshisato Sakai, Taro Kanao, Yohei Hamakawa, Ryo Hidaka, Masaya Yamasaki and Kosuke Tatsumura, “High-performance combinatorial optimization based on classical mechanics”, Science Advances 7, eabe7953, 2021 Summary of the Invention [Problem to be solved by the invention]

[0010] The problem to be solved by the present invention is to efficiently update combinatorial optimization problems when they are generated in response to a plurality of types of situations. [Means for solving the problem]

[0011] An information processing device according to an embodiment executes processing on data. The information processing device includes a solver device and an information processing circuit. The solver device stores a plurality of first weight values ​​and a plurality of second weight values, and solves a combinatorial optimization problem that minimizes a cost function including a plurality of weight values ​​obtained by combining the plurality of first weight values ​​and the plurality of second weight values. The information processing circuit repeatedly acquires first data as the data. The information processing circuit repeatedly acquires second data as the data asynchronously with the timing of acquiring the first data. The information processing circuit updates the plurality of first weight values ​​stored in the solver device based on the first data. The information processing circuit updates the plurality of second weight values ​​stored in the solver device based on the second data. [Brief description of the drawings]

[0012] [Figure 1] A diagram showing a model of the Ising problem. [Diagram 2] FIG. 2 illustrates internal variables used by the simulated branching algorithm. [Diagram 3] 4 is a flowchart showing a process flow of a simulated branching machine. [Figure 4] FIG. 1 is a diagram showing a configuration of an information processing system including an Ising machine. [Diagram 5] FIG. 1 is a diagram showing a configuration of an information processing system including a simulated branching machine. [Figure 6] Diagram of the market system. [Figure 7] FIG. 1 is a diagram showing the arrangement of an information processing apparatus according to a first embodiment. [Figure 8] FIG. 4 is a diagram showing timing of a first processing example of the information processing device. [Figure 9] FIG. 11 is a diagram showing timing of a second processing example of the information processing device. [Figure 10] FIG. 11 is a diagram showing an example of weight values ​​stored in the solver device according to the second embodiment. [Figure 11]FIG. 13 is a configuration diagram of a solver device according to a third embodiment. [Figure 12] FIG. [Figure 13] FIG. [Figure 14] FIG. 11 is a configuration diagram of a matrix calculation circuit according to a third embodiment. [Figure 15] FIG. 13 is a configuration diagram of a matrix calculation circuit according to a fourth embodiment. [Figure 16] FIG. 13 is a configuration diagram of a matrix calculation circuit according to a fifth embodiment. [Figure 17] FIG. 13 is a configuration diagram of a matrix calculation circuit according to a sixth embodiment. [Figure 18] FIG. 13 is a configuration diagram of a matrix calculation circuit according to the seventh embodiment. [Figure 19] FIG. 13 is a configuration diagram of a matrix calculation circuit according to an eighth embodiment. [Figure 20] FIG. 1 is a diagram showing an example of the configuration of a control system. [Figure 21] FIG. 2 is a hardware configuration diagram of an information processing device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] (Premise) First, terms and techniques that are the basis for the description of the embodiments will be described.

[0014] A combinatorial optimization problem is a problem in which a cost function is defined with multiple decision variables (e.g., discrete variables) representing the state of a system to be optimized as arguments, and a combination of values ​​of multiple decision variables that minimizes the defined cost function is solved. The cost function includes multiple decision variables representing the state of the system as arguments, and is a linear or higher function of the multiple decision variables. For example, the cost function is expressed by a linear or quadratic function of the multiple decision variables. The cost function may be a cubic or higher function of the multiple decision variables. In other words, the cost function is a function that sums up multiple terms. Each of the multiple terms is a function that multiplies one or more of the multiple decision variables, up to a predetermined number of them, by a coefficient. In addition, the coefficient in each of the multiple terms is a real number and is also called a weight value. In other words, each of the multiple terms that constitute the cost function is expressed by multiplying one or more of the multiple decision variables by any one of the multiple weight values.

[0015] The state of the system, represented by the decision variables, is called a solution. The universe of possible solutions for the state of the system is called the solution space. The solution that gives the minimum of the cost function is called an exact solution. The solution that gives a value close to the minimum of the cost function is called a good solution.

[0016] An exact solution method is a method for finding an exact solution that gives a minimum value of a cost function for a combinatorial optimization problem, and is a method that guarantees that the solution is an exact solution.

[0017] A heuristic solution is a solution method for combinatorial optimization problems that finds an exact solution that minimizes the cost function or a good solution that is close to the minimum of the cost function. Heuristic solutions are also called discovery solutions. Heuristic solutions do not guarantee the accuracy of the solution, that is, an index that indicates how close the solution is to the minimum of the cost function. Heuristic solutions can output a solution with practically significant accuracy in a shorter solution time than exact solutions.

[0018] The computational complexity of a solution to a combinatorial optimization problem is the amount of calculations required to obtain a solution, such as the number of multiply-and-accumulate operations. The solution time required to obtain a solution to a combinatorial optimization problem depends not only on the computational complexity but also on the configuration of the computer that processes the calculations. For example, the solution time becomes shorter as the computer's computational parallelism and operating frequency increase.

[0019] A QUBO (Quadratic Unconstrained Binary Optimization) problem is an unconstrained quadratic optimization problem in which the decision variables are binary. In a QUBO problem, each of a number of terms included in a cost function is expressed by a linear or quadratic expression of the decision variables. In a narrowly defined QUBO problem, the decision variables are binary variables of 0 or 1. In this embodiment, the QUBO problem represents a narrowly defined problem in which the decision variables are 0 or 1. In a narrowly defined QUBO problem, the decision variables may also be called bit variables.

[0020] The cost function for the QUBO problem is H in Eq. (1). total_QUBO It is expressed by:

number

[0021] FIG. 1 is a diagram showing a model of the Ising problem. The Ising problem is a problem of searching for the ground state of the Ising model. The Ising problem is one of the QUBO problems. The decision variables of the Ising problem represent discrete variables of -1 or +1.

[0022] The cost function for the Ising problem is H in Eq. (2). total_Ising It is expressed by:

number

[0023] If the decision variable is s i The QUBO problem corresponds to the problem of searching for the ground state of the Ising model, which is one of the magnetic models in statistical mechanics. i is sometimes called the spin variable. The number of decision variables, N, is sometimes called the spin number. H total_Ising is sometimes called the Zing energy. total_Ising N s for which i The vector represented by is sometimes called the ground state (ground spin configuration).

[0024] The cost function of the QUBO problem and the cost function of the Ising problem differ only in the value of the constant. Therefore, the QUBO problem and the Ising problem are the same as combinatorial optimization problems. In other words, the QUBO problem and the Ising problem can be converted into each other. For example, the Ising problem and the QUBO problem can be converted into each other by formula (3-1), formula (3-2), formula (3-3), and formula (3-4).

number

[0025] QUBO and Ising problems are known to be NP-complete. That is, many NP-hard problems can be transformed into QUBO or Ising problems in polynomial time. Therefore, many practical combinatorial optimization problems can be transformed into QUBO or Ising problems.

[0026] An Ising machine is a device that solves Ising problems. Most Ising machines solve Ising problems using heuristic solutions. Ising machines based on various principles, such as electronic engineering, optics, quantum mechanics, and statistical mechanics, have been proposed. Many Ising machines can output exact or good solutions in a short time.

[0027] The simulated branching algorithm is an algorithm for solving combinatorial optimization problems. The simulated branching algorithm is a heuristic solution algorithm.

[0028] The simulated bifurcation algorithm is shown in, for example, Non-Patent Documents 1-2 and Patent Documents 2-6. The simulated bifurcation algorithm was discovered based on the idea of ​​a quantum mechanical optimization method based on the quantum adiabatic theorem, and is therefore also called a quantum-inspired algorithm. The simulated bifurcation algorithm can solve a combinatorial optimization problem in which the cost function is a quadratic function of multiple decision variables. The simulated bifurcation algorithm can also solve a combinatorial optimization problem in which the cost function is a cubic or higher function of multiple decision variables, that is, a HUBO (Higher Order Binary Optimization) problem. For example, a simulated bifurcation algorithm that solves a HUBO problem is shown in Patent Document 5. The simulated bifurcation algorithm can also solve a combinatorial optimization problem in which some or all of the multiple decision variables include variables with continuous values. A simulated bifurcation algorithm that solves a combinatorial optimization problem in which some or all of the multiple decision variables include variables with continuous values ​​is shown in Patent Document 6.

[0029] The simulated bifurcation machine is a computing device that executes processing according to a simulated bifurcation algorithm. The simulated bifurcation machine that solves the QUBO problem or the Ising problem is an example of an Ising machine. In this embodiment, the simulated bifurcation machine solves the Ising problem.

[0030] FIG. 2 is a diagram showing the internal variables used by the simulated branching algorithm.

[0031] The simulated branching algorithm is a method to determine the number of decision variables (s1 to s N When solving a combinatorial optimization problem in which the cost function is expressed using N ) and N momentum variables (y1~y N ) is used. That is, the simulated bifurcation algorithm uses 2×N internal variables.

[0032] N location variables (x i ) is the number of N decision variables (si ) in one-to-one correspondence. That is, the i-th position variable (x i ) is the i-th decision variable (s i ) corresponding to the N momentum variables (y i ) is the number of N decision variables (s i ) corresponds to the i-th momentum variable (y i ) is the i-th decision variable (s i )

[0033] 3 is a flow chart showing the flow of processing of the simulated branching machine. The simulated branching machine executes processing according to the simulated branching algorithm in the flow shown in FIG.

[0034] First, in S11, the simulated bifurcation machine obtains an Ising problem. Specifically, the simulated bifurcation machine obtains J, which is a matrix including N×N coefficients, and h, which includes N bias coefficients.

[0035] Next, in S12, the simulated branching machine calculates 2×N internal variables, i.e., N position variables (x1 to x N ) and N momentum variables (y1~y N ) is initialized. The simulated branching machine initializes N position variables (x1 to x N ) and the initial values ​​of N momentum variables (y1~y N The initial values ​​of N position variables (x1 to x N ) and the initial values ​​of N momentum variables (y1~y N The initial value of x1 to x2 may be generated by a random number generator or may be set to a predetermined value. Since the simulated branching machine is a heuristic, the initial value of x1 to x2 may be set to a predetermined value even if the same problem is being solved. N ) and the initial values ​​of N momentum variables (y1~y N) is different, a different good solution may be output.

[0036] Next, the simulated branching machine repeats the process from S14 to S16 a preset number of times (loop process between S13 and S17). The process from S14 to S16 is performed by iterating N position variables (x1 to x N ) by a matrix containing weight values ​​of N rows and N columns, and N ) and N momentum variables (y1~y N ) is a time evolution process.

[0037] In S14, the simulated bifurcation machine calculates N momentum variables (y1 to y N ) in the y update process. The simulated bifurcation machine updates the i-th momentum variable (y i In the update process of N position variables (x1~x N ) and the i-th position variable (x i ) and the other (N-1) location variables (x 1~i-1, x i+1~N ) and N coefficients (J i,j ) and the i-th bias coefficient (h i ) and the i-th momentum variable (y i ) to update the

[0038] Next, in S15, the simulated branching machine calculates N position variables (x1 to x N ) in the x update process. The simulated branch machine updates the i-th position variable (x i In the update process of the i-th momentum variable (y i ) to the i-th position variable (x i ) to update the

[0039] The simulated branching machine may execute the process of S14 and the process of S15 in an interchangeable order.

[0040] Next, in S16, the simulated branching machine calculates N position variables (x1 to x N ), the simulated branching machine performs wall processing on the position variables whose absolute values ​​exceed 1. Furthermore, the simulated branching machine also performs wall processing on the momentum variables corresponding to the position variables whose absolute values ​​exceed 1. For example, in wall processing, the simulated branching machine changes the absolute value of the position variable whose absolute value exceeds 1 to 1 or a value smaller than 1 while keeping the sign the same. Also, for example, in wall processing, the simulated branching machine changes the value of the momentum variable corresponding to the position variable whose absolute value exceeds 1 to 0.

[0041] The simulated bifurcation algorithm has variations in the calculation of x-update processing, y-update processing, and wall processing. For example, the simulated bifurcation algorithm has variations such as the adiabatic simulated bifurcation (aSB) algorithm, the ballistic simulated bifurcation (bSB) algorithm, and the discrete simulated bifurcation (dSB) algorithm.

[0042] When executing processing according to the adiabatic simulated branching algorithm, the simulated branching machine executes the calculation shown in formula (4-1) in the y update processing (S14), and executes the calculation shown in formula (4-2) in the x update processing (S15). Note that when executing processing according to the adiabatic simulated branching algorithm, the simulated branching machine does not execute the wall processing (S15).

number

[0043] When executing processing according to the ballistic simulated branching algorithm, the simulated branching machine performs the calculation shown in equation (5-1) in the y update processing (S14), the calculation shown in equation (5-2) in the x update processing (S15), and the calculation shown in equation (5-3) in the wall processing (S16).

number

[0044] When executing processing according to the discrete simulated branching algorithm, the simulated branching machine performs the calculation shown in equation (6-1) in the y update processing (S14), the calculation shown in equation (6-2) in the x update processing (S15), and the calculation shown in equation (6-3) in the wall processing (S16).

number

[0045] In addition, in formulas (4-1), (4-2), (5-1), (5-2), (5-3), (6-1), (6-2) and (6-3), t k and t k+1 represents the time. k+1 t k This is the time obtained by adding a unit time (Δt) to the current time.

[0046] x i (t k ) is the time (t k ) the i-th position variable (x i ) value. i (t k+1 ) is the time (t k+1 ) the i-th position variable (x i ) value. i (t k ) is the time (t k ) the i-th momentum variable (y i ) value. i (t k+1 ) is the time (t k+1 ) the i-th momentum variable (yi ) value.

[0047] K, a0, η, and c0 are predetermined constants. k ) is a function that changes with time. k ) is a positive real number that increases as time increases, for example, a(t1)=0, and is a function that becomes a0 at the end time (T) (a(T)=a0). Also, sgn(x i (t k )) is the time (t k ) the i-th position variable (x i ), which is a function that outputs the sign of x i (t k ) is 0 or more, then +1, x i (t k ) is less than 0, it becomes -1.

[0048] When the simulated branching machine has executed the processes of S14 to S16 a predetermined number of times, that is, when it has executed the operations until time t reaches the final time T, it exits the loop process between S13 and S17 and proceeds to S18.

[0049] In S18, the simulated branching machine calculates the N position variables (x1 to x N ), or N position variables (x1~x N ) are calculated based on N decision variables (s1 to s N ) The simulated branching machine outputs N decision variables (s1 to s N ) the i-th decision variable (s i ) to sgn(x i ) is used as the basis for the calculation.

[0050] When the simulated branching machine finishes the process of S18, it ends the process according to the simulated branching algorithm.

[0051] The number of times the time-evolution process (loop process between S13 and S17) is repeated is determined in advance depending on the application. The amount of calculation required for one process in the time-evolution process (one process from S14 to S16) does not vary. For this reason, the simulated branching machine can reduce fluctuations in the solution-finding time. Therefore, even if the simulated branching machine is applied to a real-time system with time constraints that require processing to be completed by a certain time, it can reliably output a solution by the certain time.

[0052] Also, as shown in Patent Document 2, for example, the simulated branching machine can be configured using a dedicated parallel processing circuit including a large number of arithmetic units. This allows the simulated branching machine to extremely shorten the calculation time for one processing in time-evolution processing. Also, unlike software processing, the simulated branching machine implemented in a dedicated hardware circuit does not generate any interrupt processing, so the solution-finding time is strictly fixed. For example, the simulated branching machine implemented in a dedicated hardware circuit can fix the time until a solution is obtained in clock cycle units. Therefore, when applied to a real-time system, the simulated branching machine implemented in a dedicated hardware circuit can output a solution while more reliably observing time constraints.

[0053] FIG. 4 is a diagram showing a configuration of an information processing system including an Ising machine and a host device. An information processing system having a function of solving a combinatorial optimization problem can be configured, for example, by an Ising machine and a host device. The host device executes processes other than the processes executed by the Ising machine. In this case, the Ising machine is introduced for the purpose of shortening the time required to solve the combinatorial optimization problem, and is considered to be an accelerator or offloader. The host device includes a general-purpose processor, an offloader other than the Ising machine, a memory, a storage, a sensor, an actuator, a communication interface, and the like.

[0054] The host device provides at least information for identifying the QUBO problem (matrix (Q)) or information for identifying an Ising problem (matrix (J) and bias coefficient array (h)) to the Ising machine. The Ising machine may obtain the information for identifying the QUBO problem (matrix (Q)) and convert it into information for identifying an Ising problem (matrix (J) and bias coefficient array (h)). Then, after the optimization process, the Ising machine outputs N decision variables (s1 to s N ) opt ) is returned to the host device.

[0055] FIG. 5 is a diagram showing a configuration of an information processing system including a simulated branching machine and a host device.

[0056] The information processing system having a function of solving a combinatorial optimization problem may include a simulated bifurcation machine as an Ising machine. In this case, the host device provides information (matrix (J) and bias coefficient (h)) for identifying an Ising problem to the simulated bifurcation machine. Furthermore, the host device provides N position variables (x1 to x N ) and the initial values ​​of N momentum variables (y1~y N ) to the simulated branch machine. The host device may also provide various constants and functions (e.g., K, a0, c 0、 a(t) and Δt) may be given to the simulated bifurcation machine. After the optimization process, the simulated bifurcation machine outputs N decision variables (s1 to s N ) opt ), we use N position variables (x1~x N ) opt ) may be sent back to the host device.

[0057] (First embodiment) Next, the market system 10 according to the first embodiment will be described.

[0058] 6 is a diagram showing the configuration of the market system 10. The market system 10 executes electronic trading of a plurality of targets by a plurality of participants. More specifically, the market system 10 accepts buy orders and sell orders from each of the plurality of participants for each of the plurality of targets, matches the price and quantity of the accepted buy order with the price and quantity of the sell order, and electronically completes the trade.

[0059] In this embodiment, the market system 10 executes buying and selling transactions of multiple stocks (multiple brands of stocks) as electronic transactions of multiple targets. Note that the targets are not limited to stocks, and may be securities such as bonds, stock investment trusts, real estate investment trusts, and futures thereof, financial products such as foreign exchange, interest rates, and interest rate futures, or commodities such as gold, crude oil, and grains, and commodity futures thereof, as long as they are tradable in the market.

[0060] The market system 10 includes a market server device 12 and a plurality of client devices 14 .

[0061] The market server device 12 is a computer used by a market administrator. The market server device 12 is connected to a plurality of client devices 14 via a network.

[0062] Each of the client devices 14 is a device used by a market participant, and is realized, for example, by a computer.

[0063] Each of the multiple client devices 14 determines which stock among the multiple stocks to trade. Each of the multiple client devices 14 generates an order packet including trading information for the stock among the multiple stocks that it has decided to trade, and transmits the packet to the market server device 12. The order packet includes, as the trading information, for example, identification information for identifying the stock to be traded among the multiple stocks, a buying / selling direction, price (i.e., stock price), and quantity (i.e., number of shares) representing a sell order or a buy order for the stock identified by the identification information. The price is not limited to a specific value, and may be, for example, a value at the time of the transaction being concluded after the market opens, or a value having a certain range.

[0064] Market server device 12 executes trading of a plurality of stocks. Market server device 12 includes a receiving unit 16, a matching unit 17, and a distribution unit 18.

[0065] The receiving unit 16 receives the order packets transmitted from each of the multiple client devices 14. The receiving unit 16 provides the matching unit 17 with information on the received order packets.

[0066] The matching unit 17 matches the price and quantity of sell orders with the price and quantity of buy orders for each of a plurality of stocks, and completes transactions between sell orders and buy orders whose prices and quantities match in the order in which they are received. The matching unit 17 provides the distribution unit 18 with information about orders that have been completed and information about orders that have not been completed.

[0067] The distribution unit 18 distributes market condition packets including information indicating the status of stock transactions to multiple client devices 14 simultaneously based on the information acquired from the matching unit 17. A market condition packet is generated, for example, for each of multiple stocks. The market condition packet includes identification information for identifying the stock and a transaction price, which is the latest price at which a transaction was concluded for the stock identified by the identification information.

[0068] The market condition packet may also include quote information for each of a plurality of stocks. The quote information is information indicating the price and quantity of unsettled buy orders and information indicating the price and quantity of unsettled sell orders for each of a plurality of stocks.

[0069] The distribution unit 18 distributes market condition packets irregularly. For example, when a trade is concluded, the distribution unit 18 distributes a market condition packet for the stock for which the trade is concluded. For example, each of the multiple client devices 14 acquires the market condition packet distributed irregularly, and determines which of the multiple stocks to trade based on information contained in the acquired market condition packet. Then, each of the multiple client devices 14 generates an order packet for the determined stock and transmits it to the market server device 12.

[0070] The information processing device 20 according to the present embodiment functions as a client device 14 in the market system 10. The information processing device 20 may be realized by a computer including a processor, a memory, and the like, or may be configured to include a dedicated hardware circuit in addition to a processor, a memory, and the like.

[0071] Here, the information processing device 20 generates a combinatorial optimization problem based on market condition packets acquired at irregular intervals, solves the generated combinatorial optimization problem, and based on the solution to the combinatorial optimization problem obtained by solving it, decides whether or not to trade each of the multiple stocks.

[0072] In this embodiment, the information processing device 20 uses a function shown in equation (7) as a cost function in a combinatorial optimization problem.

number

[0073] In formula (7), N is an integer equal to or greater than 2 and represents the number of stocks traded in market server device 12. i and j are integers equal to or greater than 1 and equal to or less than N, and are indexes that identify each of the stocks.

[0074] The cost function in equation (7) includes N decision variables. i is a binary variable, 0 or 1, that indicates whether to trade the i-th stock among multiple stocks. j is a binary variable of 0 or 1, and is a decision variable that indicates whether or not to trade the j-th stock among multiple stocks. i and b j represents 1 if a transaction is made and 0 if a transaction is not made.

[0075] t represents any time between the start time and the end time of trading in one day. t is 0 at the start time of trading and increases as time passes from the start time of trading. In this embodiment, t is an integer and represents time as an index.

[0076] p i (t) is the trading price of the i-th stock at time t, i.e., the stock price at time t. p i (0) is the trading price at the opening of trading for the i-th stock, i.e., the stock price at the opening of trading.

[0077] p i (t) / p i (0)-1 represents the rate of change based on the trading price at the start of trading. i (t) / p i If (0)-1 is greater than 0, it indicates that the price of the i-th stock is rising, and if it is less than 0, it indicates that the price of the i-th stock is falling.

[0078] σ i,j is the correlation value that represents the correlation between the i-th stock and the j-th stock. For example, σ i,jis the average value of the difference in the daily rate of change between the i-th stock and the j-th stock from the day before the trading day to a specified number of days before (for example, five days before). The daily rate of change of the i-th stock is the ratio of the closing price of the i-th stock on the day to the closing price of the i-th stock on the previous day. The difference in the daily rate of change between the i-th stock and the j-th stock is the difference between the daily rate of change of the i-th stock and the daily rate of change of the j-th stock. Therefore, σ i,j The larger the correlation between the daily rate of change of the i-th stock and the daily rate of change of the j-th stock, the smaller the .

[0079] α and β are preset constants.

[0080] The first term on the right side of the cost function in formula (7) is a term that evaluates the difference between the rate of change of each of multiple stocks and a preset value α. Therefore, the cost function in formula (7) decreases when trading stocks whose rate of change is greater than α.

[0081] The second term on the right hand side of the cost function in equation (7) is a term that evaluates the magnitude of correlation in the daily rate of change difference for each combination of two stocks included in the N stocks. Therefore, the cost function in equation (7) decreases, for example, when trading a combination of two stocks with a small correlation in the daily rate of change difference and opposite buying and selling directions. In addition, the cost function in equation (7) decreases, for example, when trading a stock group that includes multiple stocks with the same number of stocks for which sell orders are placed and the same number of stocks for which buy orders are placed, and with a small correlation in the daily rate of change difference between the stocks.

[0082] From the above, the combinatorial optimization problem of minimizing the cost function of equation (7) can obtain a solution that diversifies risk by buying and selling stocks with large rates of change while increasing the number of pairs of two stocks that have low correlation, for example, a small difference in daily rate of change.

[0083] The information processing device 20 determines the direction of buying and selling for the i-th stock, i.e., whether to make a sell order or a buy order, based on the rate of change. For example, when making a buy order in the case of an upward trend, i.e., when following the trend, the information processing device 20 makes a buy order when the rate of change is positive and a sell order when the rate of change is negative. Conversely, when making a sell order in the case of an upward trend, i.e., when following the trend, the information processing device 20 makes a sell order when the rate of change is positive and a buy order when the rate of change is negative. In this embodiment, the information processing device 20 makes a sell order when the rate of change is positive and a buy order when the rate of change is negative.

[0084] In addition, the rate of change of the i-th stock changes every time the trading price of the i-th stock changes. Therefore, the first term on the right hand side of the cost function in equation (7) changes in response to changes in the trading price of any of the N stocks. For example, the first term on the right hand side of the cost function in equation (7) may change on the order of a few nanoseconds.

[0085] In contrast, the daily rate difference between the i-th stock and the j-th stock changes at the close of trading. Therefore, the second term on the right-hand side of the cost function in equation (7) changes from day to day. Thus, the update time interval for the second term on the right-hand side of the cost function in equation (7) is much longer than the first term on the right-hand side of the cost function in equation (7).

[0086] In addition, the rate of change of the i-th stock changes irregularly. Therefore, the timing of change of the first term on the right side of the cost function of formula (7) is asynchronous with the timing of change of the second term on the right side of the cost function of formula (7).

[0087] The information processing device 20 obtains a solution to a combinatorial optimization problem that minimizes such a cost function, i.e., the values ​​of the N decision variables. The information processing device 20 decides to trade stocks corresponding to the decision variables having a value of 1 among the N decision variables. The information processing device 20 then generates an order packet including trading information for the stocks for which it has been decided to execute the trade among the multiple stocks, and transmits the order packet to the market server device 12.

[0088] The information processing device 20 may solve a combinatorial optimization problem that minimizes a cost function other than the cost function shown in equation (7).

[0089] FIG. 7 is a diagram showing the configuration of the information processing device 20 according to the first embodiment.

[0090] The information processing device 20 acquires data, generates a combinatorial optimization problem based on the acquired data, and generates output data based on a solution to the generated combinatorial optimization problem. The information processing device 20 acquires first data and second data as data. Then, the information processing device 20 outputs the generated output data to a first device different from the information processing device 20.

[0091] In this embodiment, the information processing device 20 receives a market condition packet irregularly provided by the market server device 12 as the first data. The information processing device 20 also acquires a correlation value for each combination of two stocks included in the N stocks as the second data. For example, the information processing device 20 acquires the daily rate difference of increase and decrease for each day as the correlation value of the combination of two stocks. The information processing device 20 generates a plurality of weight values ​​to be included in a cost function in a combinatorial optimization problem based on the received market condition packet and the correlation value for each combination of two stocks included in the N stocks. The information processing device 20 solves a combinatorial optimization problem that minimizes a cost function including the generated plurality of weight values. The information processing device 20 generates an order packet as output data based on the solution of the combinatorial optimization problem obtained by solving it. Then, in this embodiment, the information processing device 20 transmits the generated order packet to the market server device 12, which is an example of a first device.

[0092] The information processing device 20 includes a first input memory 31, a second input memory 32, a first acquisition unit 33, a second acquisition unit 34, a solver device 40, a first update unit 41, a second update unit 42, and a processing execution unit 46.

[0093] The first input memory 31 stores a plurality of first input values ​​that are the basis of a plurality of weight values ​​included in the cost function of the combinatorial optimization problem. In this embodiment, the first input memory 31 stores values ​​according to a plurality of trading prices as the plurality of first input values. The values ​​according to the trading prices stored in the first input memory 31 correspond one-to-one to the plurality of stocks. That is, the first input memory 31 stores a value according to the trading price for each of the plurality of stocks. The value according to the trading price may be the trading price, or may be a value obtained by performing a predetermined process or calculation on the trading price. For example, the value according to the trading price may be a rate of change that indicates the ratio of the latest trading price to the trading price at the start of trading.

[0094] The second input memory 32 stores a plurality of second input values ​​that are the basis of a plurality of weight values ​​included in the cost function of the combinatorial optimization problem. In this embodiment, the second input memory 32 stores, as the plurality of second input values, correlation values ​​for each combination of two stocks among the plurality of stocks for all combinations of two stocks. For example, when the plurality of stocks is N stocks (N is an integer equal to or greater than 2), the second input memory 32 stores {N×(N−1) / 2} correlation values. For example, the correlation value between the i-th stock among the N stocks and the j-th stock of the N stocks is the difference in daily rate of change between the i-th stock and the j-th stock.

[0095] The first acquisition unit 33 acquires first data that is repeatedly given at irregular intervals. The first data acquired by the first acquisition unit 33 includes first input information related to at least one of the multiple targets. When the first acquisition unit 33 acquires the first data, the first acquisition unit 33 rewrites a first input value corresponding to a target related to the first input information included in the acquired first data, among the multiple first input values ​​stored in the first input memory 31, based on the first input information included in the acquired first data.

[0096] In this embodiment, the first acquisition unit 33 irregularly and repeatedly acquires a market condition packet, which is an example of the first data to be provided, from the market server device 12. The market condition packet includes the trading price of at least one of the multiple stocks as first input information. When the first acquisition unit 33 acquires the market condition packet, the first acquisition unit 33 rewrites the value corresponding to the trading price of the stock indicated in the acquired market condition packet, among the values ​​corresponding to the trading prices of each of the multiple stocks stored in the first input memory 31, based on the trading price included in the acquired market condition packet.

[0097] The second acquisition unit 34 acquires the second data given repeatedly. The second data acquired by the second acquisition unit 34 includes second input information related to a pair of two targets among the multiple targets. When acquiring the second data, the second acquisition unit 34 rewrites the second input value corresponding to the pair of two targets related to the second input information included in the acquired second data, among the multiple second input values ​​stored in the second input memory 32, based on the second input information included in the acquired second data.

[0098] In this embodiment, the second acquisition unit 34 acquires closing price information, which is an example of the second data that is repeatedly provided, from the stock information provider. The stock information provider is a device provided on a network, and may be, for example, the market server device 12, or may be a device other than the market server device 12. The closing price information includes a correlation value of a pair of two stocks among the multiple stocks as second input information. When acquiring the closing price information, the second acquisition unit 34 rewrites the correlation value included in the acquired closing price information, among the correlation values ​​for each combination of two stocks stored in the second input memory 32, based on the correlation value included in the acquired closing price information.

[0099] The second acquisition unit 34 acquires the second data asynchronously with the timing at which the first acquisition unit 33 acquires the first data. For example, the first acquisition unit 33 acquires a market condition packet every time the market server device 12 distributes a market condition packet. Therefore, the first acquisition unit 33 may repeatedly acquire market condition packets on the order of a time period of, for example, a few seconds or a few milliseconds. In contrast, the second acquisition unit 34 acquires closing price information after the closing time of trading and before the closing time of trading on the next day. Therefore, the second acquisition unit 34 acquires closing price information repeatedly on the order of a time period of, for example, every day. The second acquisition unit 34 acquires the closing price information at a timing asynchronous with the market condition packet.

[0100] The second acquisition unit 34 also acquires correlation values ​​for all pairs of two stocks that can be combined with multiple stocks every day. The second acquisition unit 34 then rewrites the correlation values ​​stored in the second input memory 32 for all pairs of two stocks that can be combined with multiple stocks every day.

[0101] The solver device 40 solves a combinatorial optimization problem for minimizing a cost function including a plurality of weight values. The solver device 40 then outputs a solution to the combinatorial optimization problem obtained by solving the problem. In this embodiment, the solver device 40 is a simulated bifurcation machine, which is an Ising machine, and is implemented in a dedicated hardware circuit. Note that the solver device 40 may solve the combinatorial optimization problem based on another algorithm instead of the simulated bifurcation machine.

[0102] The solver device 40 includes a first weight memory 51 and a second weight memory 52 .

[0103] The first weight memory 51 stores a plurality of first weight values. The second weight memory 52 stores a plurality of second weight values. The plurality of weight values ​​included in the cost function are generated by combining a plurality of first weight values ​​and a plurality of second weight values. Therefore, in the process of solving a combinatorial optimization problem, the solver device 40 generates a plurality of weight values ​​by combining a plurality of first weight values ​​stored in the first weight memory 51 and a plurality of second weight values, and solves the combinatorial optimization problem.

[0104] In this embodiment, the first weight memory 51 stores the coefficients included in the first term on the right side included in the cost function shown in equation (7) as a plurality of first weight values. That is, in this embodiment, each of the plurality of first weight values ​​stored in the first weight memory 51 is a coefficient of a linear term in the cost function which is a quadratic function, that is, a coefficient included in the bias coefficient array (h). Also, in this embodiment, the second weight memory 52 stores the coefficients included in the second term on the right side included in the cost function shown in equation (7) as a plurality of second weight values. That is, in this embodiment, each of the plurality of second weight values ​​stored in the second weight memory 52 is a coefficient of a quadratic term in the cost function which is a quadratic function, that is, a coefficient included in the matrix (J).

[0105] The solver device 40 starts solving the combinatorial optimization problem in response to updating one of the multiple first weight values ​​stored in the first weight memory 51 and the multiple second weight values ​​stored in the second weight memory 52. ​​In this way, when the multiple weight values ​​included in the cost function change, that is, when the combinatorial optimization problem changes, the solver device 40 can output a solution to the changed combinatorial optimization problem.

[0106] The first updating unit 41 generates a plurality of first weighting values ​​based on the first data acquired by the first acquiring unit 33, and updates the plurality of first input values ​​stored in the first input memory 31. More specifically, the first updating unit 41 generates a plurality of first weighting values ​​based on the plurality of first input values ​​stored in the first input memory 31, and writes the generated plurality of first weighting values ​​to the first weighting memory 51.

[0107] In this embodiment, the first update unit 41 generates a bias coefficient array (h) based on the first term on the right side included in the cost function shown in equation (7), and writes the generated bias coefficient array (h) to the first weight memory 51. More specifically, the first update unit 41 generates a bias coefficient array (h) obtained by the first term on the right side of equation (7) based on values ​​corresponding to the trading prices of multiple stocks stored in the first input memory 31, and writes the generated bias coefficient array (h) to the first weight memory 51.

[0108] Furthermore, the first updating unit 41 generates a plurality of first weight values ​​in response to acquiring the first data or at a preset first period, and writes the generated first weight values ​​into the first weight memory 51. In this embodiment, the first updating unit 41 generates a plurality of first weight values ​​in response to acquiring a market condition packet by the first acquiring unit 33, or at a preset first period, and writes the generated first weight values ​​into the first weight memory 51.

[0109] However, the first update unit 41 does not update the multiple first weight values ​​stored in the first weight memory 51 while the solver device 40 is solving. In addition, the preset first period does not have to be at regular intervals and may vary over time.

[0110] The second updating unit 42 generates a plurality of second weighting values ​​based on the second data acquired by the second acquiring unit 34, and updates the plurality of second input values ​​stored in the second input memory 32. More specifically, the second updating unit 42 generates a plurality of second weighting values ​​based on the plurality of second input values ​​stored in the second input memory 32, and writes the generated plurality of second weighting values ​​to the second weighting memory 52.

[0111] In this embodiment, the second updating unit 42 generates a matrix (J) based on the second term on the right side included in the cost function shown in equation (7), and writes the generated matrix (J) to the second weighting memory 52. ​​More specifically, the second updating unit 42 generates a matrix (J) obtained by the second term on the right side of equation (7) based on the multiple correlation values ​​stored in the second input memory 32, and writes the generated matrix (J) to the second weighting memory 52.

[0112] Furthermore, the second updating unit 42 generates a plurality of second weighting values ​​in response to acquiring the second data or at a preset second cycle, and writes the generated second weighting values ​​to the second weighting memory 52. ​​In the present embodiment, the second updating unit 42 generates a plurality of second weighting values ​​in response to acquiring the closing price information by the second acquiring unit 34, or at a preset second cycle, and writes the generated second weighting values ​​to the second weighting memory 52.

[0113] However, the second update unit 42 does not update the multiple second weight values ​​stored in the second weight memory 52 while the solver device 40 is solving. In addition, the preset second period does not have to be at regular intervals and may vary over time.

[0114] The process execution unit 46 obtains a solution to the combinatorial optimization problem from the solver device 40. In this embodiment, the process execution unit 46 calculates the solution to the combinatorial optimization problem by solving a plurality of decision variables (b1 to b N ) as a solution. In response to receiving the solution from the solver device 40, the process execution unit 46 executes a process based on the received solution.

[0115] For example, when the processing execution unit 46 acquires a solution to a combinatorial optimization problem from the solver device 40, the processing execution unit 46 generates output data including output information indicating to perform a predetermined operation on at least one stock among the multiple stocks identified by the solution, based on the acquired solution. Then, the processing execution unit 46 outputs the output data to the first device.

[0116] In this embodiment, when the process execution unit 46 acquires a solution to a combinatorial optimization problem from the solver device 40, it generates an order packet, which is an example of output data. The order packet includes, as output information, a plurality of decision variables (b1 to b N The order packet includes transaction information indicating that a buy order or a sell order, which is a predetermined operation, is to be placed for the stock corresponding to the decision variable having the value (1) indicating that a transaction is to be placed among the values ​​of the decision variables (1) and (2), which indicates that a transaction is to be performed. Then, the process execution unit 46 outputs the generated order packet to the market server device 12, which is an example of the first device.

[0117] 8 is a timing chart showing a first processing example of the information processing device 20. The information processing device 20 executes processing, for example, according to the flow shown in FIG.

[0118] The first acquisition unit 33 acquires a market condition packet from the market server device 12 (t1 and t5 in FIG. 8). When the first acquisition unit 33 acquires the market condition packet, the first acquisition unit 33 rewrites, among the values ​​corresponding to the respective trading prices of the multiple stocks stored in the first input memory 31, the values ​​corresponding to the trading prices of the stocks related to the trading prices included in the market condition packet.

[0119] When any of the values ​​corresponding to the multiple trading prices stored in the first input memory 31 is rewritten by the first acquisition unit 33, the first update unit 41 generates multiple first weight values ​​based on the values ​​corresponding to the respective trading prices of the multiple stocks stored in the first input memory 31. Then, the first update unit 41 writes the generated multiple first weight values ​​into the first weight memory 51 of the solver device 40, and causes the solver device 40 to execute a solution-finding process (t2 and t6 in FIG. 8).

[0120] The second acquisition unit 34 acquires the closing price information (t9 in FIG. 8). When the second acquisition unit 34 acquires the closing price information, the second acquisition unit 34 rewrites the multiple correlation values ​​stored in the second input memory 32.

[0121] When the second acquisition unit 34 rewrites the correlation values ​​stored in the second input memory 32, the second update unit 42 generates a plurality of second weight values ​​based on the correlation values ​​stored in the second input memory 32. Then, the second update unit 42 writes the generated second weight values ​​into the second weight memory 52 of the solver device 40, and causes the solver device 40 to execute a solution-finding process (t in FIG. 8 ). 10 ).

[0122] The solver device 40 starts the solution-finding process after the first weight values ​​are written to the first weight memory 51 and after the second weight values ​​are written to the second weight memory 52. ​​When the solver device 40 completes the solution-finding process, it provides the solution to the combinatorial optimization problem to the process execution unit 46 (t3, t7, t 11 ).

[0123] The process execution unit 46 generates an order packet in response to acquiring the solution to the combinatorial optimization problem from the solver device 40. Then, the process execution unit 46 outputs the generated order packet to the market server device 12 (t4, t8, t 11 ).

[0124] 9 is a timing chart showing a second processing example of the information processing device 20. The information processing device 20 may execute processing according to the flow shown in FIG.

[0125] The solver device 40 may start the solution-finding process only when either one of the multiple first weight values ​​stored in the first weight memory 51 or the multiple second weight values ​​stored in the second weight memory 52 is updated. For example, the solver device 40 may start the solution-finding process only when the multiple second weight values ​​stored in the second weight memory 52 are updated by the second update unit 42 (at time t 21 ), and does not start the solution-finding process. This allows the information processing device 20 to prevent the generation and output of order packets from occurring after the closing time of stock trading by the market server device 12 until the start time of the next trading.

[0126] Furthermore, the first update unit 41 may execute a process of generating a plurality of first weight values ​​and writing the generated plurality of first weight values ​​into the first weight memory 51 at regular time intervals, regardless of acquisition of a market condition packet by the first acquisition unit 33. For example, in the example of Fig. 9, the first update unit 41 executes a process of generating a plurality of first weight values ​​and writing the plurality of first weight values ​​at every time T from the trading start time.

[0127] In this way, the information processing device 20 according to this embodiment generates a plurality of first weight values ​​in response to a market condition packet and writes them into the first weight memory 51, and generates a plurality of second weight values ​​in response to closing price information and writes them into the second weight memory 52. ​​Thereby, the information processing device 20 does not need to generate a plurality of second weight values ​​when it acquires a market condition packet, and does not need to generate a plurality of first weight values ​​when it acquires closing price information. Therefore, the information processing device 20 does not need to generate and write all of the plurality of weight values ​​when it acquires either a market condition packet or closing price information, and therefore the combinatorial optimization problem to be executed by the solver device 40 can be efficiently updated.

[0128] Second embodiment Next, a market system 10 according to a second embodiment will be described. The market system 10 according to the second embodiment has substantially the same functions and configurations as those of the first embodiment, so elements having substantially the same functions and configurations are denoted by the same reference numerals, and detailed descriptions thereof will be omitted except for the differences.

[0129] FIG. 10 is a diagram showing a plurality of first weighting values ​​stored in the first weighting memory 51 and a plurality of second weighting values ​​stored in the second weighting memory 52 according to the second embodiment.

[0130] The information processing device 20 according to the second embodiment solves a QUBO problem for minimizing a cost function, which is a quadratic function including N decision variables, by reducing it to an Ising problem for minimizing an Ising model. In this case, the solver device 40 generates a matrix (J) including correlation coefficients of N rows by N columns and a bias coefficient array (h) including N bias coefficients based on a plurality of first weight values ​​stored in a first weight memory 51 and a plurality of second weight values ​​stored in a second weight memory 52 during the solution process.

[0131] In the second embodiment, the first updating unit 41 generates a first matrix (J1) including N rows x N columns of first weight values ​​as a plurality of first weight values, and writes it into the first weight memory 51. In addition, the second updating unit 42 generates a second matrix (J2) including N rows x N columns of second weight values ​​as a plurality of second weight values, and writes it into the second weight memory 52.

[0132] Then, the solver device 40 calculates the weight value (J i,j ), the first weight value (J1 i,j ) and the second weight value of the i-th row and j-th column in the second matrix (J2 i,j ) and performs addition. In this way, the solver device 40 reads out the weight value (J i,j ) can be used to perform processing.

[0133] The solver device 40 calculates the first weight value (J1 i,j ) and the second weight value (J2 i,j Alternatively, the solver device 40 may perform subtraction, multiplication or division instead of addition with the first weight value (J1 i,j ) and the second weight value (J2 i,j ) as an argument.

[0134] Furthermore, in the second embodiment, the first updating unit 41 may write, as the multiple first weight values, a first array (h1) including N first weight values ​​into the first weight memory 51 instead of or in addition to the first matrix (J1) including N rows x N columns of first weight values. Furthermore, the second updating unit 42 may write, as the multiple first weight values, a second array (h2) including N second weight values ​​into the second weight memory 52 instead of or in addition to the second matrix (J2) including N rows x N columns of second weight values.

[0135] Then, the solver device 40 calculates the i-th weight value (h i), the i-th first weight value (h1 i ) and the i-th second weight value (h2 i ) and performs addition. In this way, the solver device 40 reads out the i-th weight value (h i ) can be used to perform processing.

[0136] The solver device 40 calculates the i-th first weight value (h1 i ) and the i-th second weight value in the second array (h2) (h2 i Alternatively, the solver device 40 may perform subtraction, multiplication, or division instead of addition with the i-th first weight value (h1 i ) and the i-th second weight value in the second array (h2) (h2 i ) as an argument.

[0137] For example, in the second embodiment, when the cost function shown in formula (7) is used, the first update unit 41 generates a first array (h1) representing the coefficient of the first term on the right side of formula (7) and a first matrix (J1) in which all coefficients are 0, and writes them into the first weight memory 51. Also, in the second embodiment, when the cost function shown in formula (7) is used, the second update unit 42 generates a second array (h2) in which all coefficients are 0, and a second matrix (J2) representing the coefficient of the second term on the right side of formula (7), and writes them into the second weight memory 52. ​​This allows the solver device 40 to calculate a solution to the optimization problem that minimizes the cost function shown in formula (7).

[0138] Third embodiment Next, a market system 10 according to a third embodiment will be described. The market system 10 according to the third embodiment has substantially the same functions and configurations as those of the second embodiment, so elements having substantially the same functions and configurations are denoted by the same reference numerals, and detailed descriptions thereof will be omitted except for the differences.

[0139] 11 is a diagram showing the configuration of a solver device 40 according to the third embodiment. The information processing device 20 according to the third embodiment includes the solver device 40 that executes a simulated bifurcation algorithm.

[0140] The solver device 40 includes an arithmetic circuit 71 , an input circuit 72 , an output circuit 73 , and a setting circuit 74 .

[0141] The arithmetic circuit 71 increases a parameter t representing time by unit time (Δt) from an initial time (for example, 0) to an end time. The arithmetic circuit 71 calculates a first variable (x i ) and the second variable (y i ) is calculated. The N virtual points correspond to the N spins in the Ising model. The i-th virtual point of the N virtual points corresponds to the i-th spin of the N spins in the Ising model.

[0142] The first variable (x i ) is a position variable that represents the position of the corresponding virtual point. i ) is the momentum variable that represents the momentum of the corresponding virtual point.

[0143] The calculation circuit 71 calculates N first variables (x i ) and N second variables (y i ) in sequence for each unit time and for the first variable (x i ) and the second variable (y i ) alternately. More specifically, the arithmetic circuit 71 executes the arithmetic shown in the algorithms of equations (4-1) and (4-2) for each unit time from the initial time to the end time. The arithmetic circuit 71 may execute the arithmetic shown in the algorithms of equations (5-1), (5-2) and (5-3), or may execute the arithmetic shown in the algorithms of equations (6-1), (6-2) and (6-3). The arithmetic circuit 71 calculates the N first variables (x i) (i.e., the positions of the N virtual points) are binarized to calculate a solution to the combinatorial optimization problem.

[0144] Prior to the arithmetic processing by the arithmetic circuit 71, the input circuit 72 receives N first variables (x i ) and N second variables (y i ) and provides them to the arithmetic circuit 71. After the arithmetic processing by the arithmetic circuit 71 is completed, the output circuit 73 acquires the solution to the combinatorial optimization problem from the arithmetic circuit 71. Then, the output circuit 73 outputs the acquired solution. The setting circuit 74 sets each parameter in the arithmetic circuit 71 prior to the arithmetic processing by the arithmetic circuit 71.

[0145] Fig. 12 is a diagram showing a block configuration of the arithmetic circuit 71. In the explanation of Fig. 12, the target time (second time) is any time when the time from the initial time to the end time is divided into unit times. The immediately preceding time (first time) is the time one unit time before the target time. In Fig. 12, the immediately preceding time (first time) is represented as t1. Moreover, the target time (second time) is represented as t2.

[0146] The arithmetic circuit 71 includes an X memory 81, a Y memory 82, an action arithmetic circuit 83, a time evolution circuit 84 (first circuit), and a control circuit 85.

[0147] The X memory 81 stores the N first variables (x i As the time is updated, the X memory 81 stores the N first variables (x i That is, the X memory 81 stores the N first variables (x i When the first variable (x i (t2)) is the new N first variables (x i Prior to the calculation, the setting circuit 74 writes the N first variables xi Write to X memory 81.

[0148] The Y memory 82 stores N second variables (y i As the time is updated, the Y memory 82 stores the N second variables (y i That is, the Y memory 82 stores N second variables (y i When the second variable (y i (t2)) is the N second variables (y i (t1)). Prior to the calculation, the setting circuit 74 writes the N second variables y i is written to Y memory 82.

[0149] The action calculation circuit 83 calculates the N first variables (x j (t1)) from the X memory 81. Then, the action calculation circuit 83 obtains the update value (z i (t1)) is calculated.

[0150] The time evolution circuit 84 calculates the update value (z i The time evolution circuit 84 obtains the first variable (x i (t1)) is obtained from the X memory 81, and the second variable (y i The time evolution circuit 84 then obtains the first variable (x i (t2)) is calculated, and the first variable (x iAt the same time, the time evolution circuit 84 rewrites the second variable (y i (t2)) is calculated, and the second variable (y i Rewrite (t1).

[0151] The control circuit 85 sequentially updates the target time (t2) for each unit time (Δt) to provide the action calculation circuit 83 and the time evolution circuit 84 with a first variable (x i (t)) and the second variable (y i (t)) are calculated sequentially.

[0152] Furthermore, the control circuit 85 generates an index (i) for identifying the N virtual points by incrementing from 1 to N for each unit time. The control circuit 85 provides the index (i) to the action calculation circuit 83 and the time evolution circuit 84 to calculate the first variable (x i (t2)) and the second variable (y i The action calculation circuit 83 and the time evolution circuit 84 calculate a plurality of first variables (x i (t2)) and multiple second variables (y i (t2)) may be calculated in parallel.

[0153] 13 is a diagram showing the configuration of the action calculation circuit 83. The action calculation circuit 83 has a first weight memory 51, a second weight memory 52, a matrix calculation circuit 91, a first adder circuit 93, an α function circuit 94, and a second adder circuit 96.

[0154] The first weight memory 51 includes a first J memory 101 and a first h memory 103. The second weight memory 52 includes a second J memory 102 and a second h memory 104.

[0155] The first J memory 101 stores a first matrix (J1) including (N×N) first weight values. The second J memory 102 stores a second matrix (J2) including (N×N) second weight values.

[0156] J1 i , j represents the first weight value in the i-th row and j-th column of the first matrix. i , j represents the second weight value in the i-th row and j-th column of the second matrix. i , j and J2 i , j The sum of these is the weight value of row i and column j of the matrix (J) in the Ising model. In other words, the matrix (J) in the Ising model is a matrix obtained by adding the first matrix (J1) and the second matrix (J2).

[0157] The first h memory 103 stores a first array (h1) including N first weight values. The second h memory 104 stores a second matrix (h2) including N second weight values.

[0158] h1 i represents the i-th first weight value contained in the first array. i represents the i-th second weight value contained in the second array. i and h2 i The sum of and becomes the i-th weight value of the array (h) that contains the bias coefficient in the Ising model.

[0159] Prior to the calculation, the setting circuit 74 receives the first matrix (J1) and the first array (h1) generated by the first updating unit 41. Then, the setting circuit 74 writes the first matrix (J1) to the first J memory 101, and writes the first array (h1) to the first h memory 103. Prior to the calculation, the setting circuit 74 receives the second matrix (J2) and the second array (h2) generated by the second updating unit 42. Then, the setting circuit 74 writes the second matrix (J2) to the second J memory 102, and writes the second array (h2) to the second h memory 104.

[0160] The matrix calculation circuit 91 reads from the X memory 81 the N first variables (x j The matrix calculation circuit 91 obtains N first weight values ​​(J1 (t1)) included in the target row from the first J memory 101 and the second J memory 102 for each of the N virtual points. i,j ) and N second weight values ​​(J2 i,j Then, the matrix calculation circuit 91 obtains N first variables (x j (t1)) and the N weight values ​​(J i,j ) and perform a multiply-and-accumulate operation.

[0161] The first adder circuit 93 calculates, for each of the N virtual points, a corresponding first weight value (h1 i ), and retrieves the corresponding second weight value (h2) from the second memory 104 among the N second weight values ​​included in the second array (h2). i Then, the first adder circuit 93 calculates the first weight value (h1 i ) and the second weight value obtained (h2 i ) to obtain the bias coefficient (h i ) is calculated.

[0162] The α function circuit 94 receives the target bias coefficient (h i ) for each of the N virtual points. i α(t1)} is calculated, where α(t) is a preset function.

[0163] The second adder circuit 96 adds, for each of the N virtual points, a value representing the result of the calculation by the matrix calculation circuit 91 and a value representing the result of the calculation by the α function circuit 94. Through this calculation, the second adder circuit 96 obtains, for each of the N virtual points, an update value (z i(t1)).

number

[0164] FIG. 14 is a diagram showing the configuration of a matrix calculation circuit 91 according to the third embodiment, together with a first J memory 101, a second J memory 102, and an X memory 81.

[0165] The first J memory 101 stores a first matrix (J1). Every time a clock is given, the first J memory 101 stores one first weight value (J1) out of the N×N first weight values ​​included in the first matrix (J1). i,j ). The first J memory 101 outputs N first weight values ​​in a row specified by an index (i). The index (i) is a value that specifies one of the N virtual points. The index (i) is repeatedly incremented by a value from 1 to N, and is updated every N clocks. Therefore, the first J memory 101 raster scans the N×N first weight values ​​included in the first matrix (J1) and outputs the first weight value (J1 i,j That is, the first J memory 101 outputs the N first weight values ​​{J1 1,1 ,J1 1,2 ,…,J1 1,N} from the first column to the Nth column, and then the N first weight values ​​{J1 2,1 ,J1 2,2 ,…,J1 2,N} from the 1st column to the Nth column. After that, the first J memory 101 outputs N first weight values ​​in the same manner for each row up to the Nth row. Then, the first J memory 101 outputs the first weight value (J1 N,N ), then it returns to the first line and repeats the same process.

[0166] The second J memory 102 stores the second matrix (J2). Every time a clock is given, the second J memory 102 stores one second weight value (J2 i,jThe second J memory 102 outputs N second weighting values ​​in the row specified by the index (i). Therefore, the second J memory 102 raster scans the N×N second weighting values ​​included in the second matrix (J2) and outputs the second weighting values ​​(J2 i,j That is, the second J memory 102 outputs the N second weight values ​​{J2 1,1 ,J2 1,2 ,…,J2 1,N} from the first column to the Nth column, and then the N second weight values ​​{J2 2,1 ,J2 2,2 ,…,J2 2,N} from the first column to the Nth column in sequence. After that, the second J memory 102 outputs N second weight values ​​in the same manner for each row up to the Nth row. Then, the second J memory 102 outputs the second weight value (J2 N,N ), then it returns to the first line and repeats the same process.

[0167] The X memory 81 stores the N first variables (x j The X memory 81 stores N first variables (x j (t1)) to the first variable (x1(t1)) and then the Nth first variable (x N The X memory 81 outputs the first variable (x j After outputting the first variable (x N The X memory 81 outputs the first variable (x N (t1)).

[0168] The matrix calculation circuit 91 according to the third embodiment includes a first weighting and adding circuit 113, a first multiplication circuit 115, and a first accumulating and adding circuit .

[0169] The first weighting circuit 113 adds the first weighting value (J1 i,j) and the second weight value (J2 i,j ) and the weighted value (J i,j ) for each clock. In this way, the first weighting circuit 113 raster-scans a matrix (J) containing N×N weighting values ​​and outputs the weighting values ​​(J i,j ) can be output. This allows the first weighting addition circuit 113 to calculate the matrix (J) by performing matrix addition of the first matrix (J1) and the second matrix (J2).

[0170] The first multiplier circuit 115 multiplies the weight value (J i,j ) and the first variable output from X memory 81 (x j (t1)) and output the multiplied value.

[0171] The first cumulative addition circuit 116 includes an adder 121, a reset selector 122, and a latch circuit 123. The adder 121 adds the multiplied value output from the first multiplication circuit 115 and the value stored in the latch circuit 123. The reset selector 122 provides the value output from the adder 121 to the latch circuit 123. Furthermore, the reset selector 122 provides 0 to the latch circuit 123 instead of the value output from the adder 121 every N clocks, that is, in synchronization with the update of the index (i). The latch circuit 123 takes in and stores the value output from the reset selector 122 for each clock.

[0172] The first accumulating circuit 116 accumulates the multiplied values ​​output from the first multiplying circuit 115 to calculate a product-sum calculation value for each clock. The first accumulating circuit 116 resets the product-sum calculation value to 0 for every N clocks, that is, in synchronization with the update of the index (i). The first accumulating circuit 116 also outputs the product-sum calculation value in the cycle immediately before resetting the product-sum calculation value to 0. As a result, the first accumulating circuit 116 accumulates the N weight values ​​included in the row corresponding to the index (i) in the matrix (J) and the N first variables (x j(t1)) can be multiplied and accumulated to output a product of the product.

[0173] In this way, the matrix calculation circuit 91 according to the third embodiment calculates the matrix (J) by performing matrix addition on the first matrix (J1) and the second matrix (J2). Then, the matrix calculation circuit 91 calculates the matrix (J) by adding the N first variables (x j By performing matrix multiplication of matrix (J) with matrix (t1), N multiplication and accumulation values ​​(z´ i (t1) (an example of the N second intermediate variables).

number

[0174] As described above, the matrix calculation circuit 91 according to the third embodiment calculates a matrix (J) obtained by adding a first matrix (J1) that is a plurality of first weight values ​​and a second matrix (J2) that is a plurality of second weight values, and a matrix (J) obtained by multiplying N first variables (x j (t1)) can be used to perform a multiply-and-accumulate operation.

[0175] (Fourth embodiment) Next, a market system 10 according to the fourth embodiment will be described. The market system 10 according to the fourth embodiment is the same as that of the third embodiment, except for the matrix calculation circuit 91. Below, the matrix calculation circuit 91 according to the fourth embodiment will be described, and detailed descriptions of the same configuration as that of the third embodiment will be omitted.

[0176] FIG. 15 is a diagram showing the configuration of a matrix calculation circuit 91 according to the fourth embodiment, together with a first J memory 101, a second J memory 102, and an X memory 81.

[0177] The matrix operation circuit 91 according to the fourth embodiment includes a second multiplication circuit 131, a third multiplication circuit 132, a second accumulating and adding circuit 133, a third accumulating and adding circuit 134, and a first output adding circuit 135.

[0178] The second multiplication circuit 131 multiplies the first weight value (J1i,j ) and the first variable (x j The third multiplier circuit 132 multiplies the second weighting value (J2 i,j ) and the first variable (x j (t1)) and outputs the second multiplied value.

[0179] The second accumulating circuit 133 has the same configuration as the first accumulating circuit 116 according to the third embodiment. The second accumulating circuit 133 calculates a first product-sum calculation value by accumulating the first multiplied values ​​output from the second multiplier circuit 131 for each clock. The second accumulating circuit 133 resets the first product-sum calculation value to 0 for every N clocks, that is, in synchronization with the update of the index (i). The second accumulating circuit 133 outputs the first product-sum calculation value in the cycle immediately before resetting the first product-sum calculation value to 0. As a result, the second accumulating circuit 133 calculates, for every N clocks, N first weight values ​​included in the row corresponding to the index (i) in the first matrix (J1) and N first variables (x j (t1)) to generate a first product-sum value.

[0180] The third accumulating circuit 134 has the same configuration as the first accumulating circuit 116 according to the third embodiment. The third accumulating circuit 134 calculates a second product-sum calculation value by accumulating the second multiplied value output from the third multiplier circuit 132 for each clock. The third accumulating circuit 134 resets the second product-sum calculation value to 0 for every N clocks, that is, in synchronization with the update of the index (i). The third accumulating circuit 134 outputs the second product-sum calculation value in the cycle immediately before resetting the second product-sum calculation value to 0. As a result, the third accumulating circuit 134 calculates, for every N clocks, N second weight values ​​included in the row corresponding to the index (i) in the second matrix (J2) and N first variables (x j (t1)) to generate a second multiply-and-accumulate value.

[0181] The first output adder circuit 135 adds the first cumulative addition value in the cycle immediately before the second cumulative addition circuit 133 resets the first cumulative addition value to 0, and the second cumulative addition value in the cycle immediately before the third cumulative addition circuit 134 resets the second cumulative addition value to 0. The first output adder circuit 135 outputs the sum of the first cumulative addition value and the second cumulative addition value every N clocks, that is, in synchronization with the update of the index (i), as a product-sum operation value (z' i (t1)).

[0182] In this way, the matrix calculation circuit 91 according to the fourth embodiment calculates the N first variables (x j The matrix operation circuit 91 performs matrix multiplication of the N first variables (x j Then, the matrix operation circuit 91 performs matrix multiplication of the N first product-sum operation values ​​and the N second product-sum operation values ​​to generate N second product-sum operation values ​​(z' i (t1)) is calculated.

[0183] As described above, the matrix calculation circuit 91 according to the fourth embodiment calculates the matrix (J) obtained by adding the first matrix (J1) which is a plurality of first weight values ​​and the second matrix (J2) which is a plurality of second weight values, and the matrix (J) obtained by multiplying the N first variables (x j (t1)) can be used to perform a multiply-and-accumulate operation.

[0184] Fifth embodiment Next, a market system 10 according to the fifth embodiment will be described. The market system 10 according to the fifth embodiment is the same as that of the third embodiment, except for the matrix calculation circuit 91, the first J memory 101, and the second J memory 102. Below, the matrix calculation circuit 91 according to the fifth embodiment will be described, and detailed descriptions of the same configuration as that of the third embodiment will be omitted.

[0185] FIG. 16 is a diagram showing the configuration of a matrix calculation circuit 91 according to the fifth embodiment, together with a first J memory 101, a second J memory 102, and an X memory 81.

[0186] The first J memory 101 according to the fifth embodiment includes N first row memories 141-1 to 141-N. The i-th first row memory 141-i of the N first row memories 141-1 to 141-N stores N first weight values ​​{J1 i,1 ,J1 i,2 ,…,J1 i,N Each of the N first row memories 141-1 to 141-N stores N first weight values ​​one by one for each clock, such as the first weight value (J1 i,1 ), the first weight value in the Nth column (J1 i,N ) is output.

[0187] The second J memory 102 according to the fifth embodiment includes N second row memories 142-1 to 142-N. The i-th second row memory 142-i of the N second row memories 142-1 to 142-N stores N second weight values ​​{J2 i,1 ,J2 i,2 ,…,J2 i,N Each of the N second row memories 142-1 to 142-N stores N second weight values, one at a time, for each clock, starting with the second weight value (J2 i,1 ) in order, the second weight value (J2 i,N ) is output.

[0188] The X memory 81 according to the fifth embodiment stores N first variables (x j (t1)) is output in parallel.

[0189] The matrix calculation circuit 91 according to the fifth embodiment includes N second weighting addition circuits 143-1 to 143-N, N fourth multiplication circuits 144-1 to 144-N, and a first summation circuit 145.

[0190] The N second weighting addition circuits 143-1 to 143-N correspond one-to-one to the N rows. The i-th second weighting addition circuit 143-i of the N second weighting addition circuits 143-1 to 143-N corresponds to the i-th row of the N rows. The i-th second weighting addition circuit 143-i calculates the N first weight values ​​{J1 i,1 ,J1 i,2 ,…,J1 i,N} for each clock. The i-th second weighting addition circuit 143-i acquires N second weighting values ​​{J2 i,1 ,J2 i,2 ,…,J2 i,N The i-th second weighting addition circuit 143-i acquires the first weighting value (J1 i,j ) and the second weight value (J2 i,j ) and the weight value (J i,j ). Such N second weighting addition circuits 143-1 to 143-N can generate N weighting values ​​for each of the N columns in the matrix (J) by performing a process of adding a column in the first matrix (J1) and a column in the second matrix (J2) for one column for each of the N columns.

[0191] The N fourth multiplication circuits 144-1 to 144-N correspond one-to-one to the N rows. Among the N fourth multiplication circuits 144-1 to 144-N, the i-th fourth multiplication circuit 144-i corresponds to the i-th row of the N rows. The i-th fourth multiplication circuit 144-i receives the weighting value (J) of the i-th row in the matrix (J) from the i-th second weighting addition circuit 143-i for each clock. i,j In addition, the i-th fourth multiplication circuit 144-i acquires the N first variables (x j (t1)), the first variable (x iThe i-th fourth multiplication circuit 144-i obtains the weight value (J i,j ) and the first variable (x i Such N fourth multiplier circuits 144-1 to 144-N output the i-th multiplied value obtained by multiplying the i-th weight value (J i,j ) and the N first variables (x j (t1)) j (t1)), N multiplied values ​​can be generated for each of the N columns in the matrix (J).

[0192] The first summation circuit 145 acquires N multiplied values ​​output from the N fourth multiplication circuits 144-1 to 144-N for each clock. The first summation circuit 145 adds up all of the N multiplied values ​​for each clock. The first summation circuit 145 multiplies the sum for each clock by the N weight values ​​included in the column corresponding to the index (i) in the matrix (J) and the N first variables (x j (t1)) and the sum of products (z´ i (t1)).

[0193] In this way, the matrix calculation circuit 91 according to the fifth embodiment performs a process of matrix addition for one column of the columns in the first matrix (J1) and the columns in the second matrix (J2) for each of the N columns, thereby generating N weight values ​​for each of the N columns. Next, the matrix calculation circuit 91 generates the i-th weight value (J i,j ) and the N first variables (x j (t1)) j Then, the matrix calculation circuit 91 sums up the N multiplication values ​​for each of the N columns to generate N multiplication values ​​(z' i (t1)) is calculated.

[0194] The matrix calculation circuit 91 according to the fifth embodiment calculates a matrix (J) obtained by adding a first matrix (J1) that is a plurality of first weight values ​​and a second matrix (J2) that is a plurality of second weight values, and calculates a matrix (J) obtained by adding N first variables (x j (t1)) can be executed in parallel for N rows.

[0195] Sixth embodiment Next, a market system 10 according to the sixth embodiment will be described. The market system 10 according to the sixth embodiment is the same as that of the fifth embodiment, except for the matrix calculation circuit 91. Below, the matrix calculation circuit 91 according to the sixth embodiment will be described, and detailed descriptions of the same configuration as that of the fifth embodiment will be omitted.

[0196] FIG. 17 is a diagram showing the configuration of a matrix calculation circuit 91 according to the sixth embodiment, together with a first J memory 101, a second J memory 102, and an X memory 81.

[0197] The matrix calculation circuit 91 according to the sixth embodiment includes N fifth multiplication circuits 151-1 to 151-N, N sixth multiplication circuits 152-1 to 152-N, a second summation circuit 153, a third summation circuit 154, and a second output addition circuit 155.

[0198] The N fifth multiplication circuits 151-1 to 151-N correspond one-to-one to the N rows. The i-th fifth multiplication circuit 151-i of the N fifth multiplication circuits 151-1 to 151-N corresponds to the i-th row of the N rows. The i-th fifth multiplication circuit 151-i multiplies the N first weight values ​​{J1 i,1 ,J1 i,2 ,…,J1 i,N} at each clock. In addition, the i-th fifth multiplication circuit 151-i acquires N first variables (x j (t1)), the first variable (x iThe i-th fifth multiplication circuit 151-i obtains the first weight value (J1 i,j ) and the first variable (x i The N fifth multiplier circuits 151-1 to 151-N output the i-th first multiplied value obtained by multiplying the i-th first weight value (J1 i,j ) and the N first variables (x j (t1)) j (t1)), N first multiplication values ​​can be calculated for each of the N columns.

[0199] The N sixth multiplication circuits 152-1 to 152-N correspond one-to-one to the N rows. The i-th sixth multiplication circuit 152-i of the N sixth multiplication circuits 152-1 to 152-N corresponds to the i-th row of the N rows. The i-th sixth multiplication circuit 152-i multiplies the N second weight values ​​{J2 i,1 ,J2 i,2 ,…,J2 i,N} at each clock. The i-th sixth multiplication circuit 152-i also acquires N first variables (x j (t1)), the first variable (x i The i-th sixth multiplier circuit 152-i obtains the second weight value (J2 i,j ) and the first variable (x i The N sixth multiplier circuits 152-1 to 152-N output the i-th second multiplied value obtained by multiplying the i-th second weight value (J2 i,j ) and the N first variables (x j (t1)) j(t1)), N second multiplication values ​​can be calculated for each of the N columns.

[0200] The second summation circuit 153 acquires N first multiplied values ​​output from the N fifth multiplication circuits 151-1 to 151-N for each clock. The second summation circuit 153 adds up all of the N first multiplied values ​​for each clock. The second summation circuit 153 multiplies the sum for each clock by the N first weight values ​​included in the column corresponding to the index (i) in the first matrix (J1) and the N first variables (x j (t1)) is output as a first product-sum operation value obtained by product-sum operation.

[0201] The third summation circuit 154 acquires N second multiplied values ​​output from the N sixth multiplication circuits 152-1 to 152-N for each clock. The third summation circuit 154 adds up all of the N second multiplied values ​​for each clock. The third summation circuit 154 sums up the sum for each clock with the N second weighting values ​​included in the column corresponding to the index (i) in the second matrix (J2) and the N first variables (x j (t1)) is output as a second multiply-and-accumulate value obtained by multiplying and accumulating the first multiply-and-accumulate value.

[0202] The second output adder circuit 155 obtains the first product-sum operation value from the second summing circuit 153 and obtains the second product-sum operation value from the third summing circuit 154 for each clock. The second output adder circuit 155 adds the first product-sum operation value and the second product-sum operation value for each clock. Then, the second output adder circuit 155 multiplies the sum by the N weight values ​​included in the row corresponding to the index (i) in the matrix (J) and the N first variables (x j (t1)) and the sum of products (z´ i (t1)).

[0203] In this way, the matrix calculation circuit 91 according to the sixth embodiment calculates, for each of the N columns, the i-th first weight value (J1 i,j ) and the N first variables (x j(t1)) j The matrix calculation circuit 91 multiplies the second weight value (J2 (t1)) among the N second weight values ​​included in the second matrix (J2) for each of the N columns to calculate N first multiplication values. i,j ) and the i-th first variable (x j (t1)) to calculate N second multiplied values. Next, the matrix operation circuit 91 calculates a first product-sum operation value by adding together all of the N first multiplied values ​​for each of the N columns. Furthermore, the matrix operation circuit 91 calculates a second product-sum operation value by adding together all of the N second multiplied values ​​for each of the N columns. Then, the matrix operation circuit 91 adds together the first product-sum operation value and the second product-sum operation value for each of the N columns to calculate the N product-sum operation values ​​(z´ i (t1)) is calculated.

[0204] The matrix calculation circuit 91 according to the sixth embodiment calculates a matrix (J) obtained by adding a first matrix (J1) that is a plurality of first weight values ​​and a second matrix (J2) that is a plurality of second weight values, and calculates a matrix (J) obtained by adding N first variables (x j (t1)) can be executed in parallel for N rows.

[0205] Seventh embodiment Next, a market system 10 according to the seventh embodiment will be described. The market system 10 according to the seventh embodiment is the same as that of the third embodiment, except for the matrix calculation circuit 91, the first J memory 101, and the second J memory 102. Below, the matrix calculation circuit 91 according to the seventh embodiment will be described, and detailed descriptions of the same configuration as that of the third embodiment will be omitted.

[0206] FIG. 18 is a diagram showing the configuration of a matrix calculation circuit 91 according to the seventh embodiment, together with a first J memory 101, a second J memory 102, and an X memory 81.

[0207] The first J memory 101 according to the seventh embodiment includes N first column memories 161-1 to 161-N. The i-th first column memory 161-i among the N first column memories 161-1 to 161-N stores N first weight values ​​{J1 1,i ,J1 2,i ,…,J1 N,i Each of the N first column memories 161-1 to 161-N stores N first weight values, one at a time, for each clock, starting with the first weight value (J1 1,i ), the first weight value (J1 N,i ) is output.

[0208] The second J memory 102 according to the seventh embodiment includes N second column memories 162-1 to 162-N. The i-th second column memory 162-i of the N second column memories 162-1 to 162-N stores N second weight values ​​{J2 1,i ,J2 2,i ,…,J2 N,i Each of the N second column memories 162-1 to 162-N stores N second weight values, one at a time, for each clock, starting with the second weight value (J2 1,i ), the second weight value (J2 N,i ) is output.

[0209] The matrix calculation circuit 91 according to the seventh embodiment includes N third weighting addition circuits 163-1 to 163-N, N seventh multiplication circuits 164-1 to 164-N, and N fourth accumulation and addition circuits 165-1 to 165-N.

[0210] The N third weighting addition circuits 163-1 to 163-N correspond one-to-one to the N columns. Among the N third weighting addition circuits 163-1 to 163-N, the i-th third weighting addition circuit 163-i corresponds to the i-th column of the N columns. The i-th third weighting addition circuit 163-i calculates the N first weight values ​​{J1 1,i ,J1 2,i ,…,J1 N,i} stored in the i-th second column memory 162-i among the N second column memories 162-1 to 162-N. 1,i ,J2 2,i ,…,J2 N,i The i-th third weighting addition circuit 163-i acquires the first weighting value (J1 j,i ) and the second weight value (J2 j,i ) and the weighted value (J j,i ). Such N third weighting addition circuits 163-1 to 163-N can generate N weighting values ​​for each of the N rows by performing a process of adding a row in the first matrix (J1) and a row in the second matrix (J2) for one row for each of the N rows.

[0211] The N seventh multiplier circuits 164-1 to 164-N correspond one-to-one to the N columns. The i-th seventh multiplier circuit 164-i of the N seventh multiplier circuits 164-1 to 164-N corresponds to the i-th column of the N columns. The i-th seventh multiplier circuit 164-i receives the weight value (J j,i In addition, the i-th seventh multiplication circuit 164-i acquires the first variable (x j The first variable (x (t1)) at the time immediately before it is output from the X memory 81 is obtained. j The i-th seventh multiplier circuit 164-i updates the weight value (J j,i ) and the first variable (x i The N seventh multiplier circuits 164-1 to 164-N multiply the i-th weight value (J j,i ) and the N first variables (x j (t1))j (t1)), N multiplied values ​​can be generated for each of the N rows.

[0212] Each of the N fourth cumulative addition circuits 165-1 to 165-N has the same configuration as the first cumulative addition circuit 116 according to the third embodiment. The N fourth cumulative addition circuits 165-1 to 165-N correspond one-to-one to the N columns. The i-th fourth cumulative addition circuit 165-i of the N fourth cumulative addition circuits 165-1 to 165-N corresponds to the i-th column of the N columns. The i-th fourth cumulative addition circuit 165-i calculates a product-sum calculation value by cumulatively adding the multiplied value output from the i-th seventh multiplication circuit 164-i for each clock. Each of the N fourth cumulative addition circuits 165-1 to 165-N resets the product-sum calculation value to 0 for each N clock. Each of the N fourth cumulative addition circuits 165-1 to 165-N outputs the product-sum calculation value in the cycle immediately before resetting the product-sum calculation value to 0. As a result, the N fourth cumulative addition circuits 165-1 to 165-N calculate a product-sum operation value obtained by cumulatively adding the N multiplied values ​​for N clocks for each of the N columns, and convert the product-sum operation value into the N weight values ​​included in the column corresponding to the index (i) in the matrix (J) and the N first variables (x j (t1)) and the sum of products (z´ i (t1)).

[0213] In this way, the matrix calculation circuit 91 according to the seventh embodiment performs a process of performing matrix addition for one row between a row in the first matrix (J1) and a row in the second matrix (J2) for each of the N rows, thereby generating N weight values ​​for each of the N rows. Next, the matrix calculation circuit 91 generates the i-th weight value (J i,j ) and the N first variables (x j (t1)) j Then, the matrix calculation circuit 91 accumulates the N multiplication values ​​for each of the N columns to generate N product sum calculation values ​​(z'i (t1)) is calculated.

[0214] The matrix calculation circuit 91 according to the seventh embodiment calculates a matrix (J) obtained by adding a first matrix (J1) that is a plurality of first weight values ​​and a second matrix (J2) that is a plurality of second weight values, and N first variables (x j (t1)) can be executed in parallel for N columns.

[0215] Eighth embodiment Next, a market system 10 according to the eighth embodiment will be described. The market system 10 according to the eighth embodiment is the same as that of the seventh embodiment, except for the matrix calculation circuit 91. Below, the matrix calculation circuit 91 according to the eighth embodiment will be described, and detailed descriptions of the same configuration as that of the seventh embodiment will be omitted.

[0216] FIG. 19 is a diagram showing the configuration of a matrix calculation circuit 91 according to the eighth embodiment, together with a first J memory 101, a second J memory 102, and an X memory 81.

[0217] The matrix calculation circuit 91 according to the eighth embodiment includes N eighth multiplication circuits 171-1 to 171-N, N ninth multiplication circuits 172-1 to 172-N, N fifth cumulative addition circuits 173-1 to 173-N, N sixth cumulative addition circuits 174-1 to 174-N, and N third output addition circuits 175-1 to 175-N.

[0218] The N eighth multiplication circuits 171-1 to 171-N correspond one-to-one to the N columns. The i-th eighth multiplication circuit 171-i of the N eighth multiplication circuits 171-1 to 171-N corresponds to the i-th column of the N columns. The i-th eighth multiplication circuit 171-i calculates the N first weight values ​​{J1 1,i ,J1 2,i ,…,J1 N,i} at each clock. In addition, the i-th eighth multiplication circuit 171-i acquires the first variable (xj The first variable (x (t1)) at the time immediately before it is output from the X memory 81 is obtained. j The i-th eighth multiplier circuit 171-i updates the first weight value (J1 j,i ) and the first variable (x i The N eighth multiplier circuits 171-1 to 171-N output first multiplied values ​​obtained by multiplying the i-th first weight value (J1 j,i ) and the N first variables (x j (t1)) j (t1)), N first multiplication values ​​can be calculated.

[0219] The N ninth multiplication circuits 172-1 to 172-N correspond one-to-one to the N columns. The i-th ninth multiplication circuit 172-i of the N ninth multiplication circuits 172-1 to 172-N corresponds to the i-th column of the N columns. The i-th ninth multiplication circuit 172-i calculates N second weight values ​​{J2 1,i ,J2 2,i ,…,J2 N,i} at each clock. In addition, the i-th ninth multiplication circuit 172-i acquires the first variable (x j The i-th ninth multiplication circuit 172-i obtains the second weight value (J2 j,i ) and the first variable (x i The N ninth multiplier circuits 172-1 to 172-N output second multiplication values ​​obtained by multiplying the i-th second weight value (J2 j,i ) and the N first variables (x j (t1)) j(t1)), N second multiplied values ​​can be calculated.

[0220] Each of the N fifth cumulative addition circuits 173-1 to 173-N has the same configuration as the first cumulative addition circuit 116 according to the third embodiment. The N fifth cumulative addition circuits 173-1 to 173-N correspond one-to-one to the N columns. The i-th fifth cumulative addition circuit 173-i of the N fifth cumulative addition circuits 173-1 to 173-N corresponds to the i-th column of the N columns. The i-th fifth cumulative addition circuit 173-i calculates a first product-sum calculation value by cumulatively adding the first multiplied value output from the i-th eighth multiplication circuit 171-i for each clock. Each of the N fifth cumulative addition circuits 173-1 to 173-N resets the first product-sum calculation value to 0 for each N clock. Each of the N fifth cumulative addition circuits 173-1 to 173-N outputs the first product-sum calculation value in the cycle immediately before resetting the first product-sum calculation value to 0. Such N fifth cumulative addition circuits 173-1 to 173-N can calculate a first product-sum operation value for each of the N columns by cumulatively adding the N first multiplication values ​​for N clocks for each of the N columns.

[0221] Each of the N sixth cumulative addition circuits 174-1 to 174-N has the same configuration as the first cumulative addition circuit 116 according to the third embodiment. The N sixth cumulative addition circuits 174-1 to 174-N correspond one-to-one to the N columns. The i-th sixth cumulative addition circuit 174-i of the N sixth cumulative addition circuits 174-1 to 174-N corresponds to the i-th column of the N columns. The i-th sixth cumulative addition circuit 174-i calculates a second product-sum calculation value by cumulatively adding the second multiplied value output from the i-th ninth multiplication circuit 172-i for each clock. Each of the N sixth cumulative addition circuits 174-1 to 174-N resets the second product-sum calculation value to 0 for each N clock. Each of the N sixth cumulative addition circuits 174-1 to 174-N outputs the second product-sum calculation value in the cycle immediately before resetting the second product-sum calculation value to 0. Such N sixth cumulative addition circuits 174-1 to 174-N can calculate a second product-sum operation value for each of the N columns by cumulatively adding the N second multiplication values ​​for N clocks for each of the N columns.

[0222] The N third output adder circuits 175-1 to 175-N correspond one-to-one to the N columns. Among the N third output adder circuits 175-1 to 175-N, the i-th third output adder circuit 175-i corresponds to the i-th column of the N columns. The i-th third output adder circuit 175-i adds the first cumulative sum output from the i-th fifth cumulative adder circuit 173-i and the second cumulative sum from the i-th sixth cumulative adder circuit 174-i every N clocks. As a result, the N third output adder circuits 175-1 to 175-N calculates a value obtained by adding the first cumulative sum and the second cumulative sum for each of the N columns, based on the N weight values ​​included in the column corresponding to the index (i) in the matrix (J) and the N first variables (x j (t1)) and the sum of products (z´ i (t1)).

[0223] In this way, the matrix calculation circuit 91 according to the eighth embodiment calculates, for each of the N rows, the i-th first weight value (J1 j,i) and the N first variables (x j (t1)) j The matrix calculation circuit 91 multiplies the i-th second weight value (J2 (t1)) among the N second weight values ​​included in the second matrix (J2) for each of the N rows to calculate N first multiplication values. j,i ) and the i-th first variable (x j (t1)) to calculate N second multiplied values. Next, the matrix operation circuit 91 accumulates the N first multiplied values ​​for each of the N columns to calculate a first accumulated value for each of the N columns. Also, the matrix operation circuit 91 accumulates the N second multiplied values ​​for each of the N columns to calculate a second accumulated value for each of the N columns. Then, the matrix operation circuit 91 adds the first accumulated value and the second accumulated value for each of the N columns to calculate N product-sum operation values ​​(z´ i (t1)) is calculated.

[0224] The matrix calculation circuit 91 according to the eighth embodiment calculates a matrix (J) obtained by adding a first matrix (J1) that is a plurality of first weight values ​​and a second matrix (J2) that is a plurality of second weight values, and calculates a matrix (J) obtained by adding N first variables (x j (t1)) can be executed in parallel for N columns.

[0225] Ninth embodiment Next, a control system 210 according to a ninth embodiment will be described.

[0226] In the first to eighth embodiments, an example has been described in which the information processing device 20 is applied to the market system 10. The information processing device 20 is not limited to the market system 10, and can be applied to other systems as long as the systems execute processing using a combinatorial optimization problem on data that changes over time. For example, the information processing device 20 can be applied to a control system 210 that controls the movement of a moving object.

[0227] 20 is a diagram showing an example of the configuration of a control system 210 according to the 9th embodiment. The control system 210 controls a moving object that moves autonomously, such as a self-driving car, a drone, or a robot.

[0228] The control system 210 includes an object detection device 212 , an information processing device 20 , and a control device 214 .

[0229] The object detection device 212 acquires image data from, for example, a camera that captures an image of the surroundings of the moving object to be controlled. The object detection device 212 may acquire sensor data from other sensor devices in addition to image data. The object detection device 212 detects coordinate data representing three-dimensional coordinates for one or more objects around the moving object based on the acquired image data, sensor data, etc. Furthermore, the object detection device 212 may also detect the three-dimensional coordinates of the moving object itself to be controlled.

[0230] The object detection device 212 irregularly and repeatedly outputs data including identification information for identifying one of one or more objects, and coordinate data (input information) representing the coordinates of the object identified by the identification information, to the information processing device 20. Note that the input information may include, in addition to the coordinate data, other related information such as the moving speed, acceleration, moving direction, and type of the object identified by the identification information.

[0231] The control device 214 acquires output data including output information indicating a predetermined operation to be performed on the mobile object in order to control the mobile object from the information processing device 20. The control device 214 controls the mobile object based on the acquired output data.

[0232] The output information may also indicate that a predetermined operation is to be performed on any one of one or more objects around the moving body. For example, the output information may include information indicating that information indicating movement control, a predetermined instruction, a warning, or the like is to be given to any one of one or more objects around the moving body. In this case, the output data includes identification information for identifying any one of the one or more objects, and the output information. Furthermore, when such output data is received, the control device 214 executes a predetermined operation on the object identified by the identification information included in the output data.

[0233] The information processing device 20 has the same configuration as those described in the first to ninth embodiments.

[0234] The information processing device 20 generates a combinatorial optimization problem based on the first data and second data irregularly provided by the object detection device 212, and causes the solver device 40 to solve the combinatorial optimization problem. Note that the information processing device 20 may acquire the second data from another sensor device or data processing device instead of the object detection device 212. Then, the information processing device 20 acquires a solution to the combinatorial optimization problem from the solver device 40, generates output data based on the solution in response to acquiring the solution, and outputs the generated output data to the control device 214, which is an example of a first device.

[0235] When generating combinatorial optimization problems according to a plurality of types of situations, the information processing device 20 according to this embodiment can efficiently update the combinatorial optimization problems and cause the solver device 40 to solve them.

[0236] (Hardware configuration) Fig. 21 is a diagram showing an example of a hardware configuration of the information processing device 20. A partial configuration in the information processing device 20 not including the solver device 40 is realized by, for example, a computer having a hardware configuration as shown in Fig. 21. The information processing device 20 includes a CPU (Central Processing Unit) 301, a RAM (Random Access Memory) 302, a ROM (Read Only Memory) 303, a storage device 304, and a communication interface device 305. These components are connected by a bus.

[0237] The CPU 301 is one or more processors that executes arithmetic processing, control processing, etc. according to a program. The CPU 301 uses a predetermined area of ​​the RAM 302 as a working area and executes various processes in cooperation with programs stored in the ROM 303, the storage device 304, etc.

[0238] The RAM 302 is a memory such as a Synchronous Dynamic Random Access Memory (SDRAM), and functions as a work area for the CPU 301. The ROM 303 is a memory that stores programs and various information in a non-rewritable manner.

[0239] The storage device 304 is a device that writes and reads data to a semiconductor storage medium such as a flash memory, or a magnetically or optically recordable storage medium, etc. The storage device 304 writes and reads data to the storage medium in response to control from the CPU 301. The communication interface device 305 communicates with external devices via a network in response to control from the CPU 301.

[0240] A program executed by the computer causes the computer to function as the information processing device 20. This program is deployed on the RAM 302 by the CPU 301 (processor) and executed.

[0241] In addition, the program executed by the computer is provided as a file in a format that can be installed on the computer or in a format that can be executed by the computer, and is recorded on a computer-readable recording medium such as a CD-ROM, a flexible disk, a CD-R, or a DVD (Digital Versatile Disk).

[0242] The program may be stored on a computer connected to a network such as the Internet and provided by being downloaded via the network. The program may be provided or distributed via a network such as the Internet. The program executed by the information processing device 20 may be provided by being pre-installed in the ROM 303 or the like.

[0243] The program for making the computer function as the information processing device 20 has a modular configuration including, for example, a first acquisition module, a second acquisition module, a solver module, a first update module, a second update module, and a process execution module. When this program is executed by the CPU 301, each module is loaded into the RAM 302, and the CPU 301 functions as the first acquisition unit 33, the second acquisition unit 34, the solver device 40, the first update unit 41, the second update unit 42, and the process execution unit 46. When the CPU 301 has multiple processors, these units may be divided and assigned to multiple processors. In addition, this program causes the RAM 302 and the storage device 304 to function as the first input memory 31 and the second input memory 32. Note that these configurations may be partially or entirely configured by hardware.

[0244] The solver device 40 may be realized by one or more reconfigurable semiconductor devices such as a field-programmable gate array (FPGA). The solver device 40 may be realized by one or more CPUs, microprocessors, graphics processing units (GPUs), application specific integrated circuits (ASICs), or electronic circuits including these circuits.

[0245] The solver device 40 may be incorporated in the information processing device 20. For example, the solver device 40 may be incorporated as an accelerator in a part of the information processing device 20. The solver device 40 may also include some of the functions of the information processing device 20, such as a first update unit 41 and a second update unit 42.

[0246] Furthermore, when the information processing device 20 is realized by a reconfigurable semiconductor device such as an FPGA, the circuit information (configuration data) to be written into the reconfigurable semiconductor device to operate the reconfigurable semiconductor device as the information processing device 20 may be stored on a computer connected to a network such as the Internet and provided by being downloaded via the network. Furthermore, the circuit information (configuration data) to be written into the reconfigurable semiconductor device to operate the reconfigurable semiconductor device as the information processing device 20 may be provided by being recorded on a computer-readable recording medium.

[0247] Furthermore, when the information processing device 20 is realized by a semiconductor device such as an ASIC, the circuit information representing the configuration of a circuit described in a hardware description language used in the design and manufacture of the information processing device 20 may be stored on a computer connected to a network such as the Internet and provided by downloading it via the network. Furthermore, the circuit information representing the configuration of a circuit described in a hardware description language used in the design and manufacture of the information processing device 20 may be provided by being recorded on a computer-readable recording medium.

[0248] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims.

[0249] (Additional Note) The above-described embodiments can be summarized as the following technical solutions.

[0250] [Technical proposal 1] An information processing device that executes processing on data, a solver device that stores a plurality of first weight values ​​and a plurality of second weight values, and solves a combinatorial optimization problem that minimizes a cost function including a plurality of weight values ​​obtained by combining the plurality of first weight values ​​and the plurality of second weight values; An information processing circuit; Equipped with The information processing circuit includes: As the data, first data is repeatedly acquired; Repeatedly acquiring second data as the data asynchronously with the timing of acquiring the first data; updating the plurality of first weight values ​​stored in the solver device based on the first data; updating the plurality of second weight values ​​stored in the solver device based on the second data; Information processing device.

[0251] [Technical proposal 2] The information processing circuit includes: In updating the plurality of first weight values, the plurality of first weight values ​​are updated in response to the acquisition of the first data or at a predetermined first cycle; In updating the plurality of second weight values, the plurality of second weight values ​​are updated in response to acquisition of the second data or at a predetermined second cycle. An information processing device according to technical proposal 1.

[0252] [Technical proposal 3] The solver device starts solving the combinatorial optimization problem in response to updating one of the plurality of first weight values ​​and the plurality of second weight values. An information processing device according to technical proposal 1 or 2.

[0253] [Technical proposal 4] The information processing circuit includes: In updating the plurality of first weight values, the plurality of first weight values ​​are not updated during the solution of the solver device; In updating the plurality of second weight values, the plurality of second weight values ​​are not updated during the solution of the solver device. An information processing device described in any one of technical proposals 1 to 3.

[0254] [Technical proposal 5] The information processing circuit further obtains a solution to the combinatorial optimization problem from the solver device, and executes a process based on the solution in response to obtaining the solution. An information processing device described in any one of technical proposals 1 to 4.

[0255] [Technical proposal 6] The information processing circuit, in the processing based on the solution, outputting output data based on the solution; When new first data and / or new second data is acquired during the solution process, output of the output data based on the solution is stopped. An information processing device according to technical proposal 5.

[0256] [Technical proposal 7] The cost function is a quadratic function, each of the plurality of first weight values ​​is a coefficient of a linear term included in the quadratic function; Each of the plurality of second weight values ​​is a coefficient of a quadratic term included in the quadratic function. An information processing device described in any one of technical proposals 1 to 6.

[0257] [Technical proposal 8] the cost function includes N decision variables (N is an integer equal to or greater than 2), and the weight values ​​include a matrix including weight values ​​of N rows by N columns; The cost function is expressed as a quadratic function of the N decision variables. An information processing device described in any one of technical proposals 1 to 6.

[0258] [Technical proposal 9] Each of the N decision variables included in the cost function is a binary discrete variable. An information processing device according to Technical Proposal 8.

[0259] [Technical proposal 10] The combinatorial optimization problem is a QUBO (Quadratic Unconstrained Binary Optimization) problem. An information processing device described in Technical Proposal 9.

[0260] [Technical proposal 11] The solver device solves the QUBO problem by reducing it to an Ising problem that minimizes an Ising model. An information processing device according to technical proposal 10.

[0261] [Technical proposal 12] The solver device solves the Ising problem by a simulated bifurcation algorithm. An information processing device according to technical proposal 11.

[0262] [Technical proposal 13] The cost function is a cubic or higher function of N decision variables (N is an integer equal to or greater than 2); The combinatorial optimization problem is a HUBO (Higher Order Binary Optimization) problem. An information processing device described in Technical Proposal 7.

[0263] [Technical proposal 14] The solver device comprises: a matrix calculation circuit that calculates N second intermediate variables at a first time by matrix multiplying N first intermediate variables at the first time by the matrix; a first circuit that calculates, based on the N second intermediate variables at the first time, N first variables at a second time after the first time and N second variables at the second time; a control circuit that causes the matrix calculation circuit and the first circuit to execute processing from a start time to an end time; an output circuit that generates and outputs the solution based on the N first variables at the end time; Equipped with An i-th spin (i is an integer between 1 and N) among N spins in the Ising model corresponds to an i-th point among N points, an i-th first variable among the N first variables corresponds to the i-th spin; an i-th second variable among the N second variables corresponds to the i-th spin; the i-th first variable represents a position of a point corresponding to the i-th spin; The i-th second variable represents the momentum of a point corresponding to the i-th spin, an i-th first intermediate variable among the N first intermediate variables corresponds to the i-th first variable; the i-th first intermediate variable is the i-th first variable or a value obtained by multiplying the i-th first variable by a preset coefficient, The i-th second intermediate variable among the N second intermediate variables corresponds to the i-th second variable. An information processing device according to technical proposal 12.

[0264] [Technical proposal 15] the plurality of first weight values ​​includes a first matrix including N rows by N columns of first weight values; the plurality of second weight values ​​includes a second matrix including N rows by N columns of second weight values; The matrix is ​​expressed by matrix addition of the first matrix and the second matrix. An information processing device according to Technical Proposal 14.

[0265] [Technical proposal 16] The matrix calculation circuit includes: calculating the matrix by performing matrix addition on the first matrix and the second matrix; Calculating the N number of second intermediate variables at the first time by performing matrix multiplication of the N number of first intermediate variables at the first time by the matrix. An information processing device according to Technical Proposal 15.

[0266] [Technical proposal 17] The matrix calculation circuit includes: performing a matrix multiplication of the N first intermediate variables at the first time by the first matrix to generate N first multiply-accumulate values; performing a matrix multiplication of the N first intermediate variables at the first time by the second matrix to generate N second multiply-accumulate values; The N number of second intermediate variables at the first time are calculated by performing a matrix addition on the N number of first multiply-and-accumulate values ​​and the N number of second multiply-and-accumulate values. An information processing device according to Technical Proposal 15.

[0267] [Technical proposal 18] performing a process of performing a matrix addition of one column of the first matrix and one column of the second matrix to generate N weight values; multiplying an i-th weight value among the N weight values ​​by the i-th first intermediate variable to generate N multiplied values; The N second intermediate variables at the first time are calculated by summing the N multiplied values. An information processing device according to Technical Proposal 15.

[0268] [Technical proposal 19] The matrix calculation circuit includes: multiplying an i-th first weight value among the N first weight values ​​included in the first matrix by the i-th first intermediate variable to calculate N first multiplication values; multiplying an i-th second weight value among the N second weight values ​​included in the second matrix by the i-th first intermediate variable to calculate N second multiplied values; Calculating a first sum-of-products value by adding up all of the N first multiplied values; Calculating a second sum-of-products operation value by adding up all of the N second multiplied values; The N second intermediate variables at the first time are calculated by adding the first product-sum operation value and the second product-sum operation value. An information processing device according to Technical Proposal 15.

[0269] [Technical proposal 20] The matrix calculation circuit includes: performing a process of performing a matrix addition of one row of the first matrix and one row of the second matrix to generate N weight values; multiplying an i-th weight value among the N weight values ​​by the i-th first intermediate variable to generate N multiplied values; The N second intermediate variables at the first time are calculated by accumulating the N multiplied values. An information processing device according to Technical Proposal 15.

[0270] [Technical proposal 21] The matrix calculation circuit includes: multiplying an i-th first weight value among the N first weight values ​​included in the first matrix by the i-th first intermediate variable to calculate N first multiplication values; multiplying an i-th second weight value among the N second weight values ​​included in the second matrix by the i-th first intermediate variable to calculate N second multiplied values; Calculating a first cumulative sum value by accumulating the N first multiplied values; Calculating a second cumulative sum by accumulating the N second multiplied values; The N second intermediate variables at the first time are calculated by adding the first cumulative sum and the second cumulative sum. An information processing device according to Technical Proposal 15.

[0271] [Technical proposal 22] In the acquisition of the first data, a market condition packet is acquired as the first data from a market server device that trades a plurality of targets; the market packet includes a trading price for at least one of the plurality of objects; a plurality of decision variables included in the cost function in the combinatorial optimization problem correspond one-to-one to the plurality of targets; Each of the plurality of decision variables represents whether or not to trade a corresponding one of the plurality of objects. An information processing device described in any one of technical proposals 1 to 21.

[0272] [Technical proposal 23] The first data includes coordinate data representing coordinates of an object. An information processing device described in any one of technical proposals 1 to 21.

[0273] [Technical proposal 24] An information processing method for executing processing on data by an information processing device and a solver device, comprising: the solver device stores a plurality of first weight values ​​and a plurality of second weight values, and solves a combinatorial optimization problem that minimizes a cost function including a plurality of weight values ​​obtained by combining the plurality of first weight values ​​and the plurality of second weight values; The information processing device, As the data, first data is repeatedly acquired; Repeatedly acquiring second data as the data asynchronously with the timing of acquiring the first data; updating the plurality of first weight values ​​stored in the solver device based on the first data; updating the plurality of second weight values ​​stored in the solver device based on the second data; Information processing methods.

[0274] [Technical proposal 25] A program for causing a computer to function as an information processing device that executes processing on data using a solver device, the solver device stores a plurality of first weight values ​​and a plurality of second weight values, and solves a combinatorial optimization problem that minimizes a cost function including a plurality of weight values ​​obtained by combining the plurality of first weight values ​​and the plurality of second weight values; The computer, As the data, first data is repeatedly acquired; Repeatedly acquiring second data as the data asynchronously with the timing of acquiring the first data; updating the plurality of first weight values ​​stored in the solver device based on the first data; updating the plurality of second weight values ​​stored in the solver device based on the second data; Make it work like this program.

[0275] [Technical proposal 26] Circuit information describing a configuration of a circuit, the circuit information being written in a hardware description language, causing the circuit to function as an information processing device that performs processing on data; The information processing device includes: a solver device that stores a plurality of first weight values ​​and a plurality of second weight values, and solves a combinatorial optimization problem that minimizes a cost function including a plurality of weight values ​​obtained by combining the plurality of first weight values ​​and the plurality of second weight values; An information processing circuit; Equipped with The information processing circuit includes: As the data, first data is repeatedly acquired; Repeatedly acquiring second data as the data asynchronously with the timing of acquiring the first data; updating the plurality of first weight values ​​stored in the solver device based on the first data; updating the plurality of second weight values ​​stored in the solver device based on the second data; Circuit information.

[0276] [Technical proposal 27] Circuit information to be written into a reconfigurable semiconductor device in order to operate the reconfigurable semiconductor device, causing the reconfigurable semiconductor device to function as an information processing device that executes processing on data; The information processing device includes: a solver device that stores a plurality of first weight values ​​and a plurality of second weight values, and solves a combinatorial optimization problem that minimizes a cost function including a plurality of weight values ​​obtained by combining the plurality of first weight values ​​and the plurality of second weight values; An information processing circuit; Equipped with The information processing circuit includes: As the data, first data is repeatedly acquired; Repeatedly acquiring second data as the data asynchronously with the timing of acquiring the first data; updating the plurality of first weight values ​​stored in the solver device based on the first data; updating the plurality of second weight values ​​stored in the solver device based on the second data; Circuit information. [Explanation of symbols]

[0277] 10. Market System 12 Market Server Equipment 14 Client Device 16 Receiving section 17 Matching section 18 Distribution Department 20 Information processing device 31 First input memory 32 Second input memory 33 First acquisition part 34 Second acquisition part 40 Solver Device 41 1st update part 42 2nd update part 46 Processing Execution Unit 51 First weight memory 52 Second Weight Memory 71 Arithmetic circuit 72 Input circuit 73 Output circuit 74 Setting circuit 81X Memory 82 Y Memory 83 Action calculation circuit 84 Time-evolving circuits 85 Control circuit 91 Matrix calculation circuit 93 First Adding Circuit 94 Alpha Function Circuit 96 Second Adding Circuit 113 First weighting circuit 115 First Multiplier Circuit 116 First cumulative addition circuit 121 Adder 122 Reset Selector 123 Latch Circuit 131 Second Multiplier Circuit 132 Third Multiplier Circuit 133 Second Accumulation Addition Circuit 134 Third Accumulation Addition Circuit 135 First output summing circuit 143 Second weighting circuit 144 4th multiplier circuit 145 First Total Circuit 151 5th multiplier circuit 152 6th Multiplier Circuit 153 Second Totalizer Circuit 154 3rd Total Circuit 155 Second output adder circuit 161 1st row memory 162 2nd row memory 163 3rd weighting circuit 164 7th Multiplier Circuit 165 4th accumulating circuit 171 8th Multiplier Circuit 172 9th Multiplication Circuit 173 5th cumulative addition circuit 174 6th cumulative addition circuit 175 3rd output adder circuit

Claims

1. An information processing device that executes processing on data, a solver device that stores a plurality of first weight values ​​and a plurality of second weight values ​​and solves a combinatorial optimization problem that minimizes a cost function including a plurality of weight values ​​obtained by combining the plurality of first weight values ​​and the plurality of second weight values; An information processing circuit; Equipped with The information processing circuit includes: As the data, first data is repeatedly acquired; Repeatedly acquiring second data as the data asynchronously with the timing of acquiring the first data; updating the plurality of first weight values ​​stored in the solver device based on the first data; updating the plurality of second weight values ​​stored in the solver device based on the second data; Information processing device.

2. The information processing circuit includes: In updating the plurality of first weight values, the plurality of first weight values ​​are updated in response to the acquisition of the first data or at a predetermined first cycle; In updating the plurality of second weight values, the plurality of second weight values ​​are updated in response to acquisition of the second data or at a predetermined second cycle. The information processing device according to claim 1 .

3. The solver device starts solving the combinatorial optimization problem in response to updating one of the plurality of first weight values ​​and the plurality of second weight values. The information processing device according to claim 1 .

4. The information processing circuit includes: In updating the plurality of first weight values, the plurality of first weight values ​​are not updated during the solution of the solver device; In updating the plurality of second weight values, the plurality of second weight values ​​are not updated during the solution of the solver device. The information processing device according to claim 1 .

5. The information processing circuit further obtains a solution to the combinatorial optimization problem from the solver device, and executes a process based on the solution in response to obtaining the solution. The information processing device according to claim 1 .

6. The information processing circuit, in the processing based on the solution, outputting output data based on the solution; When new first data and / or new second data is acquired during the solution process, output of the output data based on the solution is stopped. The information processing device according to claim 5 .

7. The cost function is a quadratic function, each of the plurality of first weight values ​​is a coefficient of a linear term included in the quadratic function; Each of the plurality of second weight values ​​is a coefficient of a quadratic term included in the quadratic function. The information processing device according to claim 1 .

8. The cost function includes N decision variables (N is an integer equal to or greater than 2), and the weight values ​​include a matrix including weight values ​​of N rows by N columns, The cost function is expressed as a quadratic function of the N decision variables. The information processing device according to claim 1 .

9. Each of the N decision variables included in the cost function is a binary discrete variable. The information processing device according to claim 8.

10. The combinatorial optimization problem is a quadratic unconstrained binary optimization problem (QUBO). The information processing device according to claim 9.

11. The solver device solves the QUBO problem by reducing it to an Ising problem that minimizes an Ising model. The information processing device according to claim 10.

12. The solver device solves the Ising problem by a simulated bifurcation algorithm. The information processing device according to claim 11.

13. The cost function is a cubic or higher function of N decision variables (N is an integer equal to or greater than 2); The combinatorial optimization problem is a HUBO (Higher Order Binary Optimization) problem. The information processing device according to claim 7.

14. The solver device comprises: a matrix calculation circuit that calculates N second intermediate variables at a first time by matrix multiplying N first intermediate variables at the first time by the matrix; a first circuit that calculates, based on the N second intermediate variables at the first time, N first variables at a second time after the first time and N second variables at the second time; a control circuit that causes the matrix calculation circuit and the first circuit to execute processing from a start time to an end time; an output circuit that generates and outputs the solution based on the N first variables at the end time; Equipped with An i-th spin (i is an integer between 1 and N) among N spins in the Ising model corresponds to an i-th point among N points, an i-th first variable among the N first variables corresponds to the i-th spin; an i-th second variable among the N second variables corresponds to the i-th spin; The i-th first variable represents a position of a point corresponding to the i-th spin, The i-th second variable represents the momentum of a point corresponding to the i-th spin, an i-th first intermediate variable among the N first intermediate variables corresponds to the i-th first variable; the i-th first intermediate variable is the i-th first variable or a value obtained by multiplying the i-th first variable by a preset coefficient, The i-th second intermediate variable among the N second intermediate variables corresponds to the i-th second variable. The information processing device according to claim 12.

15. the plurality of first weight values ​​includes a first matrix including N rows by N columns of first weight values; the plurality of second weight values ​​includes a second matrix including N rows by N columns of second weight values; The matrix is ​​expressed by matrix addition of the first matrix and the second matrix. The information processing device according to claim 14.

16. The matrix calculation circuit includes: calculating the matrix by performing matrix addition on the first matrix and the second matrix; Calculating the N second intermediate variables at the first time by performing matrix multiplication of the N first intermediate variables at the first time by the matrix. The information processing device according to claim 15.

17. The matrix calculation circuit includes: performing a matrix multiplication of the N first intermediate variables at the first time by the first matrix to generate N first multiply-add values; performing a matrix multiplication of the N first intermediate variables at the first time by the second matrix to generate N second multiply-accumulate values; The N number of second intermediate variables at the first time are calculated by performing a matrix addition on the N number of first multiply-add values ​​and the N number of second multiply-add values. The information processing device according to claim 15.

18. performing a process of performing a matrix addition of one column of the first matrix and one column of the second matrix to generate N weight values; multiplying an i-th weight value among the N weight values ​​by the i-th first intermediate variable to generate N multiplied values; The N second intermediate variables at the first time are calculated by summing the N multiplied values. The information processing device according to claim 15.

19. The matrix calculation circuit includes: multiplying an i-th first weight value among the N first weight values ​​included in the first matrix by the i-th first intermediate variable to calculate N first multiplication values; multiplying an i-th second weight value among the N second weight values ​​included in the second matrix by the i-th first intermediate variable to calculate N second multiplied values; calculating a first sum-of-products value by adding up all of the N first multiplied values; calculating a second sum-of-products operation value by adding up all of the N second multiplied values; The N second intermediate variables at the first time are calculated by adding the first product-sum operation value and the second product-sum operation value. The information processing device according to claim 15.

20. The matrix calculation circuit includes: performing a process of performing a matrix addition of one row of the first matrix and one row of the second matrix to generate N weight values; multiplying an i-th weight value among the N weight values ​​by the i-th first intermediate variable to generate N multiplied values; The N second intermediate variables at the first time are calculated by accumulating the N multiplied values. The information processing device according to claim 15.

21. The matrix calculation circuit includes: multiplying an i-th first weight value among the N first weight values ​​included in the first matrix by the i-th first intermediate variable to calculate N first multiplication values; multiplying an i-th second weight value among the N second weight values ​​included in the second matrix by the i-th first intermediate variable to calculate N second multiplied values; Calculating a first cumulative sum by cumulatively adding the N first multiplied values; calculating a second cumulative sum by accumulating the N second multiplied values; The N second intermediate variables at the first time are calculated by adding the first cumulative sum and the second cumulative sum. The information processing device according to claim 15.

22. In the acquisition of the first data, a market condition packet is acquired as the first data from a market server device that trades a plurality of targets; the market packet includes a trading price for at least one of the plurality of objects; a plurality of decision variables included in the cost function in the combinatorial optimization problem correspond one-to-one to the plurality of targets; Each of the plurality of decision variables represents whether or not to trade a corresponding one of the plurality of objects.

22. An information processing device according to any one of claims 1 to 21.

23. The first data includes coordinate data representing coordinates of an object.

22. An information processing device according to any one of claims 1 to 21.

24. An information processing method for executing processing on data by an information processing device and a solver device, comprising: the solver device stores a plurality of first weight values ​​and a plurality of second weight values, and solves a combinatorial optimization problem that minimizes a cost function including a plurality of weight values ​​obtained by combining the plurality of first weight values ​​and the plurality of second weight values; The information processing device, As the data, first data is repeatedly acquired; Repeatedly acquiring second data as the data asynchronously with the timing of acquiring the first data; updating the plurality of first weight values ​​stored in the solver device based on the first data; updating the plurality of second weight values ​​stored in the solver device based on the second data; Information processing methods.

25. A program for causing a computer to function as an information processing device that executes processing on data using a solver device, the solver device stores a plurality of first weight values ​​and a plurality of second weight values, and solves a combinatorial optimization problem that minimizes a cost function including a plurality of weight values ​​obtained by combining the plurality of first weight values ​​and the plurality of second weight values; The computer, As the data, first data is repeatedly acquired; Repeatedly acquiring second data as the data asynchronously with the timing of acquiring the first data; updating the plurality of first weight values ​​stored in the solver device based on the first data; updating the plurality of second weight values ​​stored in the solver device based on the second data; Make it work like this program.

26. Circuit information describing a configuration of a circuit, the circuit information being written in a hardware description language, causing the circuitry to function as an information processing device that performs processing on data; The information processing device includes: a solver device that stores a plurality of first weight values ​​and a plurality of second weight values ​​and solves a combinatorial optimization problem that minimizes a cost function including a plurality of weight values ​​obtained by combining the plurality of first weight values ​​and the plurality of second weight values; An information processing circuit; Equipped with The information processing circuit includes: As the data, first data is repeatedly acquired; Repeatedly acquiring second data as the data asynchronously with the timing of acquiring the first data; updating the plurality of first weight values ​​stored in the solver device based on the first data; updating the plurality of second weight values ​​stored in the solver device based on the second data; Circuit information.

27. Circuit information to be written into a reconfigurable semiconductor device in order to operate the reconfigurable semiconductor device, causing the reconfigurable semiconductor device to function as an information processing device that executes processing on data; The information processing device includes: a solver device that stores a plurality of first weight values ​​and a plurality of second weight values ​​and solves a combinatorial optimization problem that minimizes a cost function including a plurality of weight values ​​obtained by combining the plurality of first weight values ​​and the plurality of second weight values; An information processing circuit; Equipped with The information processing circuit includes: As the data, first data is repeatedly acquired; Repeatedly acquiring second data as the data asynchronously with the timing of acquiring the first data; updating the plurality of first weight values ​​stored in the solver device based on the first data; updating the plurality of second weight values ​​stored in the solver device based on the second data; Circuit information.

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