Display device and manufacturing method for display device

Abstract

To suppress the decrease in display quality.SOLUTION: In one embodiment, a display device includes: a substrate; an insulating layer that is disposed over the substrate; a first lower electrode and a second lower electrode that are disposed on the insulating layer and are apart from each other; a first common layer that is disposed on the first lower electrode and the second lower electrode; a first light-emitting layer that is disposed on the first common layer and overlaps with the first lower electrode in a plan view; a second light-emitting layer that is disposed on the first common layer, overlaps with the second lower electrode in the plan view, is apart from the first light-emitting layer, and is formed of a material different from that of the first light-emitting layer; a barrier layer that is disposed on the first common layer between the first light-emitting layer and the second light-emitting layer and surrounds the first light-emitting layer and the second light-emitting layer in the plan view; a second common layer that is disposed on the first light-emitting layer, the second light-emitting layer, and the barrier layer; and an upper electrode that is disposed on the second common layer.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a display device and a method for manufacturing a display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) as display elements have been proposed. These display elements include a common layer formed across multiple pixels. The common layer includes a functional layer such as a hole transport layer.

[0003] However, in a display device having adjacent display elements that emit light of different colors, carriers (e.g., holes) may flow from the emitting display element to the adjacent display element through a common layer, which may cause the adjacent display element to emit light unintentionally, resulting in a deterioration in the display quality of the display device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-12366 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device capable of suppressing deterioration in display quality and a method for manufacturing the display device. [Means for solving the problem]

[0006] According to one embodiment, the display device comprises: the first light-emitting layer being disposed on the first common layer and overlapping the first lower electrode in a planar view; a second light-emitting layer being disposed on the first common layer and overlapping the second lower electrode in a planar view, the second light-emitting layer being separated from the first light-emitting layer and being formed of a material different from the first light-emitting layer; a barrier layer being disposed on the first common layer between the first light-emitting layer and the second light-emitting layer and surrounding the first light-emitting layer and the second light-emitting layer in a planar view; a second common layer being disposed on the first light-emitting layer, the second light-emitting layer, and the barrier layer; and an upper electrode being disposed on the second common layer.

[0007] According to one embodiment, a method for manufacturing a display device includes the steps of: forming an insulating layer above a substrate; forming a first lower electrode and a second lower electrode spaced apart from each other on the insulating layer; forming a rib on the insulating layer forming a first opening overlapping the first lower electrode in a planar view and a second opening overlapping the second lower electrode; forming a first common layer on the first lower electrode, the second lower electrode, and the rib; forming a first light-emitting layer on the first common layer overlapping the first lower electrode in a planar view; forming a second light-emitting layer on the first common layer overlapping the second lower electrode in a planar view, away from the first light-emitting layer, and made of a material different from the first light-emitting layer; forming a barrier layer located on the first common layer between the first light-emitting layer and the second light-emitting layer, and surrounding each of the first light-emitting layer and the second light-emitting layer in a planar view; forming a second common layer on the first light-emitting layer, the second light-emitting layer, and the barrier layer; and forming an upper electrode on the second common layer. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic plan view showing a configuration example of a display device. [Diagram 2] FIG. 2 is a diagram showing an example of a layout of sub-pixels. [Diagram 3]FIG. 3 is a schematic cross-sectional view of the display device taken along the line AA in FIG. [Figure 4] FIG. 4 is a diagram showing an example of the configuration of a display element. [Diagram 5] FIG. 5 is a schematic enlarged view of part B in FIG. [Figure 6] FIG. 6 is a diagram for explaining a manufacturing method of the display device. [Figure 7] FIG. 7 is a diagram for explaining a manufacturing method of the display device. [Figure 8] FIG. 8 is a diagram for explaining a manufacturing method of the display device. [Figure 9] FIG. 9 is a diagram for explaining a manufacturing method of the display device. [Figure 10] FIG. 10 is a diagram for explaining a manufacturing method of the display device. [Figure 11] FIG. 11 is a diagram for explaining a manufacturing method of the display device. [Figure 12] FIG. 12 is a diagram for explaining a manufacturing method of the display device. [Figure 13] FIG. 13 is a diagram for explaining a manufacturing method of the display device. [Figure 14] FIG. 14 is a diagram for explaining a manufacturing method of the display device. [Figure 15] FIG. 15 is a diagram for explaining a manufacturing method of the display device. [Figure 16] FIG. 16 is a diagram for explaining a manufacturing method of the display device. [Figure 17] FIG. 17 is a schematic cross-sectional view showing another configuration example of the display device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and those who are skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed explanations may be omitted as appropriate.

[0010] In addition, in the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. Viewing various elements parallel to the third direction Z is called a planar view.

[0011] 1 is a schematic plan view showing a configuration example of a display device DSP. The display device DSP is an organic electroluminescence display device having, for example, an organic light-emitting diode (OLED) as a display element, and can be mounted on televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and the like. The display device DSP includes a substrate 10. The substrate 10 is formed of an insulating material such as glass or plastic.

[0012] The display device DSP has a display area DA for displaying an image, and a peripheral area SA surrounding the display area DA. The display area DA has a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y. The pixels PX have a plurality of sub-pixels SP. In one example, the pixel PX has a red sub-pixel SP1, a blue sub-pixel SP2, and a green sub-pixel SP3. Note that the pixel PX may have four or more sub-pixels including sub-pixels of other colors such as white in addition to the above three sub-pixels.

[0013] 1, the subpixel SP includes a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements constituted by, for example, thin film transistors.

[0014] In the pixel switch 2, the gate electrode is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element 20. Note that the configuration of the pixel circuit 1 is not limited to the example shown in the figure.

[0015] The display element 20 is an organic light-emitting diode (OLED) serving as a light-emitting element. For example, the subpixel SP1 includes a display element 20 that emits light corresponding to a red wavelength, the subpixel SP2 includes a display element 20 that emits light corresponding to a blue wavelength, and the subpixel SP3 includes a display element 20 that emits light corresponding to a green wavelength. The configuration of the display element 20 will be described later.

[0016] Fig. 2 is a diagram showing an example of the layout of subpixels SP1, SP2, and SP3. In the example of Fig. 2, subpixels SP1 and SP3 are aligned in the second direction Y. Subpixels SP1 and SP3 are also aligned in the first direction X with subpixel SP2.

[0017] When the subpixels SP1, SP2, and SP3 are laid out as shown in Fig. 2, the display area DA is formed with a column in which the subpixels SP1 and SP3 are alternately arranged in the second direction Y, and a column in which a plurality of subpixels SP2 are arranged in the second direction Y. These columns are arranged alternately in the first direction X. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in Fig. 2. For example, the subpixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0018] The display device DSP further includes a rib 5 indicated by a dashed line. The rib 5 has an opening OP1, an opening OP2, and an opening OP3 in the subpixel SP1, the subpixel SP2, and the subpixel SP3, respectively. In a plan view, the areas of the openings OP1 and OP3 are different from the area of ​​the opening OP2. In the example of FIG. 2, the area of ​​the opening OP2 is larger than the areas of the openings OP1 and OP3. The area of ​​the opening OP1 is equal to the area of ​​the opening OP3. The areas of the openings OP1, OP2, and OP3 may be different from each other or may all be the same.

[0019] The rib 5 has a plurality of ribs 5x extending along the first direction X and a plurality of ribs 5y extending along the second direction Y. The plurality of ribs 5x are respectively arranged between the openings OP1 and OP3 adjacent to each other in the second direction Y, and between the two openings OP2 adjacent to each other in the second direction Y. The plurality of ribs 5y are respectively arranged between the openings OP1 and OP2 adjacent to each other in the first direction X, and between the openings OP2 and OP3 adjacent to each other in the first direction X.

[0020] 2, the rib 5x and the rib 5y are connected to each other, so that the rib 5 is formed in a lattice shape surrounding the openings OP1, OP2, and OP3, respectively.

[0021] The display device DSP further includes lower electrodes LE1, LE2, and LE3, emitting layers EM1, EM2, and EM3, and a barrier layer BA. The lower electrode LE1 overlaps the opening OP1 in a planar view. The lower electrode LE2 overlaps the opening OP2 in a planar view. The lower electrode LE3 overlaps the opening OP3 in a planar view. The peripheral portions of the lower electrodes LE1, LE2, and LE3 overlap the rib 5 in a planar view. The lower electrodes LE1, LE2, and LE3 are separated from each other.

[0022] The light emitting layer EM1 overlaps the lower electrode LE1 and the opening OP1 in a planar view. The light emitting layer EM2 overlaps the lower electrode LE2 and the opening OP2 in a planar view. The light emitting layer EM3 overlaps the lower electrode LE3 and the opening OP3 in a planar view. The light emitting layers EM1, EM2, and EM3 are separated from each other.

[0023] The barrier layer BA indicated by solid lines has a plurality of barrier layers BAx extending along the first direction X and a plurality of barrier layers BAy extending along the second direction Y. The plurality of barrier layers BAx are respectively disposed between the light emitting layers EM1 and EM3 adjacent to each other in the second direction Y, and between the two light emitting layers EM2 adjacent to each other in the second direction Y. The plurality of barrier layers BAy are respectively disposed between the light emitting layers EM1 and EM2 adjacent to each other in the first direction X, and between the light emitting layers EM2 and EM3 adjacent to each other in the first direction X.

[0024] The barrier layer BAx is located immediately above the rib 5x, and the barrier layer BAy is located immediately above the rib 5y. In other words, the barrier layer BA is located immediately above the rib 5.

[0025] 2, the barrier layer BAx and the barrier layer BAy are connected to each other, so that the barrier layer BA is formed in a lattice shape surrounding the light emitting layers EM1, EM2, and EM3, respectively.

[0026] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line AA in FIG. The display device DSP further includes a circuit layer 11, an insulating layer 12, common layers CL1 and CL2, an upper electrode UE, and a sealing layer 13.

[0027] The circuit layer 11 is disposed on the substrate 10. The insulating layer 12 is disposed above the substrate 10. The circuit layer 11 is covered with the insulating layer 12. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in Fig. 1, and various wirings such as the scanning line GL, the signal line SL, and the power supply line PL. The insulating layer 12 includes, for example, an inorganic insulating layer and an organic insulating layer.

[0028] The lower electrodes LE1, LE2, and LE3 are each disposed on an insulating layer 12. Although omitted in Fig. 3, the lower electrodes LE1, LE2, and LE3 are electrically connected to the pixel circuit 1 shown in Fig. 1 through a contact hole penetrating the insulating layer 12.

[0029] The rib 5 is disposed on the insulating layer 12. The peripheral edges of each of the lower electrodes LE1, LE2, and LE3 are covered with the rib 5. The rib 5 is formed of, for example, an organic material.

[0030] The common layer CL1 is disposed on the lower electrodes LE1, LE2, LE3, and the rib 5. The emitting layers EM1, EM2, and EM3 are disposed on the common layer CL1.

[0031] The barrier layer BA is disposed on the common layer CL1 between the light-emitting layers EM1, EM2, and EM3. In the example of Fig. 3, the thickness of the barrier layer BA is equal to the thickness of each of the light-emitting layers EM1, EM2, and EM3. The thickness of the barrier layer BA may be greater than the thickness of each of the light-emitting layers EM1, EM2, and EM3, or may be smaller than the thickness of each of the light-emitting layers EM1, EM2, and EM3.

[0032] The common layer CL2 is disposed on the emitting layers EM1, EM2, EM3, and the barrier layer BA. The upper electrode UE is disposed on the common layer CL2. The sealing layer 13 is disposed on the upper electrode UE. The sealing layer 13 includes an organic layer for flattening unevenness caused by the ribs 5, and an inorganic layer for protecting the emitting layers EM1, EM2, and EM3 from moisture and the like.

[0033] The lower electrode LE1, the lower electrode LE2, and the lower electrode LE3 may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may be a laminate of a transparent conductive material and a metal material.

[0034] The upper electrode UE is formed of a metal material such as magnesium or silver, etc. However, the upper electrode UE may be formed of a transparent conductive material such as ITO or IZO.

[0035] In one example, the lower electrodes LE1, LE2, and LE3 correspond to an anode of a display element, and the upper electrode UE corresponds to a cathode of the display element.

[0036] The light-emitting layers EM1, EM2, and EM3 are formed of different materials. In one example, the light-emitting layer EM1 is formed of a material that emits red light, the light-emitting layer EM2 is formed of a material that emits blue light, and the light-emitting layer EM3 is formed of a material that emits green light.

[0037] The barrier layer BA is formed of, for example, a material containing silicon-based quantum dots or a silicon-based indirect transition material. As a material for forming the barrier layer BA, for example, a material with an extremely small quantum yield is preferable. Note that the barrier layer BA is not limited to a silicon-based material.

[0038] The hole injection barrier of the barrier layer BA is larger than that of the light emitting layer EM2 that emits blue light. In addition, as shown in Fig. 2, when the barrier layer BA is disposed between the light emitting layer EM1 and the light emitting layer EM2, between the light emitting layer EM1 and the light emitting layer EM3, and between the light emitting layer EM2 and the light emitting layer EM3, the hole injection barrier of the barrier layer BA is larger than that of each of the light emitting layer EM1, the light emitting layer EM2, and the light emitting layer EM3.

[0039] FIG. 4 is a diagram showing an example of the configuration of the display element 20. As shown in FIG. The lower electrode LE shown in Fig. 4 corresponds to the lower electrode LE1, the lower electrode LE2, and the lower electrode LE3 shown in Fig. 3. The light-emitting layer EM shown in Fig. 4 corresponds to the light-emitting layer EM1, the light-emitting layer EM2, and the light-emitting layer EM3 shown in Fig. 3.

[0040] In one example, the common layer CL1 includes a hole injection layer HIL, a hole transport layer HTL, and an electron blocking layer EBL as functional layers. The hole injection layer HIL is disposed on the lower electrode LE. The hole transport layer HTL is disposed on the hole injection layer HIL. The electron blocking layer EBL is disposed on the hole transport layer HTL. The emitting layer EM is disposed on the electron blocking layer EBL.

[0041] In one example, the common layer CL2 includes a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL as functional layers. The hole blocking layer HBL is disposed on the light emitting layer EM. The electron transport layer ETL is disposed on the hole blocking layer HBL. The electron injection layer EIL is disposed on the electron transport layer ETL. The upper electrode UE is disposed on the electron injection layer EIL.

[0042] In addition, in addition to the above-mentioned functional layers, the common layer CL1 and the common layer CL2 may include other functional layers such as a carrier generation layer as necessary, or at least one of the above-mentioned functional layers may be omitted.

[0043] Fig. 5 is a schematic enlarged view of part B in Fig. 3. The effects obtained by the display device DSP according to this embodiment will be described below with reference to Fig. 5. Note that, although the following describes the case where the emitting layer EM2 emits light, the same effects can be obtained when the emitting layer EM1 or the emitting layer EM3 emits light.

[0044] First, a problem that may arise when the display device DSP does not include a barrier layer BA will be described. Here, a case will be described where the subpixel SP1 does not emit light and the subpixel SP2 emits light. When the emitting layer EM2 emits light, holes flow from the subpixel SP2 to the subpixel SP1 through the common layer CL1. If the hole injection barrier of the emitting layer EM1 is smaller than the hole injection barrier of the emitting layer EM2, the holes that flow into the subpixel SP1 combine with the electrons injected into the emitting layer EM1, causing the vicinity of the end E1E of the emitting layer EM1 to emit light. Such undesired light emission of the emitting layer EM1 causes poor color mixing and reduces the display quality.

[0045] On the other hand, in this embodiment, the display device DSP includes a barrier layer BA on the common layer CL1 between the emission layers EM1 and EM2. The emission layers EM1 and EM2 are separated from each other by the width W of the barrier layer BA. Therefore, when the emission layer EM2 emits light, holes flowing through the common layer CL1 and electrons flowing through the common layer CL2 are combined and consumed in the barrier layer BA, which is closer to the emission layer EM2 than the emission layer EM1. Therefore, the number of holes flowing to the subpixel SP1 is reduced. This makes it possible to suppress undesired emission of light from the emission layer EM1 and to suppress deterioration of display quality.

[0046] In addition, the hole injection barrier of the barrier layer BA is larger than the hole injection barriers of the emission layers EM1 and EM2. Therefore, when the emission layer EM2 emits light, the probability that carriers will combine in the emission layer EM2, which has a smaller hole injection barrier than the barrier layer BA, increases. As a result, the number of carriers flowing to the subpixel SP1 is further reduced, and the emission of the emission layer EM1 can be further suppressed. This makes it possible to further suppress the deterioration of the display quality. In addition, the increased probability of carriers combining in the emission layer EM2 increases the luminous efficiency in the emission layer EM2, and improves the life of the display element.

[0047] In addition, the barrier layer BA is formed of a material containing silicon-based quantum dots with a low quantum yield. Therefore, even if carriers are bonded in the barrier layer BA, the barrier layer BA hardly emits light. Even if the barrier layer BA emits light, the light emission is very weak. Therefore, the carrier bond in the barrier layer BA hardly affects the display quality of the image displayed on the display device DSP.

[0048] Moreover, the barrier layer BA is formed of an indirect transition material. Therefore, when carriers combine in the barrier layer BA, they are released as thermal energy. This heat increases the temperature of each of the common layers CL1 and CL2 in contact with the barrier layer BA. When the temperature of the common layers CL1 and CL2 increases, the resistance value increases, so that the flow of carriers in the common layers CL1 and CL2 near the barrier layer BA is restricted. Therefore, when the emitting layer EM2 emits light, the number of carriers flowing to the subpixel SP1 decreases. This makes it possible to suppress the light emission of the emitting layer EM1 and to prevent a deterioration in display quality.

[0049] Next, an example of a method for manufacturing the display device DSP will be described. Figures 6 to 16 are diagrams for explaining the method for manufacturing the display device DSP.

[0050] 6, an insulating layer 12 is formed above a substrate 10. Specifically, a circuit layer 11 is formed on the substrate 10, and an insulating layer 12 is formed on the circuit layer 11. Subsequently, as shown in FIG. 7, on the insulating layer 12, the lower electrodes LE1, LE2, and LE3 are formed so as to be spaced apart from each other.

[0051] 8, a rib 5 is formed on the insulating layer 12. The rib 5 has an opening OP1 overlapping the lower electrode LE1 in a plan view, an opening OP2 overlapping the lower electrode LE2, and an opening OP3 overlapping the lower electrode LE3.

[0052] 9, a common layer CL1 is formed on the lower electrodes LE1, LE2, LE3, and the rib 5. In one example, the common layer CL1 includes a hole injection layer, a hole transport layer, and an electron block layer as functional layers. The common layer CL1 contacts the lower electrode LE1 at the opening OP1, contacts the lower electrode LE2 at the opening OP2, and contacts the lower electrode LE3 at the opening OP3.

[0053] 10, the emitting layers EM1, EM2, and EM3 are formed on the common layer CL1 at a distance from each other. The emitting layer EM1 is formed so as to overlap the lower electrode LE1 and the opening OP1 in a planar view. The emitting layer EM2 is formed so as to overlap the lower electrode LE2 and the opening OP2 in a planar view. The emitting layer EM3 is formed so as to overlap the lower electrode LE3 and the opening OP3 in a planar view.

[0054] The light-emitting layers EM1, EM2, and EM3 are formed of materials that emit light in different wavelength ranges. In one example, the light-emitting layer EM1 is formed of a material that emits red light, the light-emitting layer EM2 is formed of a material that emits blue light, and the light-emitting layer EM3 is formed of a material that emits green light. The order in which the light-emitting layers EM1, EM2, and EM3 are formed is not particularly limited.

[0055] 11, a barrier layer BA is formed on the emitting layers EM1, EM2, EM3, and common layer CL1. Specifically, a material for forming the barrier layer BA is applied onto the emitting layers EM1, EM2, EM3, and common layer CL1, and then dried to form the barrier layer BA. Examples of a method for applying the material include an inkjet method, a spin coat method, and a printing method. Also, for example, a material obtained by mixing the material for forming the barrier layer BA with a photoacid generator may be applied by the above method.

[0056] The material for forming the barrier layer BA may be, for example, a material containing silicon-based quantum dots or a silicon-based indirect transition material. The material for forming the barrier layer BA is preferably, for example, a material with an extremely low quantum yield. Note that the barrier layer BA is not limited to a silicon-based material.

[0057] The barrier layer BA has a hole injection barrier greater than that of the blue-emitting emitting layer EM2, and in one example, the barrier layer BA has a hole injection barrier greater than that of each of the emitting layers EM1, EM2, and EM3.

[0058] 12, a resist 61 is applied onto the barrier layer BA, and the resist 61 is patterned. This forms the resist 61 overlapping the barrier layer BA between the light emitting layer EM1, the light emitting layer EM2, and the light emitting layer EM3.

[0059] 13, the barrier layer BA exposed from the resist 61 is removed by etching using the resist 61 of FIG. 12 as a mask. Then, the resist 61 is removed. As a result, the barrier layer BA is formed, which is located on the common layer CL1 between the light emitting layers EM1, EM2, and EM3 and surrounds the light emitting layers EM1, EM2, and EM3 in a plan view. In the example of FIG. 13, the barrier layer BA is formed to a thickness equal to that of the light emitting layers EM1, EM2, and EM3. The barrier layer BA may be formed to a thickness greater than that of the light emitting layers EM1, EM2, and EM3, or may be formed to a thickness smaller than that of the light emitting layers EM1, EM2, and EM3.

[0060] 14, a common layer CL2 is formed on the emitting layer EM1, the emitting layer EM2, the emitting layer EM3, and the barrier layer BA. In one example, the common layer CL2 includes a hole blocking layer, an electron transport layer, and an electron injection layer as functional layers.

[0061] Subsequently, as shown in FIG. 15, the upper electrode UE is formed on the common layer CL2. Subsequently, as shown in FIG. 16, a sealing layer 13 is formed on the upper electrode UE. Through the above steps, the display device DSP according to this embodiment is obtained.

[0062] Next, another example of the configuration of the display device DSP will be described. Elements that are the same as or similar to those of the display device DSP described above are given the same reference numerals, and duplicated explanations will be omitted.

[0063] Fig. 17 is a schematic cross-sectional view showing another configuration example of the display device DSP. The display device DSP in Fig. 17 includes, for example, a quantum dot light-emitting diode (QLED) as a display element. In addition, the display device DSP in Fig. 17 does not include an element corresponding to the rib 5 shown in Fig. 3.

[0064] The common layer CL1 is disposed on the insulating layer 12. The common layer CL1 covers the lower electrodes LE1, LE2, and LE3. That is, the common layer CL1 is in contact with the insulating layer 12 at a position overlapping the barrier layer BA.

[0065] The light-emitting layers EM1, EM2, and EM3 are formed of a material containing quantum dots. In one example, the light-emitting layer EM1 is formed of a material containing quantum dots that emit red light, the light-emitting layer EM2 is formed of a material containing quantum dots that emit blue light, and the light-emitting layer EM3 is formed of a material containing quantum dots that emit green light.

[0066] The display device DSP shown in FIG. 17 can also provide the same effects as those described above.

[0067] In the above example, the lower electrode LE1 or the lower electrode LE3 corresponds to the first lower electrode, and the lower electrode LE2 corresponds to the second lower electrode. The light-emitting layer EM1 or the light-emitting layer EM3 corresponds to the first light-emitting layer, and the light-emitting layer EM2 corresponds to the second light-emitting layer. The opening OP1 or the opening OP3 corresponds to the first opening, and the opening OP2 corresponds to the second opening. The common layer CL1 corresponds to the first common layer, and the common layer CL2 corresponds to the second common layer.

[0068] All display devices and display device manufacturing methods that can be implemented by a person skilled in the art through appropriate design modifications based on the display devices and display device manufacturing methods described above as embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0069] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of the above-mentioned embodiment, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0070] Furthermore, with regard to other effects and advantages brought about by the aspects described in the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately thought up by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0071] DSP...display device, PX...pixel, SP, SP1, SP2, SP3...subpixel, 10...substrate, 12...insulating layer, 13...sealing layer, 20...display element, BA...barrier layer, CL1, CL2...common layer, EM, EM1, EM2, EM3...emissive layer, LE, LE1, LE2, LE3...lower electrode, UE...upper electrode, OP1, OP2, OP3...opening.

Claims

1. A substrate; an insulating layer disposed above the substrate; a first lower electrode and a second lower electrode spaced apart from each other and disposed on the insulating layer; a first common layer disposed on the first lower electrode and the second lower electrode; a first light-emitting layer disposed on the first common layer and overlapping the first lower electrode in a plan view; a second light-emitting layer disposed on the first common layer, overlapping the second lower electrode in a plan view, spaced apart from the first light-emitting layer, and made of a material different from that of the first light-emitting layer; a barrier layer disposed on the first common layer between the first light emitting layer and the second light emitting layer and surrounding each of the first light emitting layer and the second light emitting layer in a plan view; a second common layer disposed on the first light-emitting layer, the second light-emitting layer, and the barrier layer; an upper electrode disposed on the second common layer; A display device comprising:

2. The barrier layer is formed of a material containing quantum dots. The display device according to claim 1 .

3. The barrier layer is formed of a material including an indirect transition material. The display device according to claim 1 .

4. the indirect transition material comprises silicon; The display device according to claim 3 .

5. a hole injection barrier of the barrier layer is greater than each of the hole injection barriers of the first light emitting layer and the second light emitting layer; The display device according to claim 4.

6. The thickness of the barrier layer is equal to the thickness of each of the first light-emitting layer and the second light-emitting layer. The display device according to claim 1 .

7. the first common layer includes a hole injection layer, a hole transport layer, and an electron blocking layer; The second common layer includes a hole blocking layer, an electron transport layer, and an electron injection layer. The display device according to claim 1 .

8. a rib disposed on the insulating layer and having a first opening overlapping the first lower electrode and a second opening overlapping the second lower electrode in a plan view; the first common layer is disposed over the ribs; The barrier layer is located directly above the rib. The display device according to claim 1 .

9. In a plan view, an area of ​​the first opening is different from an area of ​​the second opening. The display device according to claim 8.

10. the first light-emitting layer is formed of a material that emits red or green light, The second light-emitting layer is formed of a material that emits blue light. The display device according to claim 8.

11. The first light emitting layer and the second light emitting layer are formed of a material containing quantum dots. The display device according to claim 1 .

12. the first common layer is in contact with the insulating layer at a position overlapping the barrier layer; The display device according to claim 11.

13. forming an insulating layer over the substrate; forming a first lower electrode and a second lower electrode spaced apart from each other on the insulating layer; forming a rib on the insulating layer, the rib forming a first opening overlapping the first lower electrode and a second opening overlapping the second lower electrode in a plan view; forming a first common layer on the first lower electrode, the second lower electrode, and the rib; a first light-emitting layer is formed on the first common layer so as to overlap the first lower electrode in a plan view; a second light-emitting layer is formed on the first common layer, overlapping the second lower electrode in a plan view, separated from the first light-emitting layer, and made of a material different from that of the first light-emitting layer; forming a barrier layer located on the first common layer between the first light emitting layer and the second light emitting layer and surrounding each of the first light emitting layer and the second light emitting layer in a plan view; forming a second common layer on the first light emitting layer, the second light emitting layer, and the barrier layer; forming an upper electrode on the second common layer; A method for manufacturing a display device.

14. The barrier layer is formed of a material containing quantum dots. The method for manufacturing the display device according to claim 13 .

15. The barrier layer is formed of a material including an indirect transition material. The method for manufacturing the display device according to claim 13 or 14.

16. the indirect transition material comprises silicon; The method for manufacturing the display device according to claim 15 .

17. a hole injection barrier of the barrier layer is greater than each of the hole injection barriers of the first light emitting layer and the second light emitting layer; The method for manufacturing the display device according to claim 16 .

18. the first common layer includes a hole injection layer, a hole transport layer, and an electron blocking layer; The second common layer includes a hole blocking layer, an electron transport layer, and an electron injection layer. The method for manufacturing the display device according to claim 13 .

19. the first light-emitting layer is formed of a material that emits red or green light; The second light emitting layer is formed of a material that emits blue light. The method for manufacturing the display device according to claim 13 .

20. Furthermore, in the step of forming the barrier layer, forming the barrier layer on the first light emitting layer, the second light emitting layer, and the first common layer; forming a resist layer overlapping the barrier layer between the first light-emitting layer and the second light-emitting layer; removing the barrier layer exposed from the resist by etching using the resist as a mask; The method for manufacturing the display device according to claim 13 .

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