Display unit and display system

Abstract

To provide a display unit and a display system that can reduce the time required from the time point of reception of a control signal for making a transition from a pause mode to a display mode until when an image is displayed on a display panel.SOLUTION: A display unit comprises: a timing control circuit 2 that supplies a timing signal C1 to a level shifter circuit 3; and a power control circuit 4. When receiving a control signal D1 for making a transition from a display mode to a pause mode from a host controller 102, the timing control circuit 2 transmits a pause signal B1 to the power control circuit 4, and stops the supply of the timing signal C1 to the level shifter circuit 3 to stop output of a gate signal from the level shifter circuit 3. When receiving the pause signal B1, the power control circuit 4 stops at least part of the supply of power to a display panel 1 and the level shifter circuit 3, while maintaining the supply of power to the timing control circuit 2.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a display device and a display system. [Background technology]

[0002] The display device described in Patent Document 1 executes control processing in either a normal operation mode in which an image is displayed on the display panel, or a sleep mode in which an image is not displayed on the display panel. This display device is configured to transition to the sleep mode if there is no touch operation for a certain period of time in the normal operation mode. The display device is also configured to transition to the normal operation mode if there is a touch operation in the sleep mode. In the sleep mode, the display device does not display images on the display panel, and therefore stops the display control unit, gate driver, and source driver. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-91224 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, the display device described in Patent Document 1 has a problem in that when transitioning from a sleep mode (pause mode) to a normal operation mode (display mode), it takes a long time from when a touch operation is detected (a touch detection signal is received) until an image is displayed on the display panel. That is, in conventional display devices, it takes a long time from when a control signal for transitioning from the pause mode to the display mode is received until an image is displayed on the display panel.

[0005] Therefore, the present disclosure has been made to solve the above-mentioned problems, and aims to provide a display device and a display system that are capable of shortening the time from when a control signal to transition from a sleep mode to a display mode is received to when an image is displayed on the display panel. [Means for solving the problem]

[0006] In order to solve the above problems, a display device according to a first aspect of the present disclosure includes a display panel, a display drive circuit that supplies a drive signal to the display panel, a timing control circuit that supplies an image signal to the display panel and supplies a timing signal to the display drive circuit, and a power control circuit that controls a state in which power is supplied to and a state in which power supply is stopped for each of the display panel, the display drive circuit, and the timing control circuit, wherein when the timing control circuit receives a control signal from a host controller to transition from a display mode in which the display panel displays a picture to a pause mode in which the display panel stops displaying, the timing control circuit sends a pause signal to the power control circuit and stops supplying the timing signal to the display drive circuit, thereby stopping the supply of the drive signal from the display drive circuit to the display panel, and when the power control circuit receives the pause signal, the power control circuit stops at least a portion of the supply of power to the display panel and the display drive circuit while maintaining the supply of power to the timing control circuit, and when the timing control circuit receives a control signal from the host controller to transition from the display mode to the pause mode, the timing control circuit stops sending the pause signal to the power control circuit and supplies the timing signal to the display drive circuit.

[0007] A display system according to a second aspect is a display system including a display device having a display panel, and a host controller that transmits to the display device a first control signal for switching from a display mode in which display is performed by the display panel to a pause mode in which display by the display panel is stopped, and a second control signal for switching from the pause mode to the display mode, in which the display device includes a display drive circuit that supplies drive signals to the display panel, a timing control circuit that supplies an image signal to the display panel and supplies a timing signal to the display drive circuit, and a power control circuit that controls a state in which power is supplied to and a state in which power supply is stopped for each of the display panel, the display drive circuit, and the timing control circuit. and a circuit, wherein the timing control circuit receives the first control signal from the host controller and sends a pause signal to the power control circuit and stops supplying the timing signal to the display drive circuit, thereby stopping supply of the drive signal from the display drive circuit to the display panel, and when the power control circuit receives the pause signal, it stops at least a portion of the supply of power to the display panel and the display drive circuit while maintaining power supply to the timing control circuit, and when the timing control circuit receives the second control signal from the host controller, it stops sending the pause signal to the power control circuit and supplies the timing signal to the display drive circuit. Effect of the Invention

[0008] According to the above configuration, the supply of power to the timing control circuit is maintained even during a period when display by the display panel is paused. This makes it possible to eliminate the time required to start up the timing control circuit from the time when a control signal for transitioning from the pause mode to the display mode is received until display by the display panel is started. As a result, it is possible to shorten the time from the time when a control signal for transitioning from the pause mode to the display mode is received until an image is displayed on the display panel. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram showing a schematic configuration of a display system 100 according to the first embodiment. [Diagram 2] FIG. 2 is a schematic diagram for explaining the configuration of the display panel 1. As shown in FIG. [Diagram 3] FIG. 3 is a schematic diagram showing the configuration of a pixel 10a in the display panel 1. As shown in FIG. [Figure 4] FIG. 4 is a functional block diagram of the timing control circuit 2 and the power control circuit 4. [Diagram 5] FIG. 5 is a functional block diagram showing the configuration of a display system 100a according to a comparative example. [Figure 6] FIG. 6 is a timing chart for explaining the operation of the display system 100a according to the comparative example. [Figure 7] FIG. 7 is a timing chart for explaining the operation of the display system 100 in the first embodiment. [Figure 8] FIG. 8 is a block diagram showing the configuration of a display system 200 according to the second embodiment. [Figure 9] FIG. 9 is a block diagram showing the configuration of a display system 300 according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present disclosure will be described based on the drawings. Note that the present disclosure is not limited to the following embodiments, and appropriate design changes can be made within the scope of the configuration of the present disclosure. In the following description, the same parts or parts having similar functions are commonly designated by the same reference numerals in different drawings, and repeated description thereof will be omitted. In addition, each configuration described in the embodiment and the modified example may be appropriately combined or modified within the scope of the gist of the present disclosure. In addition, in order to make the description easier to understand, in the drawings referred to below, the configuration is shown simplified or schematic, and some components are omitted.

[0011] [First embodiment] (Overall configuration of the display device) 1 is a block diagram showing a schematic configuration of a display system 100 in the first embodiment. The display system 100 includes a display device 101 and a host controller 102. The display system 100 is, for example, a personal computer, a tablet terminal, a smartphone, or a television device. The host controller 102 transmits an image signal A1 (video signal) to the display device 101, and also transmits a control signal D1 to the display device 101. The host controller 102 is connected to the display device 101 via an I2C bus, and performs serial communication with the display device 101. The display device 101 displays an image based on the image signal A1 from the host controller 102.

[0012] The control signal D1 also includes a signal for commanding the display mode, in which the display panel 1 of the display device 101 performs display, to be switched to a pause mode, in which the display panel 1 stops display. For example, the host controller 102 transmits the control signal D1 including a signal for transitioning from the display mode to the pause mode when no operation is input from the user for a predetermined period during the period during which the control process in the display mode is being performed, or when the user is not present within the range of photography by a camera (not shown) for a predetermined period. The host controller 102 also transmits the control signal D1 including a signal for commanding the transition from the pause mode to the display mode when an operation is input from the user during the period during which the control process in the pause mode is being performed, or when the user appears within the range of photography by the camera. Here, in the first embodiment, the host controller 102 supplies the voltage V1 to the power control circuit 4 regardless of whether the control process in the display mode or the pause mode is being performed.

[0013] The "pause mode" is a state in which display by the display panel 1 is stopped (paused) to reduce power consumption. The pause of display by the display panel 1 in the pause mode continues until the display mode is changed to (paused over multiple frames). Stopping the display means stopping the supply of signals (gate signals and source signals) from the gate drive circuit 11 and the source drive circuit 12 to the display unit 10 on the display panel 1. The "display mode" is a state in which signals (gate signals and source signals) are supplied from the gate drive circuit 11 and the source drive circuit 12 to the display unit 10, and an image is displayed on the display panel 1. Note that the transmission of signals and the supply of power indicated by dotted arrows in Figs. 1, 4, 5, 8, and 9 are performed only in the display mode. Note that the transmission of signals and the supply of power indicated by solid arrows in Figs. 1, 4, 5, 8, and 9 are performed both in the display mode and the pause mode.

[0014] (Display Device Configuration) 1, a display device 101 includes a display panel 1, a timing control circuit 2, a level shifter circuit 3, and a power control circuit 4. The level shifter circuit 3 is an example of the "display driver circuit" of the present disclosure.

[0015] Display Panel Configuration FIG. 2 is a schematic diagram for explaining the configuration of the display panel 1. The display panel 1 is a panel that displays an image. The display panel 1 is, for example, a liquid crystal display panel, an organic EL panel, or a micro LED panel. As shown in FIG. 2, the display panel 1 includes a display section 10, a gate drive circuit 11, and a source drive circuit 12. The display panel 1 includes a substrate 1a on which a plurality of gate lines 11a, a plurality of source lines 12a, and a plurality of terminals 13 are formed. The plurality of gate lines 11a intersect with the plurality of source lines 12a in a plan view. The display section 10 is a portion on the substrate 1a on which pixels 10a (see FIG. 3) are formed, and is an area that displays an image.

[0016] The gate drive circuit 11 sequentially supplies the gate signal G1, which is supplied from the level shifter circuit 3, to the multiple gate lines 11a. The gate drive circuit 11 is a circuit (GDM: Gate Driver Monolithic) formed (monolithically) on the substrate 1a.

[0017] The source driving circuit 12 is supplied with an image signal A1 (digital signal) from the timing control circuit 2. The source driving circuit 12 is also supplied with a positive voltage Vp, a negative voltage Vn, and a reset signal R1 from the power control circuit 4. The source driving circuit 12 generates a source signal using the positive voltage Vp and the negative voltage Vn based on the image signal A1 (digital signal). The source driving circuit 12 supplies the source signal to a plurality of source lines 12a. The source driving circuit 12 is an integrated circuit mounted on the substrate 1a.

[0018] The multiple terminals 13 are connected to a flexible printed circuit board (not shown). The multiple terminals 13 are connected to the timing control circuit 2, the level shifter circuit 3, and the power control circuit 4 via the flexible printed circuit board. The multiple terminals 13 are also connected to the gate drive circuit 11, the source drive circuit 12, and a common electrode wiring (not shown).

[0019] 3 is a schematic diagram showing a configuration of a pixel 10a in the display panel 1. As shown in FIG. 3, the pixel 10a is formed in an area defined by a plurality of gate lines 11a and a plurality of source lines 12a. The pixel 10a is provided with a thin film transistor 14 and a pixel electrode 15. The gate line 11a is connected to a gate electrode of the thin film transistor 14. The source line 12a is connected to a source electrode of the thin film transistor 14. The pixel electrode 15 is connected to a drain electrode of the thin film transistor 14. As a result, when a gate signal is input from the gate line 11a to the gate electrode of the thin film transistor 14, a source signal is supplied to the pixel electrode 15, and the pixel electrode 15 is charged (an image is written).

[0020] (Configuration of Timing Control Circuit) 1, the timing control circuit 2 receives a control signal D1 and an image signal A1 from a host controller 102. Then, the timing control circuit 2 supplies the image signal A1 to the display panel 1, and supplies a timing signal C1 to the level shifter circuit 3. The timing control circuit 2 is formed of, for example, an integrated circuit.

[0021] 4 is a functional block diagram of the timing control circuit 2 and the power control circuit 4. As shown in FIG. 4, the timing control circuit 2 includes a receiving unit 21, a level shifter control unit 22, an image signal control unit 23, a return operation control unit 24, and a pause signal transmitting unit 25. The receiving unit 21 receives an image signal A1 and a control signal D1 from the host controller 102. The level shifter control unit 22 transmits a timing signal C1 to the level shifter circuit 3 based on the image signal A1. The timing signal C1 includes a synchronization signal (e.g., a vertical synchronization signal) and a clock signal. The image signal control unit 23 transmits the image signal A1 to the source driving circuit 12 of the display panel 1.

[0022] When the receiving unit 21 receives a control signal D1 including a signal for transitioning from the display mode to the pause mode, the return operation control unit 24 stops the operation of the level shifter control unit 22 and stops the operation of the image signal control unit 23. This causes the supply of the timing signal C1 from the level shifter control unit 22 to stop. As the supply of the timing signal C1 stops, the gate driving circuit 11 stops outputting the gate signal. Also, the supply of the image signal A1 from the image signal control unit 23 stops. This causes the source driving circuit 12 to stop outputting the source signal. Then, the return operation control unit 24 transmits a signal to the pause signal transmitting unit 25 to instruct it to transmit the pause signal B1.

[0023] Furthermore, when the receiving unit 21 receives a control signal D1 including a signal for transitioning from the pause mode to the display mode, the return operation control unit 24 causes the level shifter control unit 22 to start (resume) operation and the image signal control unit 23 to start (resume) operation. This causes the level shifter control unit 22 to start supplying a timing signal C1. As a result of the start of supplying the timing signal C1, the gate driving circuit 11 starts outputting a gate signal. Also, the image signal control unit 23 starts supplying an image signal A1. This causes the source driving circuit 12 to start outputting a source signal. Then, the return operation control unit 24 transmits a signal to the pause signal transmitting unit 25 to instruct it to stop transmitting the pause signal B1.

[0024] The pause signal transmitting unit 25 transmits the pause signal B1 to the power control circuit 4 based on a command from the recovery operation control unit 24. For example, the pause signal transmitting unit 25 transmits the pause signal B1 by setting the level of the voltage applied to the signal line connected to the power control circuit 4 to High. Furthermore, the pause signal transmitting unit 25 stops transmitting the pause signal B1 by setting the level of the voltage applied to the signal line connected to the power control circuit 4 to Low based on a command from the recovery operation control unit 24.

[0025] (Configuration of Level Shifter Circuit) In the display mode, the level shifter circuit 3 generates a gate signal G1 based on the timing signal C1 from the timing control circuit 2, using the voltages VGH and VHL supplied from the power control circuit 4. The level shifter circuit 3 transmits the gate signal G1, which is a pulsed signal having the voltage VGH, to the multiple gate lines 11a in sequence via the gate drive circuit 11. The level shifter circuit 3 applies the voltage VGL to the multiple gate lines 11a other than the gate line 11a to which the gate signal G1 is being supplied.

[0026] (Configuration of power control circuit) The power control circuit 4 is a circuit that controls a state in which power is supplied and a state in which power supply is stopped for each of the display panel 1, the timing control circuit 2, and the level shifter circuit 3. As shown in FIG. 4, the power control circuit 4 includes a voltage detection unit 41, a power conversion unit 42, a reset signal control unit 43, and a power supply circuit control unit 44.

[0027] The voltage detection unit 41 detects the voltage V1 (voltage level is High) supplied from the host controller 102. Then, when the supply of the voltage V1 from the host controller 102 is stopped (when the voltage level becomes Low), the voltage detection unit 41 causes the reset signal control unit 43 to stop outputting the reset signal R1. Furthermore, when the supply of the voltage V1 from the host controller 102 is stopped, the voltage detection unit 41 causes the power conversion unit 42 to stop outputting the voltage. The supply of the voltage V1 from the host controller 102 is stopped, for example, when the power supply of the display system 100 is turned off and the supply of power to the host controller 102 is stopped.

[0028] The power conversion unit 42 includes a circuit power supply unit 42a, a timing control circuit power supply unit 42b, a level shifter power supply unit 42c, a source driving circuit power supply unit 42d, and a common electrode power supply unit 42e. The circuit power supply unit 42a converts a voltage V1 output from the host controller 102 into a voltage V2 for operating the display panel 1, the timing control circuit 2, and the level shifter circuit 3. The circuit power supply unit 42a then outputs the voltage V2 to the display panel 1, the timing control circuit 2, and the level shifter circuit 3. As an example of the voltage values, the voltage V1 is 3.3V and the voltage V2 is 1.8V.

[0029] The timing control circuit power supply unit 42b converts the voltage V1 output from the host controller 102 into a voltage V3 for operating the timing control circuit 2. Then, the timing control circuit power supply unit 42b outputs the voltage V3 to the timing control circuit 2. The voltage V3 has a different voltage value from the voltage V2.

[0030] The level shifter power supply unit 42c converts the voltage V1 output from the host controller 102 into voltages VGH and VGL used when the level shifter circuit 3 generates the gate signal G1. Then, the level shifter power supply unit 42c outputs the voltages VGH and VGL to the level shifter circuit 3.

[0031] The source driving circuit power supply unit 42d converts the voltage V1 output from the host controller 102 into a positive voltage Vp and a negative voltage Vn used when the source driving circuit 12 generates a source signal. Then, the source driving circuit power supply unit 42d outputs the positive voltage Vp and the negative voltage Vn to the source driving circuit 12.

[0032] The common electrode power supply unit 42e converts the voltage V1 output from the host controller 102 into a voltage Vc to be applied to the common electrode of the display panel 1. Then, the common electrode power supply unit 42e outputs the voltage Vc to the display panel 1.

[0033] The reset signal control unit 43 outputs the reset signal R1 based on a command from the voltage detection unit 41. The level shifter circuit 3 and the source drive circuit 12 stop operating when the voltage level of the reset signal R1 changes from High to Low (OFF). That is, the level shifter circuit 3 (gate drive circuit 11) outputs a gate signal when the voltage level of the reset signal R1 is High, and stops outputting the gate signal when the voltage level of the reset signal R1 is Low. The source drive circuit 12 outputs a source signal when the voltage level of the reset signal R1 is High, and stops outputting the source signal when the voltage level of the reset signal R1 is Low.

[0034] When the power supply circuit control unit 44 receives the pause signal B1 from the timing control circuit 2, it stops the supply of power from the level shifter power supply unit 42c, the source driving circuit power supply unit 42d, and the common electrode power supply unit 42e while maintaining the supply of power from the circuit power supply unit 42a and the timing control circuit power supply unit 42b of the power conversion unit 42. As a result, the level shifter circuit 3 stops the operation (output of the gate signal) as the supply of power from the level shifter power supply unit 42c stops. Also, the supply of power to the common electrode in the display panel 1 stops. Also, the supply of power from the level shifter power supply unit 42c stops, and the source driving circuit 12 stops the operation (output of the source signal). Also, the supply of power to the timing control circuit 2 is maintained. This makes it possible to save the time required to start the timing control circuit 2 from the time when the control signal D1 including the signal for shifting from the pause mode to the display mode is received until an image is displayed on the display panel 1. As a result, it is possible to shorten the time required from the time when the control signal D1 for shifting from the pause mode to the display mode is received until an image is displayed on the display panel 1.

[0035] (Display system operation) Next, the operation of the display system 100 according to the first embodiment will be described while comparing it with a display system 100a according to a comparative example. Fig. 5 is a functional block diagram showing the configuration of the display system 100a according to the comparative example. Fig. 6 is a timing chart for explaining the operation of the display system 100a according to the comparative example.

[0036] Comparative Example As shown in Fig. 5, the display system 100a includes a display device 101a and a host controller 102a. The receiver 21a of the timing control circuit 2a receives an image signal A1 from the host controller 102a. The level shifter controller 22a of the timing control circuit 2a outputs a timing signal C1 based on the image signal A1. The image signal controller 23a of the timing control circuit 2a outputs the image signal A1 to a source driving circuit.

[0037] When the host controller 102a shifts from the display mode to the pause mode, it stops the supply of the voltage V1 to the power control circuit 4a. In the power control circuit 4a, the voltage detection unit 41a stops the operation of the power conversion unit 142a based on the fact that the supply of the voltage V1 has been stopped, and stops the output of the reset signal R1 from the reset signal control unit 43a (sets the voltage level to Low). As a result, in the pause mode according to the comparative example, the supply of power to the timing control circuit 2a, the level shifter circuit, and the display panel is stopped.

[0038] 6, when the host controller 102a transitions from the pause mode to the display mode, it starts supplying a voltage V1 to the power control circuit 4a at time t1. The power control circuit 4a then starts, and after a period T1 has elapsed from time t1, starts outputting voltages V2 and V3. The timing control circuit 2a then starts. Then, it starts outputting voltages Vp, Vn, Vc, VGH, and VGL, and a reset signal R1, and at time t3, display by the display panel starts.

[0039] Operation of the First Embodiment 7, in the first embodiment, the supply of voltage V1 from the host controller 102 to the power control circuit 4 is performed in both the pause mode and the display mode. When the mode transitions from the pause mode to the display mode, the host controller 102 transmits a control signal D1 including a signal for transitioning from the pause mode to the display mode to the timing control circuit 2. The timing control circuit 2 then starts supplying a timing signal C1 to the level shifter circuit 3, and starts supplying an image signal A1 to the source drive circuit 12.

[0040] Also, at time t11, the timing control circuit 2 stops supplying the pause signal B1 to the power control circuit 4. Also, even in the pause mode, the voltage V1 is applied to the power control circuit 4, and the output of the voltages V2 and V3 from the power control circuit 4 is maintained, so that at time t11, the voltages V2 and V3 are being output. Also, since the voltage V1 is applied to the power control circuit 4, the power control circuit 4 starts outputting the voltages Vp, Vn, Vc, VGH, and VGL, and the reset signal R1 after time t1, and the display panel 1 starts displaying at time t12. As a result, according to the first embodiment, it is possible to start displaying on the display panel 1 in a period that is shorter by the period T1 from the time when the pause mode is switched to the display mode, as compared to the comparative example.

[0041] [Second embodiment] Next, the configuration of a display system 200 according to a second embodiment will be described with reference to Fig. 8. In the first embodiment, an example was shown in which the pause signal B1 was transmitted by changing the voltage level of one signal line to High or Low, but in the second embodiment, the pause signal B1 is transmitted by a command. Note that the same components as those in the first embodiment are given the same reference numerals and will not be described.

[0042] As shown in FIG. 8, the display system 200 includes a display device 201. The display device 201 includes a timing control circuit 202 and a power control circuit 204. The timing control circuit 202 according to the second embodiment is connected to the power control circuit 204 via an I2C bus and performs serial communication with the power control circuit 204. Then, the pause signal transmission unit 225 of the timing control circuit 202 transmits a pause signal B1 as a command in the serial communication. When the power supply circuit control unit 244 of the power control circuit 204 receives the command, it stops the supply of power from the level shifter power supply unit 42c, the source drive circuit power supply unit 42d, and the common electrode power supply unit 42e while maintaining the supply of power from the circuit power supply unit 42a and the timing control circuit power supply unit 42b of the power conversion unit 42. The other configurations and effects are the same as those of the first embodiment.

[0043] [Third embodiment] Next, the configuration of a display system 300 according to a third embodiment will be described with reference to Fig. 9. In the third embodiment, when a power control circuit 204 receives a pause signal B1, it stops the supply of power to the display panel 1, the level shifter circuit 3, and the source driving circuit 12 while maintaining the supply of power to the timing control circuit 202. Note that the same components as those in the first embodiment are denoted by the same reference numerals and will not be described.

[0044] 9, a display system 300 includes a display device 301. The display device 301 includes a power control circuit 304. The power control circuit 304 includes a power conversion unit 342 and a power supply circuit control unit 344. The power conversion unit 342 according to the third embodiment includes a first circuit power supply unit 342aa, a second circuit power supply unit 342ab, and a third circuit power supply unit 342ac.

[0045] The first circuit power supply unit 342aa is connected to the timing control circuit 2, and supplies a voltage V2 to the timing control circuit 2 in both the display mode and the pause mode. The second circuit power supply unit 342ab is connected to the level shifter circuit 3 (see FIG. 1), and supplies a voltage V2 to the level shifter circuit 3 in the display mode, and stops the supply of the voltage V2 to the level shifter circuit 3 in the pause mode. The third circuit power supply unit 342ac is connected to the source drive circuit 12 (see FIG. 1), and supplies a voltage V2 to the source drive circuit 12 in the display mode, and stops the supply of the voltage V2 to the source drive circuit 12 in the pause mode.

[0046] When the power supply circuit control unit 344 receives a pause signal B1 from the timing control circuit 2, it stops the supply of power to the second circuit power supply unit 342ab, the third circuit power supply unit 342ac, the level shifter power supply unit 42c, the source driving circuit power supply unit 42d, and the common electrode power supply unit 42e while maintaining the supply of power by the first circuit power supply unit 342aa and the timing control circuit power supply unit 42b. As a result, the power control circuit 304 stops the supply of power to the display panel 1, the level shifter circuit 3, and the source driving circuit 12 while maintaining the supply of power to the timing control circuit 202. As a result, the supply of power to the display panel 1, the level shifter circuit 3, and the source driving circuit 12 is stopped, so that the power consumption in the pause mode can be reduced.

[0047] [Variations] Although the embodiment of the invention has been described above, the above-mentioned embodiment is merely an example for carrying out the invention. Therefore, the present invention is not limited to the above-mentioned embodiment, and can be appropriately modified and carried out without departing from the spirit of the invention. Below, a modified example of the above-mentioned embodiment will be described.

[0048] (1) In the above first to third embodiments, the host controller supplies the voltage V1 to the power control circuit, but the present disclosure is not limited to this. That is, the voltage V1 may be supplied to the power control circuit from a power supply circuit other than the host controller.

[0049] (2) In the above first to third embodiments, the display panel is provided with a GDM, but the present disclosure is not limited to this. An integrated circuit (gate driver) including a level shifter circuit may be mounted on the substrate.

[0050] (3) In the above first to third embodiments, the display driver circuit is configured as a level shifter circuit, but the present disclosure is not limited to this. A driver circuit that sequentially supplies gate signals to a plurality of gate lines may be configured without using a level shifter circuit.

[0051] The above-mentioned configuration can also be explained as follows.

[0052] A display device according to a first configuration includes a display panel, a display drive circuit that supplies a drive signal to the display panel, a timing control circuit that supplies an image signal to the display panel and supplies a timing signal to the display drive circuit, and a power control circuit that controls a state in which power is supplied and a state in which power supply is stopped for each of the display panel, the display drive circuit, and the timing control circuit, wherein when the timing control circuit receives a control signal from a host controller to transition from a display mode in which the display panel displays a picture to a pause mode in which the display panel stops displaying, the timing control circuit sends a pause signal to the power control circuit and stops supplying the timing signal to the display drive circuit, thereby stopping the supply of the drive signal from the display drive circuit to the display panel, and when the power control circuit receives the pause signal, the power control circuit stops at least a portion of the supply of power to the display panel and the display drive circuit while maintaining the supply of power to the timing control circuit, and when the timing control circuit receives a control signal from the host controller to transition from the display mode to the pause mode, the timing control circuit stops sending the pause signal to the power control circuit and supplies the timing signal to the display drive circuit (first configuration).

[0053] According to the first configuration, the supply of power to the timing control circuit is maintained even during a period when the display panel is paused. This makes it possible to eliminate the time required to start the timing control circuit from the time when the control signal for transitioning from the pause mode to the display mode is received until the display panel starts displaying. As a result, it is possible to shorten the time from the time when the control signal for transitioning from the pause mode to the display mode is received until an image is displayed on the display panel.

[0054] In the first configuration, the power control circuit may include a first power supply circuit that supplies power having a first voltage to the timing control circuit, the display panel, and the display drive circuit, a second power supply circuit that supplies power having a second voltage to the display panel, and a third power supply circuit that supplies power having a third voltage to the display drive circuit. The power control circuit may be configured to stop the supply of power by the second power supply circuit and the third power supply circuit while maintaining the supply of power by the first power supply circuit when the power control circuit receives the pause signal (second configuration).

[0055] According to the second configuration, the supply of power from the second power supply circuit and the third power supply circuit other than the first power supply circuit that supplies power to the timing control circuit is stopped, so that it is possible to stop part of the power supply to the display panel and the display driving circuit while maintaining the supply of power to the timing control circuit.

[0056] In the first configuration, the power control circuit may be configured, when it receives the pause signal, to stop the supply of power to the display panel and the display driving circuit while maintaining the supply of power to the timing control circuit (third configuration).

[0057] According to the third configuration, the supply of power to the display panel and the display drive circuit is stopped, so that power consumption in the pause mode can be reduced.

[0058] A display system according to a fourth configuration includes a display device having a display panel, and a host controller that transmits to the display device a first control signal for switching from a display mode in which the display panel displays to a pause mode in which the display panel stops displaying, and a second control signal for switching from the pause mode to the display mode, wherein the display device includes a display drive circuit that supplies a drive signal to the display panel, a timing control circuit that supplies an image signal to the display panel and supplies a timing signal to the display drive circuit, and a power control circuit that controls the display panel, the display drive circuit, and the timing control circuit between a state in which power is supplied and a state in which power supply is stopped. the timing control circuit receives the first control signal from the host controller, sends a pause signal to the power control circuit, and stops the supply of the timing signal to the display drive circuit, thereby stopping the supply of the drive signal from the display drive circuit to the display panel, and when the power control circuit receives the pause signal, it stops at least a portion of the supply of power to the display panel and the display drive circuit while maintaining the supply of power to the timing control circuit, and when the timing control circuit receives the second control signal from the host controller, it stops sending the pause signal to the power control circuit and supplies the timing signal to the display drive circuit (fourth configuration).

[0059] According to the fourth configuration, it is possible to provide a display system that can shorten the time from when a control signal for transitioning from the sleep mode to the display mode is received until an image is displayed on the display panel. [Explanation of symbols]

[0060] 1: display panel, 2, 202: timing control circuit, 3: level shifter circuit, 4, 204, 304: power control circuit, 10: display unit, 10a: pixel, 11: gate drive circuit, 11a: gate line, 12: source drive circuit, 12a: source line, 13: terminal, 14: thin film transistor, 15: pixel electrode, 21: receiver, 22: level shifter control unit, 23: image signal control unit, 24: recovery operation control unit, 25, 225: pause signal transmission unit, 41: voltage detection unit, 42, 342: power conversion unit, 42a: circuit voltage power supply unit, 42b: timing control circuit power supply unit, 42c: level shifter power supply unit, 42d: source drive circuit power supply unit, 42e: common electrode power supply unit, 43: reset signal control unit, 44, 244, 344: power supply circuit control unit, 100, 200, 300: display system, 101, 201, 301: display device, 102: host controller, 342aa: first circuit power supply unit, 342ab: second circuit power supply unit, 342ac: third circuit power supply unit, A1: image signal, B1: pause signal, C1: timing signal, D1: control signal

Claims

1. A display panel; a display drive circuit for supplying a drive signal to the display panel; a timing control circuit that supplies an image signal to the display panel and a timing signal to the display drive circuit; a power control circuit that controls a state in which power is supplied to each of the display panel, the display drive circuit, and the timing control circuit and a state in which power supply is stopped; The timing control circuit includes: sending a pause signal to the power control circuit when a control signal for transitioning from a display mode in which display is performed by the display panel to a pause mode in which display by the display panel is stopped is received from a host controller; stopping the supply of the timing signal to the display drive circuit, thereby stopping the supply of the drive signal from the display drive circuit to the display panel; when the power control circuit receives the pause signal, the power control circuit stops at least a part of the power supply to the display panel and the display drive circuit while maintaining the power supply to the timing control circuit; The timing control circuit includes: when receiving a control signal from the host controller to transition from the display mode to the pause mode, stopping transmission of the pause signal to the power control circuit; A display device that supplies the timing signal to the display drive circuit.

2. the power control circuit includes a first power supply circuit that supplies power having a first voltage to the timing control circuit, the display panel, and the display drive circuit, a second power supply circuit that supplies power having a second voltage to the display panel, and a third power supply circuit that supplies power having a third voltage to the display drive circuit; 2 . The display device according to claim 1 , wherein the power control circuit, when receiving the pause signal, stops the supply of power by the second power supply circuit and the third power supply circuit while maintaining the supply of power by the first power supply circuit.

3. 2 . The display device according to claim 1 , wherein the power control circuit, when receiving the pause signal, stops the supply of power to the display panel and the display drive circuit while maintaining the supply of power to the timing control circuit.

4. A display device having a display panel; a host controller configured to transmit to the display device a first control signal for switching from a display mode in which the display panel performs display to a pause mode in which the display panel stops display, and a second control signal for switching from the pause mode to the display mode, The display device includes: a display drive circuit for supplying a drive signal to the display panel; a timing control circuit that supplies an image signal to the display panel and a timing signal to the display drive circuit; a power control circuit that controls a state in which power is supplied to each of the display panel, the display drive circuit, and the timing control circuit and a state in which power supply is stopped; The timing control circuit includes: receiving the first control signal from the host controller; Sending a pause signal to the power control circuit; stopping the supply of the timing signal to the display drive circuit, thereby stopping the supply of the drive signal from the display drive circuit to the display panel; when the power control circuit receives the pause signal, the power control circuit stops at least a part of the power supply to the display panel and the display drive circuit while maintaining the power supply to the timing control circuit; The timing control circuit includes: when the second control signal is received from the host controller, stopping transmission of the pause signal to the power control circuit; A display system that supplies the timing signal to the display driver circuit.

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