Information processing method, information processing system, computation quantum circuit, computation quantum circuit generation method, and program

Abstract

To provide an information processing method, an information processing system, a computation quantum circuit, a computation quantum circuit generation method, and a program that are provided with quantum algorithms that acquire a desired state easily and efficiently.SOLUTION: A method includes steps of: acquiring information about an input state represented by n computation quantum bits, information about a Hamiltonian and a repetition number K (K is an integer equal to or greater than 2) of Hamiltonian-based calculation; and allocating, according to K, a plurality of auxiliary bits to generate, on the basis of the acquisition result, a computation quantum circuit operating an operation quantum circuit with respect to the computation quantum bits and the auxiliary bits. The operation quantum circuit is configured to operate on the n computation quantum bits and includes unit gate operations corresponding to each of the allocated auxiliary bits, uses one of a plurality of different auxiliary bits as a control bit for each unit gate operation, a computation quantum bit as a target bit, changes a mode of operation on the computation quantum bit according to a state of the auxiliary bit, and outputs, on the basis of an observation result of the auxiliary bit, a state of the computation quantum bit as a computation result.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present invention relates to an information processing method, a computational quantum circuit, a method for generating a computational quantum circuit as set forth in claim 10, an information processing system, and a program. [Background technology]

[0002] Quantum information processing using quantum mechanics for information processing has been proposed. In addition, many quantum computers based on such quantum information processing have been researched. For example, Patent Document 1 discloses conventional technology for quantum information processing. Non-patent documents are references. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-135377 A [Non-patent literature]

[0004] [Non-Patent Document 1] H. Nishi, K. Hamada, Y. Nishiya, T. Kosugi, and Y. ichiro Matsushita, Analyzing computational cost of probabilistic imaginary-time evolution method (2023), arXiv:2305.04600 [quant-ph]. Summary of the Invention [Problem to be solved by the invention]

[0005] However, there is still room for improvement in the technology for obtaining a desired state, such as the ground state, of a certain Hamiltonian. [Means for solving the problem]

[0006] According to one aspect of the present invention, there is provided an information processing method. This information processing method includes the following steps. In the acquisition step, information on an input state represented by n computational quantum bits, information on a Hamiltonian, and the number of iterations K (where K is an integer equal to or greater than 2) of an operation based on the Hamiltonian are acquired. In the allocation step, a plurality of auxiliary bits are allocated according to the number of iterations K. Here, the state of each of the n computational quantum bits and the plurality of auxiliary bits is configured to be expressible using at least a first state and a second state that are observable. In the generation step, a computational quantum circuit is generated based on the acquisition result in the acquisition step. The computational quantum circuit is configured to sequentially operate a first reflection operation, a first operational quantum circuit, a second reflection operation, and a second operational quantum circuit. The first reflection operation is configured to operate on the plurality of auxiliary bits so as to change the phase of a first reflection state, which is one of the components of the first state and the components of the second state included in each of the plurality of auxiliary bits. The first operational quantum circuit is configured to act on n computation qubits corresponding to an input state, and includes unit gate operations corresponding to each of the auxiliary bits. Each of the unit gate operations is configured to change the manner of acting on the computation qubit according to the state of the auxiliary bit, with one of a plurality of different auxiliary bits as a control bit and the computation qubit as a target bit. The second reflection operation is configured to act on the computation qubit and the auxiliary bit so as to change the phase of a second reflection state, which is one of the components of the first state and the components of the second state contained in each of the computation qubit and the auxiliary bit. The second operational quantum circuit is configured to be convertible into a Hermitian conjugate circuit of the first operational quantum circuit using a predetermined unitary gate operation.

[0007] This makes it possible to provide a quantum algorithm that makes it easier to obtain a desired state more efficiently. [Brief description of the drawings]

[0008] [Figure 1] 1 is a configuration diagram illustrating an information processing system 1. [Diagram 2] 2 is a block diagram showing a hardware configuration of an information processing device 2. FIG. [Diagram 3] FIG. 2 is a block diagram showing the hardware configuration of a quantum computer 3. [Figure 4] FIG. 2 is a block diagram showing the hardware configuration of a user terminal 4. [Diagram 5] 2 is a block diagram showing the functional configuration of a processor 23. FIG. [Figure 6] FIG. 13 is a diagram showing an example of a quantum circuit QC1 of a probabilistic algorithm for preparing the ground state of a Hamiltonian. [Figure 7] FIG. 2 is a diagram illustrating an example of a computational quantum circuit 5. [Figure 8] FIG. 1 is a diagram illustrating an example of VRTE. [Figure 9] FIG. 13 is a diagram showing a modified example of the VRTE. [Figure 10] 2 is a flowchart showing an overview of information processing executed in the information processing system 1. [Figure 11] FIG. 13 is a diagram showing a simulation result of the relationship between the calculation cost and the infidelity ΔK in each method for generating the ground state of the Hamiltonian H. [Figure 12] FIG. 13 is a diagram showing the simulation results of the relationship between the probability weight |c1|−1 of the ground state of the input state |ψ> and the calculation cost, using each method. [Figure 13] This is a quantum circuit that implements the time evolution operator exp(LΔt) with a general operator L as a generator. [Figure 14] This is a quantum circuit that implements the imaginary time evolution operator exp(-HΔτ) with a general Hermitian operator H as its generator. [Figure 15] This is an example of a quantum circuit QC2 corresponding to the cosine function operator cos(tkH). [Figure 16] FIG. 13 is a diagram showing an example of a computational quantum circuit in the case where a cosine function operator cos(tkH) is adopted as a probabilistic operation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. Various characteristic features shown in the following embodiments can be combined with each other.

[0010] Incidentally, the program for realizing the software appearing in this embodiment may be provided as a non-transitory computer-readable recording medium, or may be provided so as to be downloadable from an external server, or may be provided so that the program is started on an external computer and its functions are realized on a client terminal (so-called cloud computing).

[0011] In addition, in this embodiment, the term "unit" may include, for example, a combination of hardware resources implemented by a circuit in the broad sense and software information processing that can be specifically realized by these hardware resources. In addition, in this embodiment, various information is handled, and this information is represented, for example, by physical values ​​of signal values ​​representing voltage and current, high and low signal values ​​as a binary bit collection consisting of 0 or 1, or quantum superposition (so-called quantum bits), and communication and calculation can be performed on the circuit in the broad sense.

[0012] In addition, a circuit in the broad sense is a circuit realized by at least appropriately combining a circuit, circuitry, a processor, a memory, etc. In other words, it includes an application specific integrated circuit (ASIC), a programmable logic device (e.g., a simple programmable logic device (SPLD), a complex programmable logic device (CPLD), and a field programmable gate array (FPGA)), etc.

[0013] 1. Hardware Configuration In this section, a hardware configuration of the information processing system 1 according to this embodiment will be described. <Information Processing System 1> FIG. 1 is a configuration diagram showing an information processing system 1. The information processing system 1 includes an information processing device 2, at least one quantum computer 3, and a user terminal 4. The information processing device 2, the quantum computer 3, and the user terminal 4 are configured to be able to communicate with each other via a telecommunications line. In one embodiment, the information processing system 1 is made up of one or more devices or components. For example, if the information processing system 1 is made up of only the information processing device 2, the information processing system 1 can be the information processing device 2. These components will be described below.

[0014] <Information processing device 2> 2 is a block diagram showing a hardware configuration of the information processing device 2. The information processing device 2 includes a communication unit 21, a storage unit 22, and a processor 23, and these components are electrically connected via a communication bus 20 inside the information processing device 2. Each component will be further described.

[0015] <Communications Division 21> The communication unit 21 is preferably a wired communication means such as USB, IEEE1394, Thunderbolt (registered trademark), wired LAN network communication, etc., but may also include wireless LAN network communication, mobile communication such as 3G / LTE / 5G, BLUETOOTH (registered trademark) communication, etc. as necessary. In other words, it is more preferable to implement it as a collection of multiple communication means. In other words, the information processing device 2 may communicate various information from the outside via the communication unit 21 and the network.

[0016] <Storage section 22> The storage unit 22 stores various information defined by the above description. This can be implemented, for example, as a storage device such as a solid state drive (SSD) that stores various programs and the like related to the information processing device 2 executed by the processor 23, or as a memory such as a random access memory (RAM) that stores temporarily required information (arguments, arrays, etc.) related to the program calculations. The storage unit 22 stores various programs, variables, etc. related to the information processing device 2 executed by the processor 23.

[0017] <Processor 23> The processor 23 processes and controls the overall operations related to the information processing device 2. The processor 23 is, for example, a central processing unit (CPU) not shown. The processor 23 realizes various functions related to the information processing device 2 by reading out a predetermined program stored in the storage unit 22. That is, information processing by software stored in the storage unit 22 can be specifically realized by the processor 23, which is an example of hardware, and executed as each functional unit included in the processor 23. These will be described in more detail in the next section. The processor 23 is not limited to being single, and may be implemented with multiple processors 23 for each function. Also, a combination of these may be used.

[0018] <Quantum computer 3> Fig. 3 is a block diagram showing a hardware configuration of the quantum computer 3. As shown in Fig. 3, the quantum computer 3 has a communication unit 31, a quantum memory 32, and a quantum processor 33, and these components are connected via a communication bus 30 inside the quantum computer 3. The quantum computer 3 may include an error-tolerant quantum computer, an NISQ device, or both. The quantum computer 3 of this embodiment is a gate type. Each component will be further described below.

[0019] <Communications Division 31> The communication unit 31 is used by the quantum computer 3 to communicate information with other information processing devices (including classical computers, quantum computers, or computers that combine these) or peripheral devices.

[0020] <Quantum Memory 32> The quantum memory 32 stores various information defined by the above description. In particular, the quantum memory 32 stores various programs that can be read by the quantum processor 33 described below. The quantum memory 32 also stores, as necessary, information on the physical properties of a specific material related to the calculation of the quantum computer 3. The quantum memory 32 includes a plurality of quantum bits 320. The quantum bits 320 may be implemented by any method, such as nuclear spins, photons, ions, atoms, quantum dots, and superconducting Josephson devices. The quantum bits 320 include a calculation quantum bit 321 and an auxiliary bit 322. The quantum memory 32 may include a classical memory device.

[0021] The quantum bit 320 takes any state in a state space represented by at least two basis vectors. Each state of the quantum bit 320 in this embodiment is represented by a superposition of a basis vector |1> representing a first state and a basis vector |0> representing a second state. Each of the basis vectors |0>, |1> is configured to be observable. For convenience, the quantum bit 320 includes a computation quantum bit 321 and an auxiliary bit 322. In other words, each state of the n computation quantum bits 321 and the K auxiliary bits 322 is configured to be expressible using at least the first state |0> and the second state |1>, which are observable.

[0022] <Quantum Processor 33> The quantum processor 33 performs processing and control of the overall operation related to the quantum computer 3. The quantum processor 33 realizes various functions related to the quantum computer 3 by reading out a program stored in the quantum memory 32 or a predetermined program input via the communication unit 31. Note that, although a single quantum processor 33 is shown in FIG. 3, in reality, this is not limited to this, and multiple quantum processors 33 may be provided for each function. Also, a combination of these may be used.

[0023] Quantum processor 33 is configured to be able to execute various quantum operations that can be implemented on a quantum circuit on quantum bits 320. For example, the quantum circuit is configured to prescribe a series of quantum operations on quantum bits 320. The quantum operations include, for example, quantum gate operations and observation operations. The quantum gate operations correspond to unitary operations on the quantum state of quantum bits 320. The observation operations correspond to projection operations on the quantum state of quantum bits 320. In other words, a quantum circuit such as computational quantum circuit 5 described below can be considered a type of program that causes quantum computer 3 to execute a series of quantum operations.

[0024] <User terminal 4> Next, a hardware configuration of the user terminal 4 will be described. Fig. 4 is a block diagram showing the hardware configuration of the user terminal 4. The user terminal 4 includes a communication unit 41, a memory 42, a processor 43, a display unit 44, and an input unit 45, and these components are electrically connected via a communication bus 40 inside the user terminal 4. Descriptions of the communication unit 41, the memory 42, and the processor 43 will be omitted because they are similar to the descriptions of the respective units in the information processing device 2.

[0025] <Display section 44> The display unit 44 may be included in the housing of the user terminal 4 or may be externally attached. The display unit 44 displays a screen of a graphical user interface (GUI) that can be operated by the user. This is preferably implemented by using display devices such as a CRT display, a liquid crystal display, an organic EL display, and a plasma display according to the type of the user terminal 4.

[0026] <Input section 45> The input unit 45 may be included in the housing of the user terminal 4, or may be externally attached. For example, the input unit 45 may be implemented as a touch panel integrated with the display unit 44. If it is a touch panel, the user can input a tap operation, a swipe operation, or the like. Of course, a switch button, a mouse, a QWERTY keyboard, or the like may be adopted instead of the touch panel. That is, the input unit 45 accepts an operation input made by the user. The input is transferred as a command signal to the processor 43 via the communication bus 40, and the processor 43 can execute a predetermined control or calculation as necessary.

[0027] 2. Functional configuration of processor 23 In this section, a functional configuration of the processor 23 of the information processing device 2 according to this embodiment will be described. Fig. 5 is a block diagram showing the functional configuration of the processor 23. The processor 23 includes an acquisition unit 231, an allocation unit 232, a generation unit 233, a quantum operation unit 234, and an output unit 235.

[0028] <Acquisition part 231> The acquisition unit 231 is configured to be able to acquire various pieces of information related to quantum computing from the quantum computer 3 and the user terminal 4 as an acquisition step. The acquisition unit 231 is configured to be able to acquire various pieces of information by reading out various pieces of information stored in a storage area that is at least a part of the memory unit 22 and writing the read out information in a working area that is at least a part of the memory unit 22. The storage area is, for example, an area of ​​the memory unit 22 that is implemented as a storage device such as an SSD. The working area is, for example, an area that is implemented as a memory such as a RAM.

[0029] <Allocation unit 232> As an allocation step, the allocation unit 232 is configured to allocate at least a portion of the quantum bits 320 as computation quantum bits 321 and auxiliary bits 322 .

[0030] <Generation section 233> The generation unit 233 is configured to generate various information such as quantum circuits such as the computational quantum circuit 5 based on the acquired information, etc. A quantum circuit such as the computational quantum circuit 5 is an instruction related to a series of quantum operations to be performed by the quantum processor 33 on the quantum bit 320, and is a type of program. The computational quantum circuit 5 will be described in detail later.

[0031] <Quantum operation unit 234> The quantum operation unit 234 is configured to be able to execute various quantum operations on the quantum bits 320. For example, the quantum operation unit 234 causes the quantum processor 33 to execute a series of quantum operations on the quantum bits 320 based on the computational quantum circuit 5 generated by the generation unit 233. The quantum operation unit 234 may be configured to directly execute quantum operations on the quantum bits 320, or may be configured to transmit a command to cause the quantum processor 33 to execute quantum operations. The quantum operation unit 234 of this embodiment causes the quantum processor 33 to execute quantum operations by transmitting various quantum circuits such as the computational quantum circuit 5 described later to the quantum processor 33.

[0032] <Output section 235> As an output step, output unit 235 is configured to output a calculation result based on the quantum operation by quantum operation unit 234, for example, a state of calculation quantum bit 321 calculated by the quantum circuit.

[0033] 3. Theory This section provides an overview of the theory behind this information processing.

[0034] 3.1 Quantum algorithms for obtaining the desired state Here, as an operation, a non-unitary operation f(H) based on a Hamiltonian H in a system consisting of n computational quantum bits 321 is discussed. The non-unitary operation f(H) is incorporated into the following extended unitary matrix U by introducing one auxiliary bit 322.

number

[0035] Here, the non-unitary matrix U is expressed as a submatrix related to a desired state and a state orthogonal thereto. The desired state is, for example, a state in which the auxiliary bit 322 is observed as a |0> state. The orthogonal state is, for example, a state in which it is observed as a |1> state. When an input state |ψ>*|0> is input, the following state is derived by the action of the unitary matrix U. In this specification, the operation symbol "*" generally represents a Kronecker product.

number

[0036] Any unitary matrix U can be decomposed to at least the first order of the Hamiltonian H, and the forward real-time evolution operator U RTE and the inverse real-time evolution operator U RTE † and one-qubit gate operations.

[0037] FIG. 6 is a diagram showing an example of a quantum circuit QC1 of a probabilistic algorithm for preparing a ground state of a Hamiltonian. The quantum circuit QC1 of this embodiment is configured to act on an n+1 quantum bit system composed of n computational quantum bits 321 and one auxiliary bit 322. The initial state of the n quantum bit system is a predetermined input state |ψ>, and the initial state of the auxiliary bit 322 is the |0> state. The quantum circuit QC1 first performs a predetermined unitary operation (e.g., a Hadamard gate operation and a W gate operation) on the auxiliary bit 322 to generate the auxiliary bit 322 in a superposition state of the |0> state and the |1> state. Then, the quantum circuit QC1 performs different operations on the input state |ψ> depending on the state of the auxiliary bit 322. For example, when the auxiliary bit 322 is in the |0> state, the quantum circuit QC1 performs a forward real-time evolution operator U RTE When the auxiliary bit 322 is in the |1> state, the inverse real-time evolution operator U RTE † Such an operation can be implemented, for example, by using a control gate operation in which the auxiliary bit 322 is a control bit and the n computation quantum bits 321 are target bits. The quantum circuit QC1 is then configured to perform a further predetermined unitary operation (for example, a W-gate operation. The W-gate operation is defined in Equation 24 described later) on the auxiliary bit 322, and then to perform an observation operation on the auxiliary bit 322. In this way, a quantum operation that probabilistically changes the operation mode when performing a certain operation is sometimes called a probabilistic quantum operation. When the auxiliary bit 322 is observed as a |0> state, the state of the computation quantum bit 321 can take a state in which f(H) has acted on the input state |ψ>. This makes it possible to extract a state in which f(H) has been successfully acted on the input state |ψ> using the quantum circuit QC1.

[0038] When the unitary operation U is operated multiple times, the unitary operation U includes various parameters such as the size of the imaginary time step Δτ. These parameters can be arbitrarily selected in each step in which the unitary operation U is operated. Hereinafter, for convenience of explanation, the unitary operation U in the kth step is referred to as U k Using K auxiliary bits, U k , and perform the unitary operation U k When the above is executed for k=1 to K, the input state |ψ> and the state |0> of the K auxiliary bits 322 are *K changes as follows:

number

[0039] F K (H) is f k (H) is an operator that applies (H) in sequence and is expressed as follows.

number

[0040] The fact that the k-th auxiliary bit 322 is observed in the |0> state means that f k This means that the operation of (H) was successful. Therefore, the |0> state in the auxiliary bit 322 means that f k This means a successful state in which (H) has been successfully calculated on a quantum bit system consisting of the computation quantum bit 321. For convenience of explanation, the |0> state of the auxiliary bit 322 may be referred to as a successful state below. Note that by observing and initializing the auxiliary bit 322 used in the previous step, and then reusing the initialized auxiliary bit 322, such repeated processing can be performed with a smaller number of auxiliary bits 322. Note that, k An example of (H) is the approximate imaginary time evolution operator exp(―Δτ k H) and the cosine function operator cos(t k H) and others. kis the time step width for real-time evolution. By using such a quantum circuit QC1, the state of the computation qubit 321 can be led to an energy eigenstate of the Hamiltonian H, and a desired state for a problem to be solved can be obtained using the computation qubit 321. For example, when solving a problem for finding the minimum energy or ground state of the Hamiltonian H, the desired state of the computation qubit 321 is the ground state. At this time, such a problem can be solved by the operation f k By repeatedly applying (H), it is possible to decay components of states other than the desired state (hereinafter, for convenience of explanation, may be referred to as undesired states) contained in the computation quantum bit 321. The undesired state may be, for example, an excited state. Such quantum information processing can also be used as a method of expressing a decay function having a peak in a certain state. The certain state may be, for example, an eigenstate of the Hamiltonian H, and may be either the ground state or an excited state other than the ground state (for example, a first excited state).

[0041] By observing all K ancillary bits 322 as |0> states, the entangled wave function converges to the following state:

number

[0042] P K indicates the total success probability. The total success probability is the probability that the auxiliary bit 322 is observed in the |0> state in all steps from k=1 to K. The input state |ψ> is the i-th eigenstate |λ i > can be expanded as follows:

number

[0043] c i is the i-th eigenstate |λ iFor convenience of explanation, we will treat each eigenstate as non-degenerate, but the same discussion will be valid even if there are degenerate eigenstates. i > are set in ascending order of i with respect to their energy eigenvalues.

[0044] F K If (H) is configured to dampen undesired states, then the total success probability P K is expressed as follows:

number

[0045] δ K is the infidelity that represents the calculation accuracy, and is expressed as follows:

number

[0046] For the sake of convenience, we will use F K (λ1)=1. K can be realized, for example, by performing a certain energy shift in the stochastic imaginary time evolution method. The energy shift is R z Gate operation rotation angle 2θ k , given energy value E k and the parameter s introduced in the approximation of the stochastic imaginary time evolution operator k Using 2(θ k +Δτ k s k E k ) to improve the overall success rate of quantum amplitude amplification. For details of the energy shift, please refer to Non-Patent Document 1. k Infidelity δ by (H) K A quantum algorithm that decays unwanted states to reduce the amount of Kis O(|c1| 2 ) The total success probability P K The scaling of f k (H) type, the number of auxiliary bits 322, and the non-unitary operation f k This holds true regardless of the quantum circuitry required to implement (H). For example, when the approximate ground state is unknown, e.g., |c i | 2 For =1 / N, the non-unitary operation {f k The computational cost of successfully applying at least one of the non-unitary operations f(H)} to the input state |ψ> scales as O(N). This tendency is seen in so-called stochastic operations, where applying a non-unitary operation f(H) to the computation qubit 321 is probabilistically successful, particularly depending on the state of the ancillary bit 322. In other words, the operation is a stochastic operation that can be expressed as being successful or not depending on the state of the ancillary bit 322.

[0047] When the above probabilistic method is used with a CRTE gate (controlled real-time evolution gate), the computational cost is limited to polynomials, and quantum acceleration can be effectively promoted. For example, e Circuit depth d required for CRTE gates in electronic systems CRTE scales in the following order:

number

[0048] Here, Δx represents the grid spacing of the discretized space. The computational cost at this time is expressed as follows:

number

[0049] 3.2 How to combine a multi-step scheme for probabilistic algorithms and quantum amplitude amplification (QAA) As a method for achieving further quantum acceleration in the above-mentioned operations (particularly stochastic operations), for example, there is a method for improving the observation probability of a successful state by quantum amplitude amplification. In this section, a method for combining the above-mentioned multi-step scheme related to a stochastic algorithm for obtaining the ground state of Hamiltonian H with quantum amplitude amplification (QAA) is described. Note that the following method is not limited to the ground state, but can also be appropriately used to obtain any state, for example, an eigenstate other than the ground state or a superposition state thereof. Also, the following method is not limited to operations corresponding to stochastic algorithms, but can be applied to operations corresponding to any algorithm.

[0050] The multi-step scheme is a method of repeating an operation based on the Hamiltonian H a predetermined number of times. In the following description, the number of repetitions of the operation is K. At this time, a number of auxiliary bits 322 corresponding to the number of repetitions K are used. The number of auxiliary bits 322 used in quantum amplitude amplification is arbitrary, and may be 2 or more, or K or more. Here, the number of auxiliary bits 322 is K, which is equal to the number of repetitions K. This makes it possible to reduce the number of required quantum bits while suppressing an increase in the quantum circuit depth when performing quantum amplitude amplification. For convenience of explanation, the following description will be given of a case where K auxiliary bits 322 are used.

[0051] Each auxiliary bit 322 is associated with each step of the probabilistic algorithm (operation). After the probabilistic algorithm is executed, an observation operation is performed on all of the auxiliary bits as the final step. The output state |Ψ~> of the (n+K)-qubit system consisting of n computational qubits 321 and K auxiliary bits 322 before the observation operation is expressed as follows. Note that a is a real number greater than 0 and less than 1.

number

[0052] Also, |Ψ bad > is |Ψ good>. Note that these "good" and "bad" are merely symbols for convenience, bad > are also available to the algorithm depending on the allowable error. good |0> is an example of a second reflection state, and indicates that a state in which K operations on the computation quantum bit 321 have been successful and a state in which all of the ancillary bits 322 are in the |0> state are separable states.

[0053] In one embodiment, quantum amplitude amplification is achieved by applying the amplitude amplification operator m times to the desired state |Ψ good The coefficient of > can be amplified. The amplitude amplification operator is defined as follows:

number

[0054] where Q(φ 2i-1 ,φ 2i ) is defined as follows:

number

[0055] Here, S χ is the oracle operation, S0 is the zero reflection operation, and U REF (K) is defined as follows:

number

[0056] Rotation angle {φ i Each of the rotation angles {φ i} is determined so that the increase in the success probability is an approximate sign function. Specifically, it is determined as follows:

number

[0057] In the above formula, δ represents the calculation accuracy of the success probability, and a smaller δ is preferable. The smaller the ratio of successful states included in the input state |ψ>, the larger the number of iterations m of the amplitude amplification operator must be. In other words, the rotation angle {φ i} can be determined based on the number of iterations m of the amplitude amplification operator.

[0058] Zero Reflection S0 (n) (φ) and oracle operation S χ (φ) means |Ψ good > and |Ψ bad In the effective two-dimensional space with basis vectors |Ψ~>, we rotate the output state |Ψ~> of the (n+K) qubit system. (n) (φ) and oracle operation S χ (φ) is expressed as follows:

number

[0059] The circuit depth of the zero reflection operation scales in the order of O(n) by introducing a new auxiliary bit 322 .

[0060] 3.3 About computational quantum circuits5 In this section, a computational quantum circuit 5 will be described as a quantum circuit for combining a multi-step scheme related to the stochastic imaginary time evolution method (PITE method), which is the above-mentioned probabilistic algorithm, with quantum amplitude amplification (QAA). FIG. 7 is a diagram showing an example of the computational quantum circuit 5. The computational quantum circuit 5 of this embodiment is also an expression of formula (9) as a quantum circuit, and functions as an amplitude amplification operator in a probabilistic algorithm for outputting the ground state of a predetermined Hamiltonian H. The probabilistic algorithm in this embodiment is the stochastic imaginary time evolution method (PITE method).

[0061] The computation quantum circuit 5 is configured to operate on at least one computation quantum bit 321 and at least K auxiliary bits 322 that are input. The number of computation quantum bits 321 can be set arbitrarily depending on the specific aspect of the computation, and is set to n here. The number of auxiliary bits 322 is set to K so as to correspond to the number of repetitions K of the computation. Therefore, the computation quantum circuit 5 is configured to cause the quantum processor 33 to execute a series of operations based on the Hamiltonian on the (n+K)-qubit system together with quantum amplitude amplification. The computation quantum circuit 5 is configured to operate the first reflection operation 51, the first operational quantum circuit 52, the second reflection operation 53, and the second operational quantum circuit 54 in sequence.

[0062] The first reflection operation 51 is configured to act on the multiple auxiliary bits 322 so as to change the phase of a first reflection state, which is one of the components of the first state |0> and the second state |1>, contained in each of the multiple auxiliary bits 322. The first reflection operation 51 may be configured to act individually on each of the multiple auxiliary bits 322. Also, for example, the first reflection operation 51 may change the phase of |Ψ as the first reflection state. good The first reflection operation 51 may be configured to rotate, for example, invert, the phase of the entire (n+K)-qubit system (global phase). The first reflection operation 51 rotates, for example, inverts, the sign of the component of the state of the ancillary bit coupled to |0> (in this embodiment, the first state |0>). χ (φ 2i In this embodiment, the |0> state is inverted, so this can be said to be a zero reflection to the auxiliary bit 322. In this embodiment, the rotation angles of the first reflection operation 51 are φ, φ 2i = π.

[0063] The first operational quantum circuit 52 is configured to operate on n computation qubits 321 corresponding to the input state |ψ>. The first operational quantum circuit 52 receives the input state |ψ> and the qubit states of the K auxiliary bits 322 on which the first reflection operation 51 has been performed. The first operational quantum circuit 52 operates by (UREF (K) ) † The first operational quantum circuit 52 includes K unit gate operations 522. The first operational quantum circuit 52 may further include an input transformation operation 521 and an output transformation operation 523.

[0064] The input transformation operation 521 is a one-qubit operation configured to act on each auxiliary bit 322 and to appropriately superpose the |0> and |1> states of each auxiliary bit 322. For example, the input transformation operation 521 may be a W gate operation and a z rotation gate operation R Z † z Rotary gate operation R Z † Rotation angle 2θ k is expressed as, for example, Equation 23 described later, and may be determined according to the expansion mode of the non-unitary operator.

[0065] After the input transformation operation 521 is applied to each of the auxiliary bits 322, a unit gate operation 522 is performed for each auxiliary bit 322. RTE Each of the unit gate operations 522 of the first operational quantum circuit 52 is configured to use one of a plurality of different auxiliary bits 322 as a control bit, the computation quantum bit 321 as a target bit, and change the mode of action on the computation quantum bit 321 according to the state of the auxiliary bit 322. In this embodiment, the unit gate operation 522 is configured to use a forward real-time evolution operator U RTE or the inverse real-time evolution operator U RTE † In FIG. 7, V RTE † (V RTE V RTE is a forward real-time evolution operator U RTEWhen the control bit (auxiliary bit 322) is in an undesired state (|1> state), the forward real-time evolution operator U RTE V RTE The desired state of is constructed to match the reflection state of the reflection operation that is performed immediately before it. Such a desired state is constructed by applying the forward real-time evolution operator U RTE This indicates that the operation of V has been successful, and is also called a successful state. RTE The Hermitian conjugate of V RTE † Therefore, when the corresponding auxiliary bit 322 is in the desired state |0>, the inverse real-time evolution operator U RTE † When the corresponding auxiliary bit 322 is in the undesired state |1>, the forward real-time evolution operator U RTE to the computation qubit 321. In other words, each of the unit gate operations 522 is configured to operate on the computation qubit 321 as a unit operation or a Hermitian conjugate operation of the unit operation, depending on the state of the ancillary bit 322. RTE or the inverse real-time evolution operator U RTE † The computation qubit 321 may be configured to operate on either one of the following: RTE (or the inverse real-time evolution operator U RTE † ) is configured to correspond to performing the operation once, where the desired state of the unit gate operation 522 may coincide with the first reflection state of the first reflection operation 51.

[0066] As shown in FIG. 7, after a total of K unit gate operations 522, an output conversion operation 523 is performed. The output conversion operation 523 performs a Hermitian operation of a W gate (W † The hologram is configured to sequentially perform a multiplication operation (H) and a Hadamard gate operation (H).

[0067] The first operational quantum circuit 52 includes a reference circuit 524 (specifically, a reference circuit 524 (U ref ) Hermitian operation reference circuit U ref † ). The reference circuit 524 is configured to act on the computation quantum bit 321 and to output an input state |ψ> based on the initialized state of the computation quantum bit 321. The states of the n computation quantum bits 321 after K unit gate operations 522 are operated according to the state of the ancillary bit 322 are input to the reference circuit 524. In particular, the states of the n computation quantum bits 321 output from the first operational quantum circuit 52 other than the reference circuit 524 are input to the reference circuit 524. Hereinafter, for convenience of explanation, the initialized states of the n computation quantum bits 321 may be simply referred to as the initial state. The reference circuit 524 is a quantum circuit for generating an input state |ψ> from the overall state of the n computation quantum bits 321 of the (n+K) quantum bits 320 input to the first operational quantum circuit 52. In particular, the reference circuit 524 generates an input state |ψ> from the overall state of the n computation quantum bits 321 of the (n+K) quantum bits 320 input to the first operational quantum circuit 52. In particular, the reference circuit 524 generates an input state |ψ> based on the initial state |0> *n By inputting |ψ>, an n-qubit system composed of a desired input state |ψ> is generated. This generates a state of an (n+K)-qubit system composed of the input state |ψ> and K auxiliary bits 322 set to |0>.

[0068] The reference circuit 524 can be appropriately set according to the input state |ψ> to be generated. For example, the reference circuit 524 is configured to calculate, for each of the computation qubits 321, quantum gate operations corresponding to the amplitude difference and phase difference of the components of the first state |0> between the initial state and the input state |ψ>, and the amplitude difference and phase difference of the components of the second state |1> between the initial state and the input state |ψ>. The reference circuit 524 outputs |ψ>*|0> to the computation quantum circuit 5 (specifically, the first operational quantum circuit 52). *KThe reference circuit 524 functions as a quantum circuit for inputting the state of a (n+K) quantum bit system represented by |ψ>. With this configuration, by setting an appropriate input state |ψ> for the Hamiltonian H in advance, it is possible to obtain a highly accurate calculation result with a smaller number of operations. The reference circuit 524 is configured to be executed before the first operational quantum circuit 52.

[0069] The state output from the first operational quantum circuit 52 is input to the second reflection operation 53. The second reflection operation 53 is configured to act on the computation quantum bit 321 and the auxiliary bit 322 so as to change the phase of a second reflection state, which is one of the components of the first state |0> and the components of the second state |1> contained in each of the computation quantum bit 321 and the auxiliary bit 322. The state of the auxiliary bit 322 contained in the first reflection state and the state of the auxiliary bit 322 contained in the second reflection state are a common state. In other words, the K-qubit state |0> constituted by K auxiliary bits 322 as the first reflection state is *K and a state |0> of a K-qubit system, which is a subset of the (n+K)-qubit system including the n computation qubits 321 and the K auxiliary qubits 322 as a second reflection state. *K Therefore, the "common state" does not mean that the states of the entire system input to the first reflection operation 51 and the second reflection operation 53 are the same.

[0070] The second reflection operation 53 is the zero reflection S0 in equation (9). n+K (φ 2i+1). It is not necessary for the first reflection state and the second reflection state to be the same, as long as there is a corresponding relationship based on a predetermined unitary operation. For example, the first reflection state may be the |0> state, and the second reflection state may be the |1> state. The phase of the first reflection operation 51 may be inverted with respect to the phase of the second reflection operation 53. With this configuration, it is possible to achieve phase matching and further promote quantum acceleration. In this embodiment, the rotation angle (global phase) φ of the second reflection operation 53 is 2i+1 =0, the phase of the first reflection operation 51 and the rotation angle (phase) of the second reflection operation 53 are inverted. The reference circuit 544 may be incorporated in the second reflection operation 53, not in the first operational quantum circuit 52. In this case, the second reflection operation 53 may be configured to perform zero reflection, which changes the input state |ψ> to the computational quantum circuit 5 into a |0> state, by appropriately unitarily transforming the state output from the first operational quantum circuit 52 by the reference circuit 544.

[0071] The state output from the second reflection operation 53 is input to the second operational quantum circuit 54. The second operational quantum circuit 54 is configured so as to be convertible into a Hermitian conjugate circuit of the first operational quantum circuit 52 using a predetermined unitary gate operation. For example, the second operational quantum circuit 54 is configured to be Hermitian conjugate with the first operational quantum circuit 52, and U REF (K) The second operational quantum circuit 54, like the first operational quantum circuit 52, includes an input conversion operation 541, K unit gate operations 542, an output conversion operation 543, and a reference circuit 544. The input conversion operation 541 is a Hermitian conjugate of the output conversion operation 523. The unit gate operation 542 is a Hermitian conjugate of the unit gate operation 522. The output conversion operation 543 is a Hermitian conjugate of the input conversion operation 521. The reference circuit 544 (U ref) is the Hermitian conjugate of the reference circuit 524. Of the state output from the second reflection operation 53, the portion of the auxiliary bit 322 is input to the input conversion operation 541, and the portion of the computation quantum bit 321 is input to the reference circuit 544. Thereafter, the states output from the input conversion operation 541 and the reference circuit 544 are input to K unit gate operations 542. After the operation of the K unit gate operations 542, the output state is output from the second operation quantum circuit 54 via the output conversion operation 543. Here, the unit gate operation 542 will be described, and the explanations of the input conversion operation 541, the unit gate operation 542, and the reference circuit 544 will be omitted as they are similar to those of the first operation quantum circuit 52.

[0072] The unit gate operation 542 of the second operation quantum circuit 54 is configured to be Hermitian conjugate with the unit gate operation 522 of the first operation quantum circuit 52. In this embodiment, the unit gate operation 542 is configured to be Hermitian conjugate with the unit gate operation 522 of the first operation quantum circuit 52. RTE or the inverse real-time evolution operator U RTE † Either one of the two acts. V RTE The desired state of the unit gate operation 541 is configured to match the reflected state of the reflection operation performed immediately before it. Here, the desired state of the unit gate operation 542 is configured to match the second reflected state (|0> state) of the second reflection operation 53. With this configuration, the computational quantum circuit 5 can be further simplified and the number of operations included in the computational quantum circuit 5 can be reduced.

[0073] The computational quantum circuit 5 may further include an observation operation 55. The observation operation 55 is configured to observe the state of each of the auxiliary bits 322 functioning as the control bit of the unit gate operation 522. With this configuration, a final state in which time evolution by each time-evolution gate operation is appropriately performed can be output as a computation result. Of the states output from the second computational quantum circuit 54, the observation operation 55 is performed on the part of the auxiliary bits 322. As a result, the state of the auxiliary bits 322 is projected to the state observed by the observation operation 55, and accordingly, the state of the computational quantum bit 321 is contracted to the state in which K operations are successful a predetermined allowable number of times or more. Here, the number of auxiliary bits 322 in which the second reflection state (|0> state) is observed indicates the number of times that the operation acts on the input state |ψ>. For example, the observation of the |0> state for all K auxiliary bits 322 means that all K operations have been performed on the input state |ψ>.

[0074] In this way, the state output from the computation quantum circuit 5 is a state in which an operation has been applied to the input state |ψ> in accordance with the observation result of the auxiliary bit 322. For ease of explanation, the state of the n computation quantum bits 321 output from the computation quantum circuit 5 will be referred to as a final state below.

[0075] In summary, the computational quantum circuit 5 is configured to repeat an operation based on the Hamiltonian K times for an input state |ψ> represented by n computational quantum bits 321 (where K is an integer equal to or greater than 2), and is configured to act on the n computational quantum bits 321 and the multiple auxiliary bits 322 according to K. Here, the respective states of the computational quantum bits 321 and the auxiliary bits 322 are configured to be expressible using at least a first state and a second state that are observable. The computational quantum circuit 5 is configured to act on the first reflection operation 51, the first operational quantum circuit 52, the second reflection operation 53, and the second operational quantum circuit 54 in sequence. The first reflection operation 51 is configured to act on the multiple auxiliary bits 322 so as to change the phase of the first reflection state, which is one of the components of the first state and the components of the second state included in each of the multiple auxiliary bits 322. The first operational quantum circuit 52 is configured to act on n computation qubits 321 corresponding to the input state |ψ>, and includes unit gate operations 522 corresponding to each of the auxiliary bits 322. Each of the unit gate operations 522 is configured to change the manner of action on the computation qubit 321 according to the state of the auxiliary bit 322, with one of the different auxiliary bits 322 as a control bit and the computation qubit 321 as a target bit. The second reflection operation is configured to act on the computation qubit and the auxiliary bit so as to change the phase of a second reflection state, which is one of the components of the first state and the components of the second state included in each of the computation qubit and the auxiliary bit. The second operational quantum circuit 54 is configured to be convertible into a Hermitian conjugate circuit of the first operational quantum circuit using a predetermined unitary gate operation.

[0076] According to this configuration, quantum amplitude amplification can be performed with at least one different auxiliary bit 322 assigned to each step of time evolution, so that it is possible to suppress an increase in the depth of the quantum circuit accompanying an increase in the number of repetitions, compared to the case where quantum amplitude amplification is performed using one auxiliary bit 322. Therefore, quantum acceleration can be promoted.

[0077] 3.4 Modifications of computational quantum circuit 5 It should be noted that the computational quantum circuit 5 described above is merely an example, and the specific embodiment is not limited to that shown in FIG.

[0078] The phase φ of the first reflection operation 51 and the second reflection operation 53 2i , φ 2i+1 is optional.

[0079] The first and second reflection states are arbitrary as long as they can be associated with each other by a unitary transformation or the like. In other words, the first and second operational quantum circuits 52 and 54 are not limited to being Hermitian conjugates to each other, and may include various arbitrary elements such as the arbitrariness of the global topology and the arbitrariness of the selection of the basis. In other words, the first and second operational quantum circuits 52 and 54 may be constructed to be Hermitian conjugates according to various arbitrary elements.

[0080] In the above embodiment, the unit gate operations 522 and 542 are implemented using the stochastic operator V RTE † and V RTE However, it is possible to use any probabilistic operator or even a general operator.

[0081] The construction method of the probabilistic operator is V RTE Not limited to, the operation modes are different between |0> state and |1> state (especially, U RTE With forward operators such as U RTE † ) to act on the computation qubit 321. RTE 9 is a diagram showing a modified example of the V shown in FIG. RTE V shown in Figure 8 RTE To distinguish it from V RTE It is sometimes written as '. RTE ' is a forward real-time evolution operator U RTE is applied to the computation qubit 321. Then, V RTE' does not perform any operation (in other words, performs an identity operation) when the auxiliary bit 322 is in the |0> state, and performs the inverse real-time evolution operator U RTE † This causes the V shown in Figure 8 to RTE A similar calculation can be performed.

[0082] 4. Information processing method In this chapter, the flow of information processing executed in the information processing system 1 will be described based on the above-mentioned theory. The results of the processing in each step included in the information processing described below can be output in a manner that can be recognized by the user using the display unit 44 or the like as appropriate. The information processing may include any exception processing not shown. Exception processing includes the interruption of the information processing and the omission of each process. Selection or input performed in the information processing may be based on a user operation or may be performed automatically without relying on a user operation. FIG. 10 is a flowchart showing an overview of the information processing executed in the information processing system 1.

[0083] [Step S1] First, in step S1, the acquisition unit 231 executes an acquisition process to acquire information on the input state, information on the Hamiltonian H, and the number of iterations K of the calculation based on the Hamiltonian H. In this embodiment, K is an integer equal to or greater than 2. The information on the input state |ψ> includes, for example, information on the components of the system described by the Hamiltonian H. The components of the system include, for example, the particle species included in the system, the number of each particle species, the position resolution of each particle, and the like.

[0084] [Step S2] Next, in step S2, the allocation unit 232 allocates the computational quantum bits 321 and the auxiliary bits 322 used in the quantum computation based on the result obtained in step S1. For example, the allocation unit 232 calculates the number n of computational quantum bits 321 required to express the input state |ψ> based on information on the input state |ψ>, and allocates n computational quantum bits 321 from among the quantum bits 320 based on the number n. As a result, the input state |ψ> of this embodiment is expressed by n computational quantum bits 321. Also, for example, the allocation unit 232 allocates at least K auxiliary bits 322 from among the quantum bits 320 used in the operation of the computational quantum circuit 5 described later based on the number of iterations K. In this embodiment, the allocation unit 232 allocates K auxiliary bits 322.

[0085] [Step S3] Next, the process proceeds to step S3, where the processor 23 executes an initialization process and performs preprocessing for generating an input state |ψ> to be input to the computational quantum circuit 5, which will be described later.

[0086] First, the quantum operation unit 234 transmits a command to the quantum processor 33 to initialize the states of the assigned n computation quantum bits 321 and K auxiliary bits 322 to a predetermined initial state. Based on the command, the quantum processor 33 initializes the n computation quantum bits 321 and the K auxiliary bits 322. The initial state may be defined as, for example, a state in which the respective states of the n computation quantum bits 321 and the K auxiliary bits 322 are both in the first state |0>, but is not limited to this and may be any state.

[0087] [Step S4] Next, in step S4, the generation unit 233 performs a generation process to generate a computational quantum circuit 5 based on the result acquired by the acquisition unit 231. The computational quantum circuit 5 of this embodiment is generated as an instruction for causing the quantum computer 3 to perform a quantum operation. Here, an example of a process for generating the computational quantum circuit 5 will be described.

[0088] First, the generation unit 233 starts the initialization process (in this embodiment, |0> *(n+K) ) and the input state |ψ>, the reference circuit U ref For example, the generation unit 233 compares each component of the initialization state and the input state |ψ>, and generates a reference circuit U by combining unitary gate operations to perform an operation on each of the computation qubits 321 based on the phase difference and the amplitude difference between these states. ref It is sufficient to generate

[0089] In addition, the generation unit 233 generates V RTE (For details, see RTE and its Hermitian conjugate U RTE † The generating unit 233 generates the generated V RTE , the success state is set for each of the two types of unit gate operations 522, 542. As a result, the unit gate operations 522, 542 are defined. The generation unit 233 sets the unit gate operations 522, 542 defined in this way, with each of the K auxiliary bits 322 as a control bit. Note that the input conversion operations 521, 541 and the output conversion operations 523, 543 may be preset or may be appropriately adjusted in parameters based on the acquired results. The generation unit 233 generates the first operational quantum circuit 52 using the input conversion operation 521, unit gate operation 522, output conversion operation 523, and reference circuit 524 defined in this way. Similarly, the generation unit 233 generates the second operational quantum circuit 54.

[0090] Next, the generation unit 233 generates a first reflection operation 51 so that the success state of the unit gate operation 522 corresponds to the first reflection state. In addition, the generation unit 233 generates a second reflection operation 53 so that the success state of the unit gate operation 542 corresponds to the second reflection state. In addition, the generation unit 233 generates an observation operation 55 so as to observe the state output from the second operational quantum circuit 54 for each of the K auxiliary bits 322.

[0091] The generation unit 233 generates a computational quantum circuit 5 as shown in FIG. 7 based on the first reflection operation 51, the first operational quantum circuit 52, the second reflection operation 53, the second operational quantum circuit 54, and the observation operation 55 thus generated. In other words, the information processing method includes a method for generating a computational quantum circuit 5. The generation method is a method for generating a computational quantum circuit 5. In the acquisition step, information on the input state |ψ>, information on the Hamiltonian, and the number of repetitions K of the operation based on the Hamiltonian are acquired. The number of repetitions K corresponds to K, which is the number of unit gate operations 522. In the allocation step, a plurality of auxiliary bits 322 corresponding to the number of repetitions are allocated. In the generation step, a computational quantum circuit 5 configured to repeatedly perform an operation on the computational quantum bit 321 is generated based on the result acquired in the acquisition step. The method for generating a computational quantum circuit 5 is a method for generating a so-called program, which is a command code for causing the quantum processor 33 to execute a specified quantum operation.

[0092] [Step S5] Next, the process proceeds to step S5, where the quantum operation unit 234 causes the quantum processor 33 to execute a series of quantum operations based on the computational quantum circuit 5 and the like. As a result, a series of quantum operations defined by the computational quantum circuit 5 and the like are executed on the assigned computational quantum bit 321 and auxiliary bit 322, the portion of the computational quantum bit 321 in the initialization state transitions to the input state |ψ>, and K operations are repeated while quantum amplitude amplification is performed. Thereafter, the final state output from the computational quantum circuit 5 is observed by the observation operation 55. At this time, the quantum operation unit 234 counts the number of successful states (|0> states) observed in the portion of the auxiliary bit 322 among the final states output from the computational quantum circuit 5.

[0093] [Step S6] Thereafter, the process proceeds to step S7, where the processor 23 determines whether the observed state of the auxiliary bit 322 satisfies a predetermined output condition. The output condition is a condition for determining whether to output the final state as a calculation result, and is defined, for example, by the degree of success of the operation repeatedly performed on the calculation quantum bit 321. For example, the output condition is configured to be satisfied when the number of observed successful states is equal to or greater than a preset value. The preset value is set appropriately according to, for example, the required calculation accuracy, calculation time, etc., and is at most K (when successful states are observed in all the auxiliary bits 322). The successful state may correspond to a desired state (|0> state) in the second calculation quantum circuit 54, that is, the second reflection state. Correspondence of a certain state to another state means that they can be mutually converted by, for example, a unitary operation, etc.

[0094] [Step S7] If the determination result in step S6 is positive, i.e., if it is determined that the output condition is satisfied, the process proceeds to step S7, where the states (final states) of the n computation quantum bits 321 after observation by observation operation 55 are output as the computation result. In other words, output unit 235 outputs the states of computation quantum bits 321 as the computation result based on the observation result of ancillary bits 322 (after second operational quantum circuit 54 is operated).

[0095] Thereafter, the information processing system 1 ends this information processing. The output calculation result may be used in any manner. For example, the calculation result may be used to identify the final state by an observation operation, or may be used as an input state to another quantum circuit. Furthermore, information related to the calculation result (such as the observation result of the calculation quantum bit 321) may be appropriately stored in the storage unit 22 or the like.

[0096] [Step S8] On the other hand, if the determination result in step S6 is negative, that is, if it is determined that the output condition is not satisfied, the process proceeds to step S8, where the processor 23 discards the final state.

[0097] [Step S9] Thereafter, the processor 23 determines whether or not to perform recalculation. Whether or not to perform recalculation can be appropriately determined based on, for example, the time available for calculation, the upper limit of the number of calculations, etc. If it is determined that recalculation is not necessary, the information processing system 1 ends this information processing.

[0098] [Step S10] On the other hand, if the determination result in step S10 is positive, the quantum operation unit 234 initializes the computation quantum bit 321 and the auxiliary bit 322. Thereafter, the process returns to step S6, and the quantum operation unit 234 causes the quantum processor 33 to again execute a quantum operation based on the computation quantum circuit 5, etc. In this way, the information processing system 1 generates and stores the computation results based on the computation quantum circuit 5, and executes various quantum computations.

[0099] According to the information processing as described above, quantum amplitude amplification can be performed with at least one different auxiliary bit 322 assigned to each step of time evolution, so that it is possible to suppress an increase in the depth of the quantum circuit accompanying an increase in the number of repetitions, compared to the case where quantum amplitude amplification is performed using one auxiliary bit 322. Therefore, it is possible to promote quantum acceleration.

[0100] 5. Simulation results based on computational quantum circuit 5 In this section, we will explain the results of a simulation of the above-mentioned computational quantum circuit 5. Note that the simulation was performed using Qiskit on a classical computer.

[0101] In this simulation, the following Hamiltonian of the Heisenberg spin model was used as the Hamiltonian H:

number

[0102] Here, σ j =(σ j x ,σ j y ,σj z ) is an operator that represents three-dimensional spin. j, k are indices that indicate the site numbers at which the spins are located.<j,k> indicates the combination of nearest neighbor sites on a closed one-dimensional chain. A spin system is constructed. h j denotes the uniform magnetic field strength at the jth site. The magnetic field has a strength h j was randomly selected from a uniform distribution ranging from -1 to 1. The CRTE gate is implemented by performing a fourth-order Trotter decomposition on the even-odd group of the Hamiltonian H. Multi-step PITE (a method of repeatedly executing the PITE method) was adopted as a probabilistic algorithm to generate the ground state of the Hamiltonian H. The PITE method introduces a constant energy shift to improve the total success probability, and employs scheduling of the size of the imaginary time step Δτ. For details of the scheduling, please refer to Non-Patent Document 1.

[0103] In this simulation, the inventors performed simulations using three methods, a method of repeatedly applying a single-step PITE method, a method using quantum phase estimation (QPE), and the method related to this information processing, in order to generate the ground state of the Hamiltonian H. The performance of these methods was evaluated. The method related to this information processing is a calculation method based on a quantum computing algorithm that combines the multi-step PITE method with quantum amplitude amplification, and is denoted as "PITE+QAA" in FIG. 11. For convenience of explanation, in the following explanation of the results of this simulation, the method of repeatedly applying the single-step PITE method is denoted as "PITE", the method using quantum phase estimation is denoted as QPE, and the method related to this information processing is denoted as "PITE+QAA".

[0104] Figure 11 shows the computational cost and infidelity δ for each method to generate the ground state of the Hamiltonian H. K As described above, the infidelity δ K =(1-F KFor convenience of explanation, infidelity δ K is simply denoted as δ.

[0105] This simulation was performed using a one-dimensional Heisenberg model with eight spins. In addition, each eigenstate |λ of the Hamiltonian H i The inventors used a state in which the weights of all eigenstates |λ> and |λ> were set to be equal probability weights as the initial state (input state |ψ>). Specifically, the inventors used the N eigenstates {|λ i >}'s coefficient {c i}, |c i | 2 = 1 / N. For each method, the infidelity δ decreased and the computational cost increased as the number of steps (K) of PITE, the number of digits (the number K of auxiliary bits 322 in multi-step PITE), the resolution of QPE, etc. increased. As the infidelity δ decreases, the probability of successful operation decreases and tends to approach 1 / N. Therefore, the increase in computational cost corresponds to the increase in the number of iterations K of the stochastic operation in PITE and the resolution of QPE. As shown in Figure 11, in all methods, a tendency was confirmed that the infidelity δ decreased as the computational cost (i.e., the number of iterations K, etc.) increased. On the other hand, when the infidelity δ was about 10 -7 The computational cost of reaching 10 In contrast, PITE has a 6 ~10 7 and 10 for PITE+QAA. 6 This result suggests that PITE can reduce the infidelity δ at a lower computational cost than QPE. This result also suggests that PITE+QAA can reduce errors at a lower computational cost than PITE. Therefore, in terms of computational cost and the rate of infidelity reduction ability, the usefulness of PITE as a probabilistic operation and the usefulness of this information processing method that incorporates QAA into PITE have been demonstrated.

[0106] Figure 12 shows the weights |c1| of the probability of the ground state of the input state |ψ> using each method. -1 A diagram showing a simulation result of the relationship between infidelity δ and calculation cost. K 10 -4 The estimate is for the case where |c1| is less than 0. The probability of the input state |ψ> is weighted using a Gaussian distribution of the eigenstate function whose average value is the ground state energy. In both methods, |c1| -1 As |c1| increases, the computational cost tends to increase. This indicates that the smaller the component of the ground state contained in the input state |ψ>, the more difficult it is to generate the ground state. As shown in Figure 12, the computational cost of PITE and PITE+QAA is higher than that of |c1| -1 Even in |c1|, the computational cost is smaller than that of QPE. This suggests that the probabilistic algorithm PITE is useful for QPE. -1 < 1 / 2, the computational cost of PITE was smaller than that of PITE+QAA, but |c1| -1 For |ψ>1 / 2, the computational cost of PITE+QAA is lower than that of PITE. This suggests that this information processing (PITE+QAA) is more useful than PITE, especially when the desired state (here, the ground state) is difficult to observe in the input state |ψ>.

[0107] The above simulation results demonstrate the usefulness of this information processing method.

[0108] 6.Supplement: Overview of the stochastic field imaginary time evolution method In this section, we will explain the outline of the stochastic imaginary time evolution method (PITE) used in the above information processing. Note that the symbols of operators are different from those in the above information processing, but the appropriate correspondence can be established. Figure 13 is a quantum circuit that implements the time evolution operator exp(LΔt) with a general operator L as a generator. Figure 14 is a quantum circuit that implements the imaginary time evolution operator exp(-HΔτ) with a general Hermitian operator H as a generator.

[0109] 6.1 Quantum circuits for time evolution operators with general operators as generators When a general operator L for an n-qubit system consisting of n computational quantum bits 321 is given, consider configuring a quantum circuit that implements a time evolution operator exp(LΔt) with this as a generator. For convenience of explanation, hereinafter, an n-qubit system consisting of n computational quantum bits 321 may be simply referred to as an n-qubit system, and the state of the entire n-qubit system consisting of n computational quantum bits 321 may be referred to as an n-qubit state. Δt is an infinitesimal real number that represents a time step. If the time evolution operator exp(LΔt) can be configured as a quantum circuit, it is possible to execute the time evolution operator exp(LNΔt) for any natural number N by repeating the configuration.

[0110] The non-unitary Hermitian operator M from the real constant m0 ​​is defined as in Equation 18. Also, the non-Hermitian unitary operator U is defined as in Equation 19.

number

number

[0111] Furthermore, the Hermitian operator Θ for an n-qubit system is defined as follows:

number

[0112] When κ and d0 are defined as in Equation 21 and Equation 22, respectively, θ0 is defined as in Equation 23 using these.

number

number

number

[0113] As a quantum circuit for n+2 quantum bits, the quantum circuit shown in Fig. 13 is defined. The gate W included in this is a single quantum bit transformation defined by the formula 24. Ry in Fig. 13 is a y rotation gate.

number

[0114] When an n+2 quantum bit state consisting of any n computation quantum bits 321 taking the input state |ψ> and two auxiliary bits 322 in the |0> state is input to the quantum circuit shown in Fig. 13, the overall state changes within a first-order range of Δt as shown in Formula 25 until just before measurement. As can be seen from the right-hand side of the figure, if the two auxiliary bits 322 are measured and the |0>*|0> state, which is the state of the two auxiliary bits 322, is obtained, then immediately thereafter the n quantum bit state consisting of the computation quantum bit 321 will become the desired state exp(LΔt)|ψ>, apart from a constant factor that is not physically important.

number

[0115] This means that the operator exp(LΔt) for n qubits can be probabilistically implemented using the quantum circuit QC1. In addition, because the operators exp(iκΘ) and exp(-iκΘ) for n qubits are unitary operators, they can be implemented as unitary gates for n+2 qubits by combining the auxiliary bit 322.

[0116] In other words, this information processing method includes the following steps: In the conversion step, an operator for n quantum bits is converted into a unitary gate using less than (n / 2) auxiliary bits. The unitary gate is a form in which the operator can be directly implemented. In the circuit generation step, a quantum circuit that functions as a desired time evolution operator when the auxiliary bits are observed as a predetermined state is generated based on the unitary gate. According to this aspect, the number of exponential measurements of the quantum bits can be further reduced.

[0117] 6.2 Quantum circuits for imaginary time evolution operators with general Hermitian operators as generators Regarding the quantum circuit shown in Fig. 13, in the special case where L is a Hermitian operator, a desired operation can be implemented with a smaller number of auxiliary bits. Here, in order to explicitly indicate that the operator L is Hermitian, a Hermitian operator H is used instead of L below. Examples of Hermitian operators include the electron Hamiltonian and the Ising Hamiltonian, but these are merely examples and are not limited to these.

[0118] Suppose that the Hermitian operator H for an n-qubit system is given. Consider this and the imaginary time evolution operator exp(-HΔτ) specified by the real number Δτ. From this and the real constant m0, the non-unitary Hermitian operator M is defined as shown in Equation 26.

number

[0119] Moreover, the Hermitian operator Θ for an n-qubit system is defined as follows:

number

[0120] Consider constructing a quantum circuit that obtains M|ψ> when any n-qubit state |ψ> is given. To implement operator M, consider the quantum circuit shown in FIG. 14 as a quantum circuit for n+1 qubits.

[0121] 14, the overall state changes as shown in Equation 28 until just before measurement. As can be seen from the right-hand side of the equation, if the |0> state is obtained by measuring the auxiliary bit 322 and performing an observation operation, then immediately after that the n-qubit state becomes the desired state M|ψ> (apart from constant factors that are not physically important).

number

[0122] This means that the imaginary time evolution operator M for n quantum bits can be implemented probabilistically by using the quantum circuit shown in Fig. 14. In addition, since the operators exp(iκΘ) and exp(-iκΘ) for n quantum bits are unitary operators (more specifically, real time evolution operators), they can be implemented as unitary gates for n+1 quantum bits by combining the auxiliary bit 322.

[0123] In other words, preferably, in the conversion step, the conversion unit converts the operators into a form that uses only time evolution operators and other unitary operators. The time evolution operators include Hermitian operators. In detail, in the conversion step, the conversion unit converts the operators into a format that uses only the real time evolution operator and other unitary operators. The real time evolution operator includes the unitary operator. Furthermore, the time evolution operator is configured so as to be generateable by the Hermitian operator H. Note that the format of the time evolution operator is not limited to this and is arbitrary. For example, the format of the time evolution operator may be a format in which the operator appears in the expression, or a format in which the operator belongs as an element of a set.

[0124] 6.3 Equivalent transformation of quantum circuits when Hermitian operators are used as generators Since exp(iκΘ) and exp(-iκΘ) included in the quantum circuit shown in Figure 14 are unitary operators, in principle they can be implemented as unitary gates. However, a specific method for implementing the definition of Θ in Equation 27 as a unitary gate as is is not self-evident. Therefore, if the quantum circuit shown in Figure 13 can be approximated to another circuit that performs the same calculation (transformed into a circuit that is strictly equivalent within a finite-order range of mathematical expansion), that circuit will be useful for practical quantum computing. The equivalent transformation is explained below.

[0125] s1 is defined as in equation 29. Using this, the unitary operator U RTE is defined as in Eq. (30).

number

number

[0126] When an N+1 quantum bit state consisting of n computational quantum bits 321 taking any n-qubit state |ψ> and one auxiliary bit 322 in the |0> state is input to the quantum circuit shown in Fig. 14, the overall state changes to the first order in Δτ as shown in Equation 31 by the time of measurement. The state after this change coincides with the state in Equation 28 to the first order in Δτ. This means that the quantum circuit QC1 shown in Fig. 6 is equivalent to the quantum circuit shown in Fig. 14 to the first order in Δτ.

number

[0127] exp(is1HΔτ) and exp(-is1HΔτ) are unitary real-time evolution operators, and various methods have already been proposed to efficiently implement them as quantum gates. Therefore, those existing methods can be used as is for this method.

[0128] By implementing the imaginary time evolution operator as a quantum circuit and repeating it, the time evolution operator exp(LNΔt) can be executed for a desired natural number N. Here, to correctly calculate each imaginary time step, the auxiliary bit 322 must output the |0> state. By amplifying the amplitude (probability) that the auxiliary bit 322 takes the |0> state at each imaginary time evolution step, the time evolution operator exp(LΔt) can be executed with higher probability.

[0129] Amplification of the amplitude when the auxiliary bit 322 is in the |0> state can be realized by inserting a quantum amplitude amplifier circuit. That is, preferably, the quantum circuit may further include a quantum amplitude amplifier circuit capable of improving the probability that the auxiliary bit is observed in a predetermined state. For a general operator L, the operator exp(LNΔt) can be implemented on a quantum computer, and a quantum circuit that applies the operator exp(LNΔt) to an arbitrary initial state can be realized.

[0130] However, for a general operator L, the lowest eigenvalue does not necessarily have to be a real number; it is only guaranteed that the eigenvalue will be a real number if the operator L is a Hermitian operator. If the operator L is a regular non-Hermitian operator, when the imaginary time evolution operator exp(LNΔt) is applied to any initial state with a sufficiently large number N, it will converge to an eigenstate corresponding to the eigenvalue of L with the lowest real part. However, it should be noted that a quantum circuit representing the operator exp(LNΔt) can be realized even if L is not regular.

[0131] Based on this theory, the forward real-time evolution operator U RTE is defined and the PITE method is implemented.

[0132] 7.Other The information processing system 1 may be further improved in the following manner.

[0133] The above stochastic operation is the cosine function operator cos(t k H). FIG. 15 shows the cosine function operator cos(t k Quantum circuit QC2 is an example of a quantum circuit QC2 corresponding to (H). Quantum circuit QC2 is first configured to perform a Hadamard gate operation on auxiliary bit 322. Next, quantum circuit QC2 is configured to perform a CRTE gate operation with auxiliary bit 322 as a control bit and computation qubit 321 as a target bit. This CRTE gate operation does not perform an operation on computation qubit 321 (in other words, performs an identity operation) when auxiliary bit 322 is in the |0> state, and performs a forward real-time evolution operator U RTE The parameter corresponding to the size of the real time step of the CRTE gate is arbitrary, but for example, 2t k Then, the quantum circuit QC2 is configured to perform a phase gate operation on the auxiliary bit 322. The phase gate operation is an operation for rotating the phase of the auxiliary bit 322. The phase rotation angle is arbitrary, but for example, when an energy shift of a shift amount E is used, the phase rotation angle is 2Et k It is.

[0134] Figure 16 shows the cosine function operator cos(t k16 is a diagram showing an example of a computational quantum circuit in the case where the computational quantum circuit 5 shown in FIG. 16 is adopted. Hereinafter, for convenience of explanation, the computational quantum circuit 5 shown in FIG. 16 is written as a computational quantum circuit 5a to distinguish it from the computational quantum circuit 5 shown in FIG. 7. The computational quantum circuit 5a is different from the computational quantum circuit 5 in terms of the specific aspects of the first computational quantum circuit 52 and the second computational quantum circuit 54, and the first reflection operation 51, the second reflection operation 53, and the observation operation 55 are common to the computational quantum circuit 5. Hereinafter, for convenience of explanation, the same component numbers are given to the configurations common to the computational quantum circuit 5 and the computational quantum circuit 5a, and the explanations are omitted, and the components different between the computational quantum circuit 5 and the computational quantum circuit 5a are given the suffix "a" to the component numbers of the computational quantum circuit 5. The input conversion operation 521a of the first computational quantum circuit 52a is a Hermitian conjugate operation P of the Hadamard gate operation H and the topological gate operation P. † The unit gate operation 522a is composed of one CRTE gate operation, and when the corresponding auxiliary bit 322 is in the |0> state, no operation is performed on the computation quantum bit 321, and when the corresponding auxiliary bit 322 is in the |1> state, the Hermitian conjugate operator U RTE † on the computation quantum bit 321. The output transformation operation 523a is constituted by a Hadamard gate operation H. The second computation quantum circuit 54a is constituted to be a Hermitian conjugate of the first computation quantum circuit 52a. Specifically, the input transformation operation 541a, the unit gate operation 542a, and the output transformation operation 543a are constituted to be a Hermitian conjugate of the output transformation operation 543a, a Hermitian conjugate of the unit gate operation 522a, and a Hermitian conjugate of the input transformation operation 541a, respectively. Therefore, the operations repeatedly performed by the computation quantum circuit 5 are not limited to stochastic imaginary time operations.

[0135] In the above information processing, the allocation unit 232 allocates K auxiliary bits 322 when the operation is repeated K times, but may allocate more than K auxiliary bits 322. For example, the allocation unit 232 may allocate two or more auxiliary bits 322 per operation. This allows more diverse operations to be realized by using the auxiliary bits 322 capable of expressing more diverse states as control bits, etc. The allocation unit 232 may also divide the number of repetitions K into a plurality of numbers of 2 or more, for example, K1 and K2, generate a computational quantum circuit 5 for each of the plurality of numbers of repetitions K1 and K2, and combine these computational quantum circuits 5 in series to generate a quantum circuit that repeats the operation K times as a whole as a computational quantum circuit. In this case, the allocation unit 232 may allocate less than K auxiliary bits 322, for example, the larger number of K1 and K2. In this case, for example, the quantum operation unit 234 may execute a quantum operation based on a computational quantum circuit whose iteration number corresponds to K1, initialize the auxiliary bit 322, and then execute a quantum operation based on a computational quantum circuit whose iteration number corresponds to K2 with the final state as an input state, thereby repeating the operation K times overall on the initial input state to obtain the final state. Therefore, when the iteration number K is divided into a plurality of numbers, the quantum circuit based on the divided number is also included in the computational quantum circuit 5 related to this information processing.

[0136] The computational quantum circuit 5 may not have a function related to so-called quantum amplitude amplification. The function related to quantum amplitude amplification may be realized by, for example, a first reflection operation 51, a first operational quantum circuit 52, and a second reflection operation 53. In this case, the generation unit 233 may generate a computational quantum circuit 5 including a second operational quantum circuit 54 as an operational quantum circuit according to the number of iterations K of the operation based on the Hamiltonian H. In other words, the information processing method may include the following steps. In the acquisition step, information on the input state |ψ> represented by n computational quantum bits 321, information on the Hamiltonian, and the number of iterations K (where K is an integer equal to or greater than 2) of the operation based on the Hamiltonian are acquired. In the allocation step, a plurality of auxiliary bits 322 are allocated according to the number of iterations K. In the generation step, a computational quantum circuit 5 is generated based on the results acquired in the acquisition step. The computational quantum circuit 5 is configured to operate the computational quantum circuit on the computational quantum bits 321 and the auxiliary bits 322. The computational quantum circuit is configured to operate on the n computational quantum bits 321 corresponding to the input state |ψ> and includes unit gate operations corresponding to each of the assigned auxiliary bits 322. Each of the unit gate operations is configured to use one of the different plurality of auxiliary bits 322 as a control bit, use the computational quantum bit 321 as a target bit, and change the mode of operation on the computational quantum bit 321 according to the state of the auxiliary bit 322. In the output step, the state of the computation quantum bit 321 is output as the computation result based on the observation result of the auxiliary bit 322.

[0137] Furthermore, the generation unit 233 may generate the computational quantum circuit 5 further including an observation operation 55. In this case, for example, the computational quantum circuit 5 is configured to operate the computational quantum circuit on the computational quantum bit 321 and the auxiliary bit 322, and then to perform an observation operation 55 on at least one of the multiple auxiliary bits 322. The observation operation 55 is configured to observe the state of the auxiliary bit 322 that functions as a control bit for the unit gate operation.

[0138] The information processing system 1 may be realized by a program that causes a computer to function as the information processing system 1. This program may be in a form that can be downloaded from a server, or may be executed or distributed on a cloud computer, or may be stored in a non-volatile or volatile storage medium and distributed.

[0139] The processor 23 does not need to actually execute the quantum computation by the computation quantum circuit 5 using the quantum computer 3. For example, the processor 23 may convert the quantum computation algorithm defined by the generated computation quantum circuit 5 into a computation algorithm executable by a classical computer, and then cause the classical computer to execute the computation algorithm. For example, the processor 23 may convert the quantum operation expressed by the computation quantum circuit 5 into a computation problem of a matrix, thereby converting it into a computation algorithm executable by a classical computer.

[0140] A part of the processing of the processor 23 may be converted into a calculation algorithm executable by a quantum computer, and then the quantum computer 3 may be made to execute the calculation algorithm.

[0141] The quantum computer 3 may function as a quantum measurement device. Each of the above information processing methods can constitute a technical idea by itself. For example, the information processing methods can be used for any information processing that can be processed using a quantum algorithm, such as processing other than processing for obtaining calculation results related to physical phenomena, such as calculation results of combinatorial optimization problems and traveling salesman problems. In other words, the information processing methods can be applied to any problem that is mathematically described as a Hamiltonian (for example, an eigenvalue problem of a Hamiltonian).

[0142] A part of the processing of the processor 23 may be converted into a calculation algorithm executable by a quantum computer, and then the quantum computer 3 may be made to execute the calculation algorithm.

[0143] The quantum computer 3 may function as a quantum measurement device. For example, in this case, the computational quantum circuit 5 may be used as a unitary operation for generating an initial state. In other words, the computational quantum circuit 5 may be configured to represent a quantum algorithm executed by at least one quantum measurement device. According to such a configuration, for example, when the quantum measurement device is configured to use a specific state (e.g., a ground state) of a certain Hamiltonian as a probe state of quantum measurement, the computational quantum circuit 5 may be configured to repeatedly execute an operation based on a Hamiltonian H such that the specific state is an eigenstate, thereby outputting the specific state based on the input state |ψ>. According to such a configuration, it is possible to perform a measurement that is more robust against noise in quantum measurement.

[0144] The information processing device 2 may be a classical computer, a quantum computer, or a combination of these.

[0145] The information processing system 1 can be applied to various information processing related to quantum computation such as quantum measurement and quantum communication.

[0146] The above embodiment is not limited to the information processing system 1, and may be an information processing method or an information processing program. The information processing method includes each step of the information processing system 1. The information processing program causes at least one computer to execute each step of the information processing system 1.

[0147] The information processing system 1 and the like may be provided in the following aspects.

[0148] (1) An information processing method, comprising the following steps: in an acquisition step, information on an input state represented by n computational quantum bits, information on a Hamiltonian, and a number K of iterations of an operation based on the Hamiltonian (where K is an integer equal to or greater than 2); in an allocation step, a number of auxiliary bits are allocated according to the number K of iterations, wherein each state of the n computational quantum bits and the plurality of auxiliary bits is configured to be representable using at least a first state and a second state that are observable; in a generation step, a computational quantum circuit is generated based on a result acquired in the acquisition step, wherein the computational quantum circuit is configured to sequentially operate a first reflection operation, a first operational quantum circuit, a second reflection operation, and a second operational quantum circuit, wherein the first reflection operation is a first reflection state that is any one of a component of the first state and a component of the second state included in each of the plurality of auxiliary bits; the first operational quantum circuit is configured to operate on the n computation qubits corresponding to the input state and includes unit gate operations corresponding to each of the ancillary bits, each of the unit gate operations having one of the different ancillary bits as a control bit and the computation qubit as a target bit, and configured to change a mode of operation on the computation qubit in accordance with a state of the ancillary bit; the second reflection operation is configured to operate on the computation qubit and the ancillary bit so as to change a phase of a second reflection state which is one of the components of the first state and the components of the second state contained in the computation qubit and the ancillary bit, respectively; and the second operational quantum circuit is configured to be convertible into a Hermitian conjugate circuit of the first operational quantum circuit using a predetermined unitary gate operation.

[0149] According to this configuration, since quantum amplitude amplification can be performed with at least one different auxiliary bit assigned to each step of time evolution, it is possible to suppress an increase in the depth of the quantum circuit with an increase in the number of repetitions compared to a case where an operation and quantum amplitude amplification are repeated using one auxiliary bit, and therefore it is possible to promote quantum acceleration.

[0150] (2) In the information processing method described in (1) above, the computational quantum circuit includes a reference circuit configured to act on the computational quantum bit, and the reference circuit is configured to output the input state based on an initialized state of the computational quantum bit.

[0151] According to such a configuration, by setting an appropriate input state for the Hamiltonian in advance, it is possible to obtain a highly accurate calculation result with a smaller number of operations.

[0152] (3) In the information processing method described in (1) or (2) above, the computational quantum circuit further includes an observation operation, which is configured to observe the states of the auxiliary bits that function as control bits of the unit gate operation, and further, in an output step, the state of the computational quantum bit is output as a computation result based on the observation result of the auxiliary bits.

[0153] According to this configuration, a final state in which time evolution has been appropriately performed by each time evolution gate operation can be output as a calculation result.

[0154] (4) The information processing method according to any one of (1) to (3) above, wherein a state of the ancillary bit included in the first reflection state and a state of the ancillary bit included in the second reflection state are a common state, and the second operational quantum circuit is configured to be Hermitian conjugate with the first operational quantum circuit.

[0155] According to such a configuration, the computational quantum circuit can be further simplified, and the operations included in the computational quantum circuit can be reduced.

[0156] (5) The information processing method according to any one of (1) to (4) above, wherein a phase of the first reflection operation is inverted with respect to a phase of the second reflection operation.

[0157] With this configuration, phase matching can be achieved, thereby further promoting quantum acceleration.

[0158] (6) The information processing method according to any one of (1) to (5) above, wherein the calculation is a probabilistic calculation capable of expressing whether or not the calculation will be successful depending on the state of the auxiliary bit.

[0159] (7) An information processing method according to any one of (1) to (6) above, wherein each of the unit gate operations is configured to apply either a unit operation or a Hermitian conjugate operation of the unit operation to the computation quantum bit depending on the state of the auxiliary bit, and the unit operation is configured to correspond to performing the operation once.

[0160] (8) An information processing method comprising the following steps: in an acquisition step, information on an input state represented by n computation quantum bits, information on a Hamiltonian, and a number of iterations K (where K is an integer equal to or greater than 2) of an operation based on the Hamiltonian are acquired; in an allocation step, a number of auxiliary bits are allocated in accordance with the number of iterations K; in a generation step, a computation quantum circuit is generated based on a result acquired in the acquisition step, the computation quantum circuit is configured to operate on the computation quantum bits and the auxiliary bits, the computation quantum circuit is configured to operate on the n computation quantum bits corresponding to the input state and includes unit gate operations corresponding to each of the assigned auxiliary bits, each of the unit gate operations being configured to use one of the plurality of different auxiliary bits as a control bit, use the computation quantum bit as a target bit, and change a mode of operation on the computation quantum bit in accordance with a state of the auxiliary bit; and in an output step, a state of the computation quantum bit is output as a computation result based on a result of observation of the auxiliary bit.

[0161] (9) In the information processing method described in (8) above, the computational quantum circuit is configured to, after applying the operational quantum circuit to the computational quantum bit and the auxiliary bit, further perform an observation operation on at least one of the plurality of auxiliary bits, and the observation operation is configured to observe a state of the auxiliary bit that functions as a control bit for the unit gate operation.

[0162] (10) A computational quantum circuit configured to repeat an operation based on a Hamiltonian K times for an input state represented by n computational quantum bits (where K is an integer equal to or greater than 2), and configured to act on the n computational quantum bits and a plurality of auxiliary bits according to K, wherein the states of the computational quantum bits and the auxiliary bits are configured to be representable using at least a first state and a second state that are observable, and the computational quantum circuit is configured to sequentially act on a first reflection operation, a first operational quantum circuit, a second reflection operation, and a second operational quantum circuit, and the first reflection operation is configured to act on the plurality of auxiliary bits so as to change a phase of a first reflection state, which is one of a component of the first state and a component of the second state included in each of the plurality of auxiliary bits. the first operational quantum circuit is configured to act on the n computation quantum bits corresponding to the input state and includes a unit gate operation corresponding to each of the auxiliary bits, each of the unit gate operations being configured to have one of the plurality of different auxiliary bits as a control bit, the computation quantum bit as a target bit, and to change a mode of action on the computation quantum bit depending on a state of the auxiliary bit; the second reflection operation is configured to act on the computation quantum bit and the auxiliary bit so as to change a phase of a second reflection state which is one of the components of the first state and the components of the second state contained in each of the computation quantum bit and the auxiliary bit; and the second operational quantum circuit is configured to be convertible into a Hermitian conjugate circuit of the first operational quantum circuit using a predetermined unitary gate operation.

[0163] According to this configuration, since quantum amplitude amplification can be performed with at least one different auxiliary bit assigned to each step of time evolution, it is possible to suppress an increase in the depth of the quantum circuit with an increase in the number of iterations compared to the case where quantum amplitude amplification is performed using one auxiliary bit, and therefore it is possible to promote quantum acceleration.

[0164] (11) A method for generating a computational quantum circuit as described in (10) above, wherein in an acquisition step, information about the input state, information about the Hamiltonian, and a number of iterations of an operation based on the Hamiltonian are acquired, where the number of iterations corresponds to K which is the number of unit gate operations, in an allocation step, a plurality of auxiliary bits corresponding to the number of iterations are assigned, and in a generation step, a computational quantum circuit configured to repeatedly apply the operation to the computational quantum bits is generated based on the result acquired in the acquisition step.

[0165] According to this configuration, since quantum amplitude amplification can be performed with at least one different auxiliary bit assigned to each step of time evolution, it is possible to suppress an increase in the depth of the quantum circuit with an increase in the number of iterations compared to the case where quantum amplitude amplification is performed using one auxiliary bit, and therefore it is possible to promote quantum acceleration.

[0166] (12) An information processing system comprising at least one device, the information processing system including at least one processor capable of executing a program to perform each step of the information processing method described in any one of (1) to (9) above.

[0167] According to this configuration, since quantum amplitude amplification can be performed with at least one different auxiliary bit assigned to each step of time evolution, it is possible to suppress an increase in the depth of the quantum circuit with an increase in the number of iterations compared to the case where quantum amplitude amplification is performed using one auxiliary bit, and therefore it is possible to promote quantum acceleration.

[0168] (13) A program that causes at least one computer to execute each step of the information processing method according to any one of (1) to (9) above.

[0169] According to this configuration, since quantum amplitude amplification can be performed with at least one different auxiliary bit assigned to each step of time evolution, it is possible to suppress an increase in the depth of the quantum circuit with an increase in the number of iterations compared to the case where quantum amplitude amplification is performed using one auxiliary bit, and therefore it is possible to promote quantum acceleration. Of course, this is not the case.

[0170] Finally, although various embodiments of the present invention have been described, these are presented as examples and are not intended to limit the scope of the invention. The novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. The embodiments and their modifications are included within the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0171] 1: Information processing system 2: Information processing equipment 20: Communication bus 21: Communications Department 22: Storage section 23: Processor 231: Acquisition Department 232: Allocation section 233 :Generation part 234:Quantum operation section 235: Output section 3:Quantum computer 30: Communication bus 31: Communications Department 32: Quantum memory 320: Quantum Bits 321: Computational qubits 322: Auxiliary bit 33: Quantum processor 4: User terminal 40: Communication bus 41: Communications Department 42: Memory 43: Processor 44: Display section 45: Input section 5: Computational quantum circuit 51: First reflex operation 52: First computation quantum circuit 521: Input conversion operation 522: Unit gate operation 523: Output conversion operation 524 :Reference circuit 53: Second reflection operation 54: Second computation quantum circuit 541: Input conversion operation 542: Unit gate operation 543 : Output conversion operation 544 :Reference circuit 55: Observation operations 5a: Computational quantum circuit 52a: First computational quantum circuit 521a: Input conversion operation 522a: Unit gate operation 523a : Output conversion operations 54a: Second computation quantum circuit 541a: Input conversion operation 542a: Unit gate operation 543a : Output conversion operations QC1: Quantum circuits QC2:Quantum circuit P: Phase gate operation R Z :z Rotating gate operation S0: Zero reflection S χ : Oracle operation

Claims

1. 1. An information processing method, comprising: It includes the following steps: In the acquisition step, information on an input state represented by n computational quantum bits, information on a Hamiltonian, and a number K of iterations of an operation based on the Hamiltonian (where K is an integer equal to or greater than 2) are acquired; In the allocating step, a plurality of auxiliary bits are allocated according to the number of repetitions K; wherein the states of the n computation quantum bits and the plurality of auxiliary bits are configured to be representable using at least a first state and a second state that are observable; In the generation step, a computational quantum circuit is generated based on the result obtained in the acquisition step, The computational quantum circuit is configured to sequentially operate a first reflection operation, a first operational quantum circuit, a second reflection operation, and a second operational quantum circuit; the first reflection operation is configured to act on the plurality of auxiliary bits so as to change a phase of a first reflection state, which is one of the first state component and the second state component included in each of the plurality of auxiliary bits; the first operational quantum circuit is configured to operate on the n computation qubits corresponding to the input state and includes unit gate operations corresponding to each of the ancillary bits; Each of the unit gate operations is configured to use one of the plurality of different auxiliary bits as a control bit, use the computation quantum bit as a target bit, and change an action mode on the computation quantum bit according to a state of the auxiliary bit; the second reflection operation is configured to act on the computation quantum bit and the ancillary bit so as to change a phase of a second reflection state, the second reflection state being one of the first state component and the second state component included in each of the computation quantum bit and the ancillary bit; An information processing method, wherein the second operational quantum circuit is configured to be convertible into a Hermitian conjugate circuit of the first operational quantum circuit using a predetermined unitary gate operation.

2. 2. The information processing method according to claim 1, 11. A method of information processing, comprising: the computational quantum circuit including a reference circuit configured to operate on the computation quantum bit; the reference circuit configured to output the input state based on an initialized state of the computation quantum bit.

3. 2. The information processing method according to claim 1, The computational quantum circuit further includes an observation operation, the observation operation being configured to observe a state of each of the auxiliary bits that function as control bits of the unit gate operations; Furthermore, in the output step, the state of the computation quantum bit is output as a computation result based on the observation result of the auxiliary bit.

4. 2. The information processing method according to claim 1, a state of the auxiliary bit included in the first reflective state and a state of the auxiliary bit included in the second reflective state are a common state, An information processing method, wherein the second operational quantum circuit is configured to be Hermitian conjugate with the first operational quantum circuit.

5. 2. The information processing method according to claim 1, A method of processing information, wherein a phase of the first reflection operation is inverted with respect to a phase of the second reflection operation.

6. 2. The information processing method according to claim 1, An information processing method, wherein the calculation is a probabilistic calculation capable of expressing whether or not it will be successful depending on the state of the auxiliary bit.

7. 2. The information processing method according to claim 1, An information processing method, wherein each of the unit gate operations is configured to perform either an unit operation or a Hermitian conjugate operation of the unit operation on the computation quantum bit depending on the state of the auxiliary bit, and the unit operation is configured to correspond to performing the operation once.

8. 1. An information processing method, comprising: It includes the following steps: In the acquisition step, information on an input state represented by n computation quantum bits, information on a Hamiltonian, and a number K of iterations of an operation based on the Hamiltonian (where K is an integer equal to or greater than 2) are acquired; In the allocating step, a plurality of auxiliary bits are allocated according to the number of repetitions K; In the generation step, a computational quantum circuit is generated based on the result obtained in the acquisition step; the computational quantum circuit is configured to operate an operational quantum circuit on the computational quantum bits and the ancillary bits; the operational quantum circuit is configured to operate on the n computational qubits corresponding to the input state, and includes unit gate operations corresponding to each of the assigned auxiliary bits; Each of the unit gate operations is configured to use one of the plurality of different auxiliary bits as a control bit, use the computation quantum bit as a target bit, and change an action mode on the computation quantum bit according to a state of the auxiliary bit; In the output step, the state of the computation quantum bit is output as a computation result based on the observation result of the auxiliary bit.

9. 9. The information processing method according to claim 8, the computational quantum circuit is configured to operate the operational quantum circuit on the computational quantum bit and the auxiliary bit, and then to perform an observation operation on at least one of the plurality of auxiliary bits; The information processing method, wherein the observation operation is configured to observe a state of the auxiliary bit that functions as a control bit for the unit gate operation.

10. A computational quantum circuit, comprising: The method is configured to repeat an operation based on a Hamiltonian K times for an input state represented by n computational quantum bits (where K is an integer equal to or greater than 2); configured to operate on the n computation qubits and a number of ancillary bits according to K; wherein the respective states of the computation quantum bit and the ancillary bit are configured to be representable using at least a first state and a second state that are observable; The computational quantum circuit is configured to sequentially operate a first reflection operation, a first operational quantum circuit, a second reflection operation, and a second operational quantum circuit; the first reflection operation is configured to act on the plurality of auxiliary bits so as to change a phase of a first reflection state, which is one of the first state component and the second state component included in each of the plurality of auxiliary bits; the first operational quantum circuit is configured to operate on the n computation qubits corresponding to the input state and includes unit gate operations corresponding to each of the ancillary bits; Each of the unit gate operations is configured to use one of the plurality of different auxiliary bits as a control bit, use the computation quantum bit as a target bit, and change an action mode on the computation quantum bit according to a state of the auxiliary bit; the second reflection operation is configured to act on the computation quantum bit and the ancillary bit so as to change a phase of a second reflection state, the second reflection state being one of the first state component and the second state component included in each of the computation quantum bit and the ancillary bit; A computational quantum circuit, wherein the second operational quantum circuit is configured to be convertible into a Hermitian conjugate circuit of the first operational quantum circuit using a predetermined unitary gate operation.

11. A method for generating a computational quantum circuit according to claim 10, comprising: In the acquisition step, information on the input state, information on the Hamiltonian, and the number of iterations of an operation based on the Hamiltonian are acquired, where the number of iterations corresponds to K, which is the number of times the unit gate is operated; In the allocating step, the plurality of auxiliary bits corresponding to the number of repetitions are allocated; A method for generating a computational quantum circuit, comprising: generating, in a generation step, a computational quantum circuit configured to repeatedly perform the operation on the computation quantum bit based on the result obtained in the acquisition step.

12. An information processing system comprising at least one device, 10. An information processing system comprising at least one processor capable of executing a program to perform each step of the information processing method according to any one of claims 1 to 9.

13. A program, A method for causing at least one computer to execute each step of the information processing method according to any one of claims 1 to 9.

Images