Display device

Abstract

To provide a semiconductor device which shifts a signal in a low level by a less number of transistors.SOLUTION: A semiconductor device comprises: a first transistor with a first terminal being electrically connected to first wiring, and with a second terminal being electrically connected to second wiring; a second transistor with a first terminal being electrically connected to third wiring, and with a second terminal being electrically connected to the second wiring; a third transistor with a first terminal being electrically connected to fourth wiring, and with a second terminal being electrically connected to a gate of the second transistor; a fourth transistor with a first terminal being electrically connected to fifth wiring, with a second terminal electrically connected to a gate of the third transistor, and with a gate being electrically connected to sixth wiring; and a first switch with a first terminal being electrically connected to the third wiring, and with a second terminal being electrically connected to a gate of the first transistor.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device, a display device, or the like. [Background technology]

[0002] In recent years, the development of shift register circuits consisting of transistors of the same polarity has been actively promoted. The shift register circuit of Patent Document 1 is an N-channel type transistor. When the clock signal goes high, the clock By outputting a lock signal, high-level signals are sequentially output. The shift register circuit 1 outputs low-level signals in order to output the clock signal. It is not possible.

[0003] In addition, when the shift register of Patent Document 1 is configured with P-channel transistors, However, it is not possible to output high-level signals in sequence. You will no longer be able to exert force. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2004-103226 A Summary of the Invention [Problem to be solved by the invention]

[0005] By the way, in a shift register circuit composed of N-channel transistors, It is required to output a signal of the same level sequentially. In a shift register circuit configured as above, it is required to sequentially output high-level signals. It is being done.

[0006] In view of this, one embodiment of the present invention is a transistor including an n-channel transistor, Another object of the present invention is to provide a circuit for sequentially outputting A circuit consisting of P-channel transistors that outputs high-level signals sequentially. Another object of the present invention is to provide a method for reducing the circuit scale. Another object of one embodiment of the present invention is to reduce power consumption. . [Means for solving the problem]

[0007] In one embodiment of the present invention, one of a source and a drain is electrically connected to a first wiring. a first transistor, the other of which is electrically connected to a second wiring; One of the source and the drain is electrically connected to a third wiring, and the other of the source and the drain is electrically connected to a second wiring. A second transistor electrically connected to the wiring, and one of a source and a drain of the second transistor is connected to a fourth wiring. the other of the source and drain is electrically connected to the gate of the second transistor. a third transistor electrically connected to the fifth wiring; and the other of the source and the drain is electrically connected to the gate of the third transistor. a fourth transistor having a gate electrically connected to the sixth wiring; and a first terminal electrically connected to the third wiring. The second terminal is electrically connected to the gate of the first transistor. and a first switch provided in the first region.

[0008] In the above embodiment of the present invention, the first terminal is electrically connected to the first wiring, and the second terminal may have a second switch electrically connected to the gate of the first transistor. .

[0009] In the above embodiment of the present invention, the first terminal is electrically connected to the third wiring, and the second terminal may have a third switch electrically connected to the gate of the second transistor. .

[0010] In the above embodiment of the present invention, the first to fourth transistors each have a channel formation region The insulating layer may include an oxide semiconductor. Effect of the Invention

[0011] One embodiment of the present invention is a transistor that is configured with N-channel transistors and sequentially outputs low-level signals. In addition, one embodiment of the present invention provides a circuit for inputting a P-channel transistor. It is possible to provide a circuit that is composed of transistors and outputs high-level signals sequentially. In addition, according to one embodiment of the present invention, the circuit scale can be reduced. The aspect can reduce power consumption. [Brief description of the drawings]

[0012] [Figure 1] FIG. 2 is a diagram for explaining a basic circuit according to the present invention. [Diagram 2] FIG. 1 is a diagram illustrating a sequential circuit according to the present invention. [Diagram 3] FIG. 2 is a diagram for explaining a shift register circuit according to the present invention. [Figure 4] FIG. 2 is a diagram for explaining a shift register circuit according to the present invention. [Diagram 5] FIG. 1 is a diagram illustrating a sequential circuit according to the present invention. [Figure 6] FIG. 1 is a diagram illustrating a sequential circuit according to the present invention. [Figure 7] FIG. 1 is a diagram illustrating a sequential circuit according to the present invention. [Figure 8] FIG. 1 is a diagram illustrating a sequential circuit according to the present invention. [Figure 9] FIG. 1 is a diagram illustrating a sequential circuit according to the present invention. [Figure 10] 1A and 1B are diagrams illustrating a basic circuit and a sequential circuit according to the present invention. [Figure 11] FIG. 2 is a diagram for explaining a basic circuit according to the present invention. [Figure 12] 1A and 1B are diagrams illustrating a display device according to the present invention. [Figure 13] 1A and 1B are diagrams illustrating a display device according to the present invention. [Figure 14] 1A to 1C are diagrams illustrating a transistor according to the present invention; [Figure 15] 1A to 1C are diagrams illustrating electronic devices according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. It is to be understood that the invention can be practiced in many different ways and without departing from the spirit and scope of the invention. It will be readily understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the present embodiment. In the configuration of the present invention, reference numerals indicating the same objects are common among different drawings.

[0014] In addition, the size, layer thickness, signal waveform, or Areas may be exaggerated for clarity. This is not limited to rules.

[0015] In addition, the terms first, second, third, through Nth (N is a natural number) used in this specification are structures. It is added to avoid confusion of the constituent elements, and is not a numerical limitation. do.

[0016] (Embodiment 1) In this embodiment, a basic circuit, a sequential circuit, and a shift register circuit according to one embodiment of the present invention will be described. This section explains the road.

[0017] First, a basic circuit (also referred to as a semiconductor device or a driver circuit) of this embodiment will be described.

[0018] FIG. 1(A) is a circuit diagram of a basic circuit according to the present embodiment. The transistors 101 to 105 are included.

[0019] In one embodiment of the present invention, the polarity of the transistor may be an N-channel type or a P-channel type. However, the polarities of the transistors 101 to 105 are the same. In this embodiment, the transistors 101 to 105 are preferably The following description will be given assuming that the transistor is an N-channel type.

[0020] Note that in one embodiment of the present invention, a transistor has a channel formation region made of silicon or A transistor containing a semiconductor such as germanium can be used. The transistor includes a semiconductor such as an oxide semiconductor or a nitride semiconductor in the channel formation region. The above-mentioned semiconductor may be amorphous, microcrystalline, polycrystalline, or has regions which are single crystal.

[0021] In one embodiment of the present invention, the transistor is a thin film transistor (TFT). In addition, a semiconductor substrate or an SOI substrate can be used as the transistor. A MOS transistor, a junction transistor, a bipolar transistor, etc., is formed. can be used.

[0022] Next, the connections of the basic circuit in FIG.

[0023] A first terminal (also referred to as one of a source and a drain) of the transistor 101 is connected to a wiring 11. The second terminal (also referred to as the other of the source and drain) of the transistor 101 is connected to a wiring The first terminal of the transistor 102 is connected to the wiring 13. The second terminal of the transistor 102 is connected to the wiring 12, and the gate of the transistor 102 is connected to the wiring 14. The first terminal of the transistor 103 is connected to the wiring 15, and the second terminal of the transistor 10 A second terminal of the transistor 3 is connected to the wiring 14. A first terminal of the transistor 104 is connected to the wiring 13. the second terminal of the transistor 104 is connected to the gate of the transistor 101; The gate of the transistor 104 is connected to the wiring 14. is connected to the wiring 17, and the second terminal of the transistor 105 is connected to the gate The gate of the transistor 105 is connected to a wiring 16.

[0024] The connection point between the gate of the transistor 103 and the second terminal of the transistor 105 is The gate of the transistor 101 and the second terminal of the transistor 104 are shown as N1. The connection point is indicated as node N2.

[0025] In this specification, the term "connection" means electrical connection, and includes current, voltage, potential, This corresponds to a state in which signals or charges can be supplied or transmitted. In addition to the direct connection, for example, wiring, conductive film, resistor, diode, transistor This also includes indirect connections via elements such as inverters and switching elements. nothing.

[0026] Next, signals, potentials, and the like of the wirings 11 to 17 will be described.

[0027] A potential VDD is supplied to the wiring 11. A signal OUTA is output from the wiring 12. A potential VSS is supplied to the wiring 13. A signal OUTB is output from the wiring 14. A signal CK1 is input to the wiring 16. A signal CK2 is input to the wiring 17. The SP is entered.

[0028] The potentials VDD and VSS are constant potentials. This is a higher potential than

[0029] In addition, the signals OUTA, OUTB, CK1, CK2, and SP are at high level. and a low level.

[0030] Note that the signals, potentials, and the like of the wirings 11 to 17 are not limited to those described above. A signal or potential for increasing the potential of the wiring 12 may be supplied to the wiring 1. 3 is a signal or potential for lowering the potential of the wiring 12, and / or a transistor A signal or potential for turning off the wiring 101 may be supplied to the wiring 15. A signal or potential to raise the potential of line 14, turning on transistor 102 and / or a signal or potential for turning on transistor 104. A potential or the like may be input to the wiring 16. A signal for controlling the transistor 103 is input to the wiring 17. It is only necessary that a signal, potential, or the like for that purpose is input.

[0031] In this specification and the like, a wiring to which a signal is input may be called a signal line. The wiring to which this voltage is supplied may be called a power supply line.

[0032] In one embodiment of the present invention, the wiring has a function of transmitting a signal, a potential, or the like. The wiring 15 has a function of transmitting a signal CK1.

[0033] Next, the operation of the basic circuit in FIG.

[0034] FIG. 1B is a timing chart for explaining the operation of the basic circuit of FIG. 1A. The timing chart of FIG. 1B shows the signals CK1, CK2, SP, and node N1. 4 shows a potential VN1 at the node N2, a potential VN2 at the node N3, and the signals OUTA and OUTB.

[0035] For convenience, the high-level potentials of the signals SP, CK1, and CK2 are referred to as potentials VDD, The low level potential will be described as potential VSS.

[0036] For convenience, the initial value of the potential VN1 of the node N1 is set to the potential VSS, and the initial value of the potential VN2 of the node N2 is set to the potential VSS. The initial value of the potential is explained as a potential exceeding the sum of the potential VDD and the threshold voltage of the transistor 101. do.

[0037] For convenience, the period will be described separately as period T1 and period T2.

[0038] In the period T1, the signal SP goes to a high level, the signal CK1 goes to a low level, and the signal CK 2 is the high level.

[0039] When the transistor 105 is turned on, the signal SP of the wiring 17 is supplied to the node N1. During the period T1, the signal SP is at a high level, so the potential of the node N1 rises. The potential of N1 is changed from the potential of the gate of the transistor 105 (for example, the potential VDD) to the potential of the transistor When the potential rises to a potential lower than the threshold voltage of transistor 105, transistor 105 turns off. As a result, node N1 becomes floating.

[0040] When the transistor 103 is turned on, the signal CK1 is supplied to the wiring 14. In this case, the signal CK1 is at a low level, so the potential of the wiring 14 becomes the potential VSS. The signal OUTB goes low.

[0041] When the transistor 104 is turned off, the node N2 is in a floating state. The potential of N2 is maintained at a potential exceeding the sum of the potential VDD and the threshold voltage of the transistor 101. do.

[0042] When the transistor 101 is turned on and the transistor 102 is turned off, the wiring 11 The potential VDD is supplied to the wiring 12. Therefore, the potential of the wiring 12 becomes the potential VDD. This causes the signal OUTA to go high.

[0043] In the period T2, the signal SP goes to a low level, the signal CK1 goes to a high level, and the signal CK 2 becomes low level.

[0044] When the transistor 105 is turned off, the node N1 becomes floating.

[0045] When the transistor 103 is turned on, the signal CK1 on the wiring 15 is supplied to the wiring 14. In the period T2, the signal CK1 is at a high level, so that the potential of the wiring 14 rises. At this time, the node N1 is in a floating state, and the transistor 103 is connected between the node N1 and the wiring 14. Therefore, as the potential of the wiring 14 rises, the potential of the node N1 When the potential of the node N1 becomes equal to the potential of the first terminal of the transistor 103 (for example, the potential V When the potential exceeds the sum of the potential Vdd and the threshold voltage of the transistor 103, the potential of the wiring 14 The potential becomes VDD, that is, the signal OUTB becomes high level.

[0046] When the transistor 104 is turned on, the potential VSS of the wiring 13 is supplied to the node N2. As a result, the potential of the node N2 becomes the potential VSS.

[0047] When the transistor 101 is turned off and the transistor 102 is turned on, the wiring 13 The potential VSS is supplied to the wiring 12. Therefore, the potential of the wiring 12 becomes the potential VSS. This causes the signal OUTA to go low.

[0048] As described above, the signal OUTA is at a high level during the period T1 and at a low level during the period T2. The signal OUTB is at a low level during the period T1 and at a high level during the period T2. It will be at a high level.

[0049] Next, a sequential circuit using the basic circuit of FIG.

[0050] FIG. 2(A) is a circuit diagram of a sequential circuit according to the present embodiment. The transistors 101 to 107 are provided.

[0051] The transistors 106 and 107 have the same polarity as the transistor 101. In this embodiment, the transistor 106 and the transistor 107 are preferably NMOS transistors. The following description will be given assuming that the device is of the channel type.

[0052] Note that the transistor 106 in the sequential circuit in FIG. The transistor 107 in the sequential circuit of FIG.

[0053] Next, the connections of the sequential circuit in FIG.

[0054] The connections of the transistors 101 to 105 are the same as those in the basic circuit of FIG. The first terminal of the transistor 106 is connected to the wiring 13. The second terminal of the transistor 106 is connected to the wiring 14, and the gate of the transistor 106 is A first terminal of the transistor 107 is connected to the wiring 11. The second terminal of the transistor 107 is connected to the node N2, and the gate of the transistor 107 is It is connected to wiring 16.

[0055] Next, the operation of the sequential circuit of FIG.

[0056] FIG. 2B is a timing chart for explaining the operation of the sequential circuit of FIG. 2A. The timing chart of FIG. 2B shows the signals CK1, CK2, SP, and node N1. 4 shows a potential VN1 at the node N2, a potential VN2 at the node N3, and the signals OUTA and OUTB.

[0057] For convenience, the high-level potentials of the signals SP, CK1, and CK2 are referred to as potentials VDD, The low level potential will be described as potential VSS.

[0058] For convenience, the initial value of the potential VN1 of the node N1 is set to the potential VSS, and the initial value of the potential VN2 of the node N2 is set to the potential VSS. The initial value of the potential is explained as a potential exceeding the sum of the potential VDD and the threshold voltage of the transistor 101. do.

[0059] For convenience, the period will be described separately as period T1, period T2, period T3, and period T4.

[0060] In the period T1, the signal SP goes to a high level, the signal CK1 goes to a low level, and the signal CK 2 is the high level.

[0061] When the transistor 105 is turned on, the signal SP of the wiring 17 is supplied to the node N1. During the period T1, the signal SP is at a high level, so the potential of the node N1 rises. The potential of N1 is changed from the potential of the gate of the transistor 105 (for example, the potential VDD) to the potential of the transistor When the potential rises to a potential lower than the threshold voltage of transistor 105, transistor 105 turns off. As a result, node N1 becomes floating.

[0062] When the transistor 103 is turned on and the transistor 106 is turned on, the wiring 15 The signal CK1 and the potential VSS of the wiring 13 are supplied to the wiring 14. In the period T1, the signal CK1 Since the signal OUTB is at a low level, the potential of the wiring 14 becomes the potential VSS. becomes low level.

[0063] When the transistor 107 is turned off and the transistor 104 is turned off, the node N2 Therefore, the potential of the node N2 is equal to the potential of the first terminal of the transistor 101. (for example, potential VDD) and the threshold voltage of transistor 101. .

[0064] If the initial value of the potential VN2 of the node N2 is the potential VSS, the transistor 107 is turned on. The potential VDD of the wiring 11 is supplied to the node N2.

[0065] When the transistor 101 is turned on and the transistor 102 is turned off, the wiring 11 The potential VDD is supplied to the wiring 12. Therefore, the potential of the wiring 12 becomes the potential VDD. This causes the signal OUTA to go high.

[0066] In the period T2, the signal SP goes to a low level, the signal CK1 goes to a high level, and the signal CK 2 becomes low level.

[0067] Since the transistor 105 is turned off, the node N1 is in a floating state.

[0068] When the transistor 103 is turned on and the transistor 106 is turned off, A signal CK1 is supplied to the wiring 14. Since the signal CK1 is at a high level during a period T2, The potential of the wiring 14 rises. At this time, the node N1 is in a floating state, and the transistor Between the gate of the transistor 103 and the second terminal of the transistor 103, there is a line between the node N1 and the wiring 14. Therefore, as the potential of the wiring 14 rises, the potential of the node N1 also When the potential of the node N1 becomes equal to the potential of the first terminal of the transistor 103 (for example, the potential VD D) and the threshold voltage of the transistor 103, the potential of the wiring 14 That is, the signal OUTB becomes a high level.

[0069] When the transistor 107 is turned off and the transistor 104 is turned on, the wiring 13 The potential VSS is supplied to the node N2, so that the potential of the node N2 becomes the potential VSS.

[0070] When the transistor 101 is turned off and the transistor 102 is turned on, the wiring 13 The potential VSS is supplied to the wiring 12. Therefore, the potential of the wiring 12 becomes the potential VSS. This causes the signal OUTA to go low.

[0071] In the period T3, the signal SP goes to a low level, the signal CK1 goes to a low level, and the signal CK 2 is the high level.

[0072] When the transistor 105 is turned on, the signal SP of the wiring 17 is supplied to the node N1. During the period T3, the signal SP is at a low level, so that the potential of the node N1 becomes the potential VSS. .

[0073] When the transistor 103 is turned off and the transistor 106 is turned on, the wiring 13 The potential VSS is supplied to the wiring 14. Therefore, the potential of the wiring 14 becomes the potential VSS. This causes the signal OUTB to go low.

[0074] When the transistor 107 is turned on and the transistor 104 is turned off, The potential VDD is supplied to the node N2. Therefore, the potential of the node N2 rises. The potential of transistor 107 is changed from the potential of the gate of transistor 107 (for example, potential VDD) to the potential of transistor 108. When the potential rises to a potential lower than the threshold voltage of transistor 107, the transistor 107 is turned off. , node N2 becomes floating.

[0075] When the transistor 101 is turned on and the transistor 102 is turned off, the wiring 11 The potential VDD is supplied to the wiring 12. Therefore, the potential of the wiring 12 rises. The node N2 is floating, and the gate of the transistor 101 and the second A potential difference between the node N2 and the wiring 12 is maintained between the terminals. As the potential of node N2 rises, the potential of node N2 also rises. The potential of the first terminal of the transistor 101 (for example, the potential VDD) and the threshold voltage of the transistor 101 are If the potential of the signal OU rises to a level exceeding the sum of the potentials, the potential of the wiring 12 will become the potential VDD. TA will be at a high level.

[0076] In the period T4, the signal SP goes to a low level, the signal CK1 goes to a high level, and the signal CK 2 becomes low level.

[0077] When the transistor 105 is turned off, the node N1 is in a floating state. The potential of N1 is maintained at the potential in period T3.

[0078] When the transistor 103 is turned off and the transistor 106 is turned on, the wiring 13 The potential VSS is supplied to the wiring 14. Therefore, the potential of the wiring 14 becomes the potential VSS. This causes the signal OUTB to go low.

[0079] When the transistor 107 is turned off and the transistor 104 is turned off, the node N2 Therefore, the potential of the node N2 is maintained at the potential in the period T3.

[0080] When the transistor 101 is turned on and the transistor 102 is turned off, the wiring 11 The potential VDD is supplied to the wiring 12. Therefore, the potential of the wiring 12 becomes the potential VDD. This causes the signal OUTA to go high.

[0081] As described above, the signal OUTA is at a low level during the period T2, and is at a low level during the periods T1 and T The signal OUTB is at a high level during periods T2 and T3 and T4. It is at high level during periods T1, T3, and T4.

[0082] Next, a shift register circuit using the sequential circuit of FIG. 2(A) will be described.

[0083] 3 is a circuit diagram of the shift register circuit of the present embodiment. has N (N is a natural number) sequential circuits 100 (also called N stages). , the first to third stages of sequential circuits (sequential circuit 100[1], sequential circuit 100[2], sequential circuit Only path 100[3] is shown.

[0084] As the N sequential circuits 100, the sequential circuit of FIG. 2(A) is used.

[0085] Next, the connections of the shift register circuit in FIG. 3 will be described.

[0086] The shift register circuit of FIG. 3 includes N wires 21, N wires 22, a wire 23, a wire 24, It is connected to wiring 25, wiring 26 and wiring 27.

[0087] Specifically, the sequential circuit 100 in the i-th stage (i is any one of 2 to N) (sequential circuit 100[ In the second transistor 101, the second terminal of the transistor 101 is connected to the wiring 21[i]. The gate of the transistor 102 is connected to the wiring 22[i]. The first terminal of the transistor 101 is connected to the wiring 22[i-1]. A first terminal of the transistor 102 is connected to the wiring 24. A first terminal of the transistor 103 is connected to one of the wiring 25 and the wiring 26. The gate of the transistor is connected to the other of the wiring 25 and the wiring 26 .

[0088] That is, in the sequential circuit 100[i], the wiring 21[i] corresponds to the wiring 12. Line 22[i] corresponds to wire 14. Wire 23 corresponds to wire 11. Wire 24 corresponds to wire 1. 3. One of the wiring 25 and the wiring 26 corresponds to the wiring 15. The other of 6 corresponds to wiring 16. Wiring 22[i-1] corresponds to wiring 17.

[0089] In the sequential circuit 100[i-1] or the sequential circuit 100[i+1], A first terminal of the transistor 103 is connected to the other of the wiring 25 and the wiring 26. The gate of the transistor 103 is connected to one of the wiring 25 and the wiring 26. The connection destination of the terminal of the input terminal 1 and the gate of the transistor 107 is the input terminal of the input terminal 1 in the odd-numbered stages and the even-numbered stages. Replaced.

[0090] In the sequential circuit 100[1], the first terminal of the transistor 105 is connected to the wiring 27. The connections are different from those of the sequential circuit 100 in the i-th stage.

[0091] Next, signals, potentials, and the like of the wirings 21 to 27 will be described.

[0092] A signal SOUTA is output from the wiring 21. A signal SOUTB is output from the wiring 22. A potential VDD is supplied to the wiring 23. A potential VSS is supplied to the wiring 24. A signal SCK1 is input to the wiring 25. A signal SCK2 is input to the wiring 26. A signal SSP is input to the

[0093] The signal SOUTA corresponds to the signal OUTA. The signal SOUTB corresponds to the signal OUTB. The signal SCK1 corresponds to the signal CK1 or the signal CK2. The signal SCK2 corresponds to the signal CK1. or signal CK2. Signal SSP corresponds to signal SP.

[0094] Next, the operation of the shift register circuit of FIG. 3 will be described.

[0095] FIG. 4 is a timing chart for explaining the operation of the shift register circuit of FIG. The timing chart of FIG. 4 shows the signals SSP, SCK1, SCK2, and SOUT A[1] to signal SOUTA[3], signal SOUTA[N-1], signal SOUTA[N] , signal SOUTB[1] to signal SOUTB[3], signal SOUTB[N-1], signal S Indicates OUTB[N].

[0096] When the signal SOUTB[i-1] becomes high level, the sequential circuit 100[i] is Therefore, the signal SOUTA[i] becomes high level and the signal SOUTB[ i] becomes low level.

[0097] After that, when the signals SCK1 and SCK2 are inverted, the sequential circuit 100[i] is Therefore, the signal SOUTA[i] becomes low level, and the signal SOUT B[i] becomes high level.

[0098] After that, the signals SCK1 and SOUTB[i-1] are held high until the signal SOUTB[i-1] becomes high again. Every time SCK2 is inverted, the sequential circuit 100[i] performs an operation in period T3 and an operation in period T4. Therefore, the signal SOUTA[i] becomes high level, and the signal SOU TB[i] becomes low level.

[0099] When the signal SSP goes high, the sequential circuit 100[1] stops operating during the period T1. The difference from the sequential circuit 100[i] is that

[0100] As described above, the signals SOUTA[1] to SOUTA[N] are generated when the signal SSP is at a high level. After the signal SOUTB[1] becomes a high level, the signal SOUTB[2] becomes a low level. After the signal SSP goes to high level, TB[N] goes to high level in sequence.

[0101] Next, the functions of the transistors 101 to 107 will be described.

[0102] Each of the transistors 101 to 107 has a first terminal connected to a second terminal. The first terminal has a function to control the continuity between the first terminal and the connected terminal. The transistor 10 has a function of supplying a signal or potential to a connection destination of the second terminal. 2 has a function of controlling electrical continuity or non-conduction between the wiring 13 and the wiring 12. to the wiring 12.

[0103] In addition, the transistors 101 and 103 have gates and second terminals connected to each other. For example, the transistor 101 has a function of holding a potential difference between the node N2 and It has a function of maintaining a potential difference with the wiring 12 .

[0104] The transistor 105 and the transistor 107 have first terminals connected to the second terminals. After the connection of the first terminal is made conductive, the connection of the second terminal is made non-conductive. Also, the signal or potential of the first terminal is supplied to the second terminal. After the first terminal is connected to the first terminal, the supply of a signal or potential to the first terminal is stopped. For example, After the transistor 105 makes the wiring 17 and the node N1 conductive, After the signal SP is supplied to the node N1, It has the function of stopping the supply of

[0105] The transistor 101 supplies a signal or a potential to the wiring 12 to increase the potential. The transistor 102 receives a signal or a potential for decreasing the potential of the wiring 12. The transistor 103 supplies a signal to the wiring 14 to increase the potential. The transistor 104 has a function of supplying a signal or potential to the node N2. The transistor 105 has a function of supplying a signal or a potential to turn off the transistor 101. has the function of supplying a signal or potential to the node N1 for turning on the transistor 103. The transistor 106 supplies a signal or a potential to the wiring 14 to decrease the potential. The transistor 107 has a function of turning on the transistor 101 at the node N2. The device has a function of supplying signals or electric potentials for the purpose.

[0106] In one embodiment of the present invention, the transistor is a conductive layer between the first terminal and the second terminal. Alternatively, the first transistor may be replaced with a switch having a function of controlling non-conduction. The terminal corresponds to the first terminal of the switch, and the second terminal of the transistor corresponds to the second terminal of the switch. In addition, if necessary, the gate of the transistor corresponds to the control terminal of the switch.

[0107] Next, the W / L (W: channel width, L: channel) of the transistors 101 to 107 is calculated. This section explains the length of the channel.

[0108] The W / L of the transistor 101 is greater than the W / L of the transistors 102 to 107. It is preferable that the W / L of the transistor 102 is larger than that of the transistor 104. It is preferable that the W / L of the transistor 103 is larger than the W / L of the transistor It is preferable that the W / L of the transistor 104 is larger than that of the transistor 105. It is preferable that the W / L of the transistor 106 be larger than that of the transistor 106 .

[0109] By the way, the transistors 101 to 107 are P-channel transistors. When a capacitor is used, the potential VSS is supplied to the wiring 11 and the potential VDD is supplied to the wiring 13. It is also preferable to invert the signals CK1, CK2, and SP. Then, the signals OUTA and OUTB are also inverted. When a P-channel transistor is used as the transistor 107, the above description is In the description, simply replace "rise" with "fall" and "fall" with "rise."

[0110] Next, the effects of the basic circuit, sequential circuit, and shift register circuit of this embodiment will be described. He explains.

[0111] In a circuit composed of N-channel transistors, a low-level signal is shifted. In addition, in a circuit that is configured with P-channel transistors, The bell signal can be shifted.

[0112] In addition, signals such as the signal OUTA and the signal SOUTA are generated using a small number of transistors. It is possible.

[0113] In addition, the period during which both the transistor 107 and the transistor 104 are turned on is eliminated. Therefore, the current generated between the wiring 11 and the wiring 13 can be reduced. This makes it possible to reduce power consumption.

[0114] In addition, the period during which both the transistor 101 and the transistor 102 are on is eliminated. Therefore, the current generated between the wiring 11 and the wiring 13 can be reduced. This makes it possible to reduce power consumption.

[0115] During the period when the signal CK1 is at a high level, the transistors 103 and Since the period during which both the transistors 105 and 106 are turned on can be eliminated, the distance between the wiring 15 and the wiring 13 can be reduced. Therefore, the current generated in the power supply can be reduced, and the power consumption can be reduced.

[0116] During the period T3, the transistor 105 is turned on, and the signal Therefore, the potential of the node N1 can be set to the potential VSS. This makes it easier to maintain and prevents malfunctions.

[0117] In addition, in a period T3, the transistor 107 is turned on, and the potential VDD is applied to the node N2. This makes it easier to maintain the potential of node N2 at a high potential. This makes it possible to prevent malfunctions.

[0118] In the periods T3 and T4, the transistor 106 is turned on, so that the wiring 1 3 can be supplied to the wiring 14. Therefore, the potential of the wiring 14 can be set to the potential VS This makes it easier to maintain the S and prevents malfunctions.

[0119] This embodiment mode can be implemented in appropriate combination with other embodiment modes, etc.

[0120] (Embodiment 2) In this embodiment, the basic circuit, the sequential circuit, and the shift register circuit are different from those in the first embodiment. However, the same reference numerals are used for the parts common to the first embodiment, and The explanation will be omitted.

[0121] In this embodiment, the sequential circuit of FIG. 2(A) is modified to illustrate the present embodiment. The following explanations may be given for basic circuits, sequential circuits, and shift register circuits. The configuration described in this embodiment is not limited to the sequential circuit of FIG. 2A, but may be the sequential circuit described in the first embodiment. The present invention can also be applied to other basic circuits, sequential circuits, and shift register circuits.

[0122] The basic circuit, the sequential circuit, and the shift register circuit of this embodiment are the same as those described in the first embodiment. It has the same effect as a solid effect.

[0123] First, a connection relationship of the transistor 105 that is different from that in the first embodiment will be described.

[0124] The first terminal of the transistor 105 is connected to the wiring 11, the wiring 12, the wiring 16, the wiring 17, or the node a second terminal of the transistor 105 is connected to the node N1; and a second terminal of the transistor 106 is connected to the node N2. The gate of 05 may be connected to wiring 17.

[0125] FIG. 5A shows a case where a first terminal of the transistor 105 is connected to a wiring 17 and a second terminal of the transistor 10 The second terminal of the transistor 5 is connected to the node N1, and the gate of the transistor 105 is connected to the wiring 17. FIG. 1 is a circuit diagram of a sequential circuit.

[0126] Next, a connection relationship of the transistor 107 that is different from that in the first embodiment will be described.

[0127] A first terminal of the transistor 107 is connected to the wiring 16, and a second terminal of the transistor 107 is may be connected to the node N2, and the gate of the transistor 107 may be connected to the wiring 16. A first terminal of the transistor 107 is connected to the wiring 11, and a second terminal of the transistor 107 is connected to the wiring 12. The transistor 107 may be connected to a node N2, and the gate of the transistor 107 may be connected to a wiring 11.

[0128] In FIG. 5B, the first terminal of the transistor 107 is connected to the wiring 16, and the transistor 10 A second terminal of the transistor 7 is connected to the node N2, and a gate of the transistor 107 is connected to the wiring 16. FIG. 1 is a circuit diagram of a sequential circuit.

[0129] Next, a connection relationship of the transistor 104 that is different from that in the first embodiment will be described.

[0130] A first terminal of the transistor 104 is connected to the wiring 13, and a second terminal of the transistor 104 is The gate of the transistor 104 is connected to a node N1 or a wiring 17. This is also fine.

[0131] FIG. 6A shows a case where a first terminal of the transistor 104 is connected to a wiring 13 and a second terminal of the transistor 10 The second terminal of transistor 4 is connected to node N2, and the gate of transistor 104 is connected to node N1. FIG. 1 is a circuit diagram of a sequential circuit.

[0132] Next, a connection relationship of the transistor 102 that is different from that in the first embodiment will be described.

[0133] The first terminal of the transistor 102 is connected to the wiring 13, and the second terminal of the transistor 102 is is connected to the wiring 12, and the gate of the transistor 102 is connected to the node N1 or the wiring 17. Good too.

[0134] FIG. 6B shows a case where the first terminal of the transistor 102 is connected to the wiring 13 and the transistor 10 A second terminal of the transistor 2 is connected to the wiring 12, and a gate of the transistor 102 is connected to a node N1. FIG. 1 is a circuit diagram of a sequential circuit.

[0135] Next, a connection relationship of the transistor 106 that is different from that in the first embodiment will be described.

[0136] A first terminal of the transistor 106 is connected to the wiring 13, and a second terminal of the transistor 106 is connected to the wiring 13. The gate of the transistor 106 may be connected to the wiring 14 and the gate of the transistor 107 may be connected to the wiring 16. In this way, the time during which the transistor 106 is turned on can be shortened and the period T3 Since the potential VSS of the wiring 13 can be supplied to the wiring 14 at can be stably maintained.

[0137] In FIG. 7A, the first terminal of the transistor 106 is connected to the wiring 13, and the transistor 10 The second terminal of transistor 6 is connected to wiring 14, and the gate of transistor 106 is connected to wiring 16. FIG. 1 is a circuit diagram of a sequential circuit.

[0138] Next, the transistor 201, the transistor 202, the transistor 203, and the transistor The configuration in which the sensor 204 is provided will be described.

[0139] FIG. 7B shows a transistor 201, a transistor 202, a transistor 203, and a transistor The first terminal of the transistor 201 is a wiring diagram of a sequential circuit having a transistor 204. The second terminal of the transistor 201 is connected to the line 13, and the second terminal of the transistor 202 is connected to the node N1. The gate of transistor 201 is connected to wiring 31. The first terminal of transistor 202 is connected to wiring 1. 1, the second terminal of transistor 202 is connected to node N2, and the second terminal of transistor 203 is connected to node N3. The gate of the transistor 202 is connected to the wiring 31. The first terminal of the transistor 203 is connected to the wiring 11. The second terminal of the transistor 203 is connected to the wiring 12, and the second terminal of the transistor 203 is connected to the wiring 12. The gate of the transistor 204 is connected to the wiring 31. The first terminal of the transistor 204 is connected to the wiring 13. The second terminal of the transistor 204 is connected to the wiring 14, and the gate of the transistor 204 is connected to the wiring 14. The terminal is connected to wiring 31.

[0140] A signal RE is input to the wiring 31. The signal RE is a digital signal having a high level and a low level. However, the wiring 31 is connected to the conductors of the transistors 201 to 204. It is only necessary that a signal for controlling the conduction or non-conduction is input.

[0141] In the sequential circuit 100[i], the wiring 31 corresponds to the wiring 22[i+1]. The wiring 31 is the wiring 22[i+n] such as the wiring 22[i+2] or the wiring 22[i+3]. (n is a natural number).

[0142] When the signal RE goes high, the transistors 201 to 204 are turned on. When the transistor 201 and the transistor 204 are turned on, the potential V SS is supplied to the node N1 and the wiring 14. Therefore, the potentials of the node N1 and the wiring 14 are The potential VSS is reached. Also, the transistor 202 and the transistor 203 are turned on. Therefore, the potential VDD of the wiring 11 is supplied to the node N2 and the wiring 12. The potential of the wiring 12 becomes higher than the potential VDD or the potential VSS.

[0143] On the other hand, when the signal RE goes low, the transistors 201 to 204 are turned on. It becomes Fu.

[0144] An example of the timing of the signal RE will be described. The wiring 31 corresponds to the wiring 22[i+1]. If the signal RE corresponds to the signal OUTB[i+1], then the signal RE corresponds to the signal OUTB[i+1]. It becomes high level after the period T2 (for example, the period T3 immediately after the period T2), and During period T2, the sequential circuit can be initialized. do.

[0145] Note that one, two, or three transistors selected from the transistors 201 to 204 It is also possible to provide only a transistor.

[0146] Next, the transistor 205, the transistor 206, the transistor 207, and the transistor The configuration in which the sensor 208 is provided will be described.

[0147] FIG. 8A shows a transistor 205, a transistor 206, a transistor 207, and a transistor 1 is a circuit diagram of a sequential circuit including a transistor 208. The connection of 208 is such that the gate is connected to the wiring 32 and the transistor 201 . . , different from the transistor 204.

[0148] In addition, in all or at least two of the N sequential circuits 100, the transistors 205 The gates of the transistors 208 are connected in common.

[0149] A signal INI is input to the wiring 32. The signal INI has a high level and a low level. The signal is a digital signal. However, the wiring 32 is connected to the transistors 205 to 208. It is only necessary that a signal for controlling the conduction or non-conduction of the transistor is input.

[0150] When the signal INI goes high, the transistors 205 to 208 are turned on. When the transistor 205 and the transistor 208 are turned on, The potential VSS is supplied to the node N1 and the wiring 14. The potential becomes the potential VSS. Also, the transistor 206 and the transistor 207 are turned on. As a result, the potential VDD of the wiring 11 is supplied to the node N2 and the wiring 12. The potentials of the node N2 and the wiring 12 become higher than the potential VDD or the potential VSS.

[0151] On the other hand, when the signal INI becomes low level, the transistors 205 to 208 It will be turned off.

[0152] An example of the timing of the signal INI will be described. Therefore, the first-stage sequential circuit 100 is in the period T1. Each sequential circuit 100 can be initialized before the operation in This can help prevent the following:

[0153] Note that after the signal OUTB[N] becomes high level and the signal SSP becomes high level, It is preferable that the signal INI goes to a high level before the power supply is turned on. And before the signal SSP goes high, the signal INI goes high. Good too.

[0154] Note that the first terminal of the transistor 207 may be connected to the wiring 13.

[0155] Note that the gates of the transistors 205 to 208 may be connected to the wiring 27. That is, the signal SSP may be used as the signal INI.

[0156] Note that one, two, or three selected from the transistors 205 to 208 It is also possible to provide only a transistor.

[0157] Next, a configuration in which the transistor 209 and the transistor 210 are provided will be described.

[0158] FIG. 8B is a circuit diagram of a sequential circuit including a transistor 209 and a transistor 210. A first terminal of the transistor 209 is connected to the wiring 13. The second terminal is connected to a wiring 14 , and the gate of the transistor 209 is connected to a wiring 16 . A first terminal of the transistor 210 is connected to the wiring 11, and a second terminal of the transistor 210 is connected to the wiring 11. The terminal of transistor 210 is connected to wiring 12 , and the gate of transistor 210 is connected to wiring 16 .

[0159] When the signal CK2 goes high, the transistors 209 and 210 are turned on. When the transistor 209 is turned on, the potential VSS of the wiring 13 is supplied to the wiring 14. When the transistor 210 is turned on, the potential VDD of the wiring 11 is supplied to the wiring 12. .

[0160] On the other hand, when the signal CK2 goes low, the transistors 209 and 210 It will be turned off.

[0161] The signal CK2 is at a high level during periods T1 and T3, and is at a low level during periods T2 and T4. Therefore, in the periods T1 and T3, the potential V The potential SS is supplied to the wiring 14, and the potential VDD of the wiring 11 is supplied to the wiring 12. In particular, during the period At T3, the signal CK2 goes high, so that the potential VSS of the wiring 13 is The potential VDD of the wiring 11 is periodically supplied to the wiring 12. Therefore, the potentials of the wirings 14 and 12 can be easily maintained.

[0162] Note that only one of the transistor 209 and the transistor 210 may be provided.

[0163] Next, a configuration in which the transistor 211 and the transistor 212 are provided will be described.

[0164] FIG. 9A is a circuit diagram of a sequential circuit including a transistor 211 and a transistor 212. A first terminal of the transistor 211 is connected to the wiring 17. The second terminal of the transistor 211 is connected to the first terminal of the transistor 105, and the gate of the transistor 211 is A first terminal of the transistor 212 is connected to the wiring 31. The second terminal of the resistor 212 is connected to the first terminal of the transistor 105. The gate of 212 is connected to wiring 34 .

[0165] In addition, in all or at least two of the N sequential circuits 100, The gates are connected to a common node, and the gates of transistors 212 are connected to a common node.

[0166] A signal SC1 is input to the wiring 33. The signal SC1 has a high level and a low level. The signal is a digital signal. However, the wiring 33 is connected to a A signal or potential for the purpose of the control may be input to the wiring 34. The signal SC2 is a digital signal having a high level and a low level. A signal or a potential for controlling the conduction or non-conduction of the transistor 212 is supplied to the wiring 34. It is sufficient that the information has been entered.

[0167] When the signal SC1 goes high and the signal SC2 goes low, the transistor 211 turns on and transistor 212 turns off. When transistor 211 turns on, A signal SP on a wiring 17 is supplied to a first terminal of a transistor 105 .

[0168] On the other hand, when the signal SC1 goes low and the signal SC2 goes high, the transistor 211 is turned off and transistor 212 is turned on. Then, the signal RE on the wiring 31 is supplied to the first terminal of the transistor 105.

[0169] An example of the timing of the signals SC1 and SC2 will be described. When the shift direction is from the sequential circuit 100[1] to the sequential circuit 100[N], Signal SC1 goes high and signal SC2 goes low. When the shift direction of the path is from the sequential circuit 100[N] to the sequential circuit 100[1], , the signal SC1 goes low and the signal SC2 goes high.

[0170] Next, a configuration in which the transistor 213 and the transistor 214 are provided will be described.

[0171] FIG. 9B is a circuit diagram of a sequential circuit including a transistor 213 and a transistor 214. The first terminal of the transistor 213 is connected to the second terminal of the transistor 105. The second terminal of the transistor 213 is connected to the gate of the transistor 103. The gate of the transistor 213 is connected to the wiring 11. The first terminal of the transistor 214 is The second terminal of transistor 214 is connected to the second terminal of transistor 107. The gate of transistor 214 is connected to wiring 11.

[0172] By including the transistor 213, the potential of the gate of the transistor 103 increases. Therefore, deterioration of the transistor 103 can be suppressed or insulation breakdown can be prevented. It is possible to prevent destruction, etc.

[0173] In addition, by including the transistor 214, the potential of the gate of the transistor 101 is increased. Therefore, deterioration of the transistor 101 can be suppressed or It is possible to prevent dielectric breakdown, etc. Also, the Vgs of the transistor 106 can be reduced. Therefore, deterioration of the transistor 106 can be suppressed.

[0174] The gate of the transistor 213 is connected to the wiring 12, the wiring 16, the wiring 17, and the transistor 10. The first terminal of the transistor 213 may be connected to the gate of the wiring 17. The second terminal of the transistor 213 may be connected to the first terminal of the transistor 105. good.

[0175] Note that the gate of the transistor 214 may be connected to the wiring 12, the wiring 16, or the like. A first terminal of the transistor 214 is connected to the wiring 11, and a second terminal of the transistor 214 is It may be connected to the first terminal of the transistor 107.

[0176] The gate of the transistor 106 may be connected to the second terminal of the transistor 104. .

[0177] Note that only one of the transistor 213 and the transistor 214 may be provided.

[0178] Next, a configuration in which some of the transistors are replaced with switches will be described.

[0179] FIG. 10A shows a transistor 104, a transistor 106, and a transistor 107. FIG. 1 is a circuit diagram of a sequential circuit using switches 104S, 106S, and The switch 107S is connected to the transistors 104, 106, and The first terminal of the switch 104S is connected to the wiring 13. The second terminal of switch 104S is connected to the gate of transistor 101. A first terminal of the switch 106S is connected to the wiring 13, and a second terminal of the switch 106S is connected to the wiring 14. A first terminal of the switch 107S is connected to the wiring 11, and a second terminal of the switch 107S is connected to the wiring 11. The terminal is connected to the gate of the transistor 101 .

[0180] In a period T1, the switch 104S is turned off and the switch 106S is turned on. During the period T2, the switch 104S is turned on. During the period T3, the switch 106S is turned off and the switch 107S is turned off. Then, switch 104S is turned off, switch 106S is turned on, and switch 107 During a period T4, the switch 104S is turned off, and the switch 1 Switch 06S is turned on and switch 107S is turned off.

[0181] The switch 104S may be turned on during the period T1. The switch 107S may be turned off during one of the periods T3 and T4. may be turned on in period T4.

[0182] FIG. 10B shows a basic circuit in which a switch 104S is used as the transistor 104. FIG. 11(A) shows a circuit diagram of the basic circuit of FIG. 10(B) with a switch 106S. FIG. 11(B) is a circuit diagram of the basic circuit shown in FIG. 10(B) with a switch. FIG. 1 is a circuit diagram of a basic circuit including a filter 107S.

[0183] Next, the functions of the transistors 201 to 214 will be described.

[0184] Each of the transistors 201 to 214 has a first terminal connected to a second terminal. The first terminal has a function of controlling the electrical continuity between the first terminal and the connected terminal. The transistor 2 has a function of supplying a signal or a potential to a connection destination of the second terminal. 01 has a function of controlling conduction or non-conduction between the wiring 13 and the node N1. It has the function of supplying SS to node N1.

[0185] The transistor 213 and the transistor 214 have a first terminal and a second terminal. After the connection of the first terminal is made conductive, the connection of the second terminal is made non-conductive. Also, the signal or potential of the first terminal is supplied to the second terminal. After the first terminal is connected to the first terminal, the supply of a signal or potential to the first terminal is stopped. For example, The transistor 213 is connected to the second terminal of the transistor 105 and the gate of the transistor 103. After turning on the second terminal of the transistor 105 and the gate of the transistor 103, In addition, the potential of the second terminal of the transistor 105 is set to the node N1 After the potential is supplied to the second terminal of the transistor 105, the supply of the potential to the second terminal of the transistor 105 is stopped.

[0186] By the way, the transistors 201 to 214 have the same polarity as the transistor 101. It is preferable that the

[0187] The W / L of the transistor 101 is the same as the W / L of the transistors 201 to 214. It is preferably larger than L.

[0188] This embodiment mode can be implemented in appropriate combination with other embodiment modes, etc.

[0189] (Embodiment 3) In this embodiment, a display device according to one embodiment of the present invention will be described.

[0190] FIG. 12A is a circuit diagram of the display device of the present embodiment. The display device of FIG. A pixel section 300, a gate driver 301, a gate driver 302, and a source driver 3 The pixel section 300 includes a plurality of pixels 310. The transistors 311, 312, the display element 313, and the circuit 32 are respectively 0. Note that the gate driver 302 is the same as that in the first and second embodiments. A shift register circuit can be used.

[0191] In one embodiment of the present invention, a liquid crystal element (also called a liquid crystal display element) is used as a display element. A light-emitting element (also called a light-emitting display element) can be used. This category includes elements whose brightness is controlled by pressure, specifically inorganic EL (Electroluminescent) In addition, electronic luminescence (EL) elements, organic EL elements, etc. A display medium whose contrast changes due to electrical effects, such as ink, can also be used.

[0192] Next, the connections of the display device in FIG. 12(A) will be described.

[0193] The gate driver 301 is connected to N wirings 41. The gate driver 302 is connected to N wirings 41. The source driver 303 is connected to M (M is a natural number) wirings 43. In addition, in FIG. 12A, the i-th wiring 41 (wiring 41[i]) out of the N wirings 41 is shown. ), the i-th wiring 42 (indicated as wiring 42[i]) among the N wirings 42, The jth wiring 43 (referred to as wiring 43[j]) (j is any one of 1 to M) among the lines 43 Show only.

[0194] Among the multiple pixels 310, a pixel 310 belonging to the i-th row and j-th column (referred to as pixel 310[i, j]) ) is connected to wiring 41[i], wiring 42[i], wiring 43[j] and wiring 44.

[0195] In the pixel 310[i, j], the first terminal of the transistor 311 is connected to the wiring 44. The gate of the transistor 311 is connected to the circuit 320. The terminal is connected to the second terminal of the transistor 311, and the second terminal of the transistor 312 is The display element 313 is connected to the gate of the transistor 312, and the gate of the transistor 312 is connected to the wiring 42[i]. In addition, the circuit 320 is connected to a wiring 43[j] and a wiring 41[i].

[0196] A voltage is input to the wiring 44. The wiring 44 supplies a current to the display element 313. It has the function of

[0197] The gate driver 302 is the shift register circuit of the first and second embodiments. In this case, N wires 42 correspond to N wires 21. For example, if wire 42[i] is It corresponds to wiring 21[i].

[0198] Next, the operation of the display device of FIG.

[0199] The gate driver 301 sequentially outputs a high-level signal to the N wirings 41. The source driver 302 sequentially outputs low-level signals to the N wirings 42. 03 outputs a video signal to M wirings 43 .

[0200] For example, in pixel 310[i, j], the gate driver 301 transmits a high-level signal to line 4. When the video signal is output to line 1[i], the video signal on line 43[j] is written. This is the video signal that the source driver 303 outputs to the wiring 43[j]. 0[i, j] indicates that the gate driver 301 again outputs a high-level signal to the wiring 41[i]. The video signal is held until the video signal is received, and a display according to the video signal is performed.

[0201] Specifically, when the gate driver 301 outputs a high-level signal to the wiring 41[i], The video signal is input to a circuit 320. The circuit 320 converts the video signal into The video signal is then subjected to correction according to the threshold voltage and / or mobility, etc., and the corrected video signal is then input to the transceiver. The gate of transistor 311 is then supplied with the corrected video signal. However, if the video signal is not input to the circuit 320, a current corresponding to the video signal can be supplied. the period during which the video signal is input, the period during which the circuit 320 applies correction to the video signal, and / or During the initialization period before the video signal is input to the transistor 311, the current is If this current is supplied to the display element, the gray scale will be wrong. Therefore, during the above-mentioned period, the gate driver When the driver 302 outputs a low-level signal to the wiring 42[i], the transistor Turn off 312.

[0202] The gate driver 302 is the shift register circuit of the first and second embodiments. In this case, the signals output by the gate driver 302 to the wirings 42[1] to 42[N] are The signals correspond to the signals SOUTA[1] to SOUTA[N]. For example, The signal that the output of ...

[0203] As shown in FIG. 12B, the connection point between the transistor 311 and the transistor 312 You may switch places.

[0204] The shift register circuit of the first and second embodiments is used as the gate driver 302. By this, the gate driver 302 is configured with transistors of the same polarity as the transistors of the pixels. Therefore, not only the gate driver 301 but also the gate driver The pixel section 300 and the pixel section 302 can be formed on the same substrate.

[0205] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0206] (Embodiment 4) In this embodiment, a cross-sectional structure of a pixel and a driver circuit of a display device according to one embodiment of the present invention will be described. An EL display device will be taken as an example for explanation.

[0207] FIG. 13 is a cross-sectional view of the display device of this embodiment, showing a pixel 840 and a driver circuit 841. The surface view is shown.

[0208] The pixel 840 includes a light emitting element 832 and a transistor having a function of supplying a current to the light emitting element 832. The pixel 840 includes a light-emitting element 832 and a transistor 831. In addition, a transistor for controlling the input of an image signal to the pixel 840 and / or a The semiconductor device may include various semiconductor elements such as a capacitor element for holding a potential.

[0209] The driving circuit 841 is a transistor 830 and holds the gate voltage of the transistor 830. The driver circuit 841 includes the driver circuit 841 shown in FIG. It corresponds to basic circuits, sequential circuits, shift register circuits, etc. Specifically, transistor 8 30 corresponds to the transistor 101, etc. In addition, the driving circuit 841 includes a transistor 83 In addition to the semiconductor element 833 and the capacitor element 833, various semiconductor elements such as transistors and capacitor elements are included. It may be possible.

[0210] The transistor 831 is formed by forming a conductive film serving as a gate on a substrate 800 having an insulating surface. 816, the gate insulating film 802 on the conductive film 816, and the conductive film 816 at a position overlapping the gate insulating film 802. A semiconductor film 817 located on the gate insulating film 802 and a source terminal or a drain terminal The conductive film 815 and the conductive film 818 are located over the semiconductor film 817. The film 816 also functions as a scan line.

[0211] The transistor 830 is formed by forming a conductive film serving as a gate on a substrate 800 having an insulating surface. 812, the gate insulating film 802 on the conductive film 812, and the conductive film 812 at a position overlapping the gate insulating film 802 A semiconductor film 813 located on the gate insulating film 802 and a source terminal or a drain terminal The semiconductor film 813 includes a conductive film 814 and a conductive film 819 located over the semiconductor film 813 .

[0212] The capacitor 833 is formed by forming a conductive film 812 over a substrate 800 having an insulating surface. The gate insulating film 802 and the conductive film 812 are overlapped with each other. The conductive film 819 is disposed on the substrate 811.

[0213] An insulating film 820 and an insulating layer 821 are formed on the conductive film 814, the conductive film 815, the conductive film 818, and the conductive film 819. The insulating film 821 is provided so as to be laminated in order. A conductive film 822 serving as an electrode is provided. The conductive film 822 is formed by insulating film 820 and The insulating film 821 is connected to the conductive film 818 via a contact hole 823 formed in the insulating film 821. do.

[0214] An insulating film 824 having an opening through which a part of the conductive film 822 is exposed is formed on the insulating film 821. An EL layer 825 and a cathode are provided on a part of the conductive film 822 and the insulating film 824. A conductive film 822 and a conductive film 826 that functions as a conductive film are stacked in this order. The region where the EL layer 825 and the conductive film 826 overlap corresponds to a light-emitting element 832 .

[0215] Note that in one embodiment of the present invention, the transistor is amorphous, microcrystalline, polycrystalline, or single crystal. The semiconductor film may be made of a semiconductor such as silicon or germanium. A wide gap semiconductor such as a nitride semiconductor may be used for the semiconductor film.

[0216] The semiconductor film of the transistor is made of amorphous, microcrystalline, polycrystalline, or single-crystalline silicon or When a semiconductor such as ruthenium is used, an impurity element that imparts one conductivity is added to the semiconductor. The doping of the film forms impurity regions that function as source or drain terminals. For example, by adding phosphorus or arsenic to the semiconductor film, an impurity region having n-type conductivity is formed. In addition, for example, by adding boron to the semiconductor film, a p It is possible to form an impurity region having a type of conductivity.

[0217] In addition, when an oxide semiconductor is used for a semiconductor film of a transistor, a dopant is added to the above semiconductor. By adding it to the conductive film, an impurity region that functions as a source terminal or a drain terminal is formed. The dopant may be added by ion implantation. For example, rare gases such as helium, argon, and xenon, and nitrogen, phosphorus, arsenic, and antimony For example, when nitrogen is used as a dopant, The concentration of nitrogen atoms in the pure region is 5×10 19 / cm3 More than 1×10 22 / cm 3 Below It is desirable that there be.

[0218] Silicon semiconductors are grown by vapor phase growth methods such as plasma CVD or sputtering. Amorphous silicon produced by the laser annealing method, amorphous silicon Polycrystalline silicon that has been crystallized by implanting hydrogen ions into single crystal silicon wafers. For example, single crystal silicon from which a portion has been peeled off can be used.

[0219] The oxide semiconductor contains at least indium (In) or zinc (Zn). It is preferable that the oxide semiconductor contains In and Zn. As a stabilizer to reduce the variation in the electrical characteristics of the transistors In addition, it is preferable to have gallium (Ga). Also, tin (S n) as a stabilizer. It is preferable that the stabilizer is aluminum (Al). It is.

[0220] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru It may contain one or more of the elements tetraethium (Lu).

[0221] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and In-Zn oxide. substances, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg oxides In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide (IGZO and (also written as In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Z n-based oxides, Al-Ga-Zn-based oxides, Sn-Al-Zn-based oxides, In-Hf-Zn In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide Oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides , In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn -Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide The oxide semiconductor may contain silicon.

[0222] For example, In-Ga-Zn oxide means an oxide containing In, Ga, and Zn. The ratio of In, Ga, and Zn is not important. In addition, metal elements other than In, Ga, and Zn In-Ga-Zn oxides have a sufficiently high resistance when no electric field is present, and therefore, Since the current can be made sufficiently small and the mobility is high, it is suitable for use in transistors. It is suitable as a semiconductor material.

[0223] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn oxide with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) The oxides of In:Sn:Zn=1: 1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is advisable to use an In-Sn-Zn oxide having a molecular ratio or an oxide having a composition close to that.

[0224] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, in the case of In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0225] In addition, impurities such as moisture and hydrogen, which act as electron donors, are reduced, and the acid The reduced electron vacancies result in a highly purified oxide semiconductor. A de semiconductor is an i-type (intrinsic semiconductor) or is very close to an i-type. Therefore, the off-state current of a transistor including the oxide semiconductor is extremely low. The band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more. More preferably, the concentration of impurities such as moisture or hydrogen is sufficiently reduced. In addition, an oxide semiconductor film that has been highly purified by reducing oxygen vacancies is used. This allows the off-state current of the transistor to be reduced.

[0226] Specifically, the off-state current of a transistor using a highly purified oxide semiconductor for a semiconductor film is low. For example, when the channel width is 1×10 6 μm Even with a device with a channel length of 10 μm, the voltage between the source and drain terminals (drain voltage When the applied voltage is in the range of 1V to 10V, the off-state current is measured by a semiconductor parameter analyzer. Below the limit, i.e. 1×10 -13 In this case, the characteristic of A or less can be obtained. The off-state current density, which corresponds to the off-state current divided by the transistor channel width, is 100zA. In addition, the capacitance element is connected to a transistor, and the capacitance element A circuit that controls the charge flowing into or out of a capacitance element using the transistor is used. The current density was measured using a highly purified oxide semiconductor. A conductive film is used for the channel formation region, and the charge amount per unit time of the capacitance element is used to determine the channel. The off-current density of the transistor was measured. As a result, the source terminal and drain terminal of the transistor At a terminal voltage of 3 V, an even lower off-state current density of several tens of yA / μm is obtained. Therefore, it was found that the highly purified oxide semiconductor film was used for the channel formation region. The off-state current of the transistor is significantly lower than that of a transistor using crystalline silicon. Very low.

[0227] In this specification and the like, the off-state current is a current that flows through the drain of an n-channel transistor. With the in terminal at a higher potential than the source terminal and gate terminal, the potential of the source terminal is When the gate potential is below 0V, a current flows between the source and drain terminals. In p-channel transistors, the off-state current is is the potential of the source terminal when the drain terminal is at a lower potential than the source terminal and gate. When the potential of the gate is 0 or more with respect to the potential of the This refers to the current that flows between the insulators.

[0228] For example, the oxide semiconductor film may be formed using In (indium), Ga (gallium), and Zn ( It can be formed by sputtering using a target containing In-Ga- When the Zn-based oxide semiconductor film is formed by a sputtering method, the atomic ratio is preferably In :Ga:Zn=1:1:1, 4:2:3, 3:1:2, 1:1:2, 2:1:3, or A target of In-Ga-Zn oxide with the atomic ratio of 3:1:4 is used. The oxide semiconductor film is formed by using an In-Ga-Zn oxide target having the above structure. Polycrystals or CAAC (described later) are easily formed. In, Ga, and Zn The filling rate of the target containing the above is 90% or more and 100% or less, preferably 95% or more and less than 100%. By using a target with a high filling rate, the oxide semiconductor film formed is dense. This results in a thin membrane.

[0229] In addition, when an In-Zn-based oxide material is used for the oxide semiconductor film, a target to be used The composition of the compound is In:Zn=50:1 to 1:2 in atomic ratio (InO 3:ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1:1 (molar ratio In terms of the ratio, In2O3:ZnO=10:1 to 1:2), and more preferably In:Zn= 1.5:1 to 15:1 (converted to a molar ratio of In2O3:ZnO=3:4 to 15:2) For example, the target used for forming an oxide semiconductor film made of an In-Zn oxide is When the atomic ratio is In:Zn:O=X:Y:Z, Z>1.5X+Y. The ratio of Zn Within the above range, it is possible to improve the mobility.

[0230] Specifically, the oxide semiconductor film is formed by holding the substrate in a treatment chamber that is kept in a reduced pressure state. The residual moisture in the treatment chamber is removed while introducing a sputtering gas from which hydrogen and moisture have been removed. During the film formation, the substrate temperature is preferably set to 100° C. or higher and 600° C. or lower. Preferably, the temperature may be 200° C. or higher and 400° C. or lower. In this way, the impurity concentration in the formed oxide semiconductor film can be reduced. Damage caused by tarring is reduced. To remove residual moisture in the processing chamber, an adsorption type It is preferable to use a vacuum pump. For example, a cryopump, an ion pump, a titanium sa It is preferable to use a blimpation pump. Also, as the exhaust means, a turbo pump is used. A cold trap may be added to the vacuum chamber. The deposition chamber is evacuated using a cryopump. Then, for example, hydrogen atoms, water (H2O) and other compounds containing hydrogen atoms (preferably carbon Since the exhaust gas contains fluorine atoms, the oxide semiconductor film formed in the treatment chamber is This can reduce the concentration of impurities contained in the material.

[0231] Note that moisture or hydrogen ( Water or hydrogen can form donor levels and Therefore, in one embodiment of the present invention, To reduce impurities such as moisture or hydrogen in semiconductor films (dehydration or dehydrogenation) For the oxide semiconductor film, a reduced pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, or an oxygen atmosphere is used. Under nitrogen gas atmosphere or ultra-dry air (CRDS (cavity ring-down laser spectroscopy) When measured using a dew point meter, the moisture content is 20 ppm (-55°C in dew point equivalent) or less. The heat treatment is performed in an atmosphere of air, preferably 1 ppm or less, preferably 10 ppb or less. Carry out.

[0232] By performing heat treatment on the oxide semiconductor film, moisture or hydrogen is released from the oxide semiconductor film. Specifically, the substrate temperature is 250° C. or higher and 750° C. or lower, preferably 400° C. or higher. For example, the heat treatment may be performed at 500° C. for 3 to 6 minutes. If the RTA method is used for the heat treatment, dehydration or dehydrogenation can be carried out in a short time. Therefore, processing can be performed at temperatures exceeding the distortion point of the glass substrate.

[0233] Note that the heat treatment causes oxygen to be released from the oxide semiconductor film and the oxygen to be left in the oxide semiconductor film. Therefore, in one embodiment of the present invention, a vacancy may be formed in the gate electrode in contact with the oxide semiconductor film. An insulating film containing oxygen is used as an insulating film such as a gate insulating film. After the insulating film is formed, heat treatment is performed, whereby oxygen is supplied from the insulating film to the oxide semiconductor film. With the above structure, oxygen vacancies serving as donors are reduced, and oxygen atoms contained in the oxide semiconductor film are As a result, the oxide semiconductor film can have a stoichiometric composition. This makes it possible to approach the i-type, and reduces the variation in the electrical characteristics of transistors due to oxygen vacancies. It is possible to reduce the capacitance and improve the electrical characteristics.

[0234] Note that the heat treatment for supplying oxygen to the oxide semiconductor film is performed using nitrogen, ultra-dry air, or rare earth metal. In a gas (argon, helium, etc.) atmosphere, preferably at 200°C to 400°C The gas has a water content of 20 ppm or less. It is desirable that the concentration is not more than 1 ppm, and more preferably not more than 10 ppb.

[0235] The oxide semiconductor film may be in a single crystal, polycrystalline (also referred to as polycrystalline), amorphous, or other state. Take a stance.

[0236] Preferably, the oxide semiconductor film is a CAAC-OS (C Axis Aligned Cr The film is a crystalline oxide semiconductor.

[0237] In addition, the crystal part is often small enough to fit inside a cube with one side less than 100 nm. In addition, a transmission electron microscope (TEM) The image observed by a microscope shows the amorphous and crystalline parts of the CAAC-OS film. The boundaries between the crystals and between the crystalline regions are not clear. No clear grain boundaries can be seen in the S film. In the AAC-OS film, the decrease in electron mobility caused by grain boundaries is suppressed.

[0238] The crystal parts in the CAAC-OS film have c-axes that are normal vectors to the surface on which the CAAC-OS film is formed. The triangle is aligned parallel to the normal vector of the ab plane and perpendicular to the ab plane. The metal atoms are arranged in a layered or hexagonal shape when viewed perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. The orientation of the a and b axes may be different. In this specification, when it is simply described as vertical, it means that The range of 5° to 95° is also included. This also includes the range from 1° to 5°.

[0239] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the growth surface. By adding impurities to the AC-OS film, the crystalline part becomes amorphous in the impurity-added region. It may also be pawned.

[0240] The c-axis of the crystal part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The CAAC-OS film shape (the shape of the film on which the film is formed) is Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface, the directions may differ from each other. The direction of the c-axis of the crystal is the normal vector of the surface on which the CAAC-OS film is formed. The direction of the crystal is parallel to the normal vector of the film or surface. is formed by carrying out a crystallization treatment such as a heat treatment after the film formation.

[0241] The electrical characteristics of transistors using CAAC-OS films change when exposed to visible or ultraviolet light. Therefore, the transistor has high reliability.

[0242] Note that part of oxygen contained in the oxide semiconductor film may be replaced with nitrogen.

[0243] Next, a specific example of a structure of a transistor according to one embodiment of the present invention will be described.

[0244] The transistor shown in FIG. 14A is a bottom-gate type transistor with a channel-etched structure.

[0245] The transistor shown in FIG. 14(A) has a gate electrode (gate) 16 formed on an insulating surface. 1602, a gate insulating film 1603 on the gate electrode 1602, and A semiconductor film 1604 overlapping the gate electrode 1602 and a gate electrode 1603 formed on the semiconductor film 1604 The transistor further includes a conductive film 1605 and a conductive film 1606. 1604, a conductive film 1605, and an insulating film 1607 formed on the conductive film 1606. It may be included in the composition element.

[0246] Note that the transistor shown in FIG. 14A has an insulating layer at a position overlapping with the semiconductor film 1604. It may further include a back gate electrode formed on the insulating film 1607 .

[0247] The transistor shown in FIG. 14B is a bottom-gate transistor with a channel protection structure.

[0248] The transistor shown in FIG. 14B has a gate electrode 1612 formed on an insulating surface and a gate A gate insulating film 1613 on the gate electrode 1612 and a gate insulating film 1613 on the gate electrode 1612 A semiconductor film 1614 overlapping the electrode 1612 and a channel formed on the semiconductor film 1614 A conductive film 1615 and a conductive film 1616 are formed on the semiconductor film 1614. The transistor further includes a channel protective film 1618, a conductive film 1615, and An insulating film 1617 formed over the conductive film 1616 may be included as a component thereof.

[0249] Note that the transistor shown in FIG. 14B has an insulating layer at a position overlapping with the semiconductor film 1614. It may further include a back gate electrode formed on the insulating film 1617 .

[0250] By providing a channel protective film 1618, the channel forming region of the semiconductor film 1614 and In the later process, the film is formed by plasma or etching agent during etching on the part that will be This prevents damage such as wear and tear, thus improving the reliability of the transistor. can be done.

[0251] The transistor shown in FIG. 14C is a bottom-gate type transistor having a bottom-contact structure.

[0252] The transistor shown in FIG. 14C has a gate electrode 1622 formed on an insulating surface and a gate A gate insulating film 1623 on the gate electrode 1622 and a conductive film 162 on the gate insulating film 1623 5. A conductive film 1626 and a gate electrode 1622 are overlapped on the gate insulating film 1623. In addition, the semiconductor film 1624 is formed over the conductive film 1625 and the conductive film 1626. Further, the transistor includes a conductive film 1625, a conductive film 1626, and a semiconductor film 162 The insulating film 1627 formed on the semiconductor device 4 may be included as a component thereof.

[0253] Note that the transistor shown in FIG. 14C has an insulating layer at a position overlapping with the semiconductor film 1624. It may further include a back gate electrode formed on the insulating film 1627 .

[0254] The transistor shown in FIG. 14D is a top-gate type with a bottom-contact structure.

[0255] The transistor shown in FIG. 14D includes a conductive film 1645 formed on an insulating surface, a conductive film 1 646, the insulating surface and the conductive film 1645, and the semiconductor film 164 formed on the conductive film 1646 4, and a gate insulating film formed on the semiconductor film 1644, the conductive film 1645, and the conductive film 1646. A gate insulating film 1643 and a semiconductor film 1644 overlapping the gate insulating film 1643. The transistor further includes a gate electrode 1642 formed on the gate electrode 1642. An insulating film 1647 may be included as a component thereof.

[0256] The transistor of this embodiment is used in the basic circuits, sequential circuits, and Transistors forming a shift register circuit and a display device according to the third embodiment In particular, a transistor using an oxide semiconductor has a high mobility. Therefore, the basic circuits of the first and second embodiments have a high switching current and a low off-state current. The present invention can operate the display device of the third embodiment at high speed. In addition, the amount of charge leaking from each node can be reduced.

[0257] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0258] (Embodiment 5) A basic circuit, a sequential circuit, a shift register circuit, a display device, and the like according to one embodiment of the present invention A display device, a personal computer, and an image reproducing device equipped with a recording medium (typically a DVD: Plays recording media such as Digital Versatile Discs and displays the images In addition, the present invention can be used in a display device having a display that can display images. The present invention relates to a basic circuit, a sequential circuit, a shift register circuit, a display device, and the like that can be used. Sub-devices include mobile phones, handheld game consoles, personal digital assistants, e-books, and video cameras. La, digital still camera, goggle-type display (head-mounted display), Navigation systems, audio playback devices (car audio, digital audio players) -, etc.), copiers, facsimiles, printers, printer-combination machines, automated teller machines Examples of such electronic devices include ATMs and vending machines. Specific examples of such electronic devices are shown in Figure 15.

[0259] FIG. 15A shows a portable game machine, which includes a housing 5001, a housing 5002, a display unit 5003, Display unit 5004, microphone 5005, speaker 5006, operation keys 5007, The portable game machine shown in FIG. 15(A) has two displays. The portable game machine has a display unit 5003 and a display unit 5004. This is not limited to the above.

[0260] FIG. 15B shows a display device, which includes a housing 5201, a display portion 5202, a support stand 5203, and the like. Display devices include those for personal computers, those for receiving TV broadcasts, and those for displaying advertisements. This includes all display devices for displaying information.

[0261] FIG. 15C shows a notebook personal computer, which includes a housing 5401 and a display unit 5402. 5403, a pointing device 5404, and the like.

[0262] FIG. 15D shows a portable information terminal, which includes a first housing 5601, a second housing 5602, a first display unit, and a 5603, a second display unit 5604, a connection unit 5605, and operation keys 5606. The display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 5602. The first housing 5601 and the second housing 5602 are connected to each other via a connection portion 5602. 5605, and the angle between the first housing 5601 and the second housing 5602 is The first display unit 5603 is connected to the The switching is performed according to the angle between the first housing 5601 and the second housing 5602 at the portion 5605. It may also be configured in this way.

[0263] FIG. 15E shows a mobile phone. The mobile phone includes a housing 5801, a display unit 5802, an audio input unit 5803, The device has a voice output unit 5804, an operation key 5805, a light receiving unit 5806, etc. The received light is converted into an electrical signal, allowing an external image to be captured.

[0264] This embodiment mode can be implemented in appropriate combination with other embodiment modes. [Explanation of symbols]

[0265] 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 16 Wiring 17 Wiring 21 Wiring 22 Wiring 23 Wiring 24 Wiring 25 Wiring 26 Wiring 27 Wiring 31 Wiring 32 Wiring 33 Wiring 34 Wiring 41 Wiring 42 Wiring 43 Wiring 44 Wiring 100 sequential circuits 101 Transistor 102 Transistor 103 Transistor 104 Transistor 104S Switch 105 Transistor 106 Transistor 106S Switch 107 Transistor 107S Switch 201 Transistor 202 Transistor 203 Transistor 204 Transistor 205 Transistor 206 Transistor 207 Transistor 208 Transistor 209 Transistor 210 Transistor 211 Transistor 212 Transistor 213 Transistor 214 Transistor 300 pixels 301 Gate Driver 302 Gate Driver 303 Source Driver 310 pixels 311 Transistor 312 Transistor 313 Display element 320 Circuit 800 boards 802 Gate insulating film 812 Conductive film 813 Semiconductor Film 814 Conductive film 815 Conductive Film 816 Conductive Film 817 Semiconductor Film 818 Conductive film 819 Conductive film 820 Insulating film 821 Insulating film 822 Conductive film 823 Contact Hole 824 Insulating film 825 EL layer 826 Conductive Film 830 Transistor 831 Transistor 832 Light emitting element 833 Capacitive element 840 pixels 841 Drive circuit 1602 Gate electrode 1603 Gate insulating film 1604 Semiconductor film 1605 Conductive film 1606 Conductive film 1607 Insulating film 1612 Gate electrode 1613 Gate insulating film 1614 Semiconductor film 1615 Conductive film 1616 Conductive film 1617 Insulating film 1618 Channel protection film 1622 Gate electrode 1623 Gate insulating film 1624 Semiconductor film 1625 Conductive film 1626 Conductive film 1627 Insulating film 1642 Gate electrode 1643 Gate insulating film 1644 Semiconductor film 1645 Conductive film 1646 Conductive film 1647 Insulating film 5001 Case 5002 Case 5003 Display section 5004 Display section 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5201 Case 5202 Display section 5203 Support stand 5401 Case 5402 Display section 5403 Keyboard 5404 Pointing Device 5601 Case 5602 Case 5603 Display section 5604 Display section 5605 Connection 5606 Operation key 5801 Case 5802 Display section 5803 Audio input unit 5804 Audio output unit 5805 Operation key 5806 Light receiving section CK1 signal CK2 signal N1 Node N2 Node SC1 signal SC2 signal SCK1 signal SCK2 signal T1 Period T2 Period T3 Period T4 Period VN1 potential VN2 potential VDD potential VSS potential SP signal SSP signal OUTA signal OUTB signal SOUTA signal SOUTB signal RE signal INI signal

Claims

1. A gate driver, the gate driver includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor; one of a source and a drain of the first transistor is electrically connected to a first wiring; the other of the source and the drain of the first transistor is electrically connected to a first power supply line; the other of the source and the drain of the second transistor is electrically connected to a second power supply line; one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the third transistor is electrically connected to a gate of the sixth transistor; a signal or potential for turning on the first transistor is input to the other of the source and the drain of the third transistor; a gate of the third transistor is electrically connected to a second wiring; the other of the source and the drain of the fourth transistor is electrically connected to the second power supply line; one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the fifth transistor is electrically connected to a third wiring; the other of the source and the drain of the sixth transistor is electrically connected to the second power supply line; one of a source and a drain of the seventh transistor is electrically connected to a gate of the fourth transistor; one of a source and a drain of the seventh transistor is electrically connected to a gate of the fifth transistor; a signal or potential for turning on the fifth transistor is input to the other of the source and the drain of the seventh transistor; a gate of the seventh transistor is electrically connected to the second wiring; A first clock signal is input to the second wiring, A display device in which a second clock signal is input to the third wiring.

2. A gate driver, the gate driver includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor; one of a source and a drain of the first transistor is electrically connected to a first wiring; the other of the source and the drain of the first transistor is electrically connected to a first power supply line; the other of the source and the drain of the second transistor is electrically connected to a second power supply line; one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the third transistor is electrically connected to a gate of the sixth transistor; a signal or potential for turning on the first transistor is input to the other of the source and the drain of the third transistor; a gate of the third transistor is electrically connected to a second wiring; the other of the source and the drain of the fourth transistor is electrically connected to the second power supply line; one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the fifth transistor is electrically connected to a third wiring; the other of the source and the drain of the sixth transistor is electrically connected to the second power supply line; one of a source and a drain of the seventh transistor is electrically connected to a gate of the fourth transistor; one of a source and a drain of the seventh transistor is electrically connected to a gate of the fifth transistor; a signal or potential for turning on the fifth transistor is input to the other of the source and the drain of the seventh transistor; a gate of the seventh transistor is electrically connected to the second wiring; A first clock signal is input to the second wiring, A second clock signal is input to the third wiring, The W / L (W is a channel width, L is a channel length) of the first transistor is larger than the W / L of the third transistor, the W / L of the first transistor is greater than the W / L of the fourth transistor; the W / L of the first transistor is greater than the W / L of the fifth transistor; the W / L of the first transistor is greater than the W / L of the sixth transistor; the W / L of the first transistor is greater than the W / L of the seventh transistor; A display device in which the W / L of the second transistor is larger than the W / L of the fourth transistor.

3. A gate driver and a pixel, the gate driver includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor; one of a source and a drain of the first transistor is electrically connected to a first wiring; the other of the source and the drain of the first transistor is electrically connected to a first power supply line; the other of the source and the drain of the second transistor is electrically connected to a second power supply line; one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the third transistor is electrically connected to a gate of the sixth transistor; a signal or potential for turning on the first transistor is input to the other of the source and the drain of the third transistor; a gate of the third transistor is electrically connected to a second wiring; the other of the source and the drain of the fourth transistor is electrically connected to the second power supply line; one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the fifth transistor is electrically connected to a third wiring; the other of the source and the drain of the sixth transistor is electrically connected to the second power supply line; one of a source and a drain of the seventh transistor is electrically connected to a gate of the fourth transistor; one of a source and a drain of the seventh transistor is electrically connected to a gate of the fifth transistor; a signal or potential for turning on the fifth transistor is input to the other of the source and the drain of the seventh transistor; a gate of the seventh transistor is electrically connected to the second wiring; A first clock signal is input to the second wiring, A second clock signal is input to the third wiring, the pixel includes an eighth transistor, a ninth transistor, and a light-emitting element; one of a source and a drain of the eighth transistor is electrically connected to one of a source and a drain of the ninth transistor; the other of the source and the drain of the ninth transistor is electrically connected to the light emitting element; a gate of the eighth transistor or a gate of the ninth transistor is electrically connected to the first wiring;

4. A gate driver and a pixel, the gate driver includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor; one of a source and a drain of the first transistor is electrically connected to a first wiring; the other of the source and the drain of the first transistor is electrically connected to a first power supply line; the other of the source and the drain of the second transistor is electrically connected to a second power supply line; one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the third transistor is electrically connected to a gate of the sixth transistor; a signal or potential for turning on the first transistor is input to the other of the source and the drain of the third transistor; a gate of the third transistor is electrically connected to a second wiring; the other of the source and the drain of the fourth transistor is electrically connected to the second power supply line; one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the fifth transistor is electrically connected to a third wiring; the other of the source and the drain of the sixth transistor is electrically connected to the second power supply line; one of a source and a drain of the seventh transistor is electrically connected to a gate of the fourth transistor; one of a source and a drain of the seventh transistor is electrically connected to a gate of the fifth transistor; a signal or potential for turning on the fifth transistor is input to the other of the source and the drain of the seventh transistor; a gate of the seventh transistor is electrically connected to the second wiring; A first clock signal is input to the second wiring, A second clock signal is input to the third wiring, The W / L (W is a channel width, L is a channel length) of the first transistor is larger than the W / L of the third transistor, the W / L of the first transistor is greater than the W / L of the fourth transistor; the W / L of the first transistor is greater than the W / L of the fifth transistor; the W / L of the first transistor is greater than the W / L of the sixth transistor; the W / L of the first transistor is greater than the W / L of the seventh transistor; the W / L of the second transistor is greater than the W / L of the fourth transistor; the pixel includes an eighth transistor, a ninth transistor, and a light-emitting element; one of a source and a drain of the eighth transistor is electrically connected to one of a source and a drain of the ninth transistor; the other of the source and the drain of the ninth transistor is electrically connected to the light emitting element; a gate of the eighth transistor or a gate of the ninth transistor is electrically connected to the first wiring;

Images