Array substrate and display device

Abstract

To provide an array substrate capable of inhibiting deterioration in reliability, and a display device.SOLUTION: The array substrate according to one embodiment comprises: a transparent substrate; a linear source electrode arranged on the transparent substrate; a linear drain electrode arranged in the same layer as the source electrode; at least two semiconductors connected in parallel between the source electrode and the drain electrode; and a gate electrode overlapping the source electrode, the drain electrode and the at least two semiconductors. The gate electrode includes a notch formed in a region between the at least two semiconductors.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The embodiments of the present invention relate to an array substrate and a display device. [Background technology]

[0002] In recent years, various display devices using polymer dispersed liquid crystals that can be switched between a scattering state that scatters incident light and a transparent state that transmits the incident light have been proposed. Such display devices include an array substrate on which thin film transistors are formed. In the array substrate, a plurality of small thin film transistors may be arranged closely to each other. This can suppress heat generation when a current flows through the thin film transistors, compared to a case where one large thin film transistor is arranged in the same region.

[0003] On the other hand, when multiple thin film transistors are arranged closely to each other, gaps are formed between the thin film transistors, and the load capacitance increases in the gaps. Such an increase in load capacitance affects the display quality and lifespan (service life) of the display device, and reduces the reliability of the display device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2022-168650 A [Patent Document 2] JP 2020-126218 A Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide an array substrate and a display device capable of suppressing a decrease in reliability. [Means for solving the problem]

[0006] An array substrate according to one embodiment comprises a transparent substrate, a linear source electrode disposed on the transparent substrate, a linear drain electrode disposed in the same layer as the source electrode, at least two semiconductors connected in parallel between the source electrode and the drain electrode, and a gate electrode overlapping the source electrode, the drain electrode and the at least two semiconductors, the gate electrode having a cutout portion formed in a region between the at least two semiconductors.

[0007] A display device according to one embodiment comprises a transparent substrate, a linear source electrode arranged on the transparent substrate, a linear drain electrode arranged in the same layer as the source electrode, at least two semiconductors connected in parallel between the source electrode and the drain electrode, and a gate electrode overlapping the source electrode, the drain electrode and the at least two semiconductors, the gate electrode having a cutout portion formed in a region between the at least two semiconductors. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view illustrating an example of a display device according to an embodiment. [Diagram 2] FIG. 2 is a diagram for explaining the configuration of a pixel included in the display panel according to the embodiment. [Diagram 3] FIG. 3 is a plan view showing various elements including switching elements arranged near the areas where the scanning lines and signal lines intersect. [Figure 4] FIG. 4 is a plan view showing various elements including switching elements arranged near the areas where the scanning lines and signal lines intersect. [Diagram 5] FIG. 5 is a plan view showing in detail elements constituting the switching element according to the first embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view of the display panel taken along line AB in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view of the display panel taken along line CD in FIG. [Figure 8]FIG. 8 is a plan view showing in detail elements constituting the switching element according to the second embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view of the display panel taken along line EF in FIG. [Figure 10] FIG. 10 is a plan view showing in detail elements constituting a switching element according to the third embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view of the display panel taken along line GH in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment will be described with reference to the drawings. In addition, the disclosure is merely an example, and the invention is not limited to the contents described in the following embodiments. Modifications that a person skilled in the art can easily conceive are naturally included in the scope of the disclosure. In order to make the explanation clearer, the size, shape, etc. of each part may be changed from the actual embodiment and shown diagrammatically. In multiple drawings, corresponding elements may be given the same reference numerals, and detailed explanations may be omitted.

[0010] In the following embodiments, a liquid crystal display device will be described as an example of a display device. The main configuration disclosed in the present embodiment is not limited to electrophoretic display devices and display devices equipped with self-luminous light-emitting elements such as organic electroluminescence (EL) elements, micro LEDs, and mini LEDs, but can also be applied to various electronic devices such as capacitive sensors and optical sensors.

[0011] (First embodiment) 1 is a plan view showing an example of a display device DSP according to an embodiment. In one example, the first direction X, the second direction Y, and the third direction Z are orthogonal to each other, but may intersect at an angle other than 90 degrees. The first direction X and the second direction Y correspond to a direction parallel to a main surface of a substrate constituting the display device DSP, and the third direction Z corresponds to a thickness direction of the display device DSP. In this embodiment, viewing the XY plane defined by the first direction X and the second direction Y is called planar viewing.

[0012] The display device DSP includes a display panel PNL, a wiring board 1, an IC chip 2, and a light emitting module 100.

[0013] The display panel PNL is a so-called transparent display, and includes a first substrate SUB1 (array substrate), a second substrate SUB2 (opposing substrate), a liquid crystal layer LC including polymer-dispersed liquid crystal, and a seal SE. The first substrate SUB1 and the second substrate SUB2 are formed in a flat plate shape along the XY plane. The first substrate SUB1 and the second substrate SUB2 overlap in a planar view. The area where the first substrate SUB1 and the second substrate SUB2 overlap includes a display area DA that displays an image.

[0014] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. The pixels PX are indicated by dotted lines in the figure. Each of the pixels PX includes a pixel electrode PE, which is indicated by a solid-line square in the figure.

[0015] The first substrate SUB1 includes a first transparent substrate 10, and the second substrate SUB2 includes a second transparent substrate 20. The first transparent substrate 10 has side surfaces 101 and 102 aligned along a first direction X, and side surfaces 103 and 104 aligned along a second direction Y. The second transparent substrate 20 has side surfaces 201 and 202 aligned along the first direction X, and side surfaces 203 and 204 aligned along the second direction Y.

[0016] 1, in a plan view, the side surfaces 102 and 202, the side surfaces 103 and 203, and the side surfaces 104 and 204 overlap each other, but they do not necessarily have to overlap. The side surface 201 does not overlap the side surface 101, and is located between the side surface 101 and the display area DA. The first substrate SUB1 has an extension portion Ex between the side surfaces 101 and 201. In other words, the extension portion Ex corresponds to a portion of the first substrate SUB1 that extends in the second direction Y from a portion that overlaps with the second substrate SUB2, and does not overlap with the second substrate SUB2.

[0017] 1, the display panel PNL is formed in a rectangular shape extending in the first direction X. That is, the side surfaces 101 and 102 and the side surfaces 201 and 202 are side surfaces along the long sides of the display panel PNL, and the side surfaces 103 and 104 and the side surfaces 203 and 204 are side surfaces along the short sides of the display panel PNL. The display panel PNL may be formed in a rectangular shape extending in the second direction Y, a square shape, or another polygonal shape, or another shape such as a circle or an ellipse.

[0018] The wiring board 1 and the IC chip 2 are mounted on the extending portion Ex. The wiring board 1 is, for example, a bendable flexible printed circuit board. The IC chip 2 has, for example, a built-in display driver that outputs a signal required for image display. The IC chip 2 may be mounted on the wiring board 1. In the example shown in FIG. 1, a plurality of wiring boards 1 aligned in the first direction X are mounted on the display panel PNL, but a single wiring board 1 extending in the first direction X may be mounted on the display panel PNL. Also, a plurality of IC chips 2 aligned in the first direction X are mounted on the display panel PNL, but a single IC chip 2 extending in the first direction X may be mounted on the display panel PNL.

[0019] The light emitting module 100 overlaps the extending portion Ex in a plan view and is disposed along the side surface 201 of the second transparent substrate 20.

[0020] The seal SE bonds the first substrate SUB1 and the second substrate SUB2 together. The seal SE is formed in a rectangular frame shape and surrounds the liquid crystal layer LC between the first substrate SUB1 and the second substrate SUB2.

[0021] The liquid crystal layer LC is held between the first substrate SUB1 and the second substrate SUB2. Such a liquid crystal layer LC is disposed across the area surrounded by the seal SE (including the display area DA) in a plan view.

[0022] As shown enlarged and schematic in FIG. 1, the liquid crystal layer LC includes a polymer 31 and liquid crystal molecules 32. In one example, the polymer 31 is a liquid crystal polymer. The polymer 31 is formed in stripes extending along a first direction X and aligned in a second direction Y. The liquid crystal molecules 32 are dispersed in the gaps between the polymer 31 and oriented such that their major axes are aligned along the first direction X. Each of the polymer 31 and the liquid crystal molecules 32 has optical anisotropy or refractive index anisotropy. The responsiveness of the polymer 31 to an electric field is lower than the responsiveness of the liquid crystal molecules 32 to an electric field.

[0023] In one example, the orientation direction of the polymer 31 hardly changes regardless of the presence or absence of an electric field. On the other hand, the orientation direction of the liquid crystal molecules 32 changes in response to an electric field when a high voltage equal to or higher than a threshold value is applied to the liquid crystal layer LC. When no voltage is applied to the liquid crystal layer LC (initial orientation state), the optical axes of the polymer 31 and the liquid crystal molecules 32 are nearly parallel to each other, and most of the light incident on the liquid crystal layer LC is transmitted through the liquid crystal layer LC (transparent state). When a voltage is applied to the liquid crystal layer LC, the orientation direction of the liquid crystal molecules 32 changes, and the optical axes of the polymer 31 and the liquid crystal molecules 32 cross each other. Therefore, the light incident on the liquid crystal layer LC is scattered within the liquid crystal layer LC (scattered state).

[0024] Fig. 2 is a diagram for explaining the configuration of a pixel PX included in a display panel PNL according to an embodiment. In this embodiment, as shown in Fig. 2, a configuration is explained in which scanning signals are simultaneously supplied to four scanning lines GL1 to GL4, and video signals can be simultaneously written to four pixels PX1 to PX4 arranged in the second direction Y using four signal lines SL1 to SL4.

[0025] This configuration can make one horizontal period longer than a configuration in which a scanning signal is supplied sequentially line by line. In other words, the time required to scan all pixels can be reduced to 1 / 4 of that required in a configuration in which a scanning signal is supplied sequentially line by line. Therefore, this configuration can ensure sufficient time for writing video signals in high-speed driving panels such as transparent displays and large high-definition panels.

[0026] Note that, here, a configuration will be described in which scanning signals are supplied simultaneously to four scanning lines GL1 to GL4, and video signals are written simultaneously to four pixels PX1 to PX4 arranged along the second direction Y using four signal lines SL1 to SL4 (i.e., a configuration in which a scanning signal is supplied every four lines, and a video signal is written every four lines). However, the configuration of the display panel PNL is not limited to this, and for example, it may be a configuration in which a scanning signal is supplied every line, and a video signal is written every line.

[0027] As described above, in FIG. 2, four pixels PX1 to PX4 are arranged along the second direction Y. Each of the four pixels PX1 to PX4 is electrically connected to each of the four scanning lines GL1 to GL4. Each of the four pixels PX1 to PX4 is electrically connected to each of the four signal lines SL1 to SL4. Each of the four pixels PX1 to PX4 is electrically connected to a capacitance line CW. In the following, when the four pixels PX1 to PX4 are not particularly distinguished from each other, they are simply referred to as pixels PX. Similarly, when the four scanning lines GL1 to GL4 are not particularly distinguished from each other, they are simply referred to as scanning lines GL, and when the four signal lines SL1 to SL4 are not particularly distinguished from each other, they are simply referred to as signal lines SL.

[0028] The pixel PX includes a switching element SW. The switching element SW is formed of, for example, a thin film transistor (TFT) and is electrically connected to a scanning line GL and a signal line SL. More specifically, a gate electrode of the switching element SW is connected to the scanning line GL, a source electrode of the switching element SW is connected to the signal line SL, and a drain electrode of the switching element SW is connected to the pixel electrode PE.

[0029] The common electrode CE and the capacitance wiring CW are disposed across the display area DA and its peripheral area. A predetermined voltage is applied to the common electrode CE. For example, a voltage having the same potential as that of the common electrode CE is applied to the capacitance wiring CW.

[0030] The pixel electrode PE faces the common electrode CE in the third direction Z. In the display area DA, the liquid crystal layer LC (particularly, the liquid crystal molecules 32) is driven by an electric field generated between the pixel electrode PE and the common electrode CE. The capacitance CS is formed, for example, between the capacitance line CW and the pixel electrode PE.

[0031] The switching element SW has a function of controlling the time for writing the video signal supplied from the signal line SL to the pixel PX by switching between an on state and an off state. By turning the switching element SW on, a potential corresponding to the video signal supplied from the signal line SL can be written to the capacitance CS. By turning the switching element SW off, the potential held in the capacitance CS can be maintained.

[0032] 3 and 4 are plan views showing various elements including a switching element SW arranged near an area where the scanning lines GL and the signal lines SL intersect. Note that in FIG. 3 and FIG. 4, the shapes of the elements constituting the switching element SW (particularly the shapes of the first gate electrode GE1 and the second gate electrode GE2) are simply illustrated. The detailed shapes of these elements will be described later with reference to FIG. 5.

[0033] The switching element SW includes a semiconductor OS, a first gate electrode GE1 integrated with the scanning line GL1, a source electrode SO integrated with the signal line SL1, a drain electrode DE, and a second gate electrode GE2.

[0034] The semiconductor OS is an oxide semiconductor. The semiconductor OS may be a silicon-based semiconductor such as polycrystalline silicon or amorphous silicon. In the example shown in FIG. 3, five semiconductor OS overlap the first gate electrode GE1 and are arranged at intervals along the second direction Y. Each of the five semiconductor OS constitutes a transistor Tr. The second gate electrode GE2 overlaps the first gate electrode GE1 and the semiconductor OS. The second gate electrode GE2 further overlaps the scanning line GL1, and a relay electrode R1 is interposed between the scanning line GL1 and the second gate electrode GE2.

[0035] A contact hole CH1 is formed in the insulating film interposed between the scanning line GL1 and the relay electrode R1. The relay electrode R1 is in contact with the scanning line GL1 at the contact hole CH1. A contact hole CH2 is formed in the insulating film interposed between the relay electrode R1 and the second gate electrode GE2. The second gate electrode GE2 is in contact with the relay electrode R1 at the contact hole CH2. As a result, the second gate electrode GE2 is electrically connected to the scanning line GL1, similar to the first gate electrode GE1. In other words, the first gate electrode GE1 and the second gate electrode GE2 are at the same potential as the scanning line GL1.

[0036] In addition, a contact hole CH1' having a similar role to the contact hole CH1 is formed in the insulating film interposed between the scanning line GL1 and the relay electrode R1 and in the vicinity of the contact hole CH1. Similarly, a contact hole CH2' having a similar role to the contact hole CH2 is formed in the insulating film interposed between the relay electrode R1 and the second gate electrode GE2 and in the vicinity of the contact hole CH2. These contact holes CH1' and CH2' are contact holes formed to ensure the yield of the display panel PNL. Although detailed explanation is omitted, contact holes CH3' to CH9' formed in the vicinity of the contact holes CH3 to CH9 described later are also contact holes formed to ensure the yield of the display panel PNL.

[0037] The source electrode SO and the drain electrode DE are both formed in a linear shape. The source electrode SO and the drain electrode DE each extend along the second direction Y and are arranged at intervals along the first direction X. The source electrode SO contacts one end side of each of the semiconductor OS. The drain electrode DE contacts the other end side of each of the semiconductor OS.

[0038] One end of the drain electrode DE overlaps with the pixel electrode PE (see FIG. 2) corresponding to the pixel PX1. A contact hole CH3 is formed in the insulating film interposed between the drain electrode DE and the pixel electrode PE. The drain electrode DE contacts the pixel electrode PE at the contact hole CH3. This electrically connects the switching element SW to the pixel electrode PE.

[0039] The signal lines SL1 and SL3 extend in the second direction Y while exchanging left and right positions with each other (see FIG. 2). The signal lines SL2 and SL4 extend in the second direction Y while exchanging left and right positions with each other (see FIG. 2 to FIG. 4).

[0040] The signal line SL1 extends in the second direction Y and intersects with the scanning line GL1. The signal line SL1 overlaps with the first gate electrode GE1 (scanning line GL1), the semiconductor OS, and the second gate electrode GE2.

[0041] The signal line SL3 does not intersect with the scanning line GL1, but is divided into two, a first portion SL31 and a second portion SL32, with the scanning line GL1 as a boundary. The first portion SL31 and the second portion SL32 of the signal line SL3 each extend along the second direction Y and are arranged side by side in the second direction Y at an interval. The first portion SL31 of the signal line SL3 is arranged side by side in the first direction X at an interval from each of the signal line SL1 and the first portion SL21 of the signal line SL2. The second portion SL32 of the signal line SL3 is arranged side by side in the first direction X at an interval from each of the signal line SL1 and the second portion SL42 of the signal line SL4.

[0042] The first portion SL31 and the second portion SL32 of the signal line SL3 are electrically connected by a relay electrode R2 arranged on the signal line SL3. Contact holes CH4 and CH5 are formed in the insulating film interposed between the signal line SL3 and the relay electrode R2. The first portion SL31 of the signal line SL3 contacts the relay electrode R2 at the contact hole CH4, and the second portion SL32 of the signal line SL3 contacts the relay electrode R2 at the contact hole CH5.

[0043] The signal line SL2 does not intersect with the scanning line GL1, but is divided into two, a first portion SL21 and a second portion SL22, with the scanning line GL1 as a boundary. The first portion SL21 of the signal line SL2 extends along the second direction Y. The second portion SL22 of the signal line SL2 extends generally along the second direction Y while bending so as to switch positions with the signal line SL4. The first portion SL21 of the signal line SL2 is aligned along the first direction X with a gap between it and the first portion SL31 of the signal line SL3 and the first portion SL41 of the signal line SL4. The second portion SL22 of the signal line SL2 is aligned along the first direction X with a gap between it and the second portion SL42 of the signal line SL4.

[0044] The first portion SL21 and the second portion SL22 of the signal line SL2 are electrically connected by a relay electrode R3 arranged on the signal line SL2. Contact holes CH6 and CH7 are formed in the insulating film interposed between the signal line SL2 and the relay electrode R3. The first portion SL21 of the signal line SL2 contacts the relay electrode R3 at the contact hole CH6, and the second portion SL22 of the signal line SL2 contacts the relay electrode R3 at the contact hole CH7.

[0045] The signal line SL4 intersects with the scanning line GL1 and is divided into two parts, a first portion SL41 and a second portion SL42. The first portion SL41 and the second portion SL42 of the signal line SL4 each extend along the second direction Y. The first portion SL41 of the signal line SL4 is aligned along the first direction X with a gap between them and the first portion SL21 of the signal line SL2. The second portion SL42 of the signal line SL4 is aligned along the first direction X with a gap between them and the second portion SL32 of the signal line SL3 and the second portion SL22 of the signal line SL2.

[0046] The first portion SL41 and the second portion SL42 of the signal line SL4 are electrically connected by a relay electrode R4 arranged under the signal line SL4. Contact holes CH8 and CH9 are formed in the insulating film interposed between the signal line SL4 and the relay electrode R4. The first portion SL41 of the signal line SL4 contacts the relay electrode R4 at the contact hole CH8, and the second portion SL42 of the signal line SL4 contacts the relay electrode R4 at the contact hole CH9.

[0047] 5 is a plan view showing in detail elements (mainly the first gate electrode GE1 and the second gate electrode GE2) constituting the switching element SW according to the first embodiment. As shown in FIG. 5, the first gate electrode GE1 and the second gate electrode GE2 have cutout portions NT1 and NT2, respectively.

[0048] More specifically, the first gate electrode GE1 has a notch NT1 formed in a region between the semiconductors OS arranged along the second direction Y and overlapping with the source electrode SO integral with the signal line SL1. This makes it possible to reduce the region where the source electrode SO and the first gate electrode GE1 face each other, thereby reducing the parasitic capacitance formed between the source electrode SO and the first gate electrode GE1 (i.e., the load capacitance applied to the signal line SL1 including the source electrode SO can be reduced).

[0049] Similarly, the second gate electrode GE2 has a notch NT2 formed in a region between the semiconductors OS arranged along the second direction Y and overlapping with the source electrode SO integral with the signal line SL1. This makes it possible to reduce the region where the source electrode SO and the second gate electrode GE2 face each other, thereby reducing the parasitic capacitance formed between the source electrode SO and the second gate electrode GE2 (i.e., the load capacitance applied to the signal line SL1 including the source electrode SO can be reduced).

[0050] As shown in FIG. 5, it is preferable that both the notches NT1 and NT2 are formed so as to notch the source electrode SO side, notch the drain electrode DE side.

[0051] 5 shows the shapes of the first gate electrode GE1 and the second gate electrode GE2 included in the switching element SW including the source electrode SO integral with the signal line SL1, but the shapes of the first gate electrode GE1 and the second gate electrode GE2 included in the switching element SW including the source electrode SO integral with any one of the other signal lines SL2 to SL4 are the same. That is, the first gate electrode GE1 and the second gate electrode GE2 have cutout portions NT1 and NT2 formed in the regions between the semiconductors OS aligned along the second direction Y and overlapping with the source electrode SO integral with any one of the signal lines SL1 to SL4.

[0052] By forming the above-mentioned cutout portions NT1 and NT2, a plurality of openings AP are formed in the regions between the semiconductor OS aligned in the second direction Y, as shown in FIG.

[0053] Fig. 6 is a schematic cross-sectional view of the display panel PNL along the line AB in Fig. 5. As described above, the display panel PNL includes the first substrate SUB1, the second substrate SUB2, and the liquid crystal layer LC disposed between the first substrate SUB1 and the second substrate SUB2.

[0054] The first substrate SUB1 includes a first transparent substrate 10, insulating films 11 to 14, switching elements SW, capacitance lines CW, metal lines ML, pixel electrodes PE, and an alignment film AL1.

[0055] The first gate electrode GE1, which is integral with the scanning line GL1, is disposed on the first transparent substrate 10. The first gate electrode GE1 is formed of, for example, a metal material. The insulating film 11 covers the first transparent substrate 10 and the first gate electrode GE1. The insulating film 11 may be referred to as a gate insulating film. The semiconductor OS is disposed on the insulating film 11 and is located directly above the first gate electrode GE1. The source electrode SO, which is integral with the signal line SL1, and the drain electrode DE are disposed on the insulating film 11 and are in contact with the semiconductor OS. The source electrode SO and the drain electrode DE are formed of the same metal material. The insulating film 12 covers the insulating film 11, the source electrode SO, and the drain electrode DE. The insulating film 12 is in contact with the semiconductor OS between the source electrode SO and the drain electrode DE.

[0056] The second gate electrode GE2 is disposed on the insulating film 12 and is located directly above the first gate electrode GE1 and the semiconductor OS. The second gate electrode GE2 is formed of, for example, a metal material. The insulating film 13 covers the insulating film 12 and the second gate electrode GE2.

[0057] The capacitance line CW is disposed on the insulating film 13. The metal line ML is disposed on the capacitance line CW and is in contact with the capacitance line CW. The insulating film 14 covers the capacitance line CW and the metal line ML. The pixel electrode PE is disposed on the insulating film 14. The alignment film AL1 covers the pixel electrode PE and the insulating film 14.

[0058] The insulating films 11, 12, and 14 are transparent inorganic insulating films such as silicon oxide, silicon nitride, silicon oxynitride, etc. The insulating film 13 is a transparent organic insulating film such as an acrylic resin, and the capacitance line CW and the pixel electrode PE are transparent electrodes formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0059] The second substrate SUB2 includes a second transparent substrate 20, a light-shielding layer BM, a common electrode CE, and an alignment film AL2.

[0060] The light-shielding layer BM faces the switching element SW via the liquid crystal layer LC. The common electrode CE faces the pixel electrode PE via the liquid crystal layer LC. The alignment film AL2 covers the common electrode CE.

[0061] FIG. 7 is a schematic cross-sectional view of the display panel PNL along the line CD in FIG. 5. That is, FIG. 7 is a schematic cross-sectional view of the display panel PNL in a region between the semiconductor OSs arranged along the second direction Y. As shown in FIG. 7, in the region between the semiconductor OSs arranged along the second direction Y, the first gate electrode GE1 and the source electrode SO integrated with the signal line SL1 do not face each other. Similarly, as shown in FIG. 7, in the region between the semiconductor OSs arranged along the second direction Y, the second gate electrode GE2 and the source electrode SO integrated with the signal line SL1 do not face each other. Note that, as shown in FIG. 7, the region from one end of the source electrode SO integrated with the signal line SL1 to one end of the second gate electrode GE2 is the region corresponding to the opening AP shown in FIG. 5.

[0062] As described above, the display panel PNL according to the first embodiment includes, as the switching element SW connected to the pixel PX, a first gate electrode GE1 having a notch NT1 formed in a region overlapping with the source electrode SO, and a second gate electrode GE2 having a notch NT2 formed in a region overlapping with the source electrode SO. With this configuration, it is possible to reduce both the parasitic capacitance formed between the source electrode SO and the first gate electrode GE1 and the parasitic capacitance formed between the source electrode SO and the second gate electrode GE2. Therefore, for example, compared with a configuration in which neither the first gate electrode GE1 nor the second gate electrode GE2 has a notch, it is possible to significantly reduce the load capacitance applied to the signal line SL integrated with the source electrode SO.

[0063] Second embodiment Next, a second embodiment will be described. The configuration of the second embodiment differs from that of the first embodiment described above in that the first gate electrode GE1 constituting the switching element SW does not have the notch portion NT1. In the following, the differences from the first embodiment will be mainly described, and the description of the similarities to the first embodiment will be omitted.

[0064] 8 is a plan view showing in detail elements constituting the switching element SW according to the second embodiment. As shown in FIG. 8, the first gate electrode GE1 is formed in a rectangular shape extending along the second direction Y and does not have a notch. Therefore, the first gate electrode GE1 overlaps with the source electrode SO (signal line SL1) in a region between the semiconductor OS aligned along the second direction Y. In addition, since the first gate electrode GE1 does not have a notch, the opening AP shown in FIG. 5 is not formed in the region between the semiconductor OS aligned along the second direction Y.

[0065] Fig. 9 is a schematic cross-sectional view of the display panel PNL taken along line EF in Fig. 8. As shown in Fig. 9, in a region between the semiconductor OSs aligned in the second direction Y, the first gate electrode GE1 faces the source electrode SO integrated with the signal line SL1. On the other hand, as shown in Fig. 9, in a region between the semiconductor OSs aligned in the second direction Y, the second gate electrode GE2 does not face the source electrode SO integrated with the signal line SL1.

[0066] According to this configuration, although it is not possible to reduce the parasitic capacitance formed between the source electrode SO and the first gate electrode GE1, it is possible to reduce the parasitic capacitance formed between the source electrode SO and the second gate electrode GE2. Therefore, for example, compared with a configuration in which neither the first gate electrode GE1 nor the second gate electrode GE2 has a notch, it is possible to reduce the load capacitance applied to the signal line SL integrated with the source electrode SO.

[0067] Furthermore, in the configuration according to the second embodiment, as described above, the aperture AP shown in FIG. 5 is not formed, and therefore the following effects can be obtained.

[0068] Since the switching element SW includes elements made of metal materials, such as the source electrode SO and the drain electrode DE, when light hits the switching element SW, the light is reflected, which may result in a decrease in display quality. For this reason, it is desirable to shield the area that overlaps with the switching element SW in a plan view.

[0069] Incidentally, the display panel PNL is a so-called transparent display, and images displayed in the display area DA can be viewed from both the first substrate SUB1 side and the second substrate SUB2 side. For this reason, it is desirable that in the display panel PNL, areas overlapping with the switching elements SW in a planar view are light-shielded on both the first substrate SUB1 side and the second substrate SUB2 side.

[0070] In the configuration according to the first embodiment described above, a light shielding layer BM is disposed in an area on the second substrate SUB2 side that overlaps with the switching element SW in a plan view (see FIGS. 6 and 7). This allows the light shielding layer BM to block light from the second substrate SUB2 side (second transparent substrate 20) toward the switching element SW, and the above-mentioned deterioration in display quality can be suppressed. On the other hand, in the configuration according to the first embodiment described above, an opening AP is formed in an area on the first substrate SUB1 side that overlaps with the switching element SW in a plan view, and light from the first substrate SUB1 side (first transparent substrate 10) toward the switching element SW cannot be blocked (see FIG. 7). This means that light that is incident from the first substrate SUB1 side and passes through the opening AP may hit the switching element SW and be reflected, causing a deterioration in display quality.

[0071] In contrast to this, in the configuration according to the second embodiment, the first gate electrode GE1 does not have a notch, and therefore the first gate electrode GE1 is disposed in a region on the first substrate SUB1 side overlapping with the switching element SW in a planar view, as shown in Fig. 9. With this, the first gate electrode GE1 functions as a light blocking layer that blocks light from the first substrate SUB1 side toward the switching element SW, and therefore it is possible to block the region overlapping with the switching element SW in a planar view on both the first substrate SUB1 side and the second substrate SUB2 side, and thus it is possible to suppress a decrease in display quality compared to the configuration according to the first embodiment.

[0072] Third embodiment Further, a third embodiment will be described. The configuration of the third embodiment differs from the configuration of the first embodiment described above in that the second gate electrode GE2 constituting the switching element SW does not have the notch portion NT2. In the following, the differences from the first embodiment will be mainly described, and the description of the similarities to the first embodiment will be omitted.

[0073] 10 is a plan view showing in detail elements constituting the switching element SW according to the third embodiment. As shown in FIG. 10, the second gate electrode GE2 does not have a notch, and overlaps with the source electrode SO (signal line SL1) in a region between the semiconductors OS aligned in the second direction Y.

[0074] Fig. 11 is a schematic cross-sectional view of the display panel PNL taken along line GH in Fig. 10. As shown in Fig. 11, in a region between the semiconductor OSs aligned along the second direction Y, the second gate electrode GE2 faces the source electrode SO integrated with the signal line SL1. On the other hand, as shown in Fig. 11, in a region between the semiconductor OSs aligned along the second direction Y, the first gate electrode GE1 does not face the source electrode SO integrated with the signal line SL1.

[0075] According to this configuration, although it is not possible to reduce the parasitic capacitance formed between the source electrode SO and the second gate electrode GE2, it is possible to reduce the parasitic capacitance formed between the source electrode SO and the first gate electrode GE1. Therefore, for example, compared with a configuration in which neither the first gate electrode GE1 nor the second gate electrode GE2 has a notch, it is possible to reduce the load capacitance applied to the signal line SL integrated with the source electrode SO.

[0076] According to at least one of the embodiments described above, it is possible to provide an array substrate and a display device that can reduce the load capacitance on the signal line SL integrated with the source electrode SO and suppress deterioration in reliability.

[0077] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0078] DSP...display device, PNL...display panel, SUB1...first substrate, SUB2...second substrate, LC...liquid crystal layer, 10...first transparent substrate, 11-14...insulating film, SW...switching element, GL1-GL4...scanning line, GE1...first gate electrode, OS...semiconductor, SL1-SL4...signal line, SO...source electrode, DE...drain electrode, GE2...second gate electrode, CW...capacitive wiring, ML...metal line, PE...pixel electrode, AL1, AL2...alignment film, 20...second transparent substrate, BM...light-shielding layer, CE...common electrode, NT1, NT2...cutout portion.

Claims

1. A transparent substrate; a linear source electrode disposed on the transparent substrate; a linear drain electrode disposed in the same layer as the source electrode; at least two semiconductors connected in parallel between the source electrode and the drain electrode; a gate electrode overlapping the source electrode, the drain electrode, and the at least two semiconductors; the gate electrode has a notch formed in a region between the at least two semiconductors; Array board.

2. the gate electrode includes a first gate electrode disposed below the source electrode and the drain electrode, and a second gate electrode disposed above the source electrode and the drain electrode; the first gate electrode and the second gate electrode have a notch formed in a region between the at least two semiconductors; The array substrate according to claim 1 .

3. the gate electrode includes a first gate electrode disposed below the source electrode and the drain electrode, and a second gate electrode disposed above the source electrode and the drain electrode; Among the gate electrodes, only the second gate electrode has a notch portion formed in a region between the at least two semiconductors. The array substrate according to claim 1 .

4. the gate electrode includes a first gate electrode disposed below the source electrode and the drain electrode, and a second gate electrode disposed above the source electrode and the drain electrode; Among the gate electrodes, only the first gate electrode has a notch portion formed in a region between the at least two semiconductors. The array substrate according to claim 1 .

5. The cutout portion is formed so as to cut out the source electrode side.

5. The array substrate according to claim 1, wherein the first and second electrodes are electrically connected to each other.

6. the source electrode and the drain electrode are arranged along a first direction at an interval and extend along a second direction intersecting the first direction; The at least two semiconductors are arranged along the second direction at intervals between the source electrode and the drain electrode. The array substrate according to claim 1 .

7. A transparent substrate; a linear source electrode disposed on the transparent substrate; a linear drain electrode disposed in the same layer as the source electrode; at least two semiconductors connected in parallel between the source electrode and the drain electrode; a gate electrode overlapping the source electrode, the drain electrode, and the at least two semiconductors; the gate electrode has a notch formed in a region between the at least two semiconductors; Display device.

8. the gate electrode includes a first gate electrode disposed below the source electrode and the drain electrode, and a second gate electrode disposed above the source electrode and the drain electrode; the first gate electrode and the second gate electrode have a notch formed in a region between the at least two semiconductors; The display device according to claim 7.

9. the gate electrode includes a first gate electrode disposed below the source electrode and the drain electrode, and a second gate electrode disposed above the source electrode and the drain electrode; Among the gate electrodes, only the second gate electrode has a notch portion formed in a region between the at least two semiconductors. The display device according to claim 7.

10. the gate electrode includes a first gate electrode disposed below the source electrode and the drain electrode, and a second gate electrode disposed above the source electrode and the drain electrode; Among the gate electrodes, only the first gate electrode has a notch portion formed in a region between the at least two semiconductors. The display device according to claim 7.

11. The cutout portion is formed so as to cut out the source electrode side. The display device according to any one of claims 7 to 10.

12. the source electrode and the drain electrode are arranged along a first direction at an interval and extend along a second direction intersecting the first direction; The at least two semiconductors are arranged along the second direction at intervals between the source electrode and the drain electrode. The display device according to claim 7.

Images