Subblock-wise interleaving for polar coding systems, procedures and signaling

Abstract

To provide systems, methods and means for interleaving coded bits.SOLUTION: A wireless transmit / receive unit (WTRU) may generate a plurality of polar encoded bits using polar encoding. The WTRU may divide the plurality of polar encoded bits into subblocks of equal size in a sequential manner. The WTRU may apply subblock-wise interleaving to the subblocks using an interleaver pattern. The subblocks associated with a subset of the subblocks may be interleaved, and subblocks associated with another subset of the subblocks may not be interleaved. The subblock-wise interleaving may include applying interleaving across the subblocks without interleaving bits associated with each of the subblocks.SELECTED DRAWING: Figure 22

Description

[Technical field]

[0001] Concerning sub-block-wise interleaving for polar coding systems, procedures and signalling. [Background technology]

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application Nos. 62 / 474,875, filed March 22, 2017, 62 / 500,887, filed May 3, 2017, 62 / 519,700, filed June 14, 2017, 62 / 545,615, filed August 15, 2017, and 62 / 556,104, filed September 8, 2017, the contents of which are incorporated by reference.

[0003] Mobile communications continue to evolve. The fifth generation of mobile communications technology may be referred to as 5G. 5G mobile wireless communications systems may implement various radio access technologies (RATs), including new radio (NR). Use cases for NR may include, for example, extreme mobile broadband (eMBB), ultra high reliability and low latency communications (URLLC), and massive machine type communications (mMTC). Existing coding schemes and processing of coded bits used for transmission of control information and / or data may be supplemented by new coding schemes and processing mechanisms of coded bits. Summary of the Invention

[0004] Systems, methods, and means are disclosed for interleaving polar coded bits as part of rate matching. A wireless transmit / receive unit (WTRU) may generate a plurality of polar coded bits using polar coding. The plurality of polar coded bits may be generated using a mother code length. The WTRU may divide the plurality of polar coded bits into equal sized sub-blocks. The polar coded bits may be contiguously divided into the sub-blocks. The size of each of the sub-blocks may be a ratio of the mother code length and the number of sub-blocks. The WTRU may apply sub-block-wise interleaving to the sub-blocks using an interleaver pattern. The interleaver pattern may be represented as follows:

[0005]

number

[0006] Inside d 1 () can be given by:

[0007] Sub-blocks associated with a subset of sub-blocks may be interleaved and sub-blocks associated with another subset of sub-blocks may not be interleaved. Sub-block-by-sub-block interleaving may include applying interleaving across sub-blocks without interleaving bits associated with each of the sub-blocks. For example, groups of bits or sub-blocks may be interleaved, but bits within a sub-block may not be interleaved. The interleaved and non-interleaved subsets of sub-blocks may be contiguous and non-overlapping.

[0008] The WTRU may concatenate bits from each of the interleaved sub-blocks to generate interleaved bits. For example, the concatenated bits may be formed from the sub-blocks that are interleaved, while the bits within each of the sub-blocks are not interleaved. The bits associated with each of the interleaved sub-blocks may be concatenated consecutively. The WTRU may store the interleaved bits associated with the interleaved sub-blocks in a circular buffer. The WTRU may select multiple bits (e.g., consecutive bits) for transmission from the interleaved bits. The multiple bits may be stored consecutively in the circular buffer. The multiple bits may be selected based on a rate matching scheme. The rate matching scheme may be determined based on a mother code length, an output size of the rate matching, and a code rate. The rate matching scheme may be one of a repetition scheme, a puncturing scheme, or a shortening scheme. For example, the rate matching scheme may be a repetition scheme, for example, when the output size of the rate matching is longer than the mother code length. The rate matching scheme may be a shortening scheme or a puncturing scheme when the output size of the rate matching is shorter than the mother code length. The selection between the shortening scheme and the puncturing scheme may be based on the code rate.

[0009] The first subset of interleaved subblocks may include intermediate subblocks of some of the subblocks, and the second subset of non-interleaved subblocks may be an even number of subblocks. The second subset of subblocks comprises an equal number of subblocks on each side of the first subset of subblocks. The third subset of interleaved subblocks may be adjacent to the second subset of subblocks. The fourth subset of non-interleaved subblocks may include subblocks other than the first subset of subblocks, the second subset of subblocks, and the third subset of subblocks. The fourth subset of subblocks may be adjacent to the third subset of subblocks. [Brief description of the drawings]

[0010] [Figure 1A] FIG. 1 is a system diagram illustrating an example communication system in which one or more disclosed embodiments may be implemented. [Figure 1B] 1A is a system diagram illustrating an example wireless transmit / receive unit (WTRU) that may be used within the communications system illustrated in FIG. 1A, according to one embodiment. [Figure 1C] FIG. 1B is a system diagram illustrating an example radio access network (RAN) and an example core network (CN) that may be used within the communication system illustrated in FIG. 1A, according to one embodiment. [Figure 1D] FIG. 1B is a system diagram illustrating a further exemplary RAN and a further exemplary CN that may be used within the communications system illustrated in FIG. 1A, according to one embodiment. [Diagram 2] 1 illustrates an exemplary polar encoder. [Diagram 3] 1 illustrates an exemplary polar coding. [Figure 4] 1 shows an example of parity check (PC) polar coding. [Diagram 5] 1 illustrates an example of processing control information using polar coding. [Figure 6] 1 illustrates an example implementation of rate matching control. [Figure 7] 1 illustrates an exemplary rate matching. [Figure 8] 1 illustrates an exemplary bit selection. [Figure 9] 1 illustrates an exemplary bit selection. [Figure 10] 1 illustrates an exemplary bit selection. [Figure 11] 1 illustrates an exemplary bit selection. [Figure 12] 1 illustrates an exemplary bit selection. [Figure 13] 1 illustrates an example encoding of a cyclic redundancy check (CRC)-assisted (CA) polar code that uses a long CRC. [Figure 14]13 shows an exemplary distribution of decodings for a CA polar code with a long CRC. [Figure 15] 1 shows an exemplary encoding of a CA polar code using two separate CRCs. [Figure 16] 1 illustrates an exemplary decoding of a CA polar code with two separate CRCs. [Figure 17] 1 illustrates an exemplary encoding of a PC polar code. [Figure 18] 1 illustrates an exemplary decoding of a PC polar code. [Figure 19] 13 illustrates an example decoding of a PC polar code using CA list selection. [Figure 20] 1 shows an exemplary block error rate (BLER) comparison between sub-block based puncturing and previous shortening schemes. [Figure 21] 1 illustrates an exemplary subblock-wise interleaver for polar code rate matching with 8 subblocks. [Figure 22] 1 illustrates an exemplary subblock-wise interleaver for polar code rate matching with 16 subblocks. [Figure 23A] 1 illustrates an exemplary subblock-wise interleaver for polar code rate matching with 32 subblocks. [Figure 23B] 1 illustrates an exemplary subblock-wise interleaver for polar code rate matching with 32 subblocks. [Figure 23C] 1 illustrates an exemplary subblock-wise interleaver for polar code rate matching with 32 subblocks. [Figure 24] 1 illustrates an exemplary 16 quadrature amplitude modulation (QAM) modulation. [Diagram 25] 1 illustrates an exemplary 16QAM modulation. [Figure 26] 1 shows an exemplary 16QAM modulation using four partitions. [Figure 27] 1 shows an exemplary quadrature phase shift keying (QPSK) modulation using two segments. [Figure 28] 2 shows an exemplary QPSK modulation with two partitions. [Figure 29] 2 shows an exemplary QPSK modulation using five segments. [Diagram 30] 1 illustrates an exemplary channel interleaver. [Diagram 31] An example of interleaving is shown below. [Diagram 32] 1 shows an example block interleaver that uses a depth of 5. [Diagram 33] 1 shows an exemplary performance comparison of different interleavers in a Tapped Delay Line (TDL)-A channel model with a delay spread of 100 ns, a code rate of 1 / 2, and QPSK modulation. [Diagram 34] 1 shows an exemplary performance comparison of different interleavers on a TDL-A channel model with a delay spread of 100 ns, a code rate of 1 / 2, and 16QAM modulation. [Diagram 35] 1 shows an exemplary performance comparison of different interleavers on a TDL-A channel model with a delay spread of 100 ns, a code rate of 1 / 2, and 64QAM modulation. [Diagram 36] 1 shows an example of the performance improvement that can be seen using a matrix interleaver. [Figure 37] 1 illustrates an exemplary performance comparison of various exemplary methods and approaches disclosed herein. [Figure 38] 1 illustrates an exemplary performance comparison of various exemplary methods and approaches disclosed herein. [Figure 39] 1 illustrates an exemplary performance comparison of various exemplary methods and approaches disclosed herein. [Diagram 40] 1 illustrates an exemplary performance comparison of various exemplary methods and approaches disclosed herein. [Diagram 41] 1 illustrates an exemplary performance comparison of various exemplary methods and approaches disclosed herein. [Diagram 42]1 illustrates an exemplary performance comparison of various exemplary methods and approaches disclosed herein. [Diagram 43] 1 illustrates an exemplary performance comparison of various exemplary methods and approaches disclosed herein. [Diagram 44] 1 illustrates an exemplary performance comparison of various exemplary methods and approaches disclosed herein. [Diagram 45] 1 illustrates an exemplary performance comparison of various exemplary methods and approaches disclosed herein. [Figure 46] 1 illustrates an exemplary performance comparison of various exemplary methods and approaches disclosed herein. [Figure 47] 1 illustrates an exemplary performance comparison of various exemplary methods and approaches disclosed herein. [Figure 48] 1 illustrates an exemplary performance comparison of various exemplary methods and approaches disclosed herein. [Figure 49] 1 illustrates an exemplary triangular interleaver. [Figure 50] 1 illustrates an exemplary triangular interleaver. [Figure 51] 1 illustrates an exemplary polar coding system. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] A detailed description of an illustrative example will now be described with reference to various figures. Although this description provides detailed examples of possible implementations, it should be noted that the details are illustrative and do not limit the scope in any way.

[0012] 1A illustrates an example communication system 100 in which one or more disclosed embodiments may be implemented. The communication system 100 may be a multiple access system that provides multiple wireless users with content, such as voice, data, video, messaging, broadcasts, etc. The communication system 100 may enable multiple wireless users to access such content through sharing of system resources, including wireless bandwidth. For example, the communication system 100 may employ one or more channel access methods, such as code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal FDMA (OFDMA), single carrier FDMA (SC-FDMA), zero-tail unique-word DFT-Spread OFDM (ZT UW DTS-s OFDM), unique word OFDM (UW-OFDM), resource block-filtered OFDM, filter bank multicarrier (FBMC), etc.

[0013] 1A, the communications system 100 may include wireless transmit / receive units (WTRUs) 102a, 102b, 102c, 102d, a RAN 104 / 113, a CN 106 / 115, a public switched telephone network (PSTN) 108, the Internet 110, and other networks 112, although it will be appreciated that the disclosed embodiments contemplate any number of WTRUs, base stations, networks, and / or network elements. Each of the WTRUs 102a, 102b, 102c, 102d may be any type of device configured to operate and / or communicate in a wireless environment. By way of example, the WTRUs 102a, 102b, 102c, 102d, any of which may be referred to as a “station” and / or “STA,” may be configured to transmit and / or receive wireless signals and may include user equipment (UE), mobile stations, fixed or mobile subscriber units, subscription-based units, pagers, cellular phones, personal digital assistants (PDAs), smartphones, laptops, netbooks, personal computers, wireless sensors, hotspots or Mi-Fi devices, Internet of Things (IoT) devices, watches or other wearables, head mounted displays (HMDs), vehicles, drones, medical devices and applications (e.g., remote surgery), industrial devices and applications (e.g., robots and / or other wireless devices operating in industrial and / or automated processing chain contexts), consumer electronics devices, devices operating on commercial and / or industrial wireless networks, etc. Any of the WTRUs 102a, 102b, 102c and 102d may be referred to interchangeably as a UE.

[0014] The communication system 100 may also include a base station 114a and / or a base station 114b. Each of the base stations 114a, 114b may be any type of device configured to wirelessly interface with at least one of the WTRUs 102a, 102b, 102c, 102d to facilitate access to one or more communication networks, such as the CN 106 / 115, the Internet 110, and / or other networks 112. By way of example, the base stations 114a, 114b may be a base transceiver station (BTS), a Node B, an eNode B, a home Node B, a home eNode B, a gNB, an NR Node B, a site controller, an access point (AP), a wireless router, etc. Although the base stations 114a, 114b are shown as single elements, it will be appreciated that the base stations 114a, 114b may include any number of interconnected base stations and / or network elements.

[0015] The base station 114a may be part of the RAN 104 / 113, which may also include other base stations and / or network elements (not shown), such as a base station controller (BSC), a radio network controller (RNC), relay nodes, etc. The base station 114a and / or base station 114b may be configured to transmit and / or receive wireless signals on one or more carrier frequencies, which may be referred to as cells (not shown). These frequencies may be in the licensed spectrum, the unlicensed spectrum, or a combination of the licensed and unlicensed spectrum. A cell may provide coverage for wireless services in a particular geographic area, which may be relatively fixed or may change over time. A cell may be further divided into cell sectors. For example, the cell associated with the base station 114a may be divided into three sectors. Thus, in one embodiment, the base station 114a may include three transceivers, i.e., one for each sector of the cell. In one embodiment, the base station 114a may employ multiple-input multiple-output (MIMO) technology and utilize multiple transceivers for each sector of the cell. For example, beamforming may be used to transmit and / or receive signals in a desired spatial direction.

[0016] The base stations 114a, 114b may communicate with one or more of the WTRUs 102a, 102b, 102c, 102d over an air interface 116, which may be any suitable wireless communications link (e.g., radio frequency (RF), microwave, centimeter wave, micrometer wave, infrared (IR), ultraviolet (UV), visible light, etc.). The air interface 116 may be established using any suitable radio access technology (RAT).

[0017] More specifically, as noted above, the communication system 100 may be a multiple access system and may employ one or more channel access schemes, such as CDMA, TDMA, FDMA, OFDMA, SC-FDMA, etc. For example, the base stations 114a and WTRUs 102a, 102b, 102c in the RAN 104 / 113 may implement a radio technology such as Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access (UTRA), which may establish the air interface 115 / 116 / 117 using Wideband CDMA (WCDMA). WCDMA may include communication protocols such as High Speed ​​Packet Access (HSPA) and / or Evolved HSPA (HSPA+). HSPA may include High Speed ​​Downlink (DL) Packet Access (HSDPA) and / or High Speed ​​UL Packet Access (HSUPA).

[0018] In one embodiment, the base station 114a and the WTRUs 102a, 102b, 102c may implement a radio technology such as Evolved UMTS Terrestrial Radio Access (E-UTRA), which may establish the air interface 116 using Long Term Evolution (LTE) and / or LTE Advanced (LTE-A) and / or LTE Advanced Pro (LTE-A Pro).

[0019] In one embodiment, the base station 114a and the WTRUs 102a, 102b, 102c may implement a radio technology such as New Radio (NR) radio access, which may establish the air interface 116 using NR).

[0020] In one embodiment, the base station 114a and the WTRUs 102a, 102b, 102c may implement multiple radio access technologies. For example, the base station 114a and the WTRUs 102a, 102b, 102c may implement LTE and NR radio access together, for example, using a dual connectivity (DC) principle. Thus, the air interface utilized by the WTRUs 102a, 102b, 102c may be characterized by multiple types of radio access technologies and / or transmissions sent to and from multiple types of base stations (e.g., eNBs and gNBs).

[0021] In other embodiments, the base station 114a and the WTRUs 102a, 102b, 102c may implement a wireless technology such as IEEE 802.11 (i.e., Wireless Fidelity (WiFi), IEEE 802.16 (i.e., Worldwide Interoperability for Microwave Access (WiMAX)), CDMA2000, CDMA2000 1X, CDMA2000EV-DO, Interim Standard 2000 (IS-2000), Interim Standard 95 (IS-95), Interim Standard 856 (IS-856), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), GSM EDGE (GERAN), or the like.

[0022] The base station 114b in FIG. 1A may be, for example, a wireless router, a Home NodeB, a Home eNodeB, or an access point, and may utilize any suitable RAT to facilitate wireless connectivity in a local area, such as a workplace, a home, a vehicle, a premises, an industrial facility, an air corridor (e.g., for use by drones), a road, etc. In one embodiment, the base station 114b and the WTRUs 102c, 102d may implement a radio technology such as IEEE 802.11 to establish a wireless local area network (WLAN). In one embodiment, the base station 114b and the WTRUs 102c, 102d may implement a radio technology such as IEEE 802.15 to establish a wireless personal area network (WPAN). In yet another embodiment, the base station 114b and the WTRUs 102c, 102d may utilize a cellular-based RAT (e.g., WCDMA, CDMA2000, GSM, LTE, LTE-A, LTE-A Pro, NR, etc.) to establish a picocell or femtocell. 1A, the base station 114b may have a direct connection to the Internet 110. Thus, the base station 114b may not need to access the Internet 110 via the CN 106 / 115.

[0023] The RAN 104 / 113 may be in communication with the CN 106 / 115, which may be any type of network configured to provide voice, data, application, and / or Voice over Internet Protocol (VoIP) services to one or more of the WTRUs 102a, 102b, 102c, 102d. The data may have varying Quality of Service (QoS) requirements, such as different throughput requirements, latency requirements, error resilience requirements, reliability requirements, data throughput requirements, mobility requirements, etc. The CN 106 / 115 may provide call control, charging services, mobile location-based services, prepaid calling, Internet connectivity, video distribution, etc., and / or perform high-level security functions, such as user authentication. Although not shown in FIG. 1A, it will be appreciated that the RAN 104 / 113 and / or the CN 106 / 115 may be in direct or indirect communication with other RANs employing the same RAT as the RAN 104 / 113 or a different RAT. For example, in addition to being connected to the RAN 104 / 113, which may utilize NR radio technology, the CN 106 / 115 may also be in communication with another RAN (not shown) that employs GSM, UMTS, CDMA2000, WiMAX, E-UTRA, or WiFi radio technology.

[0024] The CN 106 / 115 may also act as a gateway for the WTRUs 102a, 102b, 102c, 102d to access the PSTN 108, the Internet 110, and / or other networks 112. The PSTN 108 may include a circuit-switched telephone network that provides plain old telephone service (POTS). The Internet 110 may include a global system of interconnected computer networks and devices that use common communication protocols, such as Transmission Control Protocol (TCP), User Datagram Protocol (UDP), and / or Internet Protocol (IP) in the TCP / IP Internet protocol suite. The networks 112 may include wired and / or wireless communication networks owned and / or operated by other service providers. For example, the networks 112 may include another CN connected to one or more RANs that may employ the same RAT as the RAN 104 / 113 or a different RAT.

[0025] Some or all of the WTRUs 102a, 102b, 102c, 102d in the communications system 100 may include multi-mode capabilities (e.g., the WTRUs 102a, 102b, 102c, 102d may include multiple transceivers for communicating with different wireless networks over different wireless links). For example, the WTRU 102c shown in FIG. 1A may be configured to communicate with a base station 114a, which may employ a cellular-based radio technology, and with a base station 114b, which may employ an IEEE 802 radio technology.

[0026] 1B is a system diagram illustrating an example WTRU 102. As shown in FIG. 1B, the WTRU 102 may include, among other things, a processor 118, a transceiver 120, a transmit / receive element 122, a speaker / microphone 124, a keypad 126, a display / touchpad 128, non-removable memory 130, removable memory 132, a power source 134, a Global Positioning System (GPS) chipset 136, and / or other peripherals 138. It will be appreciated that the WTRU 102 may include any sub-combination of the above elements while remaining consistent with an embodiment.

[0027] The processor 118 may be a general purpose processor, a special purpose processor, a conventional processor, a digital signal processor (DSP), multiple microprocessors, one or more microprocessors associated with a DSP core, a controller, a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) circuit, any other type of integrated circuit (IC), a state machine, etc. The processor 118 may perform signal coding, data processing, power control, input / output processing, and / or any other functionality that enables the WTRU 102 to operate in a wireless environment. The processor 118 may be coupled to the transceiver 120, which may be coupled to the transmit / receive element 122. Although FIG. 1B illustrates the processor 118 and the transceiver 120 as separate components, it will be appreciated that the processor 118 and the transceiver 120 may be integrated together in an electronic package or chip.

[0028] The transmit / receive element 122 may be configured to transmit signals to and receive signals from a base station (e.g., base station 114a) over the air interface 116. For example, in one embodiment, the transmit / receive element 122 may be an antenna configured to transmit and / or receive RF signals. In one embodiment, the transmit / receive element 122 may be an emitter / detector configured to transmit and / or receive IR, UV, or visible light signals, for example. In yet another embodiment, the transmit / receive element 122 may be configured to transmit and / or receive both RF and light signals. It will be appreciated that the transmit / receive element 122 may be configured to transmit and / or receive any combination of wireless signals.

[0029] 1B as a single element, the WTRU 102 may include any number of transmit / receive elements 122. More particularly, the WTRU 102 may employ MIMO technology. Thus, in one embodiment, the WTRU 102 may include two or more transmit / receive elements 122 (e.g., multiple antennas) for transmitting and receiving wireless signals over the air interface 116.

[0030] The transceiver 120 may be configured to modulate signals to be transmitted by the transmit / receive element 122 and demodulate signals received by the transmit / receive element 122. As mentioned above, the WTRU 102 may have multi-mode capabilities. Thus, the transceiver 120 may include multiple transceivers to enable the WTRU 102 to communicate via multiple RATs, such as, for example, NR and IEEE 802.11.

[0031] The processor 118 of the WTRU 102 may be coupled to and receive user input data from the speaker / microphone 124, the keypad 126, and / or the display / touchpad 128 (e.g., a liquid crystal display (LCD) display unit or an organic light emitting diode (OLED) display unit). The processor 118 may also output user data to the speaker / microphone 124, the keypad 126, and / or the display / touchpad 128. Further, the processor 118 may access information from and store data in any type of suitable memory, such as non-removable memory 130 and / or removable memory 132. The non-removable memory 130 may include a random access memory (RAM), a read only memory (ROM), a hard disk, or any other type of memory storage device. The removable memory 132 may include a subscriber identity module (SIM) card, a memory stick, a secure digital (SD) memory card, or the like. In other embodiments, the processor 118 may access information from, and store data in, memory that is not physically located on the WTRU 102, such as on a server or a home computer (not shown).

[0032] The processor 118 may receive power from the power source 134 and may be configured to distribute and / or control power to other components in the WTRU 102. The power source 134 may be any suitable device for powering the WTRU 102. For example, the power source 134 may include one or more dry cell batteries (e.g., nickel-cadmium (NiCd), nickel-zinc (NiZn), nickel-metal hydride (NiMH), lithium-ion (Li-ion), etc.), solar cells, fuel cells, etc.

[0033] The processor 118 may also be coupled to a GPS chipset 136, which may be configured to provide location information (e.g., longitude and latitude) regarding the current location of the WTRU 102. In addition to, or instead of, information from the GPS chipset 136, the WTRU 102 may receive location information over the air interface 116 from base stations (e.g., base stations 114a, 114b) and / or determine its location based on the timing of signals received from two or more nearby base stations. It will be appreciated that the WTRU 102 may acquire location information by way of any suitable location determination method while remaining consistent with an embodiment.

[0034] The processor 118 may further be coupled to other peripherals 138, which may include one or more software and / or hardware modules that provide additional features, functionality, and / or wired or wireless connectivity. For example, the peripherals 138 may include an accelerometer, an e-compass, a satellite transceiver, a digital camera (for photos and / or videos), a universal serial bus (USB) port, a vibration device, a television transceiver, a hands-free headset, a Bluetooth module, a frequency modulation (FM) radio unit, a digital music player, a media player, a video game player module, an Internet browser, a virtual reality and / or augmented reality (VR / AR) device, an activity tracker, and / or the like. The peripherals 138 may include one or more sensors, which may be one or more of a gyroscope, an accelerometer, a Hall effect sensor, a magnetometer, an orientation sensor, a proximity sensor, a temperature sensor, a time sensor, a geolocation sensor, an altimeter, a light sensor, a touch sensor, a magnetometer, a barometer, a gesture sensor, a biometric sensor, and / or a humidity sensor.

[0035] The WTRU 102 may include a full-duplex radio where transmission and reception of some or all signals (e.g., associated with a subframe for both the UL (e.g., for transmission) and the downlink (e.g., for reception)) may be parallel and / or simultaneous. The full-duplex radio may include an interference management unit to eliminate and / or substantially reduce self-interference via either hardware (e.g., a choke) or signal processing via a processor (e.g., via a separate processor (not shown) or processor 118). In one embodiment, the WRTU 102 may include a half-duplex radio for transmission and reception of some or all signals (associated with a particular subframe for either the UL (e.g., for transmission) or the downlink (e.g., for reception)).

[0036] 1C is a system diagram illustrating the RAN 104 and the CN 106, according to one embodiment. As mentioned above, the RAN 104 may employ E-UTRA radio technology to communicate with the WTRUs 102a, 102b, 102c over the air interface 116. The RAN 104 may also be in communication with the CN 106.

[0037] The RAN 104 may include eNodeBs 160a, 160b, 160c, although it will be appreciated that the RAN 104 may include any number of eNodeBs while remaining consistent with an embodiment. The eNodeBs 160a, 160b, 160c may each include one or more transceivers for communicating with the WTRUs 102a, 102b, 102c over the air interface 116. In one embodiment, the eNodeBs 160a, 160b, 160c may implement MIMO technology. Thus, the eNodeB 160a, for example, may use multiple antennas to transmit wireless signals to and / or receive wireless signals from the WTRU 102a.

[0038] Each of the eNodeBs 160a, 160b, 160c may be associated with a particular cell (not shown) and may be configured to handle radio resource management decisions, handover decisions, scheduling of users in the UL and / or DL, etc. As shown in FIG 1C, the eNodeBs 160a, 160b, 160c may communicate with one another via an X2 interface.

[0039] 1C may include a Mobility Management Entity (MME) 162, a Serving Gateway (SGW) 164, and a Packet Data Network (PDN) Gateway (or PGW) 166. Although each of the above elements is shown as part of the CN 106, it will be appreciated that any of these elements may be owned and / or operated by an entity other than the CN operator.

[0040] The MME 162 may be connected to each of the eNodeBs 162a, 162b, 162c in the RAN 104 via an S1 interface and may act as a control node. For example, the MME 162 may be responsible for authenticating users of the WTRUs 102a, 102b, 102c, activating / deactivating bearers, selecting a particular serving gateway during initial attach of the WTRUs 102a, 102b, 102c, etc. The MME 162 may provide a control plane function for switching between the RAN 104 and other RANs (not shown) that employ other radio technologies such as GSM and / or WCDMA.

[0041] The SGW 164 may be connected to each of the eNodeBs 160a, 160b, 160c in the RAN 104 via an S1 interface. The SGW 164 may generally route and forward user data packets to and from the WTRUs 102a, 102b, 102c. The SGW 164 may perform other functions such as anchoring the user plane during handover between eNodeBs, triggering paging when DL data is available for the WTRUs 102a, 102b, 102c, managing and storing the context of the WTRUs 102a, 102b, 102c, etc.

[0042] The SGW 164 may be connected to a PGW 166 that may provide the WTRUs 102a, 102b, 102c with access to packet-switched networks, such as the Internet 110, to facilitate communications between the WTRUs 102a, 102b, 102c and IP-enabled devices.

[0043] The CN 106 may facilitate communications with other networks. For example, the CN 106 may provide the WTRUs 102a, 102b, 102c with access to circuit-switched networks, such as the PSTN 108, to facilitate communications between the WTRUs 102a, 102b, 102c and traditional fixed communication devices. For example, the CN 106 may include or communicate with an IP gateway (e.g., an IP Multimedia Subsystem (IMS) server) that acts as an interface between the CN 106 and the PSTN 108. Additionally, the CN 106 may provide the WTRUs 102a, 102b, 102c with access to other networks 112, which may include other wired and / or wireless networks owned and / or operated by other service providers.

[0044] Although the WTRU is depicted in FIGS. 1A-1D as a wireless terminal, in some representative embodiments in which such a terminal may be used (e.g., temporarily or permanently), it is contemplated that wired communications will interface with the communications network.

[0045] In an exemplary embodiment, the other network 112 may be a WLAN.

[0046] A WLAN in infrastructure basic service set (BSS) mode may have an access point (AP) for the BSS and one or more stations (STAs) associated with the AP. The AP may have access or interface to a distribution system (DS) or another type of wired / wireless network that carries traffic into and out of the BSS. Traffic to a STA originating from outside the BSS may arrive through the AP and be sent to the STA. Traffic originating from a STA to a destination outside the BSS may be sent to the AP for delivery to the respective destination. Traffic between STAs within a BSS may be sent through the AP, e.g., where a source STA may send traffic to the AP and the AP may send traffic to the destination STA. Traffic between STAs within a BSS may be considered and / or referred to as peer-to-peer traffic. Peer-to-peer traffic may be sent between (e.g., directly between) a source STA and a destination STA using a direct link setup (DLS). In some representative embodiments, the DLS may use 802.11e DLS or 802.11z tunneled DLS (TDLS). A WLAN using an Independent BSS (IBSS) mode may not have an AP, and STAs (e.g., all of the STAs) in or using an IBSS may communicate directly with each other. The IBSS communication mode is sometimes referred to herein as an "ad-hoc" communication mode.

[0047] When using an 802.11ac infrastructure mode of operation or a similar mode of operation, an AP may transmit a beacon on a fixed channel, such as a primary channel. The primary channel may be a fixed width (e.g., a 20 MHz wide bandwidth) or a width dynamically set via signaling. The primary channel may be an operating channel of the BSS and may be used by STAs to establish a connection with the AP. In some representative embodiments, carrier sense multiple access / collision avoidance (CSMA / CA) may be implemented, for example, in 802.11 systems. In CSMA / CA, STAs (e.g., every STA), including the AP, may sense the primary channel. If the primary channel is sensed / detected by a particular STA and / or determined to be busy, the particular STA may back off. One STA (e.g., only one station) may transmit at any given time in a given BSS.

[0048] A high throughput (HT) STA may use a 40 MHz wide channel for communication, for example, via a combination of a primary 20 MHz channel with adjacent or non-adjacent 20 MHz channels to form a 40 MHz wide channel.

[0049] A Very High Throughput (VHT) STA may support 20 MHz, 40 MHz, 80 MHz, and / or 160 MHz wide channels. A 40 MHz and / or 80 MHz channel may be formed by combining contiguous 20 MHz channels. A 160 MHz channel may be formed by combining eight contiguous 20 MHz channels or by combining two non-contiguous 80 MHz channels, sometimes referred to as an 80+80 configuration. In the 80+80 configuration, the data may be passed through a segment parser that may split the data into two streams after channel encoding. Inverse Fast Fourier Transform (IFFT) processing and time domain processing may be performed separately for each stream. The streams may be mapped onto two 80 MHz channels and the data may be transmitted by the transmitting STA. At the receiver of the receiving STA, the operations described above for the 80+80 configuration may be reversed and the combined data may be sent to the Medium Access Control (MAC).

[0050] Sub-1 GHz operation modes are supported by 802.11af and 802.11ah. Channel operating bandwidths and carriers are reduced in 802.11af and 802.11ah compared to those used in 802.11n and 802.11ac. 802.11af supports 5 MHz, 10 MHz, and 20 MHz bandwidths in TV White Space (TVWS) spectrum, and 802.11ah supports 1 MHz, 2 MHz, 4 MHz, 8 MHz, and 16 MHz bandwidths using non-TVWS spectrum. According to a representative embodiment, 802.11ah may support meter-type control / machine-type communication such as MTC devices in macro coverage areas. MTC devices may have some capabilities, for example, limited capabilities including support of some and / or limited bandwidths (e.g., only support). MTC devices may include batteries with above-threshold battery life (e.g., to maintain very long battery life).

[0051] WLAN systems that may support multiple channels and channel bandwidths, such as 802.11n, 802.11ac, 802.11af, and 802.11ah, include a channel that may be designated as a primary channel. The primary channel may have a bandwidth equal to the largest common operating bandwidth supported by all STAs in the BSS. The bandwidth of the primary channel may be set and / or limited by the STA that supports the smallest bandwidth operating mode among all STAs operating in the BSS. In an 802.11ah example, the primary channel may be 1 MHz wide for STAs (e.g., MTC-type devices) that support (e.g., only support) the 1 MHz mode, even if the AP and other STAs in the BSS support 2 MHz, 4 MHz, 8 MHz, 16 MHz, and / or other channel bandwidth operating modes. The setting of the carrier sense and / or network allocation vector (NAV) may depend on the status of the primary channel. For example, if the primary channel is busy for a STA (that only supports a 1 MHz mode of operation), it may be considered busy to transmit the entire available frequency band to the AP even if most of the frequency band remains idle and may be available for use.

[0052] In the United States, the available frequency bands that can be used by 802.11ah are from 902MHz to 928MHz. In South Korea, the available frequency bands are from 917.5MHz to 923.5MHz. In Japan, the available frequency bands are from 916.5MHz to 927.5MHz. The total available bandwidth for 802.11ah is 6MHz to 26MHz depending on the country code.

[0053] 1D is a system diagram illustrating the RAN 113 and the CN 115, according to one embodiment. As mentioned above, the RAN 113 may employ NR radio technology to communicate with the WTRUs 102a, 102b, 102c over the air interface 116. The RAN 113 may also be in communication with the CN 115.

[0054] The RAN 113 may include gNBs 180a, 180b, 180c, although it will be appreciated that the RAN 113 may include any number of gNBs while remaining consistent with an embodiment. The gNBs 180a, 180b, 180c may each include one or more transceivers for communicating with the WTRUs 102a, 102b, 102c over the air interface 116. In an embodiment, the gNBs 180a, 180b, 180c may implement MIMO technology. For example, the gNBs 180a, 108b may utilize beamforming to transmit signals to and / or receive signals from the gNBs 180a, 180b, 180c. Thus, the gNB 180a may use multiple antennas to transmit wireless signals to and / or receive wireless signals from, for example, the WTRU 102a. In one embodiment, the gNBs 180a, 180b, 180c may implement carrier aggregation technology. For example, the gNB 180a may transmit multiple component carriers to the WTRU 102a (not shown). A subset of these component carriers may be on an unlicensed spectrum, while the remaining component carriers may be on a licensed spectrum. In one embodiment, the gNBs 180a, 180b, 180c may implement coordinated multipoint (CoMP) technology. For example, the WTRU 102a may receive coordinated transmissions from the gNBs 180a and 180b (and / or gNB 180c).

[0055] The WTRUs 102a, 102b, 102c may communicate with the gNBs 180a, 180b, 180c using transmissions associated with scalable numerology. For example, the OFDM symbol spacing and / or OFDM subcarrier spacing may vary for different transmissions, different cells, and / or different portions of the wireless transmission spectrum. The WTRUs 102a, 102b, 102c may communicate with the gNBs 180a, 180b, 180c using subframes or transmission time intervals (TTIs) of varying or scalable lengths (e.g., including various numbers of OFDM symbols and / or lasting for varying lengths of absolute time).

[0056] The gNBs 180a, 180b, 180c may be configured to communicate with the WTRUs 102a, 102b, 102c in a standalone configuration and / or a non-standalone configuration. In a standalone configuration, the WTRUs 102a, 102b, 102c may communicate with the gNBs 180a, 180b, 180c without accessing other RANs (e.g., eNodeBs 160a, 160b, 160c, etc.). In a standalone configuration, the WTRUs 102a, 102b, 102c may utilize one or more of the gNBs 180a, 180b, 180c as mobility anchor points. In a standalone configuration, the WTRUs 102a, 102b, 102c may communicate with the gNBs 180a, 180b, 180c using signals in unlicensed bands. In a non-standalone configuration, the WTRUs 102a, 102b, 102c may communicate with / connect to a gNB 180a, 180b, 180c while also communicating with / connecting to another RAN, such as an eNodeB 160a, 160b, 160c. For example, the WTRUs 102a, 102b, 102c may implement DC principles to communicate with one or more gNBs 180a, 180b, 180c and one or more eNodeBs 160a, 160b, 160c substantially simultaneously. In a non-standalone configuration, the eNodeBs 160a, 160b, 160c may act as a mobility anchor for the WTRUs 102a, 102b, 102c, and the gNBs 180a, 180b, 180c may provide additional coverage and / or throughput for serving the WTRUs 102a, 102b, 102c.

[0057] Each of the gNBs 180a, 180b, 180c may be associated with a particular cell (not shown) and may be configured to handle radio resource management decisions, handover decisions, scheduling of users in the UL and / or DL, support for network slicing, dual connectivity, interconnection between NR and E-UTRA, routing of user plane data towards user plane functions (UPFs) 184a, 184b, routing of control plane information towards access and mobility management functions (AMFs) 182a, 182b, etc. As shown in FIG. 1D, the gNBs 180a, 180b, 180c may communicate with one another via an Xn interface.

[0058] 1D may include at least one AMF 182a, 182b, at least one UPF 184a, 184b, at least one Session Management Function (SMF) 183a, 183b, and possibly a Data Network (DN) 185a, 185b. Although each of the above elements is shown as part of the CN 115, it will be appreciated that any of these elements may be owned and / or operated by an entity other than the CN operator.

[0059] The AMF 182a, 182b may be connected to one or more of the gNBs 180a, 180b, 180c in the RAN 113 via an N2 interface and may act as a control node. For example, the AMF 182a, 182b may be responsible for authenticating users of the WTRUs 102a, 102b, 102c, supporting network slicing (e.g., handling different PDU sessions with different requirements), selecting a particular SMF 183a, 183b, managing registration areas, terminating NAS signaling, mobility management, etc. Network slicing may be used by the AMF 182a, 182b to customize the CN support of the WTRUs 102a, 102b, 102c based on the type of service that is utilized by the WTRUs 102a, 102b, 102c. For example, different network slices may be established for different use cases, such as services relying on highly reliable low latency (URLLC) access, services relying on enhanced massive mobile broadband (eMBB) access, services with machine-type communications (MTC) access, etc. The AMF 162 may provide a control plane function for switching between the RAN 113 and other RANs (not shown) that employ other radio technologies, such as LTE, LTE-A, LTE-A Pro, and / or non-3GPP access technologies, such as WiFi.

[0060] The SMFs 183a, 183b may be connected to the AMFs 182a, 182b in the CN 115 via an N11 interface. The SMFs 183a, 183b may also be connected to the UPFs 184a, 184b in the CN 115 via an N4 interface. The SMFs 183a, 183b may select and control the UPFs 184a, 184b and configure the routing of traffic through the UPFs 184a, 184b. The SMFs 183a, 183b may perform other functions such as managing and allocating IP addresses for UEs, managing PDU sessions, controlling policy enforcement and QoS, providing notification of downlink data, etc. The type of PDU session may be IP-based, non-IP-based, Ethernet-based, etc.

[0061] The UPFs 184a, 184b may be connected to one or more of the gNBs 180a, 180b, 180c in the RAN 113 via an N3 interface, which may provide the WTRUs 102a, 102b, 102c with access to packet-switched networks such as the Internet 110 to facilitate communications between the WTRUs 102a, 102b, 102c and IP-enabled devices. The UPFs 184, 184b may perform other functions such as routing and forwarding packets, enforcing user plane policies, supporting multi-homed PDU sessions, handling user plane QoS, buffering downlink packets, providing mobility anchoring, etc.

[0062] The CN 115 may facilitate communication with other networks. For example, the CN 115 may include or communicate with an IP gateway (e.g., an IP Multimedia Subsystem (IMS) server) that acts as an interface between the CN 115 and the PSTN 108. Additionally, the CN 115 may provide the WTRUs 102a, 102b, 102c with access to other networks 112, which may include other wired and / or wireless networks owned and / or operated by other service providers. In an embodiment, the WTRUs 102a, 102b, 102c may be connected to local data networks (DNs) 185a, 185b through the UPFs 184a, 184b via an N3 interface to the UPFs 184a, 184b and an N6 interface between the UPFs 184a, 184b and the DNs 185a, 185b.

[0063] 1A-1D and the corresponding description thereof, one or more or all of the functions described herein with respect to one or more of the WTRUs 102a-d, base stations 114a-b, eNodeBs 160a-c, MME 162, SGW 164, PGW 166, gNBs 180a-c, AMFs 182a-b, UPFs 184a-b, SMFs 183a-b, DNs 185a-b, and / or any other devices described herein may be performed by one or more emulation devices (not shown). The emulation devices may be one or more devices configured to emulate one or more or all of the functions described herein. For example, the emulation devices may be used to test other devices and / or to simulate network and / or WTRU functions.

[0064] The emulation device may be designed to perform one or more tests of other devices in a lab environment and / or in an operator network environment. For example, one or more emulation devices may perform one or more or all functions while fully or partially implemented and / or deployed as part of a wired and / or wireless communication network to test other devices in the communication network. One or more emulation devices may perform one or more or all functions while temporarily implemented / deployed as part of a wired and / or wireless communication network. The emulation device may be directly coupled to another device to test and / or perform tests using over-the-air wireless communications.

[0065] The emulation device or devices may perform one or more functions, inclusive, without being implemented / deployed as part of a wired and / or wireless communication network. For example, the emulation device may be utilized in a test lab and / or in a test scenario in an undeployed (e.g., test) wired and / or wireless communication network to perform tests of one or more components. The emulation device or devices may be test equipment. Direct RF coupling and / or wireless communication via RF circuitry (which may include, e.g., one or more antennas) may be used by the emulation device to transmit and / or receive data.

[0066] One or more of the features disclosed herein may be implemented using one or more of the devices, methods, and / or systems described in Figures 1A-1D.

[0067] Capacity-achieving codes other than turbo codes and / or low-density parity check (LDPC) codes may include polar codes, which may be linear block codes with attributes including one or more of low encoding and / or decoding complexity, a low error floor (e.g., an extremely low error floor), or an explicit construction scheme.

[0068] A polar code (N,K) may be based on an information block length K and a coding block length N. The value N may be set as a power of 2, e.g., N=2 for an integer n. n The generator matrix for the polar code can be

[0069]

number

[0070] where B N is the bit-reversed permutation matrix,

[0071]

number

[0072] denotes the nth Kronecker power,

[0073]

number

[0074] In an exemplary implementation of a polar code, the bit-reversed permutation matrix B N can be ignored at the encoder side for simplicity, and the bit reversal operation can be performed at the decoder side. Figure 2 is an example of a polar encoder with N=8.

[0075]

number

[0076] 1 shows an example implementation of the polar code.

[0077]

number

[0078] It can be given by:

[0079] For decoding of polar coded bits, successive cancellation (SC) decoding may be used. Advanced decoding schemes may also be used based on SC decoding, for example, successive cancellation list (SCL) decoding or CRC-Aided SCL (CA-SCL) decoding.

[0080] A CRC-Aided (CA) polar code may be a polar code that uses a CRC-aided Successive Erasure List (SCL) decoder. In CRC-aided decoding, the CRC bits may be used to select a final codeword from a list of candidate codewords. The final codeword may be selected at the end of the decoding. The CRC bits may be designed and used, for example, for error correction purposes instead of error detection purposes. The CRC bits may be used for partial error detection.

[0081] A code structure for a polar code may be provided. A polar code may be structured with respect to encoding and decoding. The design of a polar code may be implemented using a polar encoder.

[0082]

number

[0083] The K information bits may be placed on K bit channels, e.g., the K best bit channels. The remaining NK input bits that are not mapped to information bits may be referred to as frozen bits. The frozen bits may have fixed values, e.g., the frozen bits may be set to a value of 0. The set of positions of the frozen bits may be referred to as the frozen set F. The decision regarding the best bit channel may vary and may depend on the channel conditions. In determining the set of frozen channels, the bit channels may be ranked based on their reliability. Reliable bit channels may be categorized as good bit channels and less reliable bit channels may be categorized as bad bit channels.

[0084] The reliability of the bit channel may be calculated. For example, one or more of the Bhattacharyya bound, Monte-Carlo estimation, full transition probability matrix estimation, or Gaussian approximation may be used to calculate the reliability of the bit channel. These schemes may have different computational complexities and may be applied to different channel conditions. A parameter design signal-to-noise ratio (SNR) may be selected. For example, the design SNR may be selected before performing the reliability calculation.

[0085] The rank of the bit channel may be calculated. The rank of the bit channel may be calculated without using the design SNR parameter. For example, a rank sequence generated from the formula or extended from a small sequence. Once the rank of the bit channel is determined, the information bits may be mapped to the bit channel with high reliability. The frozen bits may be mapped to the bit channel with low reliability as shown in FIG. 3.

[0086] FIG. 4 illustrates an exemplary parity check (PC) polar coding. The difference between PC polar codes and non-PC polar codes may be the selection of a subset of frozen sub-channels as PC frozen sub-channels. A PC function may be established for error correction across sub-channels. In one example (e.g., at each parity check sub-channel position), each of the decoded bits participating in the PC function across the PC frozen sub-channels may help prune the list decoding tree. In one example, paths that satisfy the PC function may survive, and the rest may be removed on the fly. The PC function may be established as forward-only, for example, to match a successive erasure-based decoder. FIG. 4 illustrates an example of mapping information bits to the input of a PC polar code.

[0087] The introduction of PC polar codes may enable the removal of CRC bits in CA polar codes. PC polar codes may be used for error correction purposes in CRC-assisted Successive Erasure List (SCL) decoding. This may reduce the overhead of polar codes and result in more coding gain.

[0088] Polar codes may be used as channel codes for uplink (UL) and / or downlink (DL) control information. CRC bits may be used for control messages to reduce false alarm rates. Polar codes for physical channels may support one of CRC+basic polar codes or J-bit error detection CRC+concatenated polar codes. CRC+basic polar codes (e.g., CA polar) may be used with a longer CRC, e.g., a (J+J')-bit CRC and / or a distributed CRC, e.g., a J-bit CRC. The concatenated polar codes may be one or more of J'-bit CRC+basic polar, J'-bit distributed CRC+basic polar, PC polar, or hashed sequence PC polar. Coding schemes that may achieve the benefits of both mechanisms may be implemented.

[0089] Polar coding designs for control and / or data information may be given. Unlike tail-biting convolutional codes (TBCC), polar codes, which are block codes, may have a fixed block length. Rate matching for polar codes may be designed to improve performance. Rate matching selection may be performed using one or more of repetition, puncturing, and / or shortening mechanisms. Selection of the rate matching mechanism may be performed based on one or more parameters described herein.

[0090] The polar code design may include code configuration selection (e.g., CRC-assisted (CA) polar coding or parity check (PC) polar coding) and / or code sequence selection. A flexible polar coding scheme may be provided that supports multiple polar codes.

[0091] Polar coding for the control channel may be provided. Figure 5 shows an example processing of control information (e.g., downlink control information (DCI) or uplink control information (UCI)) using a polar code. The control blocks in the polar coding subsystem may include a code selection control block and a rate matching control block.

[0092] The code selection control block may determine the type of polar code to be used. The code selection control block may determine the associated CRC length. Exemplary polar code types may include the polar code types described herein, such as advanced PC polar code with CA list selection, and / or variations thereof. The determination of the polar code type may be based on one or more of a WTRU category, a WTRU capability, or a configuration. In an example, the WTRU category may correspond to the polar code. In an example, the polar code type may be configured via a Radio Resource Control (RRC) connection establishment message or an RRC connection reconfiguration message. In an example, the polar code type may be predefined. A corresponding CRC length may be determined. For example, the CRC length may be determined based on the determined polar code type. For example, for a PC polar code, a 16-bit CRC may be used, and for a CA polar code with a long CRC, a 19-bit CRC may be used, for example, when the list length is equal to 8. The code selection control block may send the CRC length information to the CRC attachment block. The CRC attachment block may pass the polar code type to the channel coding block.

[0093] The rate matching control block in FIG.

[0094]

number

[0095] The rate matching control block may perform one or more of: calculating a desired codeword length (e.g., the number of coded bits for transmission) in bits, calculating a mother code length N (e.g., after calculating the desired codeword length), determining a rate matching scheme to be used, or determining a detailed rate matching scheme. The rate matching control block may perform the calculations or make the decision based on one or more of the following uplink control information (UCI) or downlink control information (DCI) block size K, CRC length J, or code rate R.

[0096] In one example, to calculate the mother code length N, the mother code length N may be assumed to be a power of 2 due to the nature of polar codes. The mother code length N is the desired codeword length

[0097]

number

[0098] For example, if the desired codeword length is 2 n If the mother code length is slightly larger than 2 n+1 The selection of the mother code length may be based on one or more formulas. In one example, For some constant fraction τ, say

[0099]

number

[0100] About

[0101]

number

[0102] If N=2 n Become,

[0103]

number

[0104] If N=2 n+1 become.

[0105] In one example, For some fixed integer τ, such as 10,

[0106]

number

[0107] If N=2 n Become,

[0108]

number

[0109] If N=2 n+1 become. Other exemplary formulas may be similar to those above, where the value τ is a function of n. For example, if n≦5, then τ=0, and otherwise:

[0110]

number

[0111] and If n≦6, then τ=0, otherwise

[0112]

number

[0113] The mother code length formula may or may not depend on the code rate. The formula and its parameter τ may be different for each code rate or range of code rates.

[0114] The selection of the mother code length may be based on one or more look-up tables. Table 1 shows an example of a look-up table (LUT) for selecting a desired codeword length for a corresponding mother code length N. The first row of Table 1 represents a range of desired codeword lengths, and the second row represents the corresponding mother code length. For example, if the desired codeword length is 50 bits, which is in the range of [33, 70], the mother code length may be selected as 64 bits. If the desired codeword length is 275 bits, which is in the range of [141, 280], the selected mother code length may be 256 bits. In the exemplary Table 1, the maximum mother code length is fixed as 1024 bits.

[0115] [Table 1]

[0116] Table 2 shows another example of a LUT where the maximum mother code length can be 512 bits.

[0117] [Table 2]

[0118] The determination of the mother code length may depend on the code rate. In one example where the coding rate may be high (e.g., >1 / 2), the desired codeword length may be shorter than (or slightly longer than) the length of the information bits. The mother code length may be selected to be relatively longer, and thus the use of such a mother code length may contain more information than is contained at, for example, rate=1 / 2.

[0119] For example, when the mother code length depends on the code rate, the exemplary Tables 1 and 2 may be applicable to several code rates. For example, when the code rate is greater than a threshold (e.g., 1 / 2), the mother code length N may be a power of 2. The mother code length may be longer than the desired codeword length. When the code rate is less than a threshold, the mother code length N may be determined based on one or more lookup tables, such as Tables 1 and / or 2. The selection of the mother code length may depend on the modulation order. For example, Tables 1 and 2 may be used for low-order modulation (e.g., QPSK). A different set of tables may be defined for higher-order modulation (e.g., 64QAM).

[0120] Figures 37, 38, 39, and 40 show the results for 10 -3 These example simulation results show that the code rate can be 2 / 5 or less and the coded block length is 2 / 5 or less, and the minimum SNR that can be required to achieve a target BLER level of 1 / 2. n and 2 n (1+1 / 8), a repeating scheme may be selected. For example,

[0121]

number

[0122] 2 n and 2 n If the code rate is between 1 and 1 / 8 and the code rate is less than 2 / 5, the mother code length N is, for example, 2 n+1 Instead of 2 n may be selected as:

[0123] Other performance simulations of examples of punctured natural puncturing, examples of punctured natural shortening, and examples of bit-reversal shortening may give the results described herein. In such simulations, QPSK modulation and an AWGN channel may be assumed. In such simulations, a polar code using a PW sequence and a CA-SCL (L = 8) decoding algorithm may be used. A 19-bit CRC may be added to the source data. Such CRC bits may be regarded as part of the information bits.

[0124] The rate matching control block may determine the rate matching method to be used. The rate matching method may include one or more of repetition, shortening, or puncturing. The selection of the repetition rate matching method may depend on the relationship between the mother code length and the desired codeword length. For example, if the mother code length is shorter than the desired codeword length, the repetition method may be selected. Otherwise, the shortening method or the puncturing method may be selected. The selection between the shortening method and the puncturing method may depend on at least one of the code rate R or the mother code rate

[0125]

Number

[0126] . The puncturing method may perform well and thus may be used at a low code rate or a low mother code rate. The shortening method may perform well and thus may be used at a high code rate or a high mother code rate. A function of f(R m ,R) may be used. If f(R m ,R) < Thr, the puncturing method may be selected; otherwise, the shortening method may be selected.

[0127] In FIGS. 41 and 42, for a code rate of 1 / 5, 10 -2 and 10 -343 and 44 show the minimum SNR that can be used to achieve a target BLER level of 10 for code rate 1 / 3, respectively. -2 and 10 -3 45 and 46 show the minimum SNR that can be used to achieve a target BLER level of 10 for code rate 2 / 5, respectively. -2 and 10 -3 47 and 48 show the minimum SNR that can be used to achieve a target BLER level of 10 for code rate 1 / 2, respectively. -2 and 10 -3 4 indicates the minimum SNR that can be used to achieve the target BLER level of .

[0128] Based on these simulation results, it can be established that if the code rate is greater than 2 / 5, the shortening scheme can be selected. If the code rate is less than or equal to 2 / 5, the puncturing scheme can be selected. In one example, the code rate threshold for selecting the puncturing or shortening scheme can be 2 / 5.

[0129] Rate matching may be implemented using concatenated polar codes (e.g., in addition to a repetition, shortening, and / or puncturing scheme). For example, for a desired codeword length of 288 bits, 224 bits may be punctured or shortened from a mother code length of 512 bits. One method may be to repeat 32 bits from a mother code length of 256 bits. Another method may be to partition the 288 bits into 256 bits and 32 bits. A polar code may be used with a mother code length of 256 bits, and another polar code may be used with a mother code length of 32 bits. This scheme may be used when the desired codeword length is close to a sum of numbers that are a power of two. A repetition, shortening, or puncturing scheme may be applied to each component of the concatenated polar code.

[0130] An exemplary rate matching control process is shown in Figure 6. When determining the detailed rate matching scheme, one or more of the following may be applied:

[0131] When the repetition scheme is selected as the rate matching scheme, the rate matching control block of FIG. 5 may select a detailed repetition scheme. The repetition scheme may include one or more of the following: repetition from above the circular buffer (e.g., natural repetition), repetition from below the circular buffer, repetition from above the circular buffer with bit reversal, repetition from below the circular buffer with bit reversal, random selection, fixed / distributed repetition, repetition from a configured starting point in a continuous manner, or repetition from a configured starting point in an interleaving manner. 0 ,...,e N-1 Let e ​​be the polar coded bits and N+L be the number of transmitted bits. The transmitted bits for the iteration from the top of the circular buffer are e 0 ,...,e N-1 ,e 0 ,...,e L-1 The transmitted bits for the repetition from the bottom of the circular buffer can be expressed as e N-1 ,...,e 0 ,e N-1 ,...,e N-L The transmitted bits for the iteration from the top of the circular buffer with bit reversal can be expressed as e BR(0) ,...,e BR(N-1) ,e BR(0) ,...,e BR(L-1) The transmitted bits for the iteration from the top of the circular buffer with bit reversal can be expressed as e BR(N-1) ,...,e BR(0) ,e BR(N-1) ,...,e BR(N-L)The selection of the repetition scheme may depend on one or more of the number of repeated bits, the mother code length, or the code rate. Based on the determined repetition scheme, a repetition vector may be calculated. The repetition vector length may be calculated based on the desired codeword length.

[0132]

number

[0133] minus the mother code length N, where each value in the repetition vector is an index with a value between 1 and N (or between 0 and N-1). Based on the desired codeword length and the mother code length, the rate matching block may determine the N output bits of the polar encoder that may be repeated. For example, N=256,

[0134]

number

[0135] In this case, the repetition vector may be (1,2,3,4), which may imply that the first four bits of the polar encoder output are repeated. As shown in FIG. 6, the repetition vector may be sent to the rate matching block of FIG.

[0136] If a puncturing scheme is selected, the rate matching block may select a detailed puncturing scheme. The puncturing scheme may include one or more of: puncturing from above a circular buffer, puncturing from below a circular buffer, puncturing from above a circular buffer with bit inversion, puncturing from below a circular buffer with bit inversion, distributed puncturing (e.g., split natural puncturing), puncturing from a configured starting point in a contiguous manner, or puncturing from a configured starting point in an interleaving manner. 0 ,...,eN-1 Let e ​​be the polar coded bits and L be the number of punctured bits. The punctured bits for puncturing from above the circular buffer are e 0 ,...,e L-1 The punctured bits for puncturing from the bottom of the circular buffer can be expressed as e N-L ,...,e N-1 The punctured bits for puncturing from above the circular buffer with bit reversal can be expressed as e BR(0) ,...,e BR(L-1) The punctured bits for puncturing from the bottom of a circular buffer with bit reversal can be expressed as e BR(N-L) ,...,e BR(N-1) The puncturing may be represented as: n = 0, n / 4, and / or n / 2. The distributed puncturing may be from 0, N / 4, and / or N / 2. The puncturing may be performed continuously. The selection of the puncturing scheme may depend on one or more of the number of bits to be punctured, the mother code length, the code rate, etc. Based on the selected puncturing scheme and the number of bits to be punctured, a puncturing vector may be calculated. As shown in FIG. 6, the puncturing vector may be sent to a rate matching block.

[0137] If a shortening scheme is selected, the rate matching block may select a detailed shortening scheme. The shortening scheme may include one or more of shortening from the bottom of the circular buffer, shortening from the bottom of the circular buffer with bit inversion (e.g., called bit-reversal shortening), or split natural shortening. The selection of the shortening scheme may depend on one or more of the number of bits to be punctured, the mother code length, the code rate, etc. Based on the selected shortening scheme and the number of bits to be shortened, a puncturing vector may be calculated that may be sent to the rate matching block. A shortening vector that may correspond to the puncturing vector may be calculated. In the case of a polar encoder that does not use a bit-reversal operation, the shortening vector may be equal to the puncturing vector. In the case of a polar encoder that uses a bit-reversal operation, the shortening vector may be equal to the bit inversion of the puncturing vector. The shortening vector may be sent to a zero insertion sub-block in the channel coding block.

[0138] In one example, K bits of source information of downlink control information (DCI) or uplink control information (UCI) may be passed through the CRC attachment block. The length J of the CRC bits may be determined by the code selection control block of FIG. 5. This block may support possible CRC cases, a single long CRC, two separate CRCs, a normal CRC, etc. The difference between the CA polar encoding process with a single CRC (shown in FIG. 13) and the PC polar encoding process (shown in FIG. 17) may be the CRC length. The CRC may be set as J+J' for CA polar code and as J for PC polar code.

[0139] The source bits may be sent to the channel coding block of FIG. 5 (e.g., after the CRC is attached to the source bits). The channel coding block may perform a polar coding operation. As shown in FIG. 5, the channel coding block may include one or more of the following sub-blocks: a zero insertion sub-block, a bit channel mapping sub-block, a sequence generation or selection sub-block, or a polar coding sub-block. The zero insertion sub-block may insert zeros into the sequence of (K+J) (combined source bits and CRC bits). The position where the zeros should be inserted may depend on a shortened vector input from the rate matching control block. The sequence generation or selection sub-block may generate a ranked sequence (or select from a list of pre-generated ranked sequences) based on, for example, one or more of an input of a given mother code length N from the rate matching control block, a code type input from the code selection control block, and / or other factors such as channel conditions (e.g., SNR). For example, for a CA polar code with mother code length 64 and SNR of 5 dB, we may select or generate a ranked sequence, or select a ranked sequence from a list of pre-generated sequences. The bit mapping sub-block may map the information and / or CRC bits to the appropriate bit channel for the polar code. This operation depends on the code type and may input the ranked sequence. For example, for a PC polar code, the bit mapping sub-block may determine, for example, an information set, a PC frozen set, and / or a frozen set based on a given ranked sequence. For a CA polar code, the bit mapping sub-block may determine, for example, an information set and a frozen set based on a given ranked sequence. The bit mapping sub-block may embed the WTRU ID with the CRC bits using an operation, for example, an XOR operation. The WTRU ID may be embedded by XORing the WTRU ID with the PC frozen bits for the PC polar code.In one example, the WTRU ID may be included in the frozen set. In polar coding, the frozen set may correspond to a certain number of bits (e.g., 0). In this case, the certain bits may be replaced by the WTRU ID. Insertion of the WTRU ID in the frozen set may lead to undesired UEs having decoding errors. The polar coding sub-blocks are:

[0140]

number

[0141] or

[0142]

number

[0143] , a polar encoding operation (eg, a normal polar encoding operation) such as a generator matrix of

[0144] As shown in Figure 5, the polar coded bits may be sent to a rate matching block. The rate matching block may perform a puncturing or repetition operation. The selection of the puncturing or repetition vector may be received from a rate matching control block. Figure 7 shows an example of rate matching for polar coded bits. As shown in Figure 7, N=2 puncturing vectors from the polar coding block (not shown in the figure) may be received from a rate matching control block. nThe bits may be sent to an interleaver sub-block of the rate matching block. The interleaver sub-block in one example may reorder the sub-blocks so that the N polar coded bits are included therein. The operation of the interleaver sub-block may be associated with the rate matching scheme that may be used. In one example, if a circular buffer puncturing from above and / or a circular buffer puncturing from below scheme is used, the interleaver sub-block may be transparent, i.e., no specific operation may be required. In one example, if a circular buffer puncturing from above and / or a circular buffer puncturing from below scheme with bit inversion is used, the interleaver sub-block may perform a bit reversal operation on the N coded bits. In one example, if a distributed puncturing scheme is used, the interleaver sub-block may perform an interlace operation on the middle of the N coded bits. Similar operations may be used with one or more shortening and / or repetition schemes.

[0145] The interleaved bits may be stored in a circular buffer or a virtual circular buffer. As shown in FIG. 7, the operation of storing the bits in the circular buffer may be performed by a bit collection sub-block. As further shown in FIG. 7, depending on a puncturing vector or a repetition vector that may be generated by a rate matching control block, a bit selection sub-block may select bits from the circular buffer. The puncturing vector or the repetition vector may be interpreted to determine a pair of parameters (e.g., starting point, duration) associated with the circular buffer.

[0146] In one example, when a puncturing scheme from above a circular buffer may be applied, a pair of parameters may be determined (e.g., L+1,NL) when the puncturing vector is (0,...,0,1,1,...,1) and when the first L bits are 0 and the last NL bits are 1. An exemplary bit selection is shown in FIG. 8. As shown in FIG. 8, the bits used may start at the L+1 position of the circular buffer with a bit sequence length that may be NL. A similar operation may be applied to a puncturing scheme from above a circular buffer using bit reversal. In such a scheme, the bits may be stored in the circular buffer after the bit reversal operation. A similar operation may be applied to a distributed puncturing scheme. In such a scheme, the bits may be stored in the circular buffer after an interlace or interleave operation on the middle of the N coded bits.

[0147] In one example, if a puncturing scheme from the bottom of the circular buffer may be applied, a pair of parameters (e.g., 1, L) may be determined where the puncturing vector is (1,...,1,0,...,0) and where the first L bits are 1 and the last NL bits are 0. An exemplary bit selection is shown in Figure 9. As shown in Figure 9, the bits used may start at the first position of the circular buffer with the bit sequence length being L.

[0148] A similar operation may be applied to the "puncturing circular buffer from below with bit reversal" scheme, in which bits may be stored in a circular buffer after a bit reversal operation.

[0149] In one example, if a repetition scheme from the top of the circular buffer may be applied, a pair of parameters (e.g., 1, N+L) may be determined where the repetition vector is (1,...,1,0,...,0) and where the first L bits are 1 and the last NL bits are 0. An exemplary bit selection is shown in Figure 10. As shown in Figure 10, the bits used may start from the first position of the circular buffer with the bit sequence length being N+L.

[0150] In one example, if a repetition scheme from the bottom of the circular buffer may be applied, a pair of parameters (e.g., NL, N+L) may be determined where the repetition vector is (0,...,0,1,...,1) and where the first NL bits are 0 and the last L bits are 1. An exemplary bit selection is shown in Figure 11. As shown in Figure 11, the bits used may start from the first position of the circular buffer, with the bit sequence length being N+L.

[0151] The start and / or end points may be on the first or last coded bit. In some examples, neither the start nor the end point may be on the first or last coded bit. If a mixture of puncturing from above and puncturing from below schemes may be used, the start and end points may be in the middle of the coded bits. In one example, if a one-bit shortening with puncturing from above may be used, the puncturing vector may be (0,...,0,1,...,1,0), where the first L bits are 0, the following NL-1 bits are 1, and the last bit is 0. A pair of parameters (e.g., L+1, N-1) may be determined. An exemplary bit selection is shown in FIG. 12.

[0152] An advanced PC polar code with CA list selection may be provided. For example, a polar code that is a mix of PC polar codes with CRC-assisted list selection capability may be provided. Figures 13 and 14 respectively show exemplary encoding and decoding of CA polar codes with long CRC scenarios (e.g., as described herein). Figure 13 shows an exemplary encoding for a CA polar code with a long CRC. Figure 14 shows an exemplary decoding for a CA polar code with a long CRC.

[0153] As shown in FIG. 13, at the encoding side, long CRC bits (J+J') may be appended to the information bits. For example, as specified for the LTE control channel, J on the order of 16 bits may be used as the CRC length. Other values ​​of J may be used, for example, as specified for other communication systems. The value J' may depend on the list size L in a Cyclic Redundancy Check (CRC)-Aided Successive Erasure List (CA-SCL) decoder. In one example, J'=log 2 L. The K+(J+J') bits may be encoded using a basic polar code and rate matching may be applied.

[0154] As shown in Figure 14, at the decoder side, demodulated symbols may be sent to a CA-SCL decoder. The SCL decoder block may output a list of L candidate sequences to a CRC-assisted (CA) list selection block. The CA list selection block may feed back a selected sequence based on the CRC check result and / or the priority of the candidate sequences. If the L candidate sequences fail the CRC check (e.g., all the L candidate sequences fail the CRC check), a detection error may be declared.

[0155] The (J+J') bits may be used in a CRC-aided list selection process, e.g., an error correction process. If the selected sequence may pass the CRC check, an error detection check may follow the error correction.

[0156] 15 and 16 respectively show example encoding and decoding of a CA polar code using two separate CRC scenarios (e.g., as described herein). Figure 15 shows an example encoding for a CA polar code using two separate CRCs. Figure 16 shows an example decoding for a CA polar code using two separate CRCs.

[0157] As shown in Figure 15, at the encoding side, J CRC bits may be appended to the K information bits. These CRC bits may be utilized for error detection. Additional J' CRC bits may be appended to the information bits using an error detection CRC. These J' CRC bits may be utilized for error correction. The resulting (K+J+J') bits may be encoded by a PC polar coder, as shown in Figure 15. Rate matching may be applied to the polar coded bits.

[0158] As shown in FIG. 16, at the decoder side, the demodulated symbols may be sent to a CA-SCL decoder, where the SCL decoder block may provide a list of L candidate sequences to a CA list selection block. The CA list selection block may feed back the selected sequence to the SCL decoder. The CA list selection block may select a sequence based on the J′-bit CRC check result and / or the priority of the candidate sequences. If the L candidate sequences fail the CRC check (e.g., all these L candidate sequences fail the CRC check), a detection error may be declared, as shown by the downward arrow in FIG. 16. The decoded sequence or the error declaration may be passed to a CRC check block. The CRC check block may use the J-bit CRC for error detection. If the CRC check passes, the sequence may be sent to the output. Otherwise, an error may be detected and / or a decoding failure may be declared.

[0159] 17 and 18 respectively show example encoding and decoding of a PC polar code using a CRC (e.g., as described herein). Figure 17 shows example encoding using a PC polar encoder. Figure 18 shows example decoding for a PC polar code.

[0160] As shown in Figure 17, at the encoding side, J CRC bits may be appended to K information bits. These CRC bits may be utilized for error detection. (K+J) bits may be encoded using a PC polar code. The PC polar coded bits may be rate matched. In the PC polar code, some frozen bits may be selected as PC frozen bits. The PC frozen bits may be utilized for error correction, for example, in candidate sequence selection.

[0161] As shown in Figure 18, at the decoder side, the demodulated symbols may be sent to a PC-SCL decoder, where the PC-SCL decoder block may output a single sequence. This sequence may pass a CRC check. If the CRC check passes, the sequence may be sent to the output, otherwise an error may be detected and / or a decoding failure may be declared.

[0162] We disclose a PC polar code that may be a combination of a PC polar code and a CRC-assisted list selection capability. Such encoding may be, for example, similar to the exemplary PC polar coding described with respect to FIG.

[0163] FIG. 19 shows an example decoder for PC polar codes with CRC-assisted list selection. As shown in FIG. 19, at the decoder side, demodulated symbols may be sent to a concatenated PC-SCL decoder. The concatenated PC-SCL decoder block may include a modified PC-SCL decoder sub-block and a CRC-assisted list selection sub-block. The modified PC SCL decoder may generate a list of L candidate sequences for CA list selection, for example, instead of a single sequence (for example, as shown in FIG. 18). Each of the L candidate sequences may pass an internal PC check in the decoder. The modified PC SCL decoder may output L candidate sequences as an SCL decoder, unlike a PC SCL decoder that may output a single codeword, for example. These L candidate sequences may be associated with one or more ranks. The candidate sequences may pass a CRC check, for example, based on J CRC bits. If a high-rank sequence passes the CRC check, the sequence may be identified as a decoded sequence. If the sequence does not pass the CRC check, a detection / decoding failure may be declared.

[0164] The selection of the polar code type may depend on one or more of WTRU capability, WTRU category, or WTRU configuration. For example, for a WTRU with high capability, an advanced PC polar code may be utilized. For a WTRU with low capability, a basic polar code may be utilized. The selection of the polar code may be determined based on the WTRU category. For example, WTRU categories of 1, 2, 3 may correspond to basic polar codes, while WTRU categories of 4, 5, 6 may correspond to advanced PC polar codes. The performance of CA and PC polar codes may depend on the list size utilized in SCL decoding. PC polar codes may be better than CA polar codes at larger list sizes, while CA polar codes may be better than PC polar codes at smaller list sizes. The selection of the polar code to be utilized may depend on the list size that the WTRU may support. This list size may be part of the WTRU capability.

[0165] Provides puncturing vector generation for shortening and / or puncturing. Puncturing and / or shortening schemes may be utilized to exclude some bits among the output coded bits. There may be no impact on the code construction. The shortening scheme may puncture the output coded bits and set the corresponding input bits to 0. These input bits may be included in a frozen bit set. These input bits may be different from other frozen bits, which may be set to a predefined value (e.g., a non-zero value). Since some input bits are preset as frozen bits for shortening, the frozen bit set may need to be adjusted accordingly.

[0166] The corresponding input bits may depend on the inclusion of a bit-reversal (BR) operation in the polar encoding. When a BR operation is included in the polar encoding,

[0167]

number

[0168] , the input bit index corresponding to the output bit can be the BR of the output bit index. When the BR operation is not included in the polar encoding,

[0169]

number

[0170] , an input bit may correspond to an output bit if they have the same index.

[0171] The difference between puncturing and shortening may be the way in which decoding is performed. Once a log-likelihood ratio (LLR) value or probability for each output bit is calculated from the received signal, an LLR value or probability for each punctured (shortened) output bit may be defined. In the case of a puncturing scheme, for example, the LLR value may be log(1)=0, since there is the same probability that the punctured bit is 0 or 1. In the case of a shortening scheme, the LLR value may be set to log(0)=-∞, which may imply, for example, that the punctured bit is equal to 0 (e.g., always equal to 0).

[0172] The puncturing and shortening schemes may result in a puncturing vector to be used in the rate matching block, as shown in Figure 5. Puncturing and / or shortening schemes may be provided that may generate a common puncturing vector for puncturing and / or shortening.

[0173] In one example, length N=2 n Let there be M bits to be punctured or shortened from a mother code with P(i) = P(i) + P(i) + P(i) + P(i) + P(i) + P(i) + P(i) + P(i) + P(i) <Mであるとする。l s Let (i) be the input bit position corresponding to the punctured bit P(i). s (i) The bit may be shortened and set as a frozen bit.

[0174] In one example, l s (i) can be selected as follows: When i < N / 4, l s (i) = N - 1 - i When i ≥ N / 4 and

[0175]

Number

[0176] When,

[0177]

Number

[0178] When i ≥ N / 4 and

[0179]

Number

[0180] When,

[0181]

Number

[0182] Here,

[0183]

Number

[0184] can be the largest integer less than x. mod(a, b) is the remainder of a / b.

[0185] This punching / shortening can be extended as follows: When i < N / 2 G l s (i) = N - 1 - i When i ≥ N / 2G and

[0186]

number

[0187] in the case of,

[0188]

number

[0189] In one example, s (i) may be selected as follows: If mod(i,G)=0,

[0190]

number

[0191] If mod(i,G)=g≠0,

[0192]

number

[0193] In one example, sub-block based puncturing may be utilized. For a mother code length of N, N bits (e.g., N polar coded bits) may be partitioned (e.g., equally partitioned) into b sub-blocks. The b sub-blocks may be partitioned consecutively. The number of sub-blocks, b, may be assumed to be a power of 2. Each sub-block may be

[0194]

number

[0195] It may have l bits. s (i) may be selected as follows:

[0196]

number

[0197] Here, the function d 1 and d 2 can be predefined alone or 1 d 2 It may be correlated with the function d 1 () is a mapping function that can determine the location of a subblock within a set of subblocks. 2 () is a mapping function that may determine the location of bits within a subblock.

[0198] In one example, d 2 () is d 2 It can be defined in such a way that [i] = i. 1 may depend on the reliability distribution of the bit channel of the polar code. 1 [0] may correspond to the most unreliable block of the bit channel, and d 1 [1] may correspond to the second most unreliable block of the bit channel, and so on. For example, for b=2, we have d 1 [0]=1, d 1 If we have [1]=1 and b=4, then we have d 1 [0]=1, d 1 [1]=1, d 1 [2]=2, d 1 If we have [1]=3 and b=8, we have: d 1 [0]=0, d 1 [1]=1, d 1 [2]=2, d 1 [3]=4, d 1 [4]=3, d 1 [5]=5, d 1 [6]=6, d 1 [7]=7 (Pattern 1) or d 1 [0]=0, d 1 [1]=1, d 1 [2]=4, d1 [3]=2, d 1 [4]=3, d 1 [5]=5, d 1 [6]=6, d 1 [7]=7 Pattern 1 is when b=8, starting from the end index

[0199]

number

[0200] Interleaver pattern of

[0201]

number

[0202] Interlace pattern of

[0203]

number

[0204] symmetric interleaver pattern.

[0205]

number

[0206] The interleaver pattern for d 1 [0]=0, d 1 [1]=1, so Pattern 1 may be generated. Pattern 1 may be represented in tabular form as shown in Table 3. Other patterns may also be represented in tabular form.

[0207] [Table 3]

[0208] When b=16 we have: d 1 [0]=0,d 1 [1]=1,d 1 [2]=2,d 1 [3]=4,d 1 [4]=8,d 1 [5]=3,d 1 [6]=5,d 1 [7]=6,d 1 [8]=9,d 1 [9]=10,d 1

[10] =12,d 1

[11] =7,d 1

[12] =11,d 1

[13] =13,d 1

[14] =14,d 1

[15] =15(パターン2) または、 d 1 [0]=0,d 1 [1]=1,d 1 [2]=2,d 1 [3]=3,d 1 [4]=4,d 1 [5]=8,d 1 [6]=5,d 1 [7]=6,d 1 [8]=9,d 1 [9]=10,d 1

[10] =12,d 1

[11] =7,d 1

[12] =11,d 1

[13] =13,d 1

[14] =14,d 1

[15] =15 または、 d 1 [0]=0,d 1 [1]=1,d 1 [2]=2,d 1 [3]=4,d 1 [4]=3,d 1 [5]=8,d 1 [6]=5,d 1 [7]=6,d 1 [8]=9,d 1 [9]=10,d 1

[10] =12,d 1

[11] =7,d 1

[12] =11, d 1

[13] =13, d 1

[14] =14, d 1

[15] =15 Pattern 2 can be represented in tabular form as given in Table 4.

[0209] [Table 4]

[0210] When b=32 we have: d 1 [0]=0, d 1 [1]=1, d 1 [2]=2, d 1 [3]=4, d 1 [4]=8, d 1 [5]=16, d 1 [6]=3, d 1 [7]=5, d 1 [8]=6, d 1 [9]=9, d 1

[10] =10, d 1

[11] =17, d 1

[12] =12, d 1

[13] =18, d 1

[14] =20, d 1

[15] =7, d 1

[16] =24, d 1

[17] =11, d 1

[18] =13, d 1

[19] =19, d 1

[20] =14, d 1

[21] =21, d 1

[22] =22, d 1

[23] =25, d 1

[24] =26, d 1

[25] =28, d 1

[26] =15, d 1

[27] =23, d 1

[28] =27, d 1

[29] =29, d 1

[30] =30, d 1

[31] =31

[0211] Equation (1) can also be expressed as:

[0212]

number

[0213] where d' 1 [i]=b-1-d 1 [i], d' 2 [i]=B-1-d 2 [i], and / or where d' 1 [i]=d 1 [i], d' 2 [i]=d 2 [i]. In one example, d 1 () can be represented by pattern (1) or pattern (2) or any other pattern described herein. In one example, d 2 () is d 2 It can be expressed as (i)=i.

[0214] d 1 The value of [i] may be derived by sorting the values ​​that represent for each block i. If i denotes a block of input bit indices from B×(i-1) to B×(i-1)+B-1, the representative value may be the average or minimum or maximum reliability value of that range. 1 [i] may be the index of the subblock having the i-th representative value.

[0215] Derived d 1 [i] Some d in 1 [i'] and d 1 [i″] (i′≠i″) may be traded off, for example, to improve Hamming distance and error performance properties for shortening and puncturing. A common sum puncturing vector for puncturing and / or shortening may be used, and the decision to shorten or puncture may be based on a particular criterion. Such a criterion may be the code rate described herein.

[0216] A common total puncturing vector may be divided into a puncturing portion and a shortening portion, where such a common puncturing vector may be shared between the puncturing and shortening portions. In one example, the shortening is <p 0 and puncturing may be used when P(i), i≧p 0 It can be used in the case of p 0 can be fixed or can depend on the code rate (or mother code rate) or p, where p is the total number of puncturings and shortenings, and p 0 p. When truncation is used, the corresponding input bit position l s (i) may be set to 0, where P(i)=BR(l) if the BR operation is applied to a polar encoder. s (i),n), or if the BR operation is not applied to the polar encoder, P(i)=l s (i), where BR(x,n) may be the bit reversal of an integer x with respect to n bits, and the unfrozen bits may be permuted in the polar encoder according to the indexes of these zero-valued input bits, which may be excluded in the selection of the unfrozen bits.

[0217] Figure 20 shows an exemplary BLER comparison between the proposed sub-block based puncturing and shortening schemes. For the shortening example of N=512, K=126, P=182, CA-SCL decoding with list size of 8 and CRC length of 16 is applied. The example is for the second pattern or b=16. The results show that the exemplary scheme achieves 10 -3 It can have a coding gain of 0.35 dB at a BLER of 0.

[0218] When R(i) is the position of the ith repeated bit, R(i)=P(N-1-(i%N)). i may be longer than N-1 for repetition. i may be shorter than N-1 for puncturing and / or shortening. The repetition pattern may be configured based on a common puncturing vector that may be used for puncturing and shortening. An interleaver, such as the interleavers described herein, may be configured based on R(i) or P(i), and the ith bit position (index) after interleaving may be the R(i)th bit position (index) before interleaving (e.g., if the index starts from 0).

[0219] Interleaver pattern d 1 () or d' 1 () may be determined as shown in Equation 1 or Equation 2 and may be used for sub-block level interleaving. With reference to Equation 1 or Equation 2,

[0220]

number

[0221] may be the index of the bit before applying subblock-based interleaving, which corresponds to the i-th bit after applying subblock-wise interleaving. In this formula, i may be the index of the bit after interleaving. The number of bits in a subblock or the size B of the subblock may be

[0222]

number

[0223] where N is the number of polar coding bits (eg, mother code length) and b is the number of sub-blocks.

[0224]

number

[0225] may be the index of the interleaved sub-block that contains the i-th bit after interleaving.

[0226]

number

[0227] mod(i,B) may be the index of the subblock before interleaving. mod(i,B) may be the index of the i-th bit in the interleaved subblock. d 2 () may be the interleaver pattern within a sub-block. In one example, 2 (x)=x may represent that no interleaving is applied within the sub-block. 2 (mod(i,B)) may be the index of the bit in the subblock before interleaving that corresponds to the i-th bit in the subblock after applying subblock-level interleaving.

[0228] Figure 21 shows:

[0229]

number

[0230] 1 shows an example of a subblock interleaver with eight subblocks using an index. In this example, the polar coded bits may be partitioned (e.g., uniformly and contiguously) into eight subblocks (subblock 0 to subblock 7). These eight subblocks may be interleaved based on Pattern 1 of the interleaver pattern. Based on Pattern 1, these subblocks may be permuted in the order of [0, 1, 2, 4, 3, 5, 6, 7]. The permuted subblocks may be stored in a circular buffer.

[0231] In Figure 22,

[0232]

number

[0233] 1 illustrates an example of a sub-block interleaver with 16 sub-blocks using an index of [0, 1, 2, 4, 8, 3, 5, 6, 9, 10, 12, 7, 11, 13, 14, 15]. The polar coded bits may be partitioned (e.g., uniformly partitioned) into 16 sub-blocks. These 16 sub-blocks may be interleaved based on Pattern 2 of an interleaver pattern, as described herein. Based on Pattern 2, these sub-blocks may be reordered in the order [0, 1, 2, 4, 8, 3, 5, 6, 9, 10, 12, 7, 11, 13, 14, 15].

[0234] Pattern 1 of the interleaver pattern may be extended to 16 subblocks by doubling each subblock to two subblocks. For example, the middle eight subblocks may be interleaved or interlaced while the top four subblocks and the bottom four subblocks may remain intact. The interleaver pattern may be as follows: d 1 [0]=0, d 1 [1]=1, d 1 [2]=2, d 1 [3]=3, d 1 [4]=4, d 1 [5]=8, d 1 [6]=5, d 1 [7]=9, d 1 [8]=6, d 1 [9]=10, d 1

[10] =7, d 1

[11] =11, d 1

[12] =12, d 1

[13] =13, d 1

[14] =14, d 1

[15] =15

[0235] Pattern 1 of the interleaver patterns described herein may be expanded to 32 subblocks by multiplying each subblock by 4. For example, the middle 16 subblocks may be interlaced while the top 8 subblocks and bottom 8 subblocks remain intact. The interleaver pattern may be as follows: d 1 [0]=0, d 1 [1]=1, d 1 [2]=2, d 1 [3]=3, d 1 [4]=4, d 1 [5]=5, d 1 [6]=6, d 1 [7]=7, d 1 [8]=8, d 1 [9]=16, d 1

[10] =9, d 1

[11] =17, d 1

[12] =10, d 1

[13] =18, d 1

[14] =11, d 1

[15] =19, d 1

[16] =12, d 1

[17] =20, d 1

[18] =13, d 1

[19] =21, d 1

[20] =14, d 1

[21] =22, d 1

[22] =15, d 1

[23] =23, d 1

[24] =24, d 1

[25] =25, d 1

[26] =26, d 1

[27] =27, d 1

[28] =28, d 1

[29] =29, d 1

[30] =30, d 1

[31] =31

[0236] In FIG. 23A to FIG. 23C,

[0237]

number

[0238] 1 shows an example of a sub-block interleaver with 32 sub-blocks using an index of 16. In this example, the middle 16 sub-blocks may be interlaced, while the top 8 sub-blocks and bottom 8 sub-blocks may be copied directly from interleaver pattern Pattern 1 as described herein. This gives interleaver pattern Pattern 3 as follows: d 1 [0]=0, d 1 [1]=1, d 1 [2]=2, d 1 [3]=4, d 1 [4]=3, d 1 [5]=5, d 1 [6]=6, d 1 [7]=7, d 1 [8]=8, d 1 [9]=16, d 1

[10] =9, d 1

[11] =17, d 1

[12] =10, d 1

[13] =18, d 1

[14] =11, d 1

[15] =19, d 1

[16] =12, d 1

[17] =20, d 1

[18] =13, d 1

[19] =21, d 1

[20] =14, d 1

[21] =22, d 1

[22] =15, d 1

[23] =23, d 1

[24] =24, d 1

[25] =25, d 1

[26] =26, d 1

[27] =28, d 1

[28] =27, d 1

[29] =29, d 1

[30] =30, d 1

[31] =31 (Pattern 3) Pattern 3 can be represented in tabular form as shown in Table 5.

[0239] [Table 5]

[0240] The present invention may provide for the use of an interleaver after rate matching. The present invention may provide for a group-based channel interleaver. The output coded bits generated by the polar encoder may be interleaved. For example, the coded bits may be interleaved after application of a rate matching function and / or before modulation. An exemplary interleaving operation may provide improved block error rate (BLER) performance, for example, where higher order modulation may be in use or where fading channels may be present.

[0241] The input information bits may correspond to the output coded bits. The input information bits may have an associated reliability ordering. The rate-matched output coded bits may be ordered based on such reliability ordering associated with each corresponding input information bit.

[0242] c(i) may be the value of the i-th coded rate-matched bit, where i=0,1,...,NM may indicate the bit index of the output coded bits (e.g., natural order, consecutive indexing from a starting point). M may be a rate-matching parameter that may be the number of bits to be punctured or shortened. In one example, the rate matching may be performed by repetition. In such an example, M may be negative. When output bits are repeated, the index order of such output bits may be associated with the same index order associated with the original repeated bits.

[0243] cr(j) may be the value of the (NM-1-j)th reliable output coded bit, where j=0, 1,...,NM may denote the reliability index of the output coded bits. The reliability order of the output coded bits may follow the reliability order of the corresponding input bits. When the corresponding input bits may be frozen bits and / or parity bits, the associated reliability order may be a relatively low and / or lowest reliability order. When output bits may be repeated, the associated reliability order may be the same reliability order as the reliability order associated with the original repeated bits.

[0244] In one example, Q=2 q A variable modulation may be used. The number of input bits provided for modulation may be q. Such bits may be used to generate modulation symbols. There may be differences in reliability among such q bits. For example, if q=4, the first two bits may be classified as more reliable than the last two bits in LTE 16QAM. Two levels of reliability may be provided for bits modulated using 16QAM.

[0245] In one example using 64QAM (e.g., with q=6), the bits may be classified into three levels of reliability: the first two bits may be classified as the most reliable, the next or second two bits may be classified as having less reliability than the first two bits, and the last two bits may be classified as having the least reliability. q The modulation of the variables may have a q / 2 level of reliability. Several numbers and qualities of levels of reliability may be utilized.

[0246] In one example, c(i), i=0,...,NM bits may be divided into q / 2 blocks. M bits may be uniformly divided. BL(k) may denote the kth block. After division, each block may be interleaved. The interleaver may be a random interleaver, a block interleaver, a bit-reversal interleaver, a partitioned natural interleaver, etc. The effect of the selected interleaver used in rate matching may be counted (see, e.g., FIG. 7 and the accompanying description provided herein). In one example utilizing a random interleaver, the interleaving pattern may be generated from a pseudo-random sequence, which may include, e.g., Gold sequences, used in LTE technology. In the case of a block interleaver, the same or different interleaver depth may be applied to the block interleaver.

[0247] In one example, cr(j), j=0,...,NM bits may be divided into q / 2 blocks. For example, the bits may be uniformly divided. Each such block may be denoted by BL(k). Each block may be interleaved, for example, after division, using one or more interleavers. Each BL(k) block may be mapped, for example, after interleaving, to input bits to be provided for modulation, which may be associated with a particular reliability level.

[0248] The interleaved bits may be mapped to modulation symbols, for example, from q / 2 blocks as described herein. In one example, bits with high reliability provided for modulation may be associated with rate-matched coded bits with high reliability (e.g., may correspond to input bits with high reliability). In one example, bits with low reliability provided for modulation may be associated with rate-matched coded bits with low reliability (e.g., may correspond to input bits with low reliability). The kth component bit of a modulation symbol may be associated with BL(k). Figure 24 illustrates an example implementation of such an example using 16QAM, where shaded boxes may indicate more reliable bits and unshaded boxes may indicate less reliable bits.

[0249] In one example, the relatively less reliable bits provided for modulation may be associated with the relatively more reliable rate-matched coded bits (e.g., bits that may correspond to more reliable input bits). In one example, the relatively more reliable bits provided for modulation may be associated with the relatively less reliable input bits (e.g., bits that may correspond to less reliable input bits). The kth component bit of a modulation symbol may be associated with BL(q / 2-k / 2). FIG. 25 illustrates an example implementation of such an example using 16QAM, where shaded boxes may indicate more reliable bits and unshaded boxes may indicate less reliable bits. These representations may apply to one or more of the coded bits and component bits of an example modulation symbol. In other examples, 64QAM modulation and / or 256QAM modulation may be used.

[0250] In one example, the coded bits and the rate matched bits may be partitioned into q / 2 blocks. In one example, the coded bits and the rate matched bits may be partitioned into q blocks. FIG. 26 illustrates such an example implementation using 16QAM modulation and four partitions. As shown in FIG. 26, shaded boxes may indicate more reliable bits and unshaded boxes may indicate less reliable bits. FIG. 27 illustrates an example QPSK modulation using two partitions. FIG. 28 illustrates an example QPSK modulation using two partitions. 2 q The number of partitions for the modulation of a variable may comprise several partitions, for example, (q-1) partitions or a prime number of partitions, etc. Figure 29 shows an example QPSK modulation with 5 partitions. The coded bits and the rate-matched bits may or may not be uniformly partitioned. For example, the blocks may have different numbers of bits.

[0251] An example channel interleaver for a physical channel is shown in FIG. 30. Using this parallel block interleaver operation can be applied to the uplink and / or downlink. The output of the rate matching is M bits u 1 ,...,u M Suppose that M may include: These bits may be partitioned into several groups. The number of groups may be denoted by p. For simplicity, M may be divisible by p. If M is not divisible by p, null or dummy bits may be inserted into the output of rate matching so that the total number of bits is divisible by p.

[0252] The bits can be grouped based on order. The first group is u 1 ,u 2 ,...u M / p and the second group may include

[0253]

number

[0254] and the pth group may include

[0255]

number

[0256] The bits may be grouped based on the interlace order. The first group may include u 1 ,u 2 ,...,u M-p+1 and the second group may include u 2 ,u p+2 ,...,u M-p+2 The pth group may include u p ,u 2p ,...,u M The bits may be grouped based on a subgroup-wise operation. 1 ,...,v q can be generated, where the subgroups are 1 ,...,u M The subgroup v may contain some bits in the range 1 ,...,v q is the bit u in the operations described here. 1 ,...,u M may be treated as

[0257] The grouped bits can be passed to its corresponding interleaver. The interleaver can be a block interleaver of the same depth, or a block interleaver with a different depth, or an arbitrary interleaver. In one example of a block interleaver, d 1 , d 2 , ..., d p Assuming that d is the depth of these p block interleavers, some or all of the di may have different values. i can be a prime number. Other values ​​of d i may be possible.

[0258] The interleaved bits from the p groups may be combined into a combined output. The grouped interleaved bits may be combined in a group order. For example, the interleaved bits of the first group may be generated first, the interleaved bits of the second group may be generated second, etc. The grouped interleaved bits may be combined in a group order with a pattern. For example, the interleaved bits of the second group may be generated first, the interleaved bits of the fifth group may be generated second, etc. The grouped interleaved bits may be combined in an interlaced order. For example, the order may be: first bit from the first group, first bit from the second group, ..., first bit from the last group, second bit from the first group, second bit from the second group, ..., second bit from the last group, third bit from the first group, .... The grouped interleaved bits may be combined together in an interlaced order using, for example, the group order.

[0259] Figure 31 shows an example interleaving that may be performed between rate matching and modulation. In one example, interleaving may be performed first within the rate matching block. Interleaving performed after the rate matching block may take into account interleaving performed as part of the rate matching block or function.

[0260] An exemplary interleaver design may depend on the modulation order: A matrix or block interleaver that performs interleaving after a rate matching block or function for higher order modulation and performance in fading channels may be such that the number of rows is equal to the modulation order or equal to the modulation order minus one.

[0261] The block interleaver after the rate matching block may be described by the depth of the rate matching block. Figure 32 shows an example of a block interleaver using a depth of 5 (e.g., the number of rows of the block interleaver). The depth of the block interleaver may depend on the modulation order. For example, for 64QAM modulation, a block interleaver using a depth of 7 may not be sufficient (e.g., may not render the desired performance). For 16QAM modulation, a block interleaver using a depth of 7 may be sufficient (e.g., may render the desired performance).

[0262] As shown in Figures 33, 34, and 35, a block interleaver using a depth of 11 may be sufficient for QPSK, 16QAM, and / or 64QAM modulation orders, as well as for AWGN and / or fading channels. A block interleaver with a depth of 11 may follow Figure 32 with a number of rows equal to 11. A unified block interleaver with a fixed depth may be used for each of the supported modulation orders. For example, a unified block interleaver with a fixed depth may be used for each of the supported modulation orders for simplicity. Each of the supported modulations and / or modulation orders may include modulations and / or modulation orders for which gains may be achieved using a block interleaver. The block interleaver used may include a block interleaver with a depth of 11 as a bit channel interleaver after a rate matching block for modulations such as QPSK, 16QAM, 64QAM, 16QAM, and / or 64QAM. An example may use a block interleaver with a depth of 11 as the bit channel interleaver after the rate matching block for each of the supported modulation orders, e.g., for modulations that may be higher than 64QAM. A triangular interleaver may be used after the rate matching block to achieve performance like that achieved by, e.g., a block interleaver. A random interleaver may be used after the rate matching block to achieve performance like that achieved by, e.g., a block interleaver and / or a triangular interleaver.

[0263] Block interleavers with different depths may be used. For example, different depths based on the modulation order may be used. For example, a block interleaver with a depth of 5, a depth of 7, and / or a depth of 11 may be applied to QPSK modulation, and / or a block interleaver with a depth of 7 and / or a depth of 11 may be applied to 16QAM modulation. A block interleaver with a depth of 5 and / or a depth of 11 may be applied to 64QAM modulation. A block interleaver with a depth of 11 may be applied to 16QAM modulation, and / or a block interleaver with a depth of 5 may be applied to 64QAM modulation.

[0264] The depth of the block interleaver may be selected and / or specified based on the code rate. For example, for high code rates, a smaller depth may be used. For low code rates, a larger depth may be used. In one example for a code rate of 1 / 2, one or more depths may be used to achieve similar block error rate performance. In one example, a depth of 3 may be used for modulation orders (e.g., all modulation orders). In one example, for a code rate of 1 / 6, a large depth (e.g., 11) may be used for better block error rate performance than a smaller depth (e.g., 3 or 5). In one example, the depth of the block interleaver may be selected and / or specified based on the modulation order and / or code rate as described herein.

[0265] If the split natural shortening or puncturing scheme is used as the rate matching scheme, the interleaver in the rate matching block or function may be designed such that the coded bits may be equally divided into four groups, with the second and third groups of four being interlaced.

[0266] FIG. 36 illustrates an exemplary performance gain that may result from the use of a matrix interleaver after a rate matching block for 16QAM modulation. Performance simulations of an example of partitioned natural puncturing, an example of partitioned natural shortening, an example of bit reversal shortening, and an example of natural repetition may give the results described herein. In such simulations, QPSK modulation and an AWGN channel may be assumed. In such simulations, a polar code with a PW sequence and a CA-SCL (L=8) decoding algorithm may be used. A 19-bit CRC may be appended to the source data. Such CRC bits may be considered as part of the information bits.

[0267] A triangular channel interleaver may be used in uplink (UL) transmission. A parallel rectangular interleaver may be used in downlink (DL) transmission. A triangular channel interleaver may be provided.

[0268] In one example, 1 ,...,u M Let be the M output bits of the rate matcher that can be transmitted. The smallest integer P is

[0269]

number

[0270] It can be determined as follows:

[0271]

number

[0272] , and y 1 ,...,y Q y i =u i , 1 ≤ i ≤ M, and y i = null, M+1 ≤ i ≤ Q, then the bit sequence y 1 ,...,y Qmay be written into a right isosceles triangle row by row starting from the top left corner of the array as shown in Figure 49. The output of the triangular interleaver is a bit sequence, e.g., y 1 ,y P+1 ,y 2P ,... During the process, null bits may be skipped.

[0273] Various variations of the triangular interleaver may be provided. In one example, null bits may be inserted at the beginning of the bit sequence from the rate matching block. The minimum integer P is:

[0274]

number

[0275] It can be determined as follows:

[0276]

number

[0277] , and y 1 ,...,y Q y i = null, 1 ≤ i ≤ QM, and y i =u i-(Q-M) , QM≦i≦Q, then the bit sequence y 1 ,...,y Q may be written into a right isosceles triangle row by row starting from the upper left corner of the array. For example, a column-wise permutation may be applied. The output of the triangular interleaver is a bit sequence that is read out column by column starting from the first column, e.g., y 1 ,y P+1 ,y 2P ,.... During the process, null bits may be skipped. 1 ,...,u M Inserting a null bit at the beginning of u makes the first output bit 1 This can be avoided in order to

[0278] In one example, the bottom right corner of the array may be applied as shown in Figure 50. A null bit is a bit sequence u 1 ,...,u M The smallest integer P can be inserted at the end of

[0279]

number

[0280] It can be determined as follows:

[0281]

number

[0282] , and y 1 ,...,y Q y i =u i , 1≦i≦M, and y i = null, M+1 ≤ i ≤ Q, then the bit sequence y 1 ,...,y Q may be written into a right isosceles triangle row by row starting from the lower right corner of the array as shown in FIG. 50. For example, a column-wise permutation may be applied. The output of the triangular interleaver is a bit sequence, e.g., y Q-P+1 , y Q-P+2 , y Q-2P+2 , ... During the process, null bits may be skipped.

[0283] In one example, the bottom right corner of the array and the null bit correspond to the bit sequence u 1 ,...,u M The smallest integer P can be inserted at the beginning of

[0284]

number

[0285] It can be determined as follows:

[0286]

number

[0287] , and y 1 ,...,y Q y i = null, 1 ≤ i ≤ QM, and y i =u i -(QM), where Q-M+1≦i≦Q, then the bit sequence y 1 ,...,y Q may be written into a right isosceles triangle row by row starting from the lower right corner of the array as shown in FIG. 50. For example, a column-wise permutation may be applied. The output of the triangular interleaver is a bit sequence, e.g., y Q-P+1 , y Q-P+2 , y Q-2P+2 , ... During the process, null bits may be skipped. For example, a column-wise permutation may be applied to further randomize the output of the triangular interleaver.

[0288] A parallel triangular interleaver may be applied as described herein. For example, the number M of output bits from the rate matcher may be divided into B groups. Each group may or may not have the same number of bits. Dummy / null bits may be added to make each group have the same number of bits. The number of groups may depend on the modulation order. Different methods of partitioning the M output bits of the rate matcher may be utilized. A triangular interleaver may be applied to the groups. The triangular interleaver outputs for each group may be combined, for example, via a concatenation or interlacing operation. For example, v i,1 ,...,v i,Q Let v be the output bit from the i-th group. Assuming there are four groups, when the interlacing operation is applied, the final output of the channel interleaver is v 1,1 ,v 2,1 ,v 3,1,v 4,1 ,v 1,2 ,v 2,2 ,v 3,2 ,v 4,2 ,v1 ,3 ,...,v 1,Q ,v 2,Q ,v 3,Q ,v 4,Q The example shown in FIG. 30 may be applied to a triangular interleaver.

[0289] FIG. 51 illustrates an example of a polar coding system. As shown in FIG. 51, the example polar coding system may include one or more of a CRC attachment and code configuration block, a rate matching control block, a polar coding block, a rate matching block, a channel interleaving block, or a modulation block. The channel interleaving block may be referred to as a channel interleaver or a bit interleaver. In one example, the channel interleaving block may be part of a rate matching block. As shown in FIG. 51, the polar coded bits N exiting the polar coding block may be rate matched based on a rate matching scheme generated by the rate matching control block as described herein. The rate matched bits M may be passed through a channel interleaving block to interleave the M bits as described herein. The bits after the channel interleaving block may be sent to a modulation block to generate modulation symbols as described herein.

[0290] Although the features and elements of the present disclosure may be described in certain combinations, the features or elements may be used alone or in various combinations with or without other features and elements described. It should be understood that the features described herein may consider New Radio (NR), 3G, 4G, 5G, LTE, LTE-A, and / or other examples, but the features described herein are not limited to these technologies and may be applicable to other wireless systems.

[0291] The processes described above may be implemented in computer programs, software, and / or firmware embodied in a computer-readable medium for execution by a computer and / or processor. Examples of computer-readable media include, but are not limited to, electronic signals (transmitted over wired and / or wireless connections) and / or computer-readable storage media. Examples of computer-readable storage media include, but are not limited to, read-only memory (ROM), random-access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks and / or digital versatile disks (DVDs). A processor in association with software may be used to implement a radio frequency transceiver for use in a WTRU, a terminal, a base station, an RNC, and / or any host computer.

Claims

1. 1. A method implemented by a wireless transmit / receive unit (WTRU), comprising: generating a first plurality of uplink control information (UCI) bits to be transmitted within a first codeword; applying a first polar code to the first UCI bits, a first mother code length associated with the first polar code being determined based on a first codeword length for transmission of the first UCI bits, the first mother code length being smaller than the first codeword length; performing rate matching on the polar coded first UCI bits using a repetition scheme; transmitting the polar coded and rate matched first UCI bits; generating a second plurality of uplink control information (UCI) bits to be transmitted within a second codeword; applying a second polar code to the second UCI bits, a second mother code length associated with the second polar code being determined based on a second codeword length for transmission of the second UCI bits, the second mother code length being greater than the second codeword length; performing rate matching on the polar coded second UCI bits using a puncturing scheme based on a code rate for the second codeword being less than a threshold; and transmitting the polar coded and rate matched second UCI bits; generating a third plurality of uplink control information (UCI) bits to be transmitted within a third codeword; applying a third polar code to the third UCI bits, a third mother code length associated with the third polar code being determined based on a third codeword length for transmission of the third UCI bits, the third mother code length being greater than the third codeword length; performing rate matching on the polar coded third UCI bits using a shortening scheme based on a code rate for the third codeword being greater than the threshold; and transmitting the polar coded and rate matched third UCI bits; The method includes:

2. 2. The method of claim 1, wherein the second mother code length is determined based on the code rate for the second codeword, and the third mother code length is determined based on the code rate for the third codeword.

3. 2. The method of claim 1, wherein the first codeword includes a first plurality of cyclic redundancy check (CRC) bits, the second codeword includes a second plurality of CRC bits, and the third codeword includes a third plurality of CRC bits.

4. 2. The method of claim 1 , wherein the code rate for the second codeword corresponds to a first number of UCI bits and a first number of cyclic redundancy check (CRC) bits in the second codeword divided by a first number of bits encoded in the second codeword, and the code rate for the third codeword corresponds to a second number of UCI bits and a second number of CRC bits in the third codeword divided by a second number of bits encoded in the third codeword.

5. 2. The method of claim 1, wherein the first polar code comprises a first concatenated polar code, the second polar code comprises a second concatenated polar code, and the third polar code comprises a third concatenated polar code.

6. The method of claim 5 , further comprising performing the rate matching on the first concatenated polar code, the second concatenated polar code, and the third concatenated polar code.

7. 1. A wireless transmit / receive unit (WTRU) comprising a processor and a memory, the processor and the memory comprising: generating a first plurality of uplink control information (UCI) bits to be transmitted within a first codeword; applying a first polar code to the first UCI bits, a first mother code length associated with the first polar code being determined based on a first codeword length for transmission of the first UCI bits, the first mother code length being smaller than the first codeword length; performing rate matching on the polar coded first UCI bits using a repetition scheme; transmitting the polar coded and rate matched first UCI bits; generating a second plurality of uplink control information (UCI) bits to be transmitted within a second codeword; applying a second polar code to the second UCI bits, a second mother code length associated with the second polar code being determined based on a second codeword length for transmission of the second UCI bits, the second mother code length being greater than the second codeword length; performing rate matching on the polar coded second UCI bits using a puncturing scheme based on a code rate for the second codeword being less than a threshold; transmitting the polar coded and rate matched second UCI bits; generating a third plurality of uplink control information (UCI) bits to be transmitted within a third codeword; applying a third polar code to the third UCI bits, a third mother code length associated with the third polar code being determined based on a third codeword length for transmission of the third UCI bits, the third mother code length being greater than the third codeword length; performing rate matching on the polar coded third UCI bits using a shortening scheme based on a code rate for the third codeword being greater than the threshold; transmitting the polar coded and rate matched third UCI bits. The WTRU is configured as follows.

8. The WTRU of claim 7 , wherein the second mother code length is determined based on the code rate for the second codeword, and the third mother code length is determined based on the code rate for the third codeword.

9. 8. The WTRU of claim 7, wherein the first codeword includes a first plurality of cyclic redundancy check (CRC) bits, the second codeword includes a second plurality of CRC bits, and the third codeword includes a third plurality of CRC bits.

10. 8. The WTRU of claim 7, wherein the code rate for the second codeword corresponds to a first number of UCI bits and a first number of cyclic redundancy check (CRC) bits in the second codeword divided by a first number of bits encoded in the second codeword, and the code rate for the third codeword corresponds to a second number of UCI bits and a second number of CRC bits in the third codeword divided by a second number of bits encoded in the third codeword.

11. The WTRU of claim 7 , wherein the first polar code comprises a first concatenated polar code, the second polar code comprises a second concatenated polar code, and the third polar code comprises a third concatenated polar code.

12. The WTRU of claim 11 , wherein the processor and the memory are further configured to perform the rate matching on the first concatenated polar code, the second concatenated polar code, and the third concatenated polar code.

13. At least one computer-readable medium that, when executed by a processor, causes the processor to: generating a first plurality of uplink control information (UCI) bits to be transmitted within a first codeword; applying a first polar code to the first UCI bits, a first mother code length associated with the first polar code being determined based on a first codeword length for transmission of the first UCI bits, the first mother code length being smaller than the first codeword length; performing rate matching on the polar coded first UCI bits using a repetition scheme; transmitting the polar coded and rate matched first UCI bits; generating a second plurality of uplink control information (UCI) bits to be transmitted within a second codeword; applying a second polar code to the second UCI bits, a second mother code length associated with the second polar code being determined based on a second codeword length for transmission of the second UCI bits, the second mother code length being greater than the second codeword length; performing rate matching on the polar coded second UCI bits using a puncturing scheme based on a code rate for the second codeword being less than a threshold; and transmitting the polar coded and rate matched second UCI bits; generating a third plurality of uplink control information (UCI) bits to be transmitted within a third codeword; applying a third polar code to the third UCI bits, a third mother code length associated with the third polar code being determined based on a third codeword length for transmission of the third UCI bits, the third mother code length being greater than the third codeword length; performing rate matching on the polar coded third UCI bits using a shortening scheme based on a code rate for the third codeword being greater than the threshold; and transmitting the polar coded and rate matched third UCI bits; A computer-readable medium having stored thereon instructions configured to cause a computer to execute a program.

14. The instructions, when executed by the processor, cause the processor to: determining the second mother code length based on the code rate for the second codeword; determining the third mother code length based on the code rate for the third codeword; The computer readable medium of claim 13 further configured to:

15. The instructions, when executed by the processor, cause the processor to: applying a first polar code to the first UCI bits, the first mother code length associated with the first polar code being determined based on a first codeword length, the first codeword including a first plurality of cyclic redundancy check (CRC) bits; applying a second polar code to the second UCI bits, the second mother code length associated with the second polar code being determined based on a second codeword length, the second codeword including a second plurality of CRC bits; applying a third polar code to the third UCI bits, the third mother code length associated with the third polar code being determined based on a third codeword length, the third codeword including a third plurality of CRC bits; The computer readable medium of claim 13 further configured to:

16. The instructions, when executed by the processor, cause the processor to: performing rate matching on the polar coded second UCI bits, the code rate for the second codeword corresponding to a first number of UCI bits and a first number of cyclic redundancy check (CRC) bits in the second codeword divided by a first number of bits coded in the second codeword; performing rate matching on the polar coded third UCI bits, the code rate for the third codeword corresponding to a second number of UCI bits and a second number of CRC bits in the third codeword divided by a second number of bits coded in the third codeword; The computer readable medium of claim 13 further configured to:

17. The instructions, when executed by the processor, cause the processor to: applying a first polar code to the first UCI bits, the first polar code comprising a first concatenated polar code; applying a second polar code to the second UCI bits, the second polar code comprising a second concatenated polar code; and applying a third polar code to the third UCI bits, the third polar code comprising a third concatenated polar code; and The computer readable medium of claim 13 further configured to:

18. 20. The computer-readable medium of claim 17, wherein the instructions, when executed by the processor, are configured to further cause the processor to perform the rate matching on the first concatenated polar code, the second concatenated polar code, and the third concatenated polar code.

Images