Indicating device

Abstract

To improve stability of a processing process of wiring formed by using copper, aluminum, gold, silver, molybdenum and the like; or reduce impurity concentration of a semiconductor film; or improve electrical characteristics of a semiconductor device.SOLUTION: In a transistor having an oxide semiconductor film, an oxide film contacting the oxide semiconductor film, and a pair of conductive films which contact the oxide film and are formed by using copper, aluminum, gold, silver, molybdenum and the like, the oxide film has a plurality of crystal parts and has c-axis orientation in the plurality of crystal parts, and the c-axis is oriented in a direction parallel with a normal vector of a top face of the oxide semiconductor film or a top face of the oxide film.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device having a transistor and a manufacturing method thereof. [Background technology]

[0002] It is used in many flat panel displays, such as liquid crystal displays and light-emitting displays. The transistors used are amorphous silicon and single crystal silicon formed on a glass substrate. The silicon semiconductor is made of silicon semiconductor such as polycrystalline silicon or polysilicon. Transistors using semiconductors are also used in integrated circuits (ICs).

[0003] In recent years, metal oxides that exhibit semiconducting properties have been used in transistors instead of silicon semiconductors. In this specification, the term "oxide" refers to a metal oxide that exhibits semiconductor properties. Let us call them semiconductors.

[0004] For example, a transistor using zinc oxide or an In-Ga-Zn oxide as an oxide semiconductor may be used. A transistor is manufactured and used as a switching element for pixels of a display device. Techniques have been disclosed (see Patent Documents 1 and 2).

[0005] In addition, as flat panel displays become larger and higher resolution, the driving frequency becomes higher. As the wiring becomes larger, the resistance and parasitic capacitance of the wiring increases, causing wiring delays. In order to suppress this, a technique for forming wiring using copper is being investigated (Patent Document 3). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A [Patent Document 3] JP 2004-133422 A Summary of the Invention [Problem to be solved by the invention]

[0007] However, the constituent elements of the wiring, such as copper, aluminum, gold, silver, and molybdenum, It is difficult to process, and there is a problem that it diffuses into the oxide semiconductor film during processing. be.

[0008] The wiring elements, such as copper, aluminum, gold, silver, and molybdenum, are It is one of the impurities that can cause poor electrical characteristics. When the oxide semiconductor film is mixed with the oxide semiconductor film, the resistance of the film is reduced, and the film is susceptible to deterioration over time and stress. The electrical characteristics of the transistor, typically the threshold voltage, fluctuates as a result of the switching test. There is a problem.

[0009] Therefore, one embodiment of the present invention is a semiconductor device formed using copper, aluminum, gold, silver, molybdenum, or the like. Another object of the present invention is to improve the stability of a processing step of wiring that is to be formed by an acid. Another object of the present invention is to reduce the impurity concentration of the nitride semiconductor film. Another object of the present invention is to improve electrical characteristics of a semiconductor device. Another object of the present invention is to improve the reliability of a semiconductor device. Another object of the present invention is to realize high-speed operation of a semiconductor device. Another object of the present invention is to realize a semiconductor device with excellent productivity. It is an object of the present invention to realize a body device that solves all of these problems. There is no need to decide. [Means for solving the problem]

[0010] One embodiment of the present invention is a semiconductor device including an oxide semiconductor film, an oxide film in contact with the oxide semiconductor film, and a semiconductor layer including the oxide semiconductor film. A pair of conductive materials made of copper, aluminum, gold, silver, molybdenum, etc. that contacts the metal film. In a transistor having an oxide film, the oxide film has a plurality of crystal parts, In the present invention, the oxide semiconductor film or the oxide film has a c-axis orientation and the c-axis is a normal vector of the top surface of the oxide semiconductor film or the oxide film. The crystal structure is characterized in that the crystals are oriented in a direction parallel to the torsion. In the present invention, the oxide semiconductor film or the oxide film has a c-axis orientation and the c-axis is aligned along a normal vector of the top surface of the oxide semiconductor film or the oxide film. The oxide film is provided between the oxide semiconductor film and the pair of conductive films in a direction parallel to the vector. By this, the metal elements constituting the pair of conductive films, typically copper, aluminum, gold, silver, molybdenum, It is possible to prevent ribide and the like from moving to the oxide semiconductor film. In semiconductor films, copper, aluminum, gold, silver, molybdenum, etc. can be reduced. .

[0011] Further, one embodiment of the present invention is a semiconductor device including an oxide semiconductor film, an oxide film in contact with the oxide semiconductor film, and an oxide a pair of conductive films having copper, aluminum, gold, silver, or molybdenum in contact with the oxide film; a gate insulating film in contact with the oxide semiconductor film or the oxide film, and an oxide semiconductor film a gate electrode overlapping the oxide film and the semiconductor film, the oxide film having a plurality of crystal portions. The crystal parts have a c-axis orientation, and the c-axis is aligned in an oxide semiconductor film or an oxide A semiconductor device having transistors oriented parallel to the normal vector of the upper surface of the semiconductor film. be.

[0012] In addition, the orientation of the a-axis and b-axis is irregular in the multiple crystal parts contained in the oxide film. The pair of conductive films may have a single-layer structure. Alternatively, the pair of conductive films may have a laminated structure. In addition, when the pair of conductive films has a laminated structure, at least the portion in contact with the oxide film may be The film may have copper, aluminum, gold, silver, or molybdenum.

[0013] The transistor is a bottom gate transistor, and has a gate electrode and a pair of a gate insulating film, an oxide semiconductor film, and an oxide film are provided between the conductive films, the oxide insulating film is in contact with a surface of the oxide semiconductor film opposite to a surface of the oxide semiconductor film in contact with the oxide film; The gate electrode and the nitride insulating film are in contact with the oxide insulating film.

[0014] The transistor is a top-gate transistor, and the oxide semiconductor film and Between the gate electrodes, an oxide film, a pair of conductive films, and a gate insulating film are arranged in this order, and an oxide semiconductor The oxide semiconductor film is in contact with the insulating base film, and the insulating base film is a surface of the oxide semiconductor film that is in contact with the oxide film. and a nitride insulating film in contact with the oxide insulating film.

[0015] In addition, the pair of conductive films may have a protective film on the surface opposite to the surface in contact with the oxide film. .

[0016] The protective film is a nitride insulating film, typically silicon nitride, silicon oxynitride, or nitride. It may be formed of aluminum or aluminum oxynitride.

[0017] Alternatively, the protective film is a light-transmitting conductive film, typically, indium tin oxide, Indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium The insulating layer 11 may be formed of indium zinc oxide, or indium tin oxide with silicon oxide.

[0018] Alternatively, the protective film is an oxide film containing In, Ga, or Zn, typically I n-Ga oxide, In-Zn oxide, In-M-Zn oxide (M is Ga, Y, Zr, L a, Ce, or Nd). Effect of the Invention

[0019] According to one embodiment of the present invention, the electrode is formed using copper, aluminum, gold, silver, molybdenum, or the like. The stability of the wiring processing step can be improved. In a semiconductor device using a semiconductor film, impurities in an oxide semiconductor film can be reduced. According to one embodiment of the present invention, in a semiconductor device including an oxide semiconductor film, According to one embodiment of the present invention, the thermal conductivity can be improved by using an oxide semiconductor film. In the semiconductor device having the above-mentioned structure, the reliability can be improved. In addition, according to one embodiment of the present invention, a semiconductor device can be manufactured. In addition, according to one embodiment of the present invention, it is possible to realize a high productivity. It is possible to realize a semiconductor device having such a structure. [Brief description of the drawings]

[0020] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Diagram 2] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a transistor. [Diagram 3] FIG. 1 illustrates a band structure of a transistor. [Figure 4] FIG. 1 is a diagram for explaining a calculation model of IGZO(111). [Diagram 5] FIG. 1 is a diagram illustrating a diffusion path and an activation barrier of Cu. [Figure 6] FIG. 1 is a diagram illustrating a diffusion path and an activation barrier of Cu. [Figure 7] FIG. 1 is a diagram illustrating a diffusion path and an activation barrier of Cu. [Figure 8] FIG. 1 is a diagram illustrating a diffusion path and an activation barrier of Cu. [Figure 9] FIG. 1 is a diagram illustrating an activation barrier of Cu. [Figure 10] FIG. 1 is a diagram for explaining a calculation model of ZnO. [Figure 11] FIG. 1 is a diagram illustrating a diffusion path and an activation barrier of Cu. [Figure 12] FIG. 1 is a diagram illustrating a diffusion path and an activation barrier of Cu. [Figure 13] FIG. 1 is a diagram illustrating an activation barrier of Cu. [Figure 14] FIG. 1 is a cross-sectional view illustrating one embodiment of a transistor. [Figure 15] FIG. 1 is a cross-sectional view illustrating one embodiment of a transistor. [Figure 16] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 17] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a transistor. [Figure 18] 1A and 1B are a block diagram and a circuit diagram illustrating one embodiment of a semiconductor device. [Figure 19] FIG. 1 is a top view illustrating one embodiment of a semiconductor device. [Figure 20] 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 21] 1A to 1C are cross-sectional views illustrating one mode of a method for manufacturing a semiconductor device. [Figure 22]1A to 1C are cross-sectional views illustrating one mode of a method for manufacturing a semiconductor device. [Figure 23] 1A to 1C are cross-sectional views illustrating one mode of a method for manufacturing a semiconductor device. [Figure 24] 1A to 1C are cross-sectional views illustrating one mode of a method for manufacturing a semiconductor device. [Diagram 25] 1A to 1C are cross-sectional views illustrating one mode of a method for manufacturing a semiconductor device. [Figure 26] 1A to 1C are cross-sectional views illustrating one mode of a method for manufacturing a semiconductor device. [Figure 27] FIG. 1 is a diagram showing an electron microbeam diffraction pattern of an oxide semiconductor. [Figure 28] 1A and 1B are diagrams showing the results of impurity analysis and XRD analysis of an oxide semiconductor. [Figure 29] 1A and 1B are diagrams showing the results of impurity analysis and XRD analysis of an oxide semiconductor. [Diagram 30] 1A and 1B are diagrams showing the results of impurity analysis and XRD analysis of an oxide semiconductor. [Diagram 31] 1A and 1B are diagrams showing the results of impurity analysis and XRD analysis of an oxide semiconductor. [Diagram 32] FIG. 1 is a cross-sectional view illustrating one embodiment of a transistor. [Diagram 33] FIG. 1 is a cross-sectional view illustrating one embodiment of a transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and the embodiments and aspects of the present invention may be modified without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the embodiments and details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments and examples. In the following embodiments and examples, the same parts or parts having similar functions are In the case of parts, the same reference numerals or the same hatch patterns are used in common among different drawings, and the repetition The explanation of the repetition will be omitted.

[0022] In each figure described in this specification, the size, thickness, or area of ​​each component is indicated by the following formula: The figures may be exaggerated for clarity and are not necessarily limited to scale. stomach.

[0023] In addition, the terms "first," "second," "third," etc., used in this specification are used interchangeably to avoid confusion of components. The number is added for convenience and is not intended to be a numerical limit. The terms can be replaced with "second" or "third" as appropriate for explanation.

[0024] The function of the "source" and "drain" is to change the direction of the current during circuit operation. For this reason, in this specification, the terms "sauce" and "dressing" are used interchangeably. The terms "in" and "in" may be used interchangeably.

[0025] Voltage is the potential difference between two points, and potential is the electrostatic field at a certain point. This refers to the electrostatic energy (electrical potential energy) possessed by a unit charge in a particle. Generally, the potential difference between a potential at a certain point and a reference potential (for example, ground potential) This is simply called potential or voltage, and potential and voltage are often used synonymously. Therefore, in this specification, unless otherwise specified, potential may be read as voltage. In this specification, voltage may be read as potential.

[0026] In this specification, when an etching process is performed after a photolithography process, The mask formed in the photolithography process is removed.

[0027] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings. Please refer to the following for explanation.

[0028] In a transistor including an oxide semiconductor film, An example of such defects is oxygen vacancies. The threshold voltage of a transistor using a thin film is easily shifted in the negative direction. This is because charges are generated due to oxygen vacancies in the oxide semiconductor film. When a transistor has normally-on characteristics, Various problems such as malfunctions becoming more likely or power consumption increasing when not in operation In addition, the electrical characteristics of transistors, typically There is a problem in that the amount of variation in the threshold voltage increases.

[0029] One of the causes of oxygen vacancies is damage that occurs during the manufacturing process of a transistor. For example, an insulating film or a conductive film is formed on an oxide semiconductor film by plasma CVD or sputtering. When forming an oxide semiconductor film, the oxide semiconductor film may be damaged depending on the forming conditions. There are times when this happens.

[0030] In addition to oxygen deficiencies, impurities such as silicon and carbon, which are constituent elements of the insulating film, can also cause damage to the transistor. This can cause the electrical characteristics of the transistor to deteriorate. When manufacturing transistors using this technology, copper, aluminum, gold, and silver are used to suppress wiring delay. Wiring is formed using low-resistance materials such as molybdenum. Copper, aluminum, gold, silver, molybdenum, etc. are also the cause of poor electrical characteristics of transistors. Therefore, when the impurity is mixed into the oxide semiconductor film, As a result, the resistance of the oxide semiconductor film is reduced, and the transistor is degraded due to aging or a stress test. However, there is a problem in that the electrical characteristics of the transistor, typically the threshold voltage, fluctuates.

[0031] In view of the above, in this embodiment, a semiconductor device including a transistor having an oxide semiconductor film is In the above, oxygen vacancies in the oxide semiconductor film, which is a channel region, and impurities in the oxide semiconductor film One of the objectives is to reduce the concentration of substances.

[0032] On the other hand, display devices on the market are becoming larger, with screen sizes of 60 inches or more diagonally. There is a trend toward larger screen sizes, with development also taking into account screen sizes of 120 inches or more. For this reason, the glass substrates used in display devices are large, 8th generation or higher. However, when using a large-area substrate, high-temperature processing, e.g., 450 Heating at temperatures above 30°C requires large, expensive heating equipment, which increases production costs. In addition, high temperature processing can cause warping and shrinkage of the substrate, resulting in a lower yield. is reduced.

[0033] Therefore, in this embodiment, the number of heat treatment steps is small and a large-area substrate can be used. Another object of the present invention is to manufacture a semiconductor device by using heat treatment at low temperature.

[0034] 1A to 1C are a top view and a cross-sectional view of a transistor 60 included in a semiconductor device. The transistor 60 shown in FIG. 1 is a channel-etched transistor. FIG. 1(A) is a top view of a transistor 60, and FIG. 1(B) is a top view of a transistor 60 along the dashed line A- in FIG. FIG. 1(C) is a cross-sectional view taken along dashed line CD in FIG. 1(A). In FIG. 1A, for clarity, the substrate 11 and some of the components of the transistor 60 (e.g. For example, the gate insulating film 17), the oxide insulating film 23, the oxide insulating film 24, the nitride insulating film 25, etc. etc. are omitted.

[0035] The transistor 60 shown in FIG. 1B and FIG. 1C has a gate The electrode 15, the substrate 11, and the gate insulating film 17 formed on the gate electrode 15; A multilayer film 20 overlaps the gate electrode 15 via an insulating film 17, and a thin film 21 is in contact with the multilayer film 20 and serves as an electrode. and a pair of conductive films (hereinafter, referred to as a pair of electrodes 21 and 22 in the description) that function as a pair of electrodes. In addition, an oxide insulating film is formed on the gate insulating film 17, the multilayer film 20, and the pair of electrodes 21 and 22. A protective film 26 is formed by the film 23, the oxide insulating film 24, and the nitride insulating film 25. .

[0036] In the transistor 60 described in this embodiment, the multilayer film 20 includes the oxide semiconductor film 18 and The oxide semiconductor film 18 includes an oxide film 19. A part of the oxide semiconductor film 18 functions as a channel region. In addition, an oxide insulating film 23 is formed so as to contact the oxide film 19. An oxide insulating film 24 is formed so as to be in contact with the insulating film 23. That is, the oxide semiconductor film 18 and the oxide insulating film 23.

[0037] In this embodiment, the oxide film 19 is a CAAC (C Axis Aligned It is characterized by being formed using a CAAC oxide film. The details of the film will be described later. In the CAAC oxide film, no crystal grain boundaries were observed, and the c-axis orientation The c-axis is oriented in a direction parallel to the normal vector of the surface on which the crystal is formed or the upper surface. Therefore, the oxide film 19 is formed of the metal elements constituting the pair of electrodes 21 and 22, such as copper and aluminum. It functions as a film that prevents the movement of tungsten, gold, silver, molybdenum, etc. The metal elements constituting the oxide semiconductor film 18 are less likely to migrate to the oxide semiconductor film 18. The impurities contained in the oxide semiconductor film 18 in the layer 20 can be reduced. It is possible to manufacture a transistor with improved performance.

[0038] Other configuration details of transistor 60 are described below.

[0039] There is no particular restriction on the material of the substrate 11, but it should be at least strong enough to withstand the subsequent heat treatment. It is necessary to have heat resistance. For example, glass substrate, ceramic substrate, quartz substrate, surface treatment substrate, etc. A fiber substrate or the like may be used as the substrate 11. Also, a single material such as silicon or silicon carbide may be used. Crystalline semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SO It is also possible to use a semiconductor substrate such as an I-substrate, and a semiconductor element is provided on the substrate. In addition, when a glass substrate is used as the substrate 11, Generation (1500mm x 1850mm), 7th generation (1870mm x 2200mm), 8th Generation (2200mm x 2400mm), 9th generation (2400mm x 2800mm), 1st By using large area substrates such as 2950mm x 3400mm, large display devices can be produced. can be produced.

[0040] In addition, a flexible substrate is used as the substrate 11, and the transistor 60 is directly formed on the flexible substrate. Alternatively, a release layer may be provided between the substrate 11 and the transistor 60. The layer is separated from the substrate 11 after a semiconductor device is partially or completely completed thereon, and then the layer is removed. In this case, the transistor 60 is placed on a substrate having poor heat resistance. It can also be transferred to a plate or flexible substrate.

[0041] The gate electrode 15 may be made of any of a variety of materials, including chromium, copper, aluminum, gold, silver, molybdenum, tantalum, and titanium. a metal element selected from the group consisting of tungsten and tungsten, or an alloy containing the above-mentioned metal elements; The above-mentioned metal elements can be combined to form an alloy or the like. Alternatively, one or more metal elements selected from the group consisting of tin, zinc, zirconium, and zinc oxide may be used. The gate electrode 15 may have a single-layer structure or a multi-layer structure of two or more layers. A single-layer structure of an aluminum film containing titanium, a two-layer structure of an aluminum film on a titanium film, A two-layer structure in which a titanium film is laminated on a titanium nitride film, and a tungsten film is laminated on a titanium nitride film a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film; Layer structure: titanium film, aluminum film laminated on titanium film, titanium on top of aluminum film There are also three-layer structures that form a film. A compound of one or more elements selected from the group consisting of chromium, molybdenum, chromium, neodymium, and scandium. Alternatively, an alloy film having a combination of these or a nitride film may be used.

[0042] The gate electrode 15 is made of indium tin oxide or indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide with titanium oxide A light-transmitting conductive material such as indium tin oxide can also be used. A laminate structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal element may also be used.

[0043] In addition, an In-Ga-Zn-based oxynitride film is formed between the gate electrode 15 and the gate insulating film 17. , In-Sn-based oxynitride film, In-Ga-based oxynitride film, In-Zn-based oxynitride film, Sn-based oxidized nitride film, In-based oxidized nitride film, metal nitride film (InN, ZnN, etc.), etc. are provided. These films have a work function of 5 eV or more, or 5.5 eV or more, and are oxide semiconductors. Since this value is larger than the electron affinity of the body, the threshold voltage of a transistor using an oxide semiconductor can be reduced. The voltage can be shifted to the positive side, making it possible to realize a switching element with a normally-off characteristic. For example, when an In-Ga-Zn oxide / nitride film is used, at least the oxide A nitrogen concentration higher than that of the semiconductor film 18, specifically, an In-Ga-Zn-based oxynitride having 7 atomic % or more A membrane is used.

[0044] The gate insulating film 17 is made up of a nitride insulating film 17a provided on the gate electrode 15 side and an oxide semiconductor The oxide insulating film 17c is in contact with the conductor film 18. The nitride insulating film 17a has a first surface and a second surface. On the other side, the oxide insulating film 17c and the pair of electrodes 21 are in contact with the gate electrode 15. The oxide insulating film 17c is in contact with the nitride insulating film 17a on one surface and in contact with the nitride insulating film 17b on the other surface. The side surface of the oxide semiconductor film 18 is in contact with the oxide semiconductor film 18. It substantially coincides with the side surface of the insulating film 17c.

[0045] The nitride insulating film 17a is made of silicon nitride, silicon oxynitride, aluminum nitride, or oxynitride. It is formed using aluminum oxide or the like.

[0046] The nitride insulating film 17a may have a single-layer structure or a multilayer structure. The first nitride insulating film has few defects, and the second nitride insulating film has high hydrogen blocking properties. The insulating film and the gate electrode 15 may be laminated in this order from the gate electrode 15 side. By providing a small first nitride insulating film, the dielectric strength of the gate insulating film 17 can be improved. In addition, by providing a second nitride insulating film having high hydrogen blocking properties, The second insulating film 14 is formed on the oxide semiconductor film 18. It is possible to do so.

[0047] Alternatively, the nitride insulating film 17a may be a first nitride insulating film having a high impurity blocking property. a second nitride insulating film having fewer defects, and a third nitride insulating film having high hydrogen blocking properties; However, the gate electrode 15 may be stacked in this order. By providing the first nitride insulating film, which has high insulating properties, impurities from the gate electrode 15, typically Specifically, hydrogen, nitrogen, an alkali metal, an alkaline earth metal, or the like is added to the oxide semiconductor film 18. It can prevent movement.

[0048] The oxide insulating film 17c is made of a material selected from the group consisting of silicon oxide, silicon oxynitride, aluminum oxide, and halogen oxide. It is formed using fluorine, gallium oxide, Ga-Zn based metal oxide, or the like.

[0049] In this embodiment, the gate insulating film 17 is a nitride film in contact with the pair of electrodes 21 and 22. The insulating film 17a and the oxide insulating film 17c are in contact with the oxide semiconductor film 18. Since the oxide semiconductor film 18 is in contact with the gate insulating film 17, the oxide semiconductor film 18 and the gate insulating film 17 The interface state density can be reduced. The nitride insulating film 17a has a function of preventing the pair of electrodes 21 and 22 from being oxidized. Both have the function of preventing the diffusion of the metal elements that constitute the pair of electrodes 21 and 22. The pair of electrodes 21 and 22 contacts the nitride insulating film 17a, so that the resistance of the pair of electrodes 21 and 22 The resistance value is prevented from increasing, and the electrical characteristics of the transistor are prevented from deteriorating due to diffusion of the pair of electrodes 21 and 22. The decline can be prevented.

[0050] The thickness of the gate insulating film 17 is 5 nm or more and 400 nm or less, or 10 nm or more and 300 nm or less. m or less, or from 50 nm to 250 nm.

[0051] The oxide semiconductor film 18 is typically made of In-Ga oxide, In-Zn oxide, In-Mn oxide, or In-Zn oxide. -Zn oxide (M is Ga, Y, Zr, La, Ce, or Nd). The oxide semiconductor film 18 is made of InMO3(ZnO). m (M is Ga, Y, Zr, La, C It is formed using a homologous compound represented by Nd, m being a natural number.

[0052] The oxide semiconductor film 18 is an In-M-Zn oxide (M is Ga, Y, Zr, La, Ce, or In the case of In-M-Zn oxide, the sputtering target used to deposit the In-M-Zn oxide film is The atomic ratio of the metal elements in the dot preferably satisfies In≧M and Zn≧M. The atomic ratio of the metal elements in the sputtering target is In:M:Zn=1:1:1. The atomic ratio of In:M:Zn is preferably 3:1:2. The ratios are calculated by taking the number of atoms of the metal elements contained in the sputtering target as the error. This includes a variation of plus or minus 40% in the ratio.

[0053] When the oxide semiconductor film 18 is an In-M-Zn oxide, the sum of In and M is 1 When the atomic percentage of In and M is 0.00 atomic%, the atomic percentage of In is 25 atomic% or more. Above, M is less than 75 atomic% or In is 34 atomic% or more, M is 66 atomic% Less than omic percent.

[0054] The oxide semiconductor film 18 has an energy gap of 2 eV or more, or 2.5 eV or more, or In this way, the use of oxide semiconductors with a wide energy gap As a result, the off-state current of the transistor 60 can be reduced.

[0055] The thickness of the oxide semiconductor film 18 is 3 nm or more and 200 nm or less, or 3 nm or more and 100 nm or less. m or less, or between 3 nm and 50 nm.

[0056] Note that the oxide semiconductor film 18 is an oxide semiconductor having a low impurity concentration and a small density of defect states. By using a conductive film, it is possible to fabricate a transistor with even better electrical characteristics. Here, it is preferable that the impurity concentration is low and the defect level density is small (there is little oxygen vacancy). This is called high purity authentic or substantially high purity authentic.

[0057] A highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor has a small carrier generation source. Therefore, the carrier density of the oxide semiconductor film can be reduced in some cases. The transistor in which the channel region is formed has electrical characteristics (noise) that make the threshold voltage negative. -Also called Mari-on.) in some cases.

[0058] In addition, a highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor film has a low density of defect states. Since it is small, the trap state density may also be low.

[0059] In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a significantly low off-state current. Very small, with a channel width of 1×10 6 Even if the element has a channel length L of 10 μm, When the voltage between the source and drain electrodes (drain voltage) is in the range of 1V to 10V, The current is below the measurement limit of the semiconductor parameter analyzer, i.e., 1×10 -13 Below A The following characteristics can be obtained.

[0060] Therefore, a transistor in which a channel region is formed in the oxide semiconductor film has poor electrical characteristics. In some cases, the transistor can have small fluctuations and high reliability. Charges trapped in the trap level take a long time to disappear, just like fixed charges. Therefore, the channel is generated in the oxide semiconductor film having a high density of trap states. The electrical characteristics of the transistor in which the hole region is formed may become unstable. can be hydrogen, nitrogen, an alkali metal, or an alkaline earth metal.

[0061] In addition, as the oxide semiconductor film 18, an oxide semiconductor having a structure similar to that of a CAAC oxide film described later is used. Conductive film (hereinafter referred to as CAAC-OS (C Axis Aligned Crystallin) Transistors using . The electrical characteristics do not change much when exposed to visible light or ultraviolet light.

[0062] Hydrogen contained in the oxide semiconductor film reacts with oxygen that is bonded to metal atoms to form water. Oxygen vacancies are formed in the lattice from which oxygen has been removed (or in the portion from which oxygen has been removed). When hydrogen enters the gap, electrons, which act as carriers, can be generated. When it bonds with oxygen, which bonds with metal atoms, it can generate electrons, which act as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen has normally-on characteristics. It is easy to become.

[0063] For this reason, it is preferable that the amount of hydrogen in the oxide semiconductor film 18 be reduced as much as possible. Specifically, the oxide semiconductor film 18 is subjected to secondary ion mass spectrometry (SIMS). The hydrogen concentration obtained by ion mass spectrometry (DIAMS) was 5×10 19 atoms / cm 3 or less, or 1×10 19 atoms / cm 3 The following or 5×10 18 atoms / cm 3 or less, or 1×10 18 atoms / cm 3 below , or 5 × 10 17 atoms / cm 3 or less, or 1×10 16 atoms / cm 3 The following applies.

[0064] When the oxide semiconductor film 18 contains silicon or carbon, which is one of the group 14 elements, As a result, the amount of oxygen vacancies in the oxide semiconductor film 18 increases, and the oxide semiconductor film 18 becomes n-type. The concentration of silicon or carbon in the oxide semiconductor film 18, or the concentration of the oxide film 19 and the oxide semiconductor film Concentration of silicon and carbon near the interface with 18 (concentration obtained by secondary ion mass spectrometry) 2 × 10 18 atoms / cm 3 or less, or 2×10 17 atoms / cm 3 below Let us assume that.

[0065] In addition, in the oxide semiconductor film 18, an alkali metal oxide was obtained by secondary ion mass spectrometry. The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2× 10 16 atoms / cm 3 The following are the oxides of alkali metals and alkaline earth metals. When it bonds with a semiconductor, carriers may be generated, increasing the off-state current of the transistor. For this reason, the alkali metal or alkaline earth metal of the oxide semiconductor film 18 It is preferable to reduce the concentration of the genus.

[0066] In addition, when the oxide semiconductor film 18 contains nitrogen, electrons that serve as carriers are generated. The rear density increases and it becomes easier to make it n-type. As a result, The transistor having the oxide semiconductor film tends to be normally on. It is preferable that the nitrogen content is reduced as much as possible. For example, in the secondary ion mass spectrometry, The resulting nitrogen concentration is 5×10 18 atoms / cm 3 It is preferable to do the following:

[0067] The oxide semiconductor film 18 may have a non-single crystal structure, for example. , CAAC-OS, polycrystalline structure, microcrystalline structure (described later), or amorphous structure. In the crystalline structure, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states. The level density is low.

[0068] Note that the oxide semiconductor film 18 may be divided into an amorphous region, a microcrystalline region, a polycrystalline region, and a polycrystalline region. The film may be a mixed film having two or more of the following regions: a region of a CAAC-OS structure, a region of a single crystal structure, and a region of a crystalline structure. The mixed film may have, for example, an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAA In the case of a single-layer structure having two or more regions of either C-OS region or single crystal structure region, In addition, the mixed film may have, for example, an amorphous structure region, a microcrystalline structure region, and a polycrystalline structure region. A laminated structure having two or more regions of a single crystal structure region, a CAAC-OS region, or a single crystal structure region. It may have a structure.

[0069] The oxide film 19 is typically made of In-Ga oxide, In-Zn oxide, In-M-Zn An oxide (M is Ga, Y, Zr, La, Ce, or Nd) and an oxide semiconductor film The energy of the bottom of the conduction band is closer to the vacuum level than that of the oxide film 18. The difference between the energy of the conduction band minimum and the energy of the conduction band minimum of the oxide semiconductor film 18 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. That is, oxide The difference between the electron affinity of the film 19 and the electron affinity of the oxide semiconductor film 18 is 0.05 eV or more; 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less.

[0070] The oxide film 19 is an In-M-Zn oxide (M is Ga, Y, Zr, La, Ce, or N In the case of d), the sputtering target used to deposit the In-M-Zn oxide film The atomic ratio of the metal elements preferably satisfies M>In, Zn>0.5×M, and more preferably Zn≧M. The atomic ratio of the metal elements in such a sputtering target is preferably In:Ga. :Zn=1:3:2, In:Ga:Zn=1:3:3, In:Ga:Zn=1:3:4, In:Ga:Zn=1:3:5, In:Ga:Zn=1:3:6, In:Ga:Zn=1 :3:7, In:Ga:Zn=1:3:8, In:Ga:Zn=1:3:9, In:Ga :Zn=1:3:10, In:Ga:Zn=1:4:3, In:Ga:Zn=1:4:4 , In:Ga:Zn=1:4:5, In:Ga:Zn=1:4:6, In:Ga:Zn= 1:4:7, In:Ga:Zn=1:4:8, In:Ga:Zn=1:4:9, In:G a:Zn=1:4:10, In:Ga:Zn=1:5:3, In:Ga:Zn=1:5: 4, In:Ga:Zn=1:5:5, In:Ga:Zn=1:5:6, In:Ga:Zn =1:5:7, In:Ga:Zn=1:5:8, In:Ga:Zn=1:5:9, In: Ga:Zn=1:5:10, In:Ga:Zn=1:6:4, In:Ga:Zn=1:6 :5, In:Ga:Zn=1:6:6, In:Ga:Zn=1:6:7, In:Ga:Z n=1:6:8, In:Ga:Zn=1:6:9, In:Ga:Zn=1:6:10 are preferred. The metal of the sputtering target used for forming the In-M-Zn oxide film is By setting the atomic ratio of elements to M>In and Zn≧M, a CAAC oxide film can be formed. In addition, the oxide film 19 formed using the sputtering target may contain The atomic ratio of the metal elements contained in the sputtering target is calculated based on the error. This includes a variation of ±40% in the atomic ratio of the metallic elements.

[0071] The oxide film 19 is characterized in that it is formed using a CAAC oxide film.

[0072] The CAAC oxide film is one of the oxide semiconductor films having multiple crystal parts. The crystals in the AC oxide film have a c-axis orientation. (Transmission Electron Microscope) image The area of ​​the crystal part in the CAAC oxide film is 2500 nm 2 or more than 5μm 2 End , or 1000 μm 2 In addition, in the cross-sectional TEM image, the crystal portion was found to be 50% or more. If the CAAC oxide film has 80% or more, or 95% or more, the film is close to being single crystal. It becomes a thin film with physical properties.

[0073] When the CAAC oxide film is observed by TEM, clear boundaries between the crystal parts, i.e., the crystal grains, are clearly visible. Therefore, it is not possible to confirm the grain boundary. It can be said that the oxide film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0074] The CAAC oxide film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). When the metal atoms are observed, it can be confirmed that they are arranged in layers in the crystal part. Each layer of the element is formed on the surface on which the CAAC oxide film is to be formed (also called the surface on which the film is to be formed) or on the concave surface of the upper surface. The shape reflects the convexity and is aligned parallel to the surface on which the CAAC oxide film is formed or the top surface. In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. " refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This also includes cases where the angle is between 85° and 95°.

[0075] On the other hand, the CAAC oxide film was observed by TEM from a direction roughly perpendicular to the sample surface (plane T EM observation reveals that metal atoms are arranged in triangular or hexagonal shapes in the crystals. However, no regularity was observed in the arrangement of metal atoms between different crystal regions. do not have.

[0076] In addition, when electron beam diffraction is performed on the CAAC oxide film, spots (bright spots) that indicate orientation are observed. is observed.

[0077] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC oxide film had an orientation. It can be seen that...

[0078] X-ray diffraction (XRD) of CAAC oxide film When the structure was analyzed using the device, the out-of-plane method of the CAAC oxide film In the analysis, a peak may appear at a diffraction angle (2θ) of around 31°. This peak is I Since it belongs to the (00x) plane (x is an integer) of the crystal of nGaZn oxide, The crystals of the nitride film have a c-axis orientation, and the c-axis is oriented in a direction approximately perpendicular to the surface on which the film is formed or the upper surface. It can be confirmed that there is.

[0079] On the other hand, in-p X-rays are incident on the CAAC oxide film from a direction roughly perpendicular to the c-axis. In the lane method, a peak may appear at 2θ around 56°. This is attributed to the (110) plane of the InGaZn oxide crystal. In the case of a crystalline oxide semiconductor film, 2θ is fixed at about 56°, and the normal vector of the sample surface is aligned along the axis (φ When the sample is rotated around the (φ) axis while analyzing (φ scan), the results show that the bonds are equivalent to the (110) plane. In contrast, in the case of the CAAC oxide film, 2 Even when θ is fixed at around 56° and φ is scanned, no clear peak appears.

[0080] From the above, it is concluded that the orientation of the a-axis and b-axis is uniform between different crystal parts in the CAAC oxide film. Although it is irregular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which it is formed or the upper surface. Therefore, the layered structure confirmed by the cross-sectional TEM observation mentioned above is consistent with the Each layer of arranged metal atoms is in a plane parallel to the ab plane of the crystal.

[0081] The crystals are formed when the CAAC oxide film is formed or after a crystallization process such as heat treatment. As described above, the c-axis of the crystal part is aligned with the surface on which the CAAC oxide film is formed. Or, the orientation is parallel to the normal vector of the upper surface. When the shape of the crystal is changed by etching, the c-axis of the crystal is aligned with the CAAC oxide film. It may not be parallel to the normal vector of the forming surface or the top surface.

[0082] In addition, the crystallinity in the CAAC oxide film does not have to be uniform. When the crystalline part of the film is formed by crystal growth from near the top surface of the CAAC oxide film, The area near the surface may have a higher crystallinity than the area near the surface on which it is formed. When impurities are added to an AC oxide film, the crystallinity of the region to which the impurities are added changes, resulting in a In some cases, regions of differing crystallinity may be formed.

[0083] In addition, in the out-of-plane analysis of the CAAC oxide film, 2θ was 31° In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks near the c-axis indicate that some of the CAAC oxide films contain crystals that do not have the c-axis orientation. The CAAC oxide film shows a peak at 2θ of about 31° and a peak at 2θ of about 36°. It is preferable that there are no adjacent peaks.

[0084] The oxide film 19 is a film having no crystal grain boundaries, a c-axis orientation, and a c-axis aligned with the surface on which it is formed. is formed using a CAAC oxide film oriented parallel to the normal vector of the upper surface. The oxide film 19 is made of a metal element such as copper or aluminum that constitutes the pair of electrodes 21 and 22. , gold, silver, molybdenum, etc., and functions as a film that prevents the migration of the The metal elements constituting the multilayer film 2 are less likely to migrate to the oxide semiconductor film 18. In addition, the impurities contained in the oxide semiconductor film 18 can be reduced. It is possible to fabricate a transistor having such a structure.

[0085] As the oxide film 19, Ga, Y, Zr, La, Ce, or Nd is added with a higher atomic number than In. The ratio of the oxide film 19 to the oxide film 20 may have the following effects: (2) To reduce the electron affinity of the oxide film 19. (3) To reduce the electron affinity of the oxide film 19 from the outside. (4) The insulating property is higher than that of the oxide semiconductor film 18. In addition, Ga, Y, Zr, La, Ce, and Nd are metal elements that have strong bonding strength with oxygen. Therefore, by having Ga, Y, Zr, La, Ce, or Nd in a higher atomic ratio than In, , oxygen deficiency is less likely to occur.

[0086] When the oxide film 19 is an In-M-Zn oxide film, the sum of In and M is 100 atom. When the atomic percentage of In and M is 50 atomic %, the atomic percentage of In is less than 50 atomic % and that of M is less than 50 atomic %. 0 atomic% or more, or In is less than 25 atomic%, and M is 75 atomic% That is all.

[0087] The oxide semiconductor film 18 and the oxide film 19 are In-M-Zn oxide films (M is Ga , Y, Zr, La, Ce, or Nd), compared with the oxide semiconductor film 18, The atomic ratio of M (Ga, Y, Zr, La, Ce, or Nd) contained in the film 19 is large, Typically, the amount of the atoms contained in the oxide semiconductor film 18 is 1.5 times or more. The atomic ratio is more than two or three times higher.

[0088] The oxide semiconductor film 18 and the oxide film 19 are In-M-Zn oxide films (M is Ga , Y, Zr, La, Ce, or Nd), the oxide film 19 is In:M:Zn=x1: y1:z1 [atomic ratio], and the oxide semiconductor film 18 is In:M:Zn=x2:y2:z2 [atomic ratio]. If y1 / x1 is greater than y2 / x2, or y1 / x1 is greater than y2 / x2 is 1.5 times larger than y1 / x1. Or, y1 / x1 is 2 times larger than y2 / x2. Or, y1 / x1 is three times or more larger than y2 / x2. When y2 is equal to or larger than x2, a transistor including the oxide semiconductor film can be stably formed. This is preferable because it can impart electrical properties.

[0089] The oxide semiconductor film 18 and the oxide film 19 are formed of an oxide semiconductor film having a low carrier density and For example, the oxide semiconductor film 18 and the oxide film 19 have a carrier density is 1×10 17 pieces / cm 3 or less, or 1×10 15 pieces / cm 3 or less, or 1×10 1 3 pieces / cm 3 or less, or 1×10 11 pieces / cm 3 The following oxide semiconductor films and oxide films Use.

[0090] In addition, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use a material with an appropriate composition according to the required properties (e.g., the resultant mobility, threshold voltage, etc.). In order to obtain semiconductor characteristics of a transistor, the carrier density and impurity of the oxide semiconductor film 18 are controlled. By appropriately adjusting the concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. is preferred.

[0091] The oxide film 19 is formed on the oxide semiconductor film 18 when the oxide insulating film 24 is formed later. It also functions as a membrane to mitigate damage to the skin.

[0092] The thickness of the oxide film 19 is 3 nm or more and 100 nm or less, or 3 nm or more and 50 nm or less. do.

[0093] In the transistor 60 described in this embodiment, the oxide film 19 is a CAAC oxide film. Therefore, the oxide film 19 can reduce the diffusion of impurities from the outside. The amount of impurities that migrate from the pair of electrodes 21 and 22 to the oxide semiconductor film 18 can be reduced. For this reason, a pair of electrodes 2 is made of copper, aluminum, gold, silver, or molybdenum. Even if the pair of electrodes 21 and 22 are formed, the oxide film 19 is in contact with the pair of electrodes 21 and 22. Even if the film is made of low resistance materials such as copper, aluminum, gold, silver, molybdenum, etc. The pair of electrodes 21 and 22 are made of copper, aluminum, gold, silver, or molybdenum, and the oxide film 19 As a result, the threshold voltage of the transistor is Fluctuations can be reduced.

[0094] In addition, the oxide film 19 is provided between the oxide semiconductor film 18 and the oxide insulating film 23. Therefore, between the oxide film 19 and the oxide insulating film 23, a transition due to impurities and defects occurs. Even if a trap level is formed, there is no gap between the trap level and the oxide semiconductor film 18. As a result, electrons flowing through the oxide semiconductor film 18 are less likely to be captured by the trap states. It is possible to increase the on-current of the transistor and also to increase the field effect mobility. In addition, when an electron is captured in the trap level, the electron becomes a negative fixed charge. As a result, the threshold voltage of the transistor varies. Since there is a gap between the oxide semiconductor film 18 and the trap states, It is possible to reduce electron trapping, and thus the variation in threshold voltage can be reduced.

[0095] Moreover, the oxide film 19 is less likely to develop oxygen vacancies.

[0096] For these reasons, the impurity concentration and the amount of oxygen vacancies in the oxide semiconductor film 18 can be reduced. is possible.

[0097] In the transistor 60 shown in this embodiment, a A pair of electrodes 21, 22 are formed.

[0098] The pair of electrodes 21 and 22 are made of a low resistance material such as copper, aluminum, gold, silver, or molybdenum. A single metal, or a compound or alloy that has this as its main component, is used in a single-layer structure or a laminate structure. For example, a single layer structure of aluminum film containing silicon, a single layer structure of copper film, a single layer structure of gold A single-layer structure of the film, a two-layer structure of a titanium film laminated on an aluminum film, a copper-magnesium-aluminum film There are two-layer structures, such as a copper film, a silver film, or a gold film laminated on an aluminum alloy film. When the pair of electrodes 21 and 22 has a laminated structure, the film in contact with the oxide film 19 is made of copper, aluminum, or gold. It is formed using a low resistance material such as silver or molybdenum.

[0099] The pair of electrodes 21 and 22 are made of a low resistance material such as copper, aluminum, gold, silver, or molybdenum. By forming the wiring in this way, it is possible to manufacture a semiconductor device with reduced wiring delay using a large-area substrate. In addition, a semiconductor device with reduced power consumption can be manufactured.

[0100] The oxide insulating film 23 is an oxygen-permeable oxide insulating film. As a film for reducing damage to the multilayer film 20 when forming the oxide insulating film 24 to be formed later. also works.

[0101] The oxide insulating film 23 has a thickness of 5 nm or more and 150 nm or less, or 5 nm or more and 50 A silicon oxide film, a silicon oxynitride film, or the like having a thickness of 0.1 nm or less can be used. In the present specification, a silicon oxynitride film is a film having a composition in which oxygen is more abundant than nitrogen. The term silicon nitride oxide refers to a film that contains more nitrogen than oxygen. Refers to the membrane.

[0102] In addition, it is preferable that the oxide insulating film 23 has a small amount of defects. Therefore, the spin of the signal at g=2.001 originating from the silicon dangling bond Density is 3×10 17 spins / cm 3 This is because the oxide insulation If the film 23 contains a large number of defects, oxygen will be bonded to the defects, and the oxide insulating film 2 This is because the amount of oxygen permeating through 3 decreases.

[0103] In addition, it is preferable that the number of defects at the interface between the oxide insulating film 23 and the multilayer film 20 is small. Typically, the signal at g=1.93 originating from defects in the multilayer film 20 is detected by ESR measurement. The spin density of the number is 1×10 17 spins / cm 3 or below the detection limit. is preferred.

[0104] Note that in the oxide insulating film 23, all of the oxygen that has entered the oxide insulating film 23 from the outside is Some oxygen does not move outside the oxide insulating film 23 and remains in the oxide insulating film 23. As oxygen enters the oxide insulating film 23, the oxygen contained in the oxide insulating film 23 In some cases, oxygen may move in the oxide insulating film 23 due to the movement of oxygen to the outside.

[0105] When an oxide insulating film that transmits oxygen is formed as the oxide insulating film 23, the oxide insulating film 23 The oxide insulating film 23 is formed on the upper surface of the oxide insulating film 24. The oxide insulating film 23 is formed on the upper surface of the oxide insulating film 23. The semiconductor film 18 can be made to move the

[0106] An oxide insulating film 24 is formed so as to be in contact with the oxide insulating film 23. 4 is formed using an oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition. The oxide insulating film containing more oxygen than the stoichiometric composition is heated to remove the oxygen. A part of the element is released. The oxide insulating film contains more oxygen than the oxygen that satisfies the stoichiometric composition. In TDS analysis, the amount of oxygen released was 1.0 x 10 18 atoms / cm 3 or more than 3.0×10 20 atoms / cm 3 The oxide insulating film is as described above. do.

[0107] The oxide insulating film 24 has a thickness of 30 nm to 500 nm, or 50 nm or more. A silicon oxide film, a silicon oxynitride film, or the like having a thickness of 400 nm or less can be used.

[0108] In addition, it is preferable that the oxide insulating film 24 has a small amount of defects. Therefore, the spin of the signal at g=2.001 originating from the silicon dangling bond Density is 1.5×10 18 spins / cm 3 Less than or even 1×10 18 spins / cm 3 Note that the oxide insulating film 24 has a thickness smaller than that of the oxide insulating film 23. Since it is separated from the multilayer film 20 , it is acceptable for the defect density to be higher than that of the oxide insulating film 23 .

[0109] Further, oxygen, hydrogen, water, an alkali metal, an alkaline earth metal, etc. are deposited on the oxide insulating film 24. By providing the nitride insulating film 25 having the blocking effect, the oxygen from the multilayer film 20 can be prevented. It is possible to prevent diffusion to the outside and the intrusion of hydrogen, water, etc. into the multilayer film 20 from the outside. The insulating film may be silicon nitride, silicon oxynitride, aluminum nitride, or aluminum oxynitride. In addition, oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. Instead of a nitride insulating film having a blocking effect, a material having a blocking effect against oxygen, hydrogen, water, etc. is used. An oxide insulating film having a blocking effect against oxygen, hydrogen, water, etc. may be provided. The insulating film is made of aluminum oxide, aluminum oxynitride, gallium oxide, or gallium oxynitride. Hafnium, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride etc.

[0110] Next, a manufacturing method of the transistor 60 shown in FIG. 1 will be described with reference to FIG.

[0111] As shown in FIG. 2A, a gate electrode 15 is formed on a substrate 11. The nitride insulating film 17a and the oxide insulating film 17b are formed.

[0112] Here, a glass substrate is used as the substrate 11.

[0113] The method of forming the gate electrode 15 will be described below. First, the sputtering method, the CVD method, and the evaporation method are used. A conductive film is formed by deposition or the like, and a mask is formed on the conductive film by a photolithography process. Next, a part of the conductive film is etched using the mask to form the gate electrode 15. After this, the mask is removed.

[0114] The gate electrode 15 may be formed by electrolytic plating, printing, ink jet printing, or the like instead of the above-mentioned method. It may be formed by a jet method or the like.

[0115] Here, a tungsten film having a thickness of 100 nm is formed by sputtering. A mask is formed by a photolithography process, and a tungsten film is formed using the mask. The gate electrode 15 is formed by dry etching.

[0116] The nitride insulating film 17a and the oxide insulating film 17b are formed by a sputtering method, a CVD method, or a vapor deposition method. etc. are formed.

[0117] When a silicon nitride film or a silicon nitride oxide film is formed as the nitride insulating film 17a, The source gas is a deposition gas containing silicon, and nitrogen or / and ammonia. Representative examples of deposition gases containing silicon include silane, disilane, trisilane, and tetrasilane. Silane, fluorinated silane, etc.

[0118] When a silicon oxide film or a silicon oxynitride film is formed as the oxide insulating film 17b, As the source gas, it is preferable to use a deposition gas containing silicon and an oxidizing gas. Oxidizing gases include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

[0119] In addition, when a gallium oxide film is formed as the oxide insulating film 17b, MOCVD (Me Al Organic Chemical Vapor Deposition (ACVD) method It can be formed by

[0120] Next, as shown in FIG. 2B, an oxide semiconductor film 18 and an oxide A film 19 is formed.

[0121] The method for forming the oxide semiconductor film 18 and the oxide film 19 will be described below. An oxide semiconductor film to be an oxide semiconductor film 18 and an oxide film 19 are formed over the insulating film 17. Next, a mask is applied to the oxide film by a photolithography process. After the formation of the oxide semiconductor film, the oxide film is partially etched using the mask. By this, an oxide semiconductor film 18 having element isolation and an oxide semiconductor film 19 having element isolation as shown in FIG. A multilayer film 20 having a material film 19 is formed. After that, the mask is removed.

[0122] The oxide semiconductor film that becomes the oxide semiconductor film 18 and the oxide film that becomes the oxide film 19 are formed by sputtering. The shaping method is performed using the tartering method, coating method, pulsed laser deposition method, laser ablation method, etc. It can be achieved.

[0123] When the oxide semiconductor film and the oxide film are formed by a sputtering method, plasma is generated. The power supply for the operation of the device should be an RF power supply, an AC power supply, a DC power supply, etc. can be done.

[0124] The sputtering gas is a rare gas (typically argon), oxygen gas, or a mixture of a rare gas and oxygen. A mixed gas is used as appropriate. In the case of a mixed gas of rare gas and oxygen, the ratio of oxygen to rare gas is It is preferable to increase the gas ratio.

[0125] The target is appropriately selected depending on the composition of the oxide semiconductor film and the oxide film to be formed. You just need to choose.

[0126] Note that the oxide semiconductor film to be the oxide semiconductor film 18 and the oxide film to be the oxide film 19 are When the CAAC-OS film and CAAC oxide film were used, respectively, the c-axis oriented multilayer structure was observed. It is preferable to use a target having a crystalline metal oxide. The oxide-containing target is cleaved by the sputtering particles in a plane parallel to the sputtering surface. When the sputtering particles collide with the target, the cleavage plane and the atomic The weak bonds between the particles are broken, and part of the target becomes a flat particle. The plate-like particles are deposited on the surface to be formed, and the CAAC-OS film and C AAC oxide film can be formed. Note that the cleavage plane of the tabular grains is the ab plane. It may be a hexagonal prism whose cleavage plane is a plane parallel to the ab plane, or a triangular prism whose cleavage plane is a plane parallel to the ab plane. stomach.

[0127] In addition, the oxide semiconductor film to be the oxide semiconductor film 18 and the oxide film to be the oxide film 19 are In the case of In-M-Zn oxide, the atomic ratio of the metal elements in the sputtering target is Zn≧ By heating at 200°C to 500°C, hexagonal ZnO In the ab plane, Zn atoms and O atoms are bonded in a hexagonal shape and aligned along the c axis. Therefore, the ZnO was used as a seed crystal, and the plate-like particles were deposited in alignment with the ZnO orientation. In the planar TEM image, the area is 2500 nm 2 or more than 5μm 2 More than or equal to 10 00μm 2 The CAAC-OS film and the CAAC oxide film having the above crystal parts are formed. It is possible.

[0128] The oxide semiconductor film and the oxide film are not simply stacked, but are bonded in a continuous manner (particularly in this embodiment). The structure is such that the energy of the bottom of the conduction band changes continuously between each film. That is, defect levels such as trap centers and recombination centers are formed at the interfaces of each film. The stacked structure is such that no impurities such as the above are present. When impurities are present between the oxide films, the continuity of the energy bands is lost and the oxides are generated at the interface. The carriers are trapped or recombine and disappear.

[0129] To form continuous junctions, a multi-chamber deposition system equipped with a load lock chamber is required. Each film is laminated in succession using a sputtering device without exposing it to the air. Each chamber in the sputtering apparatus is required for the oxide semiconductor film. In order to remove impurities such as water as much as possible, an adsorption type vacuum pump such as a cryopump is used. High vacuum pump (5×10 -7 Pa~1×10 -4 It is preferable to use a temperature of up to about 10 Pa. Alternatively, a turbo molecular pump and cold trap can be combined to separate the chamber from the exhaust system. It is preferable to prevent the backflow of gases into the bar, especially gases containing carbon or hydrogen. stomach.

[0130] In order to obtain a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor film, Not only is it necessary to evacuate the inside of the chamber to a high vacuum, but it is also necessary to highly purify the sputtering gas. The oxygen and argon gases used for this purpose must have a dew point of -40°C or less, or -80°C or less. By using gas highly purified to below -100℃ or below -120℃, This makes it possible to prevent moisture and the like from being taken into the semiconductor film as much as possible.

[0131] Here, an In-Ga-Zn oxide target (In:Ga:Zn=1:1:1) was used. A 35-nm-thick In-Ga-Zn oxide film was deposited as an oxide semiconductor film by sputtering. After the oxide film was formed, an In-Ga-Zn oxide target (In:Ga:Zn=1:3: 4) was used for the sputtering method to deposit a 20 nm thick In-Ga-Zn oxide film. Next, a mask is formed over the oxide film, and the oxide semiconductor film and the oxide film are The oxide semiconductor film 18 and the oxide film 19 are formed by selectively etching each of the oxide semiconductor film 18 and the oxide film 19. A multilayer film 20 having the above structure is formed.

[0132] After that, first heat treatment is performed. The amounts of hydrogen and water contained in the oxide semiconductor film 18 are reduced by desorbing hydrogen, water, and the like contained in the oxide semiconductor film 18. The temperature of the heat treatment is typically 300° C. or higher and 400° C. or lower, or The temperature must be between 20℃ and 370℃.

[0133] The first heat treatment can be performed using an electric furnace, an RTA device, or the like. This allows the heat treatment to be performed at a temperature equal to or higher than the distortion point of the substrate for a short period of time. The heat treatment time can be shortened.

[0134] The first heat treatment is performed using nitrogen, oxygen, or ultra-dry air (water content 20 ppm or less, or 1 ppm or less, or 10 ppb or less of air), or rare gases (argon, helium, etc.) The above-mentioned nitrogen, oxygen, ultra-dry air, or rare gas, hydrogen, water, etc. may be added to the atmosphere. It is preferable that the heat treatment is performed in a nitrogen or rare gas atmosphere, and that the heat treatment is performed in a nitrogen or rare gas atmosphere. As a result, hydrogen contained in the oxide semiconductor film is removed. Water and the like can be desorbed and oxygen can be supplied to the oxide semiconductor film. The amount of oxygen vacancies in the oxide semiconductor film can be reduced.

[0135] Next, as shown in FIG. 2C, a part of the oxide insulating film 17b is etched to remove the oxide Through the above steps, the nitride insulating film 17a and the oxide insulating film 17 The gate insulating film 17 having the multilayer film 20 can be formed by the multilayer film 20 as a mask. The oxide insulating film 17b is then etched to form a separated oxide insulating film 17c. Alternatively, a multi-layer structure can be formed by using a mask obtained by a photolithography process. After the film 20 is formed, the oxide insulating film 17b is etched using the mask without performing a heat treatment. By this, an isolated oxide insulating film 17c is formed, and even if a heat treatment is further performed, As a result, the isolated oxide insulating film 17 can be formed without increasing the number of photomasks. In addition, a part of the nitride insulating film 17a can be exposed. .

[0136] Next, as shown in FIG. 2(D), a pair of electrodes 21 and 22 are formed.

[0137] The method for forming the pair of electrodes 21 and 22 will be described below. First, the sputtering method and the CVD method are used. Next, a conductive film is formed on the conductive film by a photolithography process. Next, the conductive film is etched using the mask to form a pair of electrodes 21 and 2 2 is formed. After this, the mask is removed.

[0138] Here, a copper film having a thickness of 400 nm is formed by sputtering. A mask is formed by a photolithography process, and the copper film is dry etched using the mask. A pair of electrodes 21 and 22 are formed by etching.

[0139] In this embodiment, the pair of electrodes 21 and 22 are formed in the gate insulating film 17 mainly by a nitride insulating material. The nitride insulating film 17c is in contact with the oxide insulating film 17a, and the contact area with the oxide insulating film 17c is extremely small. The film 17a has a function of preventing oxidation and diffusion of the metal elements constituting the pair of electrodes 21 and 22. Therefore, the pair of electrodes 21 and 22 contacts the nitride insulating film 17a of the gate insulating film 17. This makes it possible to prevent the oxidation and diffusion of the metal elements constituting the pair of electrodes 21 and 22. .

[0140] Next, as shown in FIG. 2(E), an oxide insulating layer is formed on the multilayer film 20 and the pair of electrodes 21 and 22. An insulating film 23 is formed. Next, an oxide insulating film 24 is formed on the oxide insulating film 23.

[0141] After the oxide insulating film 23 is formed, the oxide insulating film 2 is successively removed without being exposed to the air. After the oxide insulating film 23 is formed, the source gas The oxide insulating film 24 is continuously formed by adjusting one or more of the flow rate, pressure, high frequency power, and substrate temperature. By forming the oxide insulating film 23 and the oxide insulating film 24 in In addition, the impurity concentration in the oxide insulating film 24 can be reduced. The amount of oxygen vacancies in the oxide semiconductor film 18 can be reduced. It is possible.

[0142] The oxide insulating film 23 is made of a silicon oxide film placed in a vacuum-evacuated processing chamber of a plasma CVD apparatus. The substrate is kept at a temperature of 180°C to 400°C or 200°C to 370°C. The raw material gas is introduced into the processing chamber to keep the pressure in the processing chamber at 20 Pa or more and 250 Pa or less, or 10 The pressure is between 0 Pa and 250 Pa, and high-frequency power is supplied to the electrode installed in the processing chamber. As a result, a silicon oxide film or a silicon oxynitride film is formed as the oxide insulating film 23. This can be done.

[0143] As the source gas for the oxide insulating film 23, a deposition gas containing silicon and an oxidizing gas are used. Representative examples of deposition gases containing silicon include silane, disilane, Examples of oxidizing gases include oxygen, ozone, and nitrous oxide. , nitrogen dioxide, etc.

[0144] By using the above conditions, an oxide insulating film that transmits oxygen is formed as the oxide insulating film 23. In addition, by providing the oxide film 19 and the oxide insulating film 23, In the process of forming the oxide insulating film 24, damage to the oxide semiconductor film 18 can be reduced. It is.

[0145] The oxide insulating film 23 is placed in a vacuum evacuated processing chamber of a plasma CVD apparatus. The substrate is kept at 300°C or higher and 400°C or lower, or at 320°C or higher and 370°C or lower, and the processing chamber is The raw material gas is introduced into the processing chamber to set the pressure in the processing chamber to 100 Pa or more and 250 Pa or less. Depending on the conditions for supplying high frequency power to the electrodes provided in the chamber, oxide insulating film 23 is formed of oxide. A silicon nitride film or a silicon oxynitride film can be formed.

[0146] Under the film formation conditions, the substrate temperature is set to 300°C or higher and 400°C or lower, or 320°C or higher and 3 By keeping the temperature below 70℃, the bonding strength between silicon and oxygen becomes stronger. As a result, oxide insulation The film 23 is an oxide insulating film that is oxygen permeable, dense, and hard. The etching rate in 0.5% by weight hydrofluoric acid is 10 nm / min or less, or 8 It is possible to form a silicon oxide film or a silicon oxynitride film having a viscosity of 100 nm / min or less.

[0147] In addition, in this process, the oxide insulating film 23 is formed while heating. In this manner, hydrogen, water, and the like contained in the oxide semiconductor film 18 can be released. The hydrogen contained in the conductive film 18 combines with the oxygen radicals generated in the plasma to become water. Since the substrate is heated during the process of forming the oxide insulating film 23, oxygen and hydrogen are bonded to each other. The water generated by the plasma CVD method is desorbed from the oxide semiconductor film. By forming the insulating film 23, the content of water and hydrogen in the oxide semiconductor film is reduced. It is possible.

[0148] Furthermore, by setting the pressure in the treatment chamber to 100 Pa or more and 250 Pa or less, the oxide insulating film The water content in the 23 is reduced, which reduces the variation in the electrical characteristics of the transistor 60. In addition, the pressure in the processing chamber can be reduced by 100 ps. By setting the pressure to 00 Pa or more and 250 Pa or less, the oxide insulating film 23 is formed. It is possible to reduce damage to the multilayer film 20 including the conductor film 18, and the oxide semiconductor film In particular, the amount of oxygen vacancies in the oxide insulating film 23 or the oxide insulating film 18 can be reduced. The deposition temperature of the oxide insulating film 24 is increased, typically to a temperature higher than 220° C. As a result, part of oxygen contained in the oxide semiconductor film 18 is released, and oxygen vacancies are easily formed. In order to improve the reliability of the transistor, the oxide insulating film 24 to be formed later is formed to have a defect-free structure. By using film formation conditions for reducing the amount of oxygen desorbed, the amount of oxygen desorbed is easily reduced. However, it may be difficult to reduce the amount of oxygen vacancies in the oxide semiconductor film 18. The pressure in the chamber is set to 100 Pa or more and 250 Pa or less, and the oxidation during the formation of the oxide insulating film 23 is By reducing damage to the semiconductor film 18, oxygen desorption from the oxide insulating film 24 is reduced. The amount of oxygen vacancies in the oxide semiconductor film 18 can be reduced by using only a small amount of oxygen.

[0149] In addition, by increasing the amount of oxidizing gas to 100 times or more the amount of deposition gas containing silicon, The hydrogen content in the oxide insulating film 23 can be reduced. Since the amount of hydrogen mixed into the semiconductor film 18 can be reduced, the threshold voltage of the transistor can be reduced. The shift can be suppressed.

[0150] Here, the oxide insulating film 23 is made of silane at a flow rate of 30 sccm and 4000 sccm. The source gas was nitrous oxide with a flow rate of 1.0 cm, the pressure in the processing chamber was 200 Pa, and the substrate temperature was 220°C. A 27.12MHz high-frequency power source was used to supply 150W of high-frequency power to the parallel plate electrodes. A silicon oxynitride film with a thickness of 50 nm is formed by the plasma CVD method under the following conditions. In this manner, a silicon oxynitride film through which oxygen can pass can be formed. In this embodiment, the oxide insulating film 23 is formed using a high frequency power source of 27.12 MHz. However, the present invention is not limited to this, and may be implemented, for example, by using a high frequency power source of 13.56 MHz. An oxide insulating film 23 may be formed.

[0151] The oxide insulating film 24 is placed in a vacuum-evacuated processing chamber of a plasma CVD apparatus. The substrate is kept at a temperature of 180°C to 280°C or 200°C to 240°C. The raw material gas is introduced into the processing chamber to keep the pressure in the processing chamber at 100 Pa or more and 250 Pa or less, or 00 Pa to 200 Pa, and 0.17 W / cm2 to the electrode installed in the treatment chamber 2 End 0.5W / cm 2 or less than 0.25W / cm 2 More than 0.35W / cm 2 High frequency below Depending on the conditions of power supply, a silicon oxide film or a silicon oxynitride film is formed.

[0152] As the source gas of the oxide insulating film 24, a deposition gas containing silicon and an oxidizing gas are used. Representative examples of deposition gases containing silicon include silane, disilane, Examples of oxidizing gases include trisilane, fluorinated silane, etc. Examples of oxidizing gases include oxygen, ozone, and nitrous oxide. , nitrogen dioxide, etc.

[0153] The oxide insulating film 24 is formed under the conditions of high frequency irradiation with the above power density in a processing chamber at the above pressure. Supplying microwave power increases the efficiency of decomposing the source gas in the plasma, and oxygen radicals are increased. As the source gas is added, the oxidation of the source gas proceeds, so that the oxygen content in the oxide insulating film 24 becomes stoichiometric. On the other hand, in the film formed at the substrate temperature, the composition of silicon and oxygen is Since the bonding strength is weak, some of the oxygen in the film is released by the heat treatment in the subsequent process. It contains more oxygen than the stoichiometric composition, and some of the oxygen is released by heating. In addition, an oxide insulating film 23 is provided on the multilayer film 20. Therefore, in the process of forming the oxide insulating film 24, the oxide insulating film 23 is formed in a multilayer structure. The oxide film 19 serves as a protective film for the oxide semiconductor film 18. As a result, it is possible to reduce damage to the oxide semiconductor film 18 while using high-frequency power with high power density. The oxide insulating film 24 can be formed using the above.

[0154] In addition, in the deposition conditions of the oxide insulating film 24, the deposition gas containing silicon is By increasing the flow rate of the reactive gas, it is possible to reduce the number of defects in the oxide insulating film 24. Typically, ESR measurements reveal that the g value is 2.0 due to the dangling bonds of silicon. The spin density of the signal appearing in 01 is 6×10 17 spins / cm 3 Less than or equal to 3×10 17 spins / cm 3 or less, or 1.5×10 17 spins / cm 3 The following is a missing It is possible to form an oxide insulating film with few pits. As a result, the reliability of the transistor is improved. It can be done.

[0155] Here, the oxide insulating film 24 is made of silane at a flow rate of 200 sccm and SiO at a flow rate of 4000 s. The source gas was nitrous oxide (N2O) at 1.0 ccm, the pressure in the processing chamber was 200 Pa, and the substrate temperature was 220° C. A 27.12MHz high-frequency power source was used to apply 1500W of high-frequency power to the parallel plate electrodes. A silicon oxynitride film with a thickness of 400 nm is formed by the supplied plasma CVD method. The plasma CVD device has an electrode area of ​​6000 cm 2 Parallel plate plasma CVD The power supplied to the device is converted to power per unit area (power density) of 0.25W. / cm 2In this embodiment, a high frequency power source of 27.12 MHz is used. However, the present invention is not limited to this method, and may be applied to, for example, The oxide insulating film 24 may be formed using a high frequency power source of 0.56 MHz.

[0156] Next, a second heat treatment is performed. The temperature of the heat treatment is typically 150° C. or higher and 300° C. or lower. ℃ or lower, or 200℃ to 250℃.

[0157] The heat treatment can be performed using an electric furnace, an RTA device, or the like. Therefore, heat treatment can be performed at a temperature above the distortion point of the substrate for a short period of time. The processing time can be reduced.

[0158] Heat treatment is carried out in nitrogen, oxygen, or ultra-dry air (water content less than 20 ppm, or less than 1 ppm) or less than 10 ppb of air), or an atmosphere of rare gas (argon, helium, etc.) In addition, if the nitrogen, oxygen, ultra-dry air, or rare gas contains hydrogen, water, etc. It is preferable that this not be the case.

[0159] By the heat treatment, part of oxygen contained in the oxide insulating film 24 is transferred to the oxide semiconductor film 18. By this, the amount of oxygen vacancies in the oxide semiconductor film 18 can be reduced.

[0160] In the case where the oxide insulating film 23 and the oxide insulating film 24 contain water, hydrogen, or the like, Then, a nitride insulating film 25 having a blocking function is formed and a heat treatment is performed. Water, hydrogen, and the like contained in the oxide insulating film 23 and the oxide insulating film 24 are absorbed in the oxide semiconductor film 18. However, the oxidation of the oxide semiconductor film 18 is caused by the heating. It is possible to release water, hydrogen, and the like contained in the oxide insulating film 23 and the oxide insulating film 24. This reduces the variation in the electrical characteristics of the transistor 60 and suppresses the variation in the threshold voltage. It can be controlled.

[0161] Note that the oxide insulating film 24 is formed over the oxide insulating film 23 while being heated. Oxygen is transferred to the oxide semiconductor film 18, and the amount of oxygen vacancies contained in the oxide semiconductor film 18 is reduced. Therefore, the heat treatment is not necessary.

[0162] The heat treatment temperature is 150° C. or higher and 300° C. or lower, or 200° C. or higher and 250° C. or lower. By this, the diffusion of copper, aluminum, gold, silver, molybdenum, etc., and the diffusion into the oxide semiconductor film can be prevented. It is possible to suppress the inclusion of

[0163] Here, heat treatment is performed in a nitrogen and oxygen atmosphere at 220° C. for 1 hour.

[0164] In addition, when the pair of electrodes 21 and 22 are formed, the multilayer film 20 is formed by etching the conductive film. The back channel of the multilayer film 20 (the gate electrode 15 in the multilayer film 20) is damaged. However, oxygen vacancies occur on the surface facing the oxide insulating film 24 and the surface opposite the surface. By using an oxide insulating film containing more oxygen than the theoretical composition, This makes it possible to repair the oxygen vacancies occurring on the back channel side. Since the defects contained in the multilayer film 20 can be reduced, the reliability of the transistor 60 can be improved. It can be raised.

[0165] Next, the nitride insulating film 25 is formed by sputtering, CVD or the like.

[0166] When the nitride insulating film 25 is formed by the plasma CVD method, The substrate placed in the evacuated processing chamber is heated to 300°C or higher and 400°C or lower, or 320°C or lower. A temperature of 370° C. or less is preferable because a dense nitride insulating film can be formed.

[0167] When a silicon nitride film is formed as the nitride insulating film 25 by the plasma CVD method, the silicon It is preferable to use a deposition gas containing carbon, nitrogen, and ammonia as the source gas. By using a small amount of ammonia as a feed gas compared to nitrogen, the ammonia in the plasma The silicon-containing deposition gas dissociates and generates active species. This breaks the silicon-hydrogen bond and the nitrogen triple bond. Promoted bonding, fewer silicon and hydrogen bonds, fewer defects, and dense silicon nitride On the other hand, the amount of ammonia relative to nitrogen in the source gas is high. If the temperature is too low, the decomposition of the silicon-containing deposition gas and nitrogen will not proceed, and silicon and hydrogen bonds will form. As a result, defects are increased and a rough silicon nitride film is formed. For these reasons, the flow rate ratio of nitrogen to ammonia in the raw gas is set to 5 or more and 50 or less. It is preferable that the range is 10 or more and 50 or less.

[0168] Here, silane at a flow rate of 50 sccm and 5000 The source gases were nitrogen at a flow rate of 100 sccm and ammonia at a flow rate of 100 sccm. The pressure in the processing chamber was The pressure was set at 100 Pa, the substrate temperature was set at 350°C, and a 27.12 MHz high frequency power source was used for 1000 A 50 nm thick nitride film was formed by plasma CVD using a 1000 MHz high frequency power supply to parallel plate electrodes. A silicon film is formed. The plasma CVD device has an electrode area of ​​6000 cm. 2 It is flat This is a horizontal and flat type plasma CVD device, and the supplied power is expressed as power per unit area (power density ) is converted to 1.7 × 10 -1 W / cm 2 It is.

[0169] Through the above steps, a film consisting of the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film 25 is formed. A protective film 26 can be formed by the above process.

[0170] Next, a heat treatment may be performed. The temperature of the heat treatment is typically 150° C. or higher and 30 The temperature must be below 0℃, or between 200℃ and 250℃.

[0171] Through the above steps, the transistor 60 can be manufactured.

[0172] In this embodiment, a CAAC oxide film is formed between an oxide semiconductor film and a pair of electrodes. The oxide film is formed by absorbing impurities from the outside of the oxide semiconductor film. It is possible to reduce the amount of impurities diffusing from the pair of electrodes to the oxide semiconductor film. For this reason, a pair of electrodes using copper, aluminum, gold, silver, or molybdenum can be used. Even if the electrode is formed, the fluctuation in the threshold voltage of the transistor can be reduced.

[0173] In this embodiment, the first heat treatment and the second heat treatment are performed in the manufacturing process of the transistor. However, by forming a multilayer film having an oxide semiconductor film, It is possible to reduce the impurity concentration in the conductive film and to reduce the carrier concentration in the defect level. As a result, the temperature of each heat treatment was set at 400 Even if the temperature is lower than 100 °C, the amount of change in threshold voltage is equivalent to that of a transistor heat-treated at a high temperature. As a result, the cost of the semiconductor device can be reduced. do.

[0174] In addition, the oxide semiconductor film having a stoichiometric composition is overlapped with the oxide semiconductor film serving as a channel region. By forming an oxide insulating film that contains more oxygen than oxygen that is As a result, oxygen contained in the oxide semiconductor film can be transferred to the oxide semiconductor film. The defect content can be reduced.

[0175] In particular, the oxide semiconductor film that functions as a channel region and the oxygen-containing oxide film that satisfies the stoichiometric composition To form an oxide insulating film that transmits oxygen between the oxide insulating film containing more oxygen than the insulating film containing the oxide insulating film. When forming an oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition, Damage to the oxide semiconductor film can be suppressed. The amount of oxygen vacancies can be reduced.

[0176] In addition, an oxide film is formed on the oxide semiconductor film, so that oxygen having a stoichiometric composition can be obtained. When an oxide insulating film containing more oxygen than the above is formed, the oxide semiconductor film is damaged. In addition, by forming an oxide film, the oxide semiconductor film The constituent elements of an insulating film formed on the oxide semiconductor film, for example, an oxide insulating film, are mixed into the oxide semiconductor film. This can prevent the following from happening:

[0177] From the above, it is possible to provide a semiconductor device including an oxide semiconductor film, in which the amount of defects is reduced. In addition, the electrical characteristics of a semiconductor device including an oxide semiconductor film can be improved. The above semiconductor device can be obtained.

[0178] <Diffusion mechanism of metal elements in oxide semiconductor films> Here, the results of calculations on the diffusion mechanism of metal elements in an oxide semiconductor film are as follows. Shown below.

[0179] Here, the oxide semiconductor film is a semiconductor having a metal atomic ratio of In:Ga:Zn=1:1:1. An In-Ga-Zn oxide film (hereinafter referred to as IGZO) formed using a sputtering target (111). Cu is placed as a metal element between the lattices of the crystal of Ease of use calculations were performed.

[0180] The calculation model is shown in Figure 4. The four routes of Cu diffusion are indicated by the arrows in Figure 4. The activation barrier of each pathway is calculated using the Nudged Elastic Band (NEB) method. In Figure 4, each state is represented by a number. The state that requires the lowest energy to connect the two states from the final state and the This method searches for the state of the oxide semiconductor. In the membrane, the direction parallel to the normal vector of the surface on which the membrane is formed or the upper surface is the c-axis. The direction perpendicular to the c-axis direction, i.e., the ab-plane direction, is referred to as the horizontal direction.

[0181] Path 1 is the lateral diffusion of Cu between (Ga,Zn)O layers. In FIG. 4, this is a move from the initial state to state 1.

[0182] Path 2 is the vertical diffusion of Cu through the (Ga,Zn)O layer. to state 2.

[0183] Path 3 is the lateral diffusion of Cu between the (Ga,Zn)O layer and the InO2 layer. In this case, it is a move from state 2 to state 3.

[0184] Path 4 is the vertical diffusion of Cu through the InO2 layer. This is a move to state 4.

[0185] Next, the calculation conditions are shown in Table 1.

[0186] [Table 1]

[0187] In route 1, i.e., lateral diffusion between (Ga,Zn)O layers, The low barrier pathway is shown in Figure 5(A), and the activation barrier is shown in Figure 5(B). It can be seen that u is more stable in terms of energy during diffusion than between lattices. The activation barrier required for the interstitial transfer is about 0.30 eV, and even at room temperature, (Ga,Zn It is believed that lateral diffusion occurs between the (Ga,Zn)O layer and the (Ga,Zn)O layer.

[0188] Route 2, i.e., vertical diffusion through the (Ga,Zn)O layer, is the route with the lowest barrier as shown in Figure 6. The active barrier is shown in Fig. 6(B). It is unstable when present in the layer, and its activation barrier is about 0.71 eV. At high temperatures, it is believed that little vertical diffusion occurs through the (Ga,Zn)O layer.

[0189] In route 3, i.e., lateral diffusion between the (Ga,Zn)O layer and the InO2 layer, the barrier is low. The active pathway is shown in Figure 7(A) and the activation barrier is shown in Figure 7(B). It can be seen that the diffusion state is more stable in terms of energy than the interstitial state. The activation barrier for the transfer is about 0.25 eV, and even at room temperature, the (Ga,Zn)O layer-In Lateral diffusion between the O2 layers is thought to occur.

[0190] Route 4, i.e., vertical diffusion through the InO2 layer, is the route with the lowest barrier as shown in Figure 8(A). The activation barrier is shown in FIG. 8(B). When Cu is present in the InO2 layer, it is unstable. The activation barrier was about 1.90 eV. Therefore, even at high temperatures, the vertical diffusion through the InO2 layer was observed. It is thought that little scattering will occur.

[0191] From the above, the arrows shown in FIG. 4, that is, the initial state, route 1, route 2, route 3, and route The activation barriers in path 4 are shown in FIG. 9. In FIG. 9, the horizontal axis represents the distance traveled by Cu, and the vertical axis represents the activation barrier.

[0192] From Fig. 9, Cu is energetically stable when it exists between the (Ga,Zn)O layer and the InO2 layer. The activation barrier of route 4 across the InO2 layer is the highest. It can be seen that diffusion is difficult in the diffusion path beyond the nO2 layer.

[0193] As a comparative example, the results of a similar calculation for ZnO with a hexagonal crystal structure are shown below. As shown in.

[0194] The calculation model is shown in Figure 10. Here, the basic lattice of the ZnO crystal is Using a 72-atom crystal model with doubled dimensions, the Cu diffusion route is shown by the arrow in Figure 10. For the two pathways, we calculated the activation barrier of each pathway using Nudged Elastic Blocks (NEB). The calculation was performed using the Band method.

[0195] Path 1 is the vertical diffusion of Cu in the c-axis direction. This is a move to state 1.

[0196] Path 2 is the lateral diffusion of Cu in the b-axis direction. Moving to 2.

[0197] Next, the calculation conditions are shown in Table 2.

[0198] [Table 2]

[0199] In the case of the longitudinal diffusion of Cu in the c-axis direction, the diffusion path of Cu is The vertical view is shown in Fig. 11(A), and the c-axis view is shown in Fig. 11(B). The activation barrier is shown in Figure 11(C). Cu is unstable when it is in a plane surrounded by Zn. The activation barrier is about 0.73 eV. It is believed that there is almost no vertical diffusion of Cu.

[0200] Path 2, i.e., the lateral diffusion of Cu in the b-axis direction, is The vertical view is shown in Fig. 12(A), and the c-axis view is shown in Fig. 12(B). The active barrier is shown in FIG. 12(C). Cu is in the middle of diffusion and has two Cu atoms rather than being interstitial. It can be seen that the position where the bond with O is more stable in terms of energy. The activation barrier required for the Cu to move to the b-axis direction is about 0.32 eV, and the lateral movement of Cu along the b-axis direction can be seen even at room temperature. Diffusion is believed to occur.

[0201] From the above, the arrows in FIG. 10, that is, the activity in the initial state, route 1, and route 2, The gender barrier is shown in Figure 13.

[0202] As shown in Figure 13, Cu is in the middle of lateral diffusion and is at the position where it bonds with two O. The activation barrier is the highest in the longitudinal diffusion along the c-axis.

[0203] In addition, the activation barrier (about 1.9 eV) when passing through the InO2 layer, i.e., route 4 shown in FIG. In comparison, the activation barrier for vertical diffusion in ZnO (about 0.7 eV) is This indicates that the vertical Cu diffusion is smaller on IGZO(111) than on ZnO. The inhibitory effect is considered to be high.

[0204] That is, the crystal grain boundary is not confirmed, the crystal grain has a c-axis orientation, and the c-axis is perpendicular to the normal of the surface on which the crystal grain is formed or the upper surface. The CAAC oxide film, which is oriented parallel to the line vector, is placed on the oxide semiconductor film and a pair of electrodes. A pair of electrodes is formed using Cu, forming a channel-etched transistor. It can be seen that the diffusion of Cu into the oxide semiconductor film can be reduced in this case.

[0205] <Band structure of transistor> Next, the band structure of the multilayer film 20 will be described with reference to FIG.

[0206] Here, as an example, the oxide semiconductor film 18 has an energy gap of 3.15 eV. The oxide film 19 is made of In-Ga-Zn oxide with an energy gap of 3.5e The energy gap is measured using a spectroscopic ellipsometer. (HORIBA JOBIN YVON UT-300) can be used for measurement. do.

[0207] The energy difference between the vacuum level and the top of the valence band of the oxide semiconductor film 18 and the oxide film 19 (ion The electron potentials (also called electron-electron potentials) are 8 eV and 8.2 eV, respectively. The energy difference between the potential and the top of the valence band was determined by ultraviolet photoelectron spectroscopy (UPS). Photoelectron Spectroscopy (PHI) equipment It can be measured using ersaProbe.

[0208] Therefore, the vacuum level and the energy of the conduction band minimum of the oxide semiconductor film 18 and the oxide film 19 are The electron affinity difference (also called electron affinity) is 4.85 eV and 4.7 eV, respectively.

[0209] FIG. 3A shows a schematic diagram of a part of the band structure of the multilayer film 20. The case where a silicon oxide film is provided in contact with the film 20 will be described. EcI1 indicates the energy of the conduction band minimum of the silicon oxide film, and EcS1 indicates the energy of the oxide semiconductor film. EcS2 is the energy of the conduction band minimum of the oxide film 19. EcI2 indicates the energy of the bottom of the conduction band of the silicon oxide film. corresponds to the gate insulating film 17 in FIG. 1B, and EcI2 corresponds to , which corresponds to the oxide insulating film 23.

[0210] As shown in FIG. 3A, in the oxide semiconductor film 18 and the oxide film 19, The energy of changes smoothly without any barriers. In other words, it changes continuously. This is because the multilayer film 20 contains elements common to the oxide semiconductor film 18 and is an oxide A mixed layer is formed between the semiconductor film 18 and the oxide film 19 by the mutual transfer of oxygen. It can be said that this is for the purpose.

[0211] As shown in FIG. 3A, the oxide semiconductor film 18 of the multilayer film 20 serves as a well. In the transistor using 0, a channel region is formed in the oxide semiconductor film 18. In addition, since the energy of the conduction band minimum of the multilayer film 20 changes continuously, It can also be said that the oxide semiconductor film 18 and the oxide film 19 are in continuous junction.

[0212] As shown in FIG. 3A, in the vicinity of the interface between the oxide film 19 and the oxide insulating film 23, , silicon or carbon which is a constituent element of the oxide insulating film 23; Traps caused by impurities or defects in the elements copper, aluminum, gold, silver, molybdenum, etc. However, since the oxide film 19 is provided, the oxide semiconductor film 18 However, the energy between EcS1 and EcS2 can be When the energy difference is small, electrons in the oxide semiconductor film 18 exceed the energy difference and enter the trap level. When electrons are captured in the trap level, a negative charge is generated at the interface of the insulating film. This generates a charge, and the threshold voltage of the transistor shifts in the positive direction. The energy difference between EcS1 and EcS2 is 0.1 eV or more, or 0.15 eV or more. This is preferable because it reduces the fluctuation in the threshold voltage of the transistor and provides stable electrical characteristics. It is.

[0213] FIG. 3B is a schematic diagram showing a part of the band structure of the multilayer film 20. In this example, a silicon oxide film is provided in contact with the multilayer film 20. In addition, EcI1 shown in FIG. 3B is the minimum conduction band of the silicon oxide film. EcS1 represents the energy of the bottom of the conduction band of the oxide semiconductor film 18, and E cI2 indicates the energy of the bottom of the conduction band of the silicon oxide film. 1B), corresponds to the gate insulating film 17, and EcI2 corresponds to the oxide insulating film It corresponds to the membrane 23 .

[0214] In the transistor shown in FIG. 1B, the multilayer film 20 is formed when the pair of electrodes 21 and 22 are formed. On the other hand, the upper part of the oxide semiconductor film 1, i.e., the oxide film 19, may be etched. On the upper surface of the substrate 8, a mixed layer of the oxide semiconductor film 18 and the oxide film 19 is formed during the formation of the oxide film 19. This may be the case.

[0215] For example, the oxide semiconductor film 18 is an In- Ga-Zn oxide, or In-Ga-Z with In:Ga:Zn=3:1:2 [atomic ratio] n oxide as a sputtering target, and The film 19 is an In-Ga-Zn oxide having an atomic ratio of In:Ga:Zn=1:3:2. In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=1:6:4 was sputtered. In the case where the oxide film is formed by using a fluorine-based target, the oxide semiconductor film 18 is more likely to be formed of oxide. Since the Ga content of the film 19 is high, a GaOx layer or an oxide layer is formed on the upper surface of the oxide semiconductor film 18. A mixed layer containing more Ga than the compound semiconductor film 18 can be formed.

[0216] Therefore, even when the oxide film 19 is etched, the EcS1 side of the EcI2 The energy of the conduction band edge of the junction becomes high, resulting in a band structure like that shown in Figure 3(B). be.

[0217] When the band structure shown in FIG. 3B is obtained, when observing the cross section of the channel region, The multilayer film 20 may appear to be composed of only the oxide semiconductor film 18. In reality, a mixture containing more Ga than the oxide semiconductor film 18 is formed on the oxide semiconductor film 18. Since a mixed layer is formed, the mixed layer can be regarded as a 1.5 layer. When the elements contained in the multilayer film 20 are measured by, for example, EDX analysis, the mixed layer is This can be confirmed by analyzing the composition above the oxide semiconductor film 18. For example, The composition in the upper portion of the oxide semiconductor film 18 has a higher Ga content than the composition in the oxide semiconductor film 18. This can be confirmed by the configuration.

[0218] <Variation 1> In the transistor 60 according to this embodiment, a modification of the multilayer film 20 will be described with reference to FIG. explain.

[0219] In the transistor shown in FIG. 14A, the multilayer film 20 is formed from the gate insulating film 17 side in the form of a first An oxide semiconductor film 18a, a second oxide semiconductor film 18b, and an oxide film 19 are stacked in this order. There are.

[0220] The first oxide semiconductor film 18a and the second oxide semiconductor film 18b are made of the above-mentioned oxide semiconductor The first oxide semiconductor film 18a and the second oxide semiconductor film 18b are formed using a material similar to that of the first oxide semiconductor film 18. The body film 18b is an In-M-Zn oxide (M is Ga, Y, Zr, La, Ce, or Nd). In the case where the oxide semiconductor film 18 is formed of the first oxide semiconductor film 18b, the atomic ratio of In to M is smaller than that of the second oxide semiconductor film 18b. It is preferable that the oxide semiconductor film 18a is larger than the oxide semiconductor film 18b. When the atomic ratio of In to Si is large, that is, when the proportion of In is large, the carrier mobility (electron mobility) Therefore, the first oxide semiconductor film 18a in contact with the gate insulating film 17 is more By using a film with a high In ratio, it is possible to increase the on-state current of the transistor. At the same time, the field effect mobility can be increased.

[0221] In addition, the first oxide semiconductor film 18a is formed using a CAAC-OS film. Therefore, the diffusion of impurities from the first oxide semiconductor film 1 can be reduced. This makes it possible to reduce the amount of impurities that migrate to the oxide semiconductor film 8a and the second oxide semiconductor film 18b.

[0222] In the transistor shown in FIG. 14B, the multilayer film 20 is formed from the gate insulating film 17 side in the form of a first An oxide film 19a, an oxide semiconductor film 18, and a second oxide film 19b are stacked in this order.

[0223] The first oxide film 19a and the second oxide film 19b are the same as the oxide film 19 shown in the first embodiment. The first oxide film 19a and the second oxide film 19b are formed using the same material. The atomic ratio of the metal elements may be the same or different.

[0224] The first oxide film 19a is preferably thinner than the oxide semiconductor film 18. The thickness of the oxide film 19a is set to 1 nm or more and 5 nm or less, or 1 nm or more and 3 nm or less. Therefore, it is possible to reduce the amount of variation in the threshold voltage of the transistor.

[0225] The transistor illustrated in FIG. 14B has a gate insulating film 17 and an oxide semiconductor film 18. Therefore, the first oxide film 19a and the oxide semiconductor Even if a trap level is formed between the conductive films 18 due to impurities and defects, the trap There is a gap between the top level and the oxide semiconductor film 18. As a result, The electrons flowing through the gate are less likely to be captured by the trap level, which increases the on-current of the transistor. In addition, the field effect mobility can be increased. When a molecule is captured, the electron becomes a fixed negative charge. However, the oxide semiconductor film 18 and the trap level Since there is a gap between the trap level and the electron capture at the trap level can be reduced. This makes it possible to reduce the variation in the threshold voltage.

[0226] In addition, by forming the first oxide film 19a using a CAAC oxide film, Since it is possible to reduce the diffusion of impurities, the impurities that move from the outside to the oxide semiconductor film 18 can be prevented from being diffused. Therefore, the amount of impurities in the oxide semiconductor film 18 can be reduced. It is possible to reduce the degree of

[0227] <Variation 2> The pair of electrodes 21 and 22 provided in the transistor 60 in this embodiment are made of copper, Uses conductive materials that easily bond with oxygen, such as aluminum or molybdenum alone or alloys. As a result, the oxygen contained in the multilayer film 20 and the oxygen contained in the pair of electrodes 21 and 22 The conductive material contained in the multilayer film 20 is bonded to the oxygen vacant region. In some cases, the layer 20 may be contaminated with some of the constituent elements of the conductive material that forms the pair of electrodes 21 and 22. As a result, in the multilayer film 20, in the vicinity of the region in contact with the pair of electrodes 21 and 22, A low resistance region is formed. The low resistance region is in contact with a pair of electrodes 21 and 22 and is a gate insulator. It is formed between the film 17 and a pair of electrodes 21 and 22. The low resistance region has high conductivity, It is possible to reduce the contact resistance between the multilayer film 20 and the pair of electrodes 21 and 22, and thus the transistor It is possible to increase the on-current of the transistor.

[0228] The pair of electrodes 21 and 22 are made of the conductive material that easily bonds with oxygen, titanium nitride, and nitrogen. Alternatively, the layer structure may be made of a conductive material that does not easily bond with oxygen, such as tantalum oxide or ruthenium. For example, a conductive film made of a conductive material that is difficult to bond with oxygen is formed in contact with the multilayer film 20. A conductive film made of a conductive material that easily bonds with oxygen may be formed on the conductive film. By using such a layered structure, the oxide insulating film 23 is In this way, it is possible to prevent the pair of electrodes 21 and 22 from being oxidized, and the pair of electrodes 21 and 22 can be highly It is possible to suppress the development of resistance.

[0229] <Modification 3> In the transistor 60 shown in this embodiment, as shown in FIG. A protective film 26a on which an oxide insulating film 24 and a nitride insulating film 25 are laminated is provided on the insulating film 26a. The transistor illustrated in FIG. 15 has an oxide film 19 over an oxide semiconductor film 18. Therefore, the oxide film 19 functions as a protective film when the oxide insulating film 24 is formed. As a result, when the oxide insulating film 24 is formed, the oxide semiconductor film 18 is not exposed to plasma. The plasma generated when forming the oxide insulating film 24 by the plasma CVD method using a relatively high power is Can reduce damage.

[0230] In addition, oxygen contained in the oxide insulating film 24 can be directly transferred to the multilayer film 20. Therefore, the amount of oxygen supplied to the oxide semiconductor film 18 can be increased. In this case, the amount of oxygen vacancies in the oxide semiconductor film 18 can be further reduced.

[0231] In this embodiment, the multilayer film is a stacked film of the oxide semiconductor film 18 and the oxide film 19. However, an oxide film may be further provided between the gate insulating film 17 and the oxide semiconductor film 18. By providing an oxide film between the gate insulating film 17 and the oxide semiconductor film 18, The concentration of silicon and carbon in the vicinity of the interface between the insulating film 17 and the multilayer film, and the concentration of silicon and carbon in the oxide semiconductor film 18 The concentrations of silicon and carbon in the SiO2 solution can be reduced.

[0232] <Modification 4> In this embodiment, the gate electrode 15 is a boron layer provided between the substrate 11 and the multilayer film 20. The above explanation was given using a transistor with a Tom gate structure. As shown in FIG. 32(A), That is, a pair of electrodes 21 are formed on the multilayer film 20. , 22, a gate insulating film 27 is provided on the pair of electrodes 21, 22, The transistor 62 may have a gate electrode 15a on the substrate 11. Between the multilayer film 20, there is an oxide insulating film 17c in contact with the multilayer film 20, and an oxide insulating film 17c and A nitride insulating film 17a is provided in contact with the pair of electrodes 21 and 22. As shown in FIG. 1B, a gate electrode 15, a gate insulating film 17 on the gate electrode 15, and a gate A multilayer film 20 on the insulating film 17, a pair of electrodes 21 and 22 on the multilayer film 20, and the multilayer film 20 and A device having a protective film 26 on a pair of electrodes 21 and 22 and a gate electrode 15a on the protective film 26. The transistor 64 may have a dual-gate structure.

[0233] (Embodiment 2) In this embodiment, it is possible to prevent the diffusion of the metal elements constituting the pair of electrodes 21 and 22. A semiconductor device having such a transistor and a manufacturing method thereof will be described with reference to FIGS. 7 will be used to explain.

[0234] 16A to 16C are top views and A cross-sectional view of the transistor 70 shown in FIG. 16 is a channel etch type transistor. FIG. 16A is a top view of a transistor 70, and FIG. 16B is a top view of the transistor 70 shown in FIG. FIG. 16(C) is a cross-sectional view taken along dashed line AB in FIG. 16(A). 16A is a cross-sectional view of the substrate 11 and the transistor 70 for clarity. A part of the component (for example, the gate insulating film 17), the oxide insulating film 23, the oxide insulating film 24, The nitride insulating film 25 and the like are omitted.

[0235] The transistor 70 shown in FIG. 16B and FIG. 16C is a gate insulating film provided on the substrate 11. a gate electrode 15; a gate insulating film 17 formed on the substrate 11 and the gate electrode 15; A multilayer film 20 overlapping the gate electrode 15 via a gate insulating film 17 and a pair of electrodes contacting the multilayer film 20 The pair of electrodes 21 and 22 are covered with protective films 43 and 44. In addition, the gate insulating film 17, the multilayer film 20, the pair of electrodes 21 and 22, and the protective films 43 and 4 A protection layer made of an oxide insulating film 23, an oxide insulating film 24, and a nitride insulating film 25 is provided on the insulating film 4. A protective membrane 26 is formed.

[0236] The protective films 43 and 44 are formed by etching in the processing step for forming the pair of electrodes 21 and 22. The protective films 43 and 44 function as a plating protective film. The protective films 43 and 4 have a function of preventing exposure to oxygen plasma. 4 has a function of preventing the diffusion of the metal elements that constitute the pair of electrodes 21 and 22. Therefore, the protective films 43 and 44 are made of a material having plasma resistance. The electrode 44 is formed using a material that prevents the diffusion of the metal elements that constitute the pair of electrodes 21 and 22. .

[0237] The protective films 43 and 44 are made of silicon nitride, silicon oxynitride, aluminum nitride, or oxynitride. The insulating film can be formed by appropriately using a nitride insulating film made of aluminum or the like. In the present specification, the silicon nitride oxide film and the aluminum nitride oxide film are films that contain more nitrogen than oxygen. The content (atomic ratio) of silicon oxynitride film and aluminum oxynitride film are high. refers to a film that contains more oxygen than nitrogen (atomic ratio).

[0238] Alternatively, the protective films 43 and 44 may be made of indium tin oxide (hereinafter, also referred to as ITO), oxide Tungsten-containing indium oxide, tungsten oxide-containing indium zinc oxide, Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium A light-transmitting conductive material formed of zinc oxide, indium tin oxide containing silicon oxide, etc. It can be formed using a film.

[0239] Alternatively, the protective films 43 and 44 may be the oxide semiconductor film 18 or the oxide film The semiconductor device is formed by appropriately using an oxide semiconductor containing In, Ga, or Zn that can be used in the semiconductor device of 19. It can be achieved.

[0240] In addition, when the protective films 43 and 44 are formed using a conductive film having light-transmitting properties, the protective film 43 , 44 function as electrodes together with the electrodes 21, 22, respectively.

[0241] A mask made of an organic resin (typically In the first step, the resist mask is ashed with oxygen plasma. The film is removed by decomposing the film in the gas phase. Alternatively, the film is removed by ashing. The mask used is easily removed, so after ashing, the organic resin is removed using a stripping solution. The mask formed by the oil can be removed.

[0242] In addition, an oxide insulating film is formed as a protective film on the pair of electrodes 21 and 22 by sputtering or CV. When forming the electrodes 21 and 22 by the D method or the like, the electrodes 21 and 22 are exposed to oxygen plasma.

[0243] However, when the pair of electrodes 21 and 22 is exposed to oxygen plasma, , the metal elements constituting 22 react with oxygen to produce metal oxides. Since oxides are highly reactive, there is a problem that they diffuse into the multilayer film 20. When the protective films 43 and 44 are provided on the pair of electrodes 21 and 22, the protective films 43 and 44 form a mask. As a result, the pair of electrodes 21 and 22 is less likely to be exposed to oxygen plasma. The metal elements constituting the electrodes 21 and 22 react with oxygen to produce metal oxides, and In addition, the migration of metal elements constituting the pair of electrodes 21 and 22 into the multilayer film 20 can be reduced. Cut.

[0244] That is, it is possible to reduce the impurity concentration in the multilayer film 20. Therefore, it is possible to reduce the variation in the electrical characteristics of the transistor 70.

[0245] Next, a method for manufacturing the transistor 70 shown in FIG. 16 will be described with reference to FIGS. Reveal.

[0246] As in the first embodiment, the steps shown in FIG. 2(A) to FIG. 2(C) are carried out to obtain the structure shown in FIG. As shown in the figure, a gate electrode 15, a gate insulating film 17, a multilayer film 20, a conductive film 41, and A protective film 42 is then formed.

[0247] The conductive film 41 is a film that will later become the pair of electrodes 21 and 22. The materials shown in the pair of electrodes 21 and 22 can be used appropriately.

[0248] The conductive film 41 is formed by appropriately using a sputtering method, a vapor deposition method, a CVD method, a printing method, or the like. .

[0249] Here, the conductive film 41 is a copper film having a thickness of 200 nm formed by sputtering. In addition, a silicon nitride film having a thickness of 200 nm is formed as a protective film 42 by a plasma CVD method. Form.

[0250] Next, a mask is formed on the protective film 42, and then a part of the protective film 42 is etched using the mask. 17(B), protective films 43 and 44 are formed. For the etching, dry etching, wet etching, or the like can be used as appropriate. The protective films 43 and 44 function as a hard mask in a later process. Since the distance between the electrodes is the channel length of the transistor, dry etching is used, which allows anisotropic etching. It is preferable to etch the protective film 42 using

[0251] Here, a mask is formed by a photolithography process, and then the mask is dry-etched. Part of the protective film 42 is then etched to form protective films 43 and 44 .

[0252] After this, it is preferable to remove the mask. As a result, in the step of removing the mask Since the multilayer film 20 is covered with the conductive film 41 and is not exposed, the conductive film 41 is The metal elements do not migrate to the multilayer film 20. Here, the mask is removed by ashing. After softening, the mask is removed using a stripping solution.

[0253] Next, as shown in FIG. 17(C), the conductive film 41 is formed by using the protective films 43 and 44 as a mask. The pair of electrodes 21 and 22 are formed by etching a part of the protective films 43 and 44. As a condition for selectively etching the conductive film 41 without etching, the etchant is nitric acid, Chloric acid, a mixture of phosphoric acid, acetic acid and nitric acid (aluminum mixed acid solution), etc. can be used appropriately.

[0254] Here, hydrogen peroxide, ammonium acetate, malonic acid, and ethylenediamine are used as etchants. Wet with a mixture of aminetetraacetic acid and 5-amino-1H-tetrazole monohydrate The conductive film 41 is selectively etched using an etching method.

[0255] After the pair of electrodes 21 and 22 are formed, the metal elements remaining on the multilayer film 20 are removed. For example, a pair of electrodes 21 and 22, a protective layer, and a The protective films 43 and 44 are not etched, and the surface of the multilayer film 20 is etched by several nm, for example, 1 nm to 5 nm. It is preferable to use the following etching conditions. Such etching conditions include: Hydrofluoric acid, a mixture of hydrofluoric acid and ammonium fluoride (also called buffered hydrofluoric acid), A mixture of ammonia and hydrogen peroxide (also called ammonium perhydrate) can be used. Cut.

[0256] Here, a multilayer film is etched using an etchant made of 0.5% hydrofluoric acid diluted to 1 / 1000. The metal elements constituting the pair of electrodes 21 and 22 are removed from the surface of 20.

[0257] In addition, the process of forming the pair of electrodes 21 and 22 and the process of removing the pair of electrodes 22 from the surface of the multilayer film 20 are the same as those in the process of forming the multilayer film 20. In the process of removing the metal elements constituting the pair of electrodes 21 and 22, In this case, the oxide film 19 is formed using a CAAC oxide film, so that the pair of electrodes 2 The metal elements constituting the oxide semiconductor film 18 do not diffuse into the oxide semiconductor film 18. The impurity concentration of the conductive film 18 can be reduced.

[0258] Next, as in the first embodiment, as shown in FIG. 17(D), the multilayer film 20 and the pair of electrodes 21 , 22 and the pair of protective films 43 and 44.

[0259] Through the above steps, the transistor 70 can be manufactured.

[0260] In this embodiment, the transistor has protective films 43 and 44 on a pair of electrodes. The area of ​​the pair of electrodes exposed to the plasma, for example, oxygen plasma, is reduced. As a result, the generation of compounds of the metal elements that make up the conductive film due to plasma exposure is reduced. Therefore, the metal elements constituting the conductive film are less likely to migrate into the multilayer film.

[0261] In addition, an oxide film formed of a CAAC oxide film between the oxide semiconductor film and the pair of electrodes The oxide film can reduce the diffusion of impurities from the outside, and a pair of It is possible to reduce the amount of impurities that move from the electrode to the oxide semiconductor film. A pair of electrodes may be formed using aluminum, gold, silver, or molybdenum. This can reduce the variation in the threshold voltage of the transistor.

[0262] As a result, the components of the wiring and electrodes, copper, aluminum, gold, silver, molybdenum, The diffusion of impurities such as fluorine into the oxide semiconductor film included in the multilayer film can be suppressed. In addition, the concentration of impurities in the oxide semiconductor film can be reduced.

[0263] As a result, a semiconductor device having improved electrical characteristics can be obtained. A semiconductor device can be obtained.

[0264] <Variation 1> In this embodiment, the gate electrode 15 is a bottom gate electrode provided between the substrate 11 and the multilayer film 20. The above explanation was given using a transistor with a top gate structure, but as shown in FIG. That is, a pair of electrodes 21 and 22 are provided on a multilayer film 20. and a pair of electrodes 21 and 22 are provided with protective films 43 and 44 thereon. A gate insulating film 27 is formed on the protective films 43 and 44, and a gate electrode 15a is formed on the gate insulating film 27. In addition, between the substrate 11 and the multilayer film 20, The oxide insulating film 17c in contact with the multilayer film 20, and the oxide insulating film 17c and a pair of electrodes 21, 2 2 and a nitride insulating film 17a in contact with the nitride insulating film 2 are provided. A gate electrode 15, a gate insulating film 17 on the gate electrode 15, and a multilayer film on the gate insulating film 17. A film 20, a pair of electrodes 21 and 22 on the multilayer film 20, and a protective film 4 on the pair of electrodes 21 and 22. 3, 44, the multilayer film 20, the pair of electrodes 21, 22, and the protective film 26 on the protective films 43, 44 and a gate electrode 15a on the protective film 26. It can be said that:

[0265] (Embodiment 3) In this embodiment, a semiconductor device which is one embodiment of the present invention will be described with reference to drawings. Note that in this embodiment, a semiconductor device which is one embodiment of the present invention will be described using a display device as an example. do.

[0266] FIG. 18A shows an example of a semiconductor device. The semiconductor device shown in FIG. 101, a scanning line driving circuit 104, and a signal line driving circuit 106 are parallel or approximately parallel to each other. m scanning lines 107, the potentials of which are controlled by a scanning line driving circuit 104; , each are arranged in parallel or approximately in parallel, and the potentials are controlled by a signal line driving circuit 106. The pixel section 101 is arranged in a matrix. The pixel 301 is arranged parallel or approximately parallel to the signal line 109. The capacitance lines 115 are arranged along the scanning lines 107. The scanning line driver circuit 104 and the signal line driver circuit 105 may be arranged in parallel or approximately in parallel. The drive circuits 106 may be collectively referred to as a drive circuit section.

[0267] Each scanning line 107 corresponds to one of the pixels 301 arranged in m rows and n columns in the pixel section 101. The signal lines 109 are electrically connected to the n pixels 301 arranged in any one row. is m pixels 301 arranged in m rows and n columns, and m pixels 301 arranged in any one of the columns. 1. m and n are both integers of 1 or more. is m pixels 301 arranged in m rows and n columns, and m pixels 301 arranged in any one of the columns. 1. The capacitance lines 115 are arranged parallel to each other along the scanning lines 107. In the case where the pixels 301 are arranged in m rows and n columns, any one of the pixels 301 may be arranged in a matrix of m rows and n columns. The pixel array 302 is electrically connected to n pixels 301 arranged in a row.

[0268] 18B and 18C show the structure of the pixel 301 of the display device shown in FIG. 4 shows a circuit configuration that can

[0269] The pixel 301 shown in FIG. 18B includes a liquid crystal element 132, a transistor 131_1, and a capacitor. The capacitance element 133_1 is a capacitance element.

[0270] The potential of one of the pair of electrodes of the liquid crystal element 132 is appropriately set according to the specifications of the pixel 301. The alignment state of the liquid crystal element 132 is set by the written data. A common potential (common potential) is applied to one of a pair of electrodes of the liquid crystal element 132 in each pixel 301. In addition, one of the pair of electrodes of the liquid crystal element 132 for each row of pixels 301 may be applied. may be given different potentials.

[0271] For example, the display device including the liquid crystal element 132 can be driven in a TN mode, an STN mode, or the like. Mode, VA mode, ASM (Axially Symmetric Aligned M icro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid id Crystal) mode, AFLC (AntiFerroelectric Li quid Crystal) mode, MVA mode, PVA (Patterned Ve Vertical Alignment) mode, IPS mode, FFS mode, or TB A (Transverse Bend Alignment) mode may be used. In addition to the above-mentioned driving method, the display device can be driven by ECB (Electro cally Controlled Birefringence) mode, PDLC( Polymer Dispersed Liquid Crystal) mode, PNL C (Polymer Network Liquid Crystal) mode, guest However, the liquid crystal element and its driving method are not limited to these. A variety of different ones can be used.

[0272] Also, a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent. The liquid crystal element may be configured by the liquid crystal that exhibits the blue phase. Since it is short and optically isotropic, alignment treatment is not required and viewing angle dependency is small.

[0273] In the pixel 301 in the mth row and the nth column, One of the electrodes is electrically connected to the signal line DL_n, and the other is a pair of electrodes of the liquid crystal element 132. The gate electrode of the transistor 131_1 is electrically connected to the other of the scan lines G L_m. The transistor 131_1 is in an on state or an off state. By this, the write control circuit 100 has a function of controlling the writing of data of the data signal.

[0274] One of a pair of electrodes of the capacitor 133_1 is connected to a wiring to which a potential is supplied (hereinafter, a capacitor line CL ) and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 132. The value of the potential of the capacitance line CL is appropriately set according to the specifications of the pixel 301. The child 133_1 has a function as a storage capacity for storing written data.

[0275] For example, in a display device having a pixel 301 shown in FIG. 18B, The pixels 301 in each row are selected in sequence, and the transistors 131_1 are turned on to supply data signals Write the data.

[0276] The pixel 301 to which the data has been written is turned off by turning off the transistor 131_1. By repeating this process row by row, an image can be displayed.

[0277] In addition, the pixel 301 shown in FIG. 18C includes a transistor 131_2 and a capacitor 133. _2, a transistor 134, and a light-emitting element 135.

[0278] One of the source electrode and the drain electrode of the transistor 131_2 is supplied with a data signal. Further, the transistor The gate electrode of 131_2 is a wiring to which a gate signal is applied (hereinafter, referred to as a scanning line GL_m). ) is electrically connected to

[0279] The transistor 131_2 is turned on or off to output the data signal. It has a function to control writing of data.

[0280] One of a pair of electrodes of the capacitor 133_2 is connected to a wiring to which a potential is applied (hereinafter, a potential supply line VL_a), and the other is electrically connected to the source electrode of the transistor 131_2 and The gate electrode is electrically connected to the other of the drain electrodes.

[0281] The capacitor 133_2 has a function as a storage capacitor for storing written data. .

[0282] One of the source electrode and the drain electrode of the transistor 134 is connected to the potential supply line VL_a. Furthermore, the gate electrode of the transistor 134 is electrically connected to the gate of the transistor 131_ The second source electrode and the second drain electrode are electrically connected to each other.

[0283] One of the anode and the cathode of the light-emitting element 135 is electrically connected to the potential supply line VL_b. The other is electrically connected to the other of the source electrode and drain electrode of the transistor 134. will be done.

[0284] The light-emitting element 135 may be, for example, an organic electroluminescence element (also called an organic EL element). However, the light emitting element 135 is not limited to this. Alternatively, an inorganic EL element made of an inorganic material may be used.

[0285] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. and the other is supplied with a low power supply potential VSS.

[0286] In a display device having the pixel 301 of FIG. 18C, the scanning line driving circuit 104 The pixels 301 are sequentially selected, the transistors 131_2 are turned on, and the data of the data signal is input. Write.

[0287] The pixel 301 to which the data has been written is turned off by turning off the transistor 131_2. Furthermore, the state of the transistor 134 is changed according to the potential of the written data signal. The amount of current flowing between the source electrode and the drain electrode is controlled, and the light emitting element 135 The light is emitted with a brightness that corresponds to the flow rate. By performing this process row by row, an image can be displayed.

[0288] Next, a specific example of a liquid crystal display device using liquid crystal elements in the pixels 301 will be described. Here, a top view of the pixel 301 shown in FIG. 18(B) is shown in FIG. 19. In this case, the counter electrode and the liquid crystal element are omitted.

[0289] In FIG. 19, the conductive film 304c functioning as the scanning line is oriented in a direction substantially perpendicular to the signal line ( The conductive film 310d that functions as a signal line is provided so as to extend in a direction perpendicular to the plane of the drawing. The capacitor line extends in a direction substantially perpendicular to the scan line (vertical direction in the figure). The conductive film 310f extends in a direction parallel to the signal lines. The conductive film 304c that functions is electrically connected to the scanning line driver circuit 104 (see FIG. 18A). The conductive film 310d that functions as a signal line and the conductive film 310b that functions as a capacitance line are connected. 310f is electrically connected to the signal line driver circuit 106 (see FIG. 18(A)). .

[0290] The transistor 103 is provided in a region where the scanning line and the signal line intersect. The gate electrode of the gate electrode 103 is a conductive film 304c, and a gate insulating film (not shown in FIG. 19). (Not shown), a multi-layer film 308b in which a channel region is formed on the gate insulating film, The conductive film 310d and the conductive film 310e function as a source electrode and a drain electrode. The conductive film 304c also functions as a scanning line, and the region overlapping with the multilayer film 308b is a transistor. The conductive film 310d functions as a gate electrode of the transistor 103. The conductive film 310d also functions as a signal line. The region overlapping with the multilayer film 308b is the source electrode or the drain electrode of the transistor 103. In FIG. 19, the scanning line has a multilayer film at the end in the top view. Therefore, the scanning lines are located outside the end of the backlight. As a result, the multilayer film 308b included in the transistor is exposed to light. Therefore, the change in the electrical characteristics of the transistor can be suppressed.

[0291] In addition, the conductive film 310e has a light-transmitting property that functions as a pixel electrode in the opening 362c. The conductive film 316b is electrically connected to the conductive film 316b.

[0292] The capacitor 105 is connected to a conductive film 310f that functions as a capacitor line in the opening 362. The capacitance element 105 is formed by a conductive film 3 formed on the gate insulating film. 08c, a dielectric film formed of a nitride insulating film provided on the transistor 103, and The conductive film 316b has a light-transmitting property and functions as a base electrode. Since the film 308c has a light-transmitting property, the capacitor 105 has a light-transmitting property.

[0293] In this way, since the capacitor 105 has a light-transmitting property, the capacitor 105 is large and can be placed in the pixel 301. Therefore, the aperture ratio can be increased, typically by 50%. or more, or 55% or more, or 60% or more, and the charge capacity For example, a semiconductor device with high resolution, e.g., a liquid crystal display device, can be obtained. In liquid crystal display devices, the area of ​​the pixel is reduced, and the area of ​​the capacitance element is also reduced. Therefore, in a semiconductor device with high resolution, the charge capacity stored in the capacitive element is reduced. However, since the capacitor 105 shown in this embodiment has a light-transmitting property, By providing it in the pixel, it is possible to obtain sufficient charge capacity in each pixel while increasing the aperture ratio. Typically, the pixel density is 200ppi or more, or even 300ppi or more. The present invention can be suitably used in semiconductor devices having high image quality.

[0294] In addition, the pixel 301 shown in FIG. 19 has a side parallel to the conductive film 310d that functions as a signal line. In comparison, the side parallel to the conductive film 304c functioning as the scanning line is longer, and The conductive film 310f functioning as a quantity line is parallel to the conductive film 310d functioning as a signal line. As a result, the area of ​​the conductive film 310f in the pixel 301 is reduced. It is possible to reduce the number of layers, which increases the aperture ratio. The conductive film 310f is in direct contact with the conductive film 308c without using a connection electrode. Since the film 308c having the above structure transmits light, the aperture ratio can be further increased.

[0295] In addition, according to one embodiment of the present invention, the aperture ratio can be increased even in a high-resolution display device. This allows the light from light sources such as backlights to be used efficiently, and reduces the power consumption of the display device. The force can be reduced.

[0296] Next, a cross-sectional view taken along dashed line CD in FIG. 19 is shown in FIG. In the embodiment, a driving circuit section including a scanning line driving circuit 104 and a signal line driving circuit 106 (top view omitted) A cross-sectional view of the liquid crystal display device according to the present embodiment is shown in FIG. This article explains:

[0297] The liquid crystal display device shown in this embodiment has a liquid crystal display device between a pair of substrates (a substrate 302 and a substrate 342). The element 322 is sandwiched.

[0298] The liquid crystal element 322 is connected to a light-transmitting conductive film 316b above the substrate 302 to control the alignment. A liquid crystal layer 320 and a conductive film 350 are arranged in a liquid crystal display device. Note that the light-transmitting conductive film 316b is used as one electrode of the liquid crystal element 322. The conductive film 350 functions as the other electrode of the liquid crystal element 322 .

[0299] Thus, a liquid crystal display device is a device that has liquid crystal elements. The liquid crystal display device includes a driving circuit for driving a plurality of pixels. A control circuit, a power supply circuit, a signal generating circuit, a backlight module, etc., are arranged in It is also called a liquid crystal module.

[0300] In the driver circuit portion, a conductive film 304a functions as a gate electrode, and a gate insulating film A functional insulating film 305 and an insulating film 306a, a multilayer film 308a in which a channel region is formed, The conductive films 310a and 310b functioning as source and drain electrodes form a transistor. The multilayer film 308a is provided on the gate insulating film. , 310b are provided with protective films 332a, 332b. The insulating film 312 and the insulating film 314 are provided as protective films on the insulating film 332. When the protective films 332a and 332b are formed of a conductive film having a light-transmitting property, the protective films 332a and 332b are The gate electrodes 104 and 106 function as a source electrode and a drain electrode, and constitute the transistor 102.

[0301] In the pixel portion, a conductive film 304c functions as a gate electrode, and a gate insulating film The insulating film 305 and the insulating film 306b are formed on the gate insulating film. the multilayer film 308b, which functions as a source electrode and a drain electrode; The transistor 103 is formed by the conductive films 310d and 310e. Protective films 332d and 332e are provided. An insulating film 312 is provided on the protective films 332d and 332e. The insulating film 314 is provided as a protective film. When the protective films 332d and 332e are made of a conductive film having a high conductivity, the protective films 332d and 332e are The gate electrode of the transistor 103 is also a part of the transistor 103 .

[0302] In addition, a light-transmitting conductive film 316b functioning as a pixel electrode is provided between a protective film 332e and an insulating film 332b. The insulating film 312 and the insulating film 314 are connected to the conductive film 310e through an opening provided therein. .

[0303] Also, a conductive film 308c functioning as one electrode and a dielectric film The insulating film 314 and the light-transmitting conductive film 316b functioning as the other electrode form a capacitor. 105. The conductive film 308c is provided on the insulating film 306c.

[0304] In the driving circuit section, the conductive film 304a and the conductive film 304c are formed at the same time. 4b and the conductive film 31 The light-transmitting conductive film 310c is formed at the same time as the light-transmitting conductive film 316b. Connected via 6a.

[0305] The conductive film 304b and the light-transmitting conductive film 316a are The conductive film 310c and the insulating film 314 are connected to each other through an opening provided in the insulating film 314. The conductive film 316a is provided on the protective film 332c, the insulating film 312, and the insulating film 314. The connection is made at the opening.

[0306] Here, the components of the display device shown in FIG. 20 will be described below.

[0307] Conductive films 304a, 304b, and 304c are formed on the substrate 302. The conductive film 04a functions as a gate electrode of a transistor in the driver circuit portion. 304c is formed in the pixel portion 101 and functions as a gate electrode of a transistor in the pixel portion. The conductive film 304b is formed in the scanning line driver circuit 104 and is connected to the conductive film 310c. do.

[0308] For the substrate 302, the material of the substrate 11 shown in Embodiment 1 can be used as appropriate.

[0309] The conductive films 304a, 304b, and 304c may be the same as those of the gate electrode 15 shown in the first embodiment. Materials and manufacturing methods can be used as appropriate.

[0310] An insulating film 305 is formed on the substrate 302 and the conductive films 304a, 304c, and 304b. On the insulating film 305, insulating films 306a, 306b, and 306c are formed. The film 305 and the insulating films 306a and 306b are gate insulating films of the transistors in the driving circuit section, It also functions as a gate insulating film of the transistor in the pixel portion 101 .

[0311] The insulating film 305 is the nitride insulating film described in the gate insulating film 17 in the first embodiment. The insulating films 306a, 306b, and 306c are formed using the same material as in the first embodiment. The gate insulating film 17 is formed using the oxide insulating film 17c described above with respect to the gate insulating film 17 shown in FIG.

[0312] Multilayer films 308a, 308b, and conductive films are formed on the insulating films 306a, 306b, and 306c. The multilayer film 308a is formed at a position overlapping the conductive film 304a. The multilayer film 30 functions as a channel region of the transistor in the driving circuit section. The conductive film 8b is formed in a position overlapping with the conductive film 304c, and is a channel region of a transistor in a pixel portion. The conductive film 308c functions as one electrode of the capacitor 105. It works.

[0313] The multilayer films 308a and 308b and the conductive film 308c are the same as those in the first embodiment. The material and manufacturing method of the layer film 20 can be appropriately used.

[0314] The conductive film 308c is a multilayer film similar to the multilayer films 308a and 308b, and It is characterized by the fact that it contains impurities. The impurities include hydrogen. Instead, impurities include boron, phosphorus, tin, antimony, rare gas elements, alkali metals, and aluminium. Alkaline earth metals and the like may also be included.

[0315] The multilayer films 308a, 308b and the conductive film 308c are each an insulating film 306. a, 306b, and 306c, but with different impurity concentrations. The conductive film 308c has a higher impurity concentration than the conductive film 308a and 308b. For example, The hydrogen concentration in the multilayer films 308a and 308b is 5×10 19 atoms / cm 3 below , or 5 × 10 18 atoms / cm 3 or less, or 1×10 18 atoms / cm 3 or less, or 5×10 17 atoms / cm 3 or less, or 1×10 16 atoms / c m 3 The hydrogen concentration in the conductive film 308c is 8×10 19 ato ms / cm 3 or more, or 1×10 20 atoms / cm 3 or more, or 5×10 20 a toms / cm 3 The above is the case. Also, compared with the multilayer films 308a and 308b, The hydrogen concentration in the film 308c is two times or ten times or more higher.

[0316] Moreover, the conductive film 308c has a lower resistivity than the multilayer films 308a and 308b. The resistivity of the conductive film 308c is 1×10 times that of the multilayer films 308a and 308b. -8 more than 1x10 -1 times or less, typically 1×10 -3 Ωcm or more 1 ×10 4 Less than Ωcm or resistivity of 1×10 -3 Ωcm or more 1×10 -1 Less than Ωcm It would be good to have one.

[0317] The multilayer films 308a and 308b are made of a multilayer film such as insulating films 306a and 306b and an insulating film 312. Multilayer film because it is in contact with a film formed of a material that can improve the interface properties with the film. 308a and 308b function as semiconductors, and the transistors have multilayer films 308a and 308b. The resistor has excellent electrical properties.

[0318] On the other hand, the conductive film 308c is insulated from the opening 362 (see FIG. 23(C)). The insulating film 314 is in contact with the insulating film 314. The insulating film 314 is resistant to impurities from the outside, such as water, alkali metals, The film is made of a material that prevents alkaline earth metals and other elements from diffusing into the multilayer film, and is also water-resistant. Therefore, hydrogen in the insulating film 314 is formed simultaneously with the multilayer films 308a and 308b. When hydrogen diffuses into the multilayer film, it bonds with oxygen in the oxide semiconductor film included in the multilayer film. In addition, the insulating film 314 is formed by plasma CVD or spa When the multilayer films 308a and 308b are formed by the ion plasma deposition method, oxygen vacancies are formed. Hydrogen contained in the insulating film 314 enters the oxygen vacancy, and the carrier As a result, the oxide semiconductor film contained in the multilayer film becomes highly conductive. It functions as a conductor. In other words, it can be said to be a highly conductive oxide semiconductor film. The multilayer film 308a, 308b is mainly made of the same material as the multilayer film 308a, 308b, and the hydrogen concentration is The metal oxide having the increased conductivity due to the higher temperature than b is treated as a conductive film 308c. Call.

[0319] However, one aspect of the embodiment of the present invention is not limited to this, and the conductive film 308c In some cases, it is possible that the insulating film 314 is not in contact with the insulating film 314 .

[0320] In addition, one aspect of the embodiment of the present invention is not limited to this, and the conductive film 308c is In some cases, the multilayer film 308a or 308b may be formed in a separate process. In that case, the conductive film 308c is made of a material different from that of the multilayer films 308a and 308b. For example, the conductive film 308c may be made of indium tin oxide (hereinafter referred to as indium tin oxide). The transparent conductive film may be formed using a material other than ITO (hereinafter referred to as ITO), indium zinc oxide, or the like.

[0321] The semiconductor device described in this embodiment mode has a multilayer film of a transistor and a capacitor. In addition, a light-transmitting conductive film that functions as a pixel electrode is formed on the The other electrode is used. For this reason, a new conductive film is formed to form a capacitor element. Since a process for forming a capacitor is not required, the manufacturing process of the semiconductor device can be reduced. Since the electrodes are formed of a light-transmitting conductive film, the electrodes are light-transmitting. The aperture ratio of the pixel can be increased while increasing the area occupied by the element.

[0322] The protective films 332a, 332b, 332c, 332d, and 332e are the same as those shown in the second embodiment. The protective films 43 and 44 may be made of any suitable material and by any suitable method.

[0323] The conductive films 310a, 310b, 310c, 310d, and 310e are the same as those shown in the first embodiment. The material and manufacturing method for the pair of electrodes 21 and 22 can be appropriately used.

[0324] Insulating films 306a, 306b, 306c, multilayer films 308a, 308b, conductive films 308c, protective films 332a, 332b, 332c, 332d, 332e, and conductive film 31 An insulating film 312 and an insulating film 314 are formed on the layers 310a, 310b, 310c, 310d, and 310e. The insulating film 312 is formed in the same manner as the insulating film 306, in order to improve the interface characteristics with the multilayer film. It is preferable to use a material that can be used for the oxide insulating film 24 in Embodiment 1. Similar materials and manufacturing methods can be used as appropriate. The oxide insulating film 23 and the oxide insulating film 24 may be stacked.

[0325] The insulating film 314 is resistant to external impurities such as water, alkali metals, alkaline earth metals, etc. However, it is preferable to use a material that prevents diffusion into the multilayer film. The insulating film 25 can be made of any suitable material and by any suitable manufacturing method.

[0326] In addition, light-transmitting conductive films 316a and 316b are formed over the insulating film 314. The light-transmitting conductive film 316a is conductive in the opening 364a (see FIG. 24B). The conductive film 304b is electrically connected to the conductive film 304b, and the conductive film 304b is electrically connected to the conductive film 304b at the opening 364b (see FIG. 24(B)). That is, the conductive film 304b and the conductive film 310c are electrically connected to each other. The conductive film 316b having light-transmitting properties functions as a connection electrode. 3B). In FIG. 3B, the conductive film 310e is electrically connected to the conductive film 310e, and functions as a pixel electrode of the pixel. The light-transmitting conductive film 316b is used as the other of the pair of electrodes of the capacitor. It can function.

[0327] In order to form a connection structure in which the conductive film 304b and the conductive film 310c are in direct contact with each other, the conductive film 3 Before forming 10c, patterning is performed to form an opening in the insulating film 305. However, as shown in FIG. 6a connects the conductive film 304b and the conductive film 310c, It is no longer necessary to form a connection portion where the conductive film 310c is in direct contact, and one less photomask is required. That is, the number of manufacturing steps of the semiconductor device can be reduced.

[0328] The light-transmitting conductive films 316a and 316b are made of indium oxide containing tungsten oxide. Indium Zinc Oxide with Tungsten Oxide, Indium Zinc Oxide with Titanium Oxide Oxide, indium tin oxide with titanium oxide, ITO, indium zinc oxide, oxide ketone A light-transmitting conductive material such as indium-tin oxide doped with indium can be used. do.

[0329] In addition, a film having color (hereinafter, referred to as a color film 346) is formed on the substrate 342. The colored film 346 functions as a color filter. A light-shielding film 344 is formed on the substrate 342 and is adjacent to the light-shielding film 344. The colored film 346 does not necessarily have to be provided. For example, In some cases, such as when the device is black and white, the color film 346 may not be provided.

[0330] The colored film 346 may be any colored film that transmits light in a specific wavelength range. For example, A red (R) color filter that transmits light in the red wavelength range, and a green (G) color filter that transmits light in the green wavelength range. A green (G) color filter transmits light in the blue wavelength range, and a blue (B) color filter transmits light in the blue wavelength range. A filter or the like can be used.

[0331] The light-shielding film 344 may be made of a metal or other material as long as it has a function of blocking light in a specific wavelength range. Alternatively, an organic insulating film containing a black pigment or the like can be used.

[0332] In addition, an insulating film 348 is formed on the colored film 346. The insulating film 348 is planarized. The function of the colored film 346 is to prevent impurities contained therein from diffusing toward the liquid crystal element. It has the function of controlling

[0333] In addition, a conductive film 350 is formed on the insulating film 348. The conductive film 350 is The liquid crystal element has a function as the other of the pair of electrodes. An insulating film having a function as an alignment film is formed on the films 316a and 316b and the conductive film 350. It may be formed separately.

[0334] In addition, the liquid crystal layer 3 is provided between the conductive films 316a and 316b having light transmitting properties and the conductive film 350. The liquid crystal layer 320 is formed on the substrate 3 using a sealing material (not shown). The sealing material is used to prevent moisture from entering the device. In order to suppress oxidation, it is preferable to have a structure in which the inorganic material is in contact with the inorganic material.

[0335] In addition, a liquid crystal layer 320 is provided between the conductive films 316a and 316b having light-transmitting properties and the conductive film 350. A spacer may be provided to maintain the thickness (also called the cell gap) of the pixel.

[0336] Regarding a method for manufacturing an element portion provided on a substrate 302 shown in the semiconductor device shown in FIG. This will be explained with reference to FIG. 21 to FIG.

[0337] First, prepare a substrate 302. Here, a glass substrate is used as the substrate 302.

[0338] Next, a conductive film is formed on the substrate 302, and the conductive film is processed into a desired region. The conductive films 304a, 304b, and 304c are formed. In step c, a mask is formed by a first patterning in a desired region, and the mask is covered with the mask. It can be formed by etching the non-existent region (see FIG. 21(A)).

[0339] The conductive films 304a, 304b, and 304c are typically formed by deposition or CVD. The insulating film can be formed by a method such as sputtering or spin coating.

[0340] Next, an insulating film 305 is formed on the substrate 302 and the conductive films 304a, 304b, and 304c. Then, an insulating film 306 is formed over the insulating film 305 (see FIG. 21A).

[0341] The insulating film 305 and the insulating film 306 are formed by a sputtering method, a CVD method, or the like. When the insulating film 305 and the insulating film 306 are successively formed in a vacuum, impurities are easily removed. This is preferable because it suppresses the inclusion of

[0342] Next, a multilayer film 307 is formed on the insulating film 306 (see FIG. 21(B)).

[0343] Multilayer film 307 can be formed by sputtering, coating, pulsed laser deposition, and laser abrasion. The insulating layer can be formed by using a deposition method or the like.

[0344] Next, the multilayer film 307 is processed into desired regions to form island-shaped multilayer films 308a and 308b. , 308d are formed. The multilayer films 308a, 308b, 308d are formed in the desired regions. A mask is formed by patterning 2, and the area not covered by the mask is etched. The etching can be performed by dry etching or wet etching. Etching, or a combination of both can be used (Figure 21(C) reference).

[0345] Next, the insulating film 306 is processed into desired regions to form island-shaped insulating films 306a, 306b. , 306c are formed. The insulating films 306a, 306b, 306c are formed as a multilayer film 308a. , 308b, 308d by etching away the areas of the insulating film 306 that are not covered by the The etching can be dry etching, wet etching, or Alternatively, etching that combines both can be used (see FIG. 22(A)).

[0346] Next, a first heat treatment is performed. The first heat treatment is the same as the first heat treatment described in Embodiment 1. The first heat treatment is performed under the same conditions as in the first heat treatment. The crystallinity of the oxide semiconductor used in the insulating film 305 and the insulating films 306a and 306b are increased. , 306c, and the multilayer films 308a, 308b, 308d to remove impurities such as hydrogen and water. Note that the first heating step may be performed before etching the oxide semiconductor. good.

[0347] Next, the insulating films 306a, 306b, and 306c and the multilayer films 308a, 308b, and 308c are A conductive film 309 and a protective film 330 are formed over the substrate 302 (see FIG. 22B).

[0348] The conductive film 309 is formed by, for example, sputtering, vapor deposition, CVD, printing, or the like. It can be formed by

[0349] The protective film 330 is formed by using, for example, a sputtering method, a CVD method, or the like. can be done.

[0350] Next, the protective film 330 is processed into desired regions to form protective films 332a, 332b, and 333c. In addition, protective films 332a, 332b, 332c, 332d, and 332e are formed. 32d and 332e form a mask by a third patterning in a desired area, and the mask The mask can then be removed by etching the areas not covered by the mask. Remove the mask (see Figure 22(C)).

[0351] Next, the conductive film 309 is processed into a desired region to form conductive films 310a, 310b, and 311. In addition, the conductive films 310a, 310b, 310c, 310d, and 310e are formed. 10d and 310e are masks of the protective films 332a, 332b, 332c, 332d, and 332e. The mask functions as a mask and the area not covered by the mask is etched to form the This can be done (see FIG. 23(A)).

[0352] Next, insulating films 306a, 306b, 306c, multilayer films 308a, 308b, 308d, Conductive films 310a, 310b, 310c, 310d, and 310e, and protective films 332a and 33 An insulating film 311 is formed so as to cover the upper surfaces of the electrodes 2b, 332c, 332d, and 332e (FIG. 2). 3(B)).

[0353] The insulating film 311 can be formed by the same method as the oxide insulating film 23 and the oxide insulating film 24 described in Embodiment 1. A lamination can be formed using similar conditions.

[0354] Next, the insulating film 311 is processed into a desired region to form an insulating film 312 and an opening 362. The insulating film 312 and the opening 362 are formed in a desired region by forming a fourth patterning. forming a mask by etching the area not covered by the mask, It is possible to form (see FIG. 23(C)).

[0355] The opening 362 is formed so that the surface of the multilayer film 308d is exposed. The method for forming 2 can be, for example, a dry etching method. The method for forming the opening 362 is not limited to this, and may be a wet etching method or a drum etching method. A combination of dry etching and wet etching may also be used.

[0356] After that, a second heat treatment is performed to convert part of the oxygen contained in the insulating film 312 into the multilayer film 30. Oxygen is transferred to the oxide semiconductor films included in the multilayer films 308a and 308b. The amount of oxygen vacancies in the oxide semiconductor film can be reduced.

[0357] Next, an insulating film 313 is formed on the insulating film 312 and the multilayer film 308d (see FIG. 24(A)). (see).

[0358] The insulating film 313 is made of a material that is free of impurities from the outside, such as oxygen, hydrogen, water, alkali metals, It is preferable to use a material that prevents the alkaline earth metal or the like from diffusing into the multilayer film, and further It is preferable to use an inorganic insulating material containing hydrogen, typically containing nitrogen, such as a nitride insulating film. The insulating film 313 can be formed by using, for example, a CVD method. can.

[0359] The insulating film 313 is resistant to external impurities such as water, alkali metals, alkaline earth metals, etc. However, it is a film formed of a material that prevents diffusion of hydrogen into the multilayer film, and further contains hydrogen. When hydrogen of the insulating film 313 diffuses into the multilayer film 308d, the oxide contained in the multilayer film 308d In the semiconductor film, hydrogen bonds with oxygen, generating electrons as carriers. The oxide semiconductor film included in the multilayer film 308d has high conductivity, and the conductive film 30 The result is 8c.

[0360] In addition, the insulating film 313 is preferably formed at a high temperature in order to enhance blocking properties. For example, the substrate temperature is 100° C. or higher and lower than the distortion point of the substrate, or 300° C. or higher and 400° C. or lower. It is preferable to form the film by heating at a temperature of 30° C. Also, when forming the film at a high temperature, the multilayer film 308a, 308b, Oxygen is released from the oxide semiconductor used in 08b, causing an increase in carrier concentration. Therefore, the temperature must be set so that such a phenomenon does not occur.

[0361] Next, the insulating films 305, 312, 313 and the protective films 332c, 332e are processed in the desired regions. In this way, the insulating film 314 and the openings 364a, 364b, and 364c are formed. The insulating film 314 and the openings 364a, 364b, and 364c are formed by forming a fifth pattern in a desired area. A mask is formed by etching, and the area not covered by the mask is etched. (See FIG. 24(B)). In the case where the protective films 332c and 332e are formed of a conductive film having optical properties, It is not necessary to perform the switching.

[0362] The opening 364a is formed so that the surface of the conductive film 304b is exposed. The opening 364b is formed so as to expose the conductive film 310c. The conductive film 310e is formed so as to be exposed.

[0363] The openings 364a, 364b, and 364c can be formed, for example, by dry etching. However, the method for forming the openings 364a, 364b, and 364c may be different. The etching method is not limited to this, and may be a wet etching method or a dry etching method. A formation method in which wet etching is combined may also be used.

[0364] Next, a conductive film 31 is formed on the insulating film 314 so as to cover the openings 364a, 364b, and 364c. 5 is formed (see FIG. 25(A)).

[0365] The conductive film 315 can be formed by, for example, a sputtering method.

[0366] Next, the conductive film 315 is processed into a desired region to form a light-transmitting conductive film 316a, The light-transmitting conductive films 316a and 316b are formed in desired regions. A mask is formed by a sixth patterning, and the area not covered by the mask is etched. It can be formed by etching (see FIG. 25(B)).

[0367] Through the above steps, a pixel portion having a transistor and a driver circuit portion are formed on the substrate 302. In the manufacturing process shown in this embodiment, the first to sixth patterned This means that transistors and capacitors can be formed simultaneously using six masks. do.

[0368] In this embodiment, hydrogen contained in the insulating film 313 is diffused into the multilayer film 308d. The conductivity of the oxide semiconductor film included in the multilayer film 308d is increased. 8b is covered with a mask, and impurities, typically hydrogen, boron, phosphorus, tin, etc., are added to the multilayer film 308d. , antimony, rare gas elements, alkali metals, alkaline earth metals, etc. are added to form a multilayer film of 30 The conductivity of the oxide semiconductor film included in the multilayer film 308d may be increased. The method of adding elements such as phosphorus, tin, antimony, and rare gas elements is ion doping. On the other hand, the multilayer film 308d is formed by doping with an alkali metal, an alkaline earth metal, or the like. The impurities may be added by exposing the multilayer film 308d to a solution containing the impurities.

[0369] Next, the structure formed on the substrate 342 provided opposite the substrate 302 will be described below. Provide an explanation.

[0370] First, a substrate 342 is prepared. The substrate 342 is made of the same material as that of the substrate 302. Next, a light-shielding film 344 and a colored film 346 are formed on the substrate 342 (FIG. 26( See A).

[0371] The light-shielding film 344 and the colored film 346 are formed of various materials by a printing method, an ink-jet method, They are formed at desired positions by an etching method using photolithography technology.

[0372] Next, an insulating film 348 is formed on the light-shielding film 344 and the colored film 346 (see FIG. 26(B)). (see).

[0373] The insulating film 348 is an organic insulating film such as acrylic resin, epoxy resin, polyimide, etc. By forming the insulating film 348, for example, the colored film 346 It is possible to prevent impurities contained therein from diffusing to the liquid crystal layer 320 side. However, the insulating film 348 is not necessarily required, and a structure in which the insulating film 348 is not formed may be used. good.

[0374] Next, a conductive film 350 is formed over the insulating film 348 (see FIG. 26C). As the conductive film 315, the materials shown in the conductive film 315 can be used.

[0375] Through the above steps, the structure formed on the substrate 342 can be formed.

[0376] Next, the insulating film 31 formed on the substrate 302 and the substrate 342, more specifically, on the substrate 302, 4. The conductive films 316a and 316b having light transmitting properties and the conductive film 35 formed on the substrate 342 0, an alignment film 318 and an alignment film 352 are formed. The film can be formed by using a rubbing method, a photo-alignment method, or the like. A liquid crystal layer 320 is formed between the substrate 342 and the liquid crystal layer 320. or by bonding the substrate 302 and the substrate 342 together and then using the capillary phenomenon. An injection method for injecting liquid crystal can be used.

[0377] Through the above steps, the display device shown in FIG. 20 can be manufactured.

[0378] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0379] (Embodiment 4) In this embodiment, a transistor included in the semiconductor device described in the above embodiment is In this section, one embodiment applicable to an oxide semiconductor film will be described.

[0380] The oxide semiconductor film is an oxide semiconductor having a single crystal structure (hereinafter referred to as a single crystal oxide semiconductor). , a polycrystalline oxide semiconductor (hereinafter referred to as a polycrystalline oxide semiconductor), oxide semiconductors having an amorphous structure (hereinafter referred to as microcrystalline oxide semiconductors) and amorphous oxide semiconductors having an amorphous structure (hereinafter referred to as The oxide semiconductor film may be formed of one or more of the following: Alternatively, the oxide semiconductor film may be an amorphous oxide semiconductor film. The oxide semiconductor may be a single crystal oxide semiconductor having a conductor and crystal grains. A conductor, a polycrystalline oxide semiconductor, and a microcrystalline oxide semiconductor will be described.

[0381] <Single crystal oxide semiconductor> The single crystal oxide semiconductor film has a low impurity concentration and a low density of defect states (a small amount of oxygen vacancies). Therefore, the carrier density can be reduced. In addition, a transistor using a single crystal oxide semiconductor film has normally-on electrical characteristics. In addition, the single crystal oxide semiconductor film has a low impurity concentration and a small density of defect states. Therefore, the number of carrier traps may be reduced. The transistor has small fluctuations in electrical characteristics and is highly reliable.

[0382] Note that the oxide semiconductor film has a high density when the number of defects is small. High crystallinity increases density. In addition, the oxide semiconductor film has a low concentration of impurities such as hydrogen. The density of the single crystal oxide semiconductor film is higher than that of the CAAC-OS film. The CAAC-OS film has a higher density than the microcrystalline oxide semiconductor film. The conductor film has a higher density than the microcrystalline oxide semiconductor film. The density is higher than that of an crystalline oxide semiconductor film.

[0383] <Polycrystalline oxide semiconductor> In the polycrystalline oxide semiconductor film, crystal grains can be confirmed in the TEM image. The crystal grains contained in the crystalline oxide semiconductor film are, for example, 2 nm to 3 nm in a TEM image. 00 nm or less, 3 nm to 100 nm or 5 nm to 50 nm. In addition, in the case of a polycrystalline oxide semiconductor film, grain boundaries can often be observed in the TEM images. There is a match.

[0384] The polycrystalline oxide semiconductor film has a plurality of crystal grains, and the crystal orientation between the plurality of crystal grains is In addition, the polycrystalline oxide semiconductor film may be analyzed by, for example, an XRD apparatus. When performing out-of-plane analysis, single or multiple peaks appear. For example, in the case of a polycrystalline IGZO film, the 2θ value, which indicates the orientation, peaks at around 31°, Alternatively, multiple peaks may appear, indicating multiple types of orientation.

[0385] A polycrystalline oxide semiconductor film has high crystallinity and therefore may have high electron mobility. Therefore, a transistor using a polycrystalline oxide semiconductor film has high field-effect mobility. However, in the polycrystalline oxide semiconductor film, impurities may be segregated at grain boundaries. The grain boundaries of a polycrystalline oxide semiconductor film become defect states. Since a generation source or a trap state may occur, Compared with transistors using CAAC-OS films, the fluctuation in electrical characteristics is large and the reliability is low. In some cases, the transistor may have a low resistance.

[0386] <Microcrystalline oxide semiconductor> In the TEM image of the microcrystalline oxide semiconductor film, crystal parts can be clearly seen. The crystal parts contained in the microcrystalline oxide semiconductor film may have a size of 1 nm or more and 100 nm or more. In particular, the size of the particles is between 1 nm and 10 nm. Nanocrystals (nc) are microcrystals with a diameter of 1 to 3 nm or less. The oxide semiconductor film having nc-OS (nanocrystalline O The nc-OS film is called a T In EM images, grain boundaries may not be clearly visible.

[0387] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts, and therefore no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, XRD, which uses X-rays with a diameter larger than that of the crystal part, is used for nc-OS films. When structural analysis is performed using the out-of-plane method, the crystal planes are In addition, the nc-OS film had a diameter larger than that of the crystalline part (e.g. When electron beam diffraction (also called selected area electron beam diffraction) is performed using an electron beam with a diameter of 50 nm or more, On the other hand, for the nc-OS film, the diffraction pattern is crystalline. The electron beam diameter is close to the size of the crystal part or smaller than the crystal part (for example, 1 nm to 30 nm). When electron beam diffraction (also called nanobeam electron diffraction) is performed, spots are observed. In addition, when nanobeam electron diffraction was performed on the nc-OS film, a circular (ring-shaped) ) Bright areas may be observed. When diffraction occurs, multiple spots may be observed within the ring-shaped area.

[0388] Figure 27 shows the nanobeam electron diffraction patterns of the sample with the nc-OS film at different measurement points. In this example, the sample was cut in a direction perpendicular to the surface on which the nc-OS film was formed. The slice is cut to a thickness of 10 nm or less. In this example, the electron beam has a diameter of 1 nm. The incident light was incident from a direction perpendicular to the cut surface of the sample. However, when nanobeam electron diffraction is performed, a diffraction pattern showing the crystal planes is obtained, but It was found that no orientation to the crystal plane was observed.

[0389] The nc-OS film is an oxide semiconductor film that has higher order than an amorphous oxide semiconductor film. Therefore, the density of defect states in the nc-OS film is smaller than that in the amorphous oxide semiconductor film. However, the nc-OS film does not show any regularity in the crystal orientation between different crystal parts. The -OS film has a higher density of defect states than the CAAC-OS film.

[0390] Therefore, the nc-OS film may have a higher carrier density than the CAAC-OS film. An oxide semiconductor film having a high carrier density may have high electron mobility. In some cases, a transistor using an nc-OS film has high field-effect mobility. The nc-OS film has a higher defect density than the CAAC-OS film, and therefore the carrier transport Therefore, the transistor using the nc-OS film is - Compared to transistors using OS films, the fluctuation in electrical characteristics is large and the reliability is low. However, the nc-OS film can be formed even if it contains a relatively large amount of impurities. Therefore, it is easier to form than the CAAC-OS film, and is preferably used for some applications. Therefore, a semiconductor device having a transistor using an nc-OS film may be The device may be capable of being produced productively.

[0391] (Embodiment 5) The oxide semiconductor film disclosed in the above embodiment can be formed by sputtering. However, it may be formed by other methods, for example, thermal CVD. OCVD(Metal Organic Chemical Vapor Deposit) tion method and ALD (Atomic Layer Deposition) method. is also good.

[0392] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that no additional steps are required.

[0393] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the chamber is heated to atmospheric pressure. Alternatively, a film is formed by reacting the reactants near or on the substrate under reduced pressure and depositing the reactants on the substrate. You may go.

[0394] In addition, in the ALD method, the pressure inside the chamber is set at atmospheric pressure or reduced pressure, and the source gas for the reaction is The gases may be introduced into the chamber in sequence, and the film may be formed by repeating the gas introduction sequence. For example, by switching each switching valve (also called high-speed valve), two or more types of The above source gases are supplied to the chamber in order, and the first source gas is supplied to the chamber in order to prevent the mixture of the source gases. An inert gas (such as argon or nitrogen) is introduced simultaneously with or after the raw material gas. The second source gas is introduced. When an inert gas is introduced at the same time, the inert gas is It acts as a carrier gas, and even if an inert gas is introduced at the same time as the second source gas is introduced, In addition, the first source gas is discharged by evacuation instead of introducing an inert gas. After that, a second source gas may be introduced. The first source gas is adsorbed on the surface of the substrate to form a first layer. The first layer is deposited on the second layer by reacting with the second source gas introduced later. This process is repeated several times while controlling the gas introduction sequence until the desired thickness is reached. By doing so, a thin film with excellent step coverage can be formed. The thickness of the thin film is determined by the gas introduction. The thickness can be precisely adjusted by changing the number of times the sequence is repeated. This is suitable for producing miniature FETs.

[0395] Thermal CVD methods such as MOCVD and ALD have been disclosed in the embodiments described above. It is possible to form various films such as metal films, oxide semiconductor films, and inorganic insulating films. In the case of forming an nGaZnO film, trimethylindium, trimethylgallium, and Dimethyl zinc is used. The chemical formula for trimethyl indium is In(CH3)3. The chemical formula for trimethylgallium is Ga(CH3)3. The chemical formula for lead is Zn(CH3)2. Using triethylgallium (chemical formula Ga(C2H5)3) instead of methylgallium It is also possible to use diethylzinc (chemical formula Zn(C2H5)2) instead of dimethylzinc. It is also possible.

[0396] For example, an oxide semiconductor film, such as In-Ga-Zn- When forming an O film, In(CH3)3 gas and O3 gas are introduced in sequence. Then, Ga(CH3)3 gas and O3 gas are introduced simultaneously to form a GaO layer. Then, Zn(CH3)2 and O3 gases are introduced simultaneously to form a ZnO layer. The order of these layers is not limited to this example. A mixed compound layer such as an O layer, an In-Zn-O layer, or a Ga-Zn-O layer may be formed. Instead of O3 gas, H2O gas obtained by bubbling with an inert gas such as Ar can be used. However, it is preferable to use O3 gas that does not contain H. In(CH3)3 gas is also used. Alternatively, In(C2H5)3 gas may be used. Ga(C2H5)3 gas may be used. Also, instead of In(CH3)3 gas, In( C2H5)3 gas may be used. Also, Zn(CH3)2 gas may be used. EXAMPLES

[0397] In this example, impurity analysis and XRD analysis of an oxide semiconductor film are shown in FIGS. This will be explained using:

[0398] In this embodiment, four types of samples (hereinafter referred to as samples) were used for impurity analysis. Samples A1 to A4) were prepared.

[0399] First, a method for preparing sample A1 will be described below.

[0400] Sample A1 is a 100 nm thick In-Ga-Zn oxide film (hereinafter referred to as IG) on a glass substrate. A 60 nm thick copper film was then formed on the IGZO film, and a 100 nm thick copper film was then formed on the copper film. A 50 nm silicon nitride film was formed. After that, it was heated at 350°C for 1 hour in a nitrogen atmosphere. Processing was carried out.

[0401] The conditions for forming the IGZO film were as follows: sputtering with a metal oxide target (In:Ga:Zn=1:1:1) and the sputtering gas flow ratio was Ar / O2= The conditions used were 1 / 1, pressure 0.6 Pa, AC power 5000 W, and substrate temperature 170°C. .

[0402] Next, a method for fabricating the sample A2 will be described below.

[0403] In the case of sample A1, instead of the deposition conditions for the IGZO film, a metal oxide target (In: The sputtering gas flow ratio was Ar / O2=2 / 1. The pressure was 0.4 Pa, the DC power was 200 W, and the substrate temperature was 200°C. A 0 nm thick IGZO film was formed. This sample is designated as sample A2.

[0404] Next, a method for producing the sample A3 will be described below.

[0405] In the case of sample A1, instead of the deposition conditions for the IGZO film, a metal oxide target (In: The sputtering gas flow ratio was Ar / O2=2 / 1. The pressure was 0.4 Pa, the DC power was 200 W, and the substrate temperature was 200°C. A 0 nm thick IGZO film was formed. This sample was designated as sample A3.

[0406] Next, a method for producing the sample A4 will be described below.

[0407] In the case of sample A1, instead of the deposition conditions for the IGZO film, a metal oxide target (In: The sputtering gas flow ratio was Ar / O2=2 / 1. The pressure was 0.4 Pa, the DC power was 200 W, and the substrate temperature was 200°C. A 0 nm thick IGZO film was formed. This sample was designated as sample A4.

[0408] The impurity analysis results and XRD analysis results of samples A1 to A4 are shown in FIGS. Shown in Figure 31.

[0409] In each figure, (A) shows the results of impurity analysis, and (B) shows the results of XRD analysis. Impurity analysis was carried out using Secondary Ion Mass Spectroscopy (SIMS). Mass Spectrometry was used to measure the concentration of The analysis was performed along the direction of the film, that is, from the glass substrate side.

[0410] In FIG. 28(A), IGZO (1:1:1) is made of In, Ga, and Zn. This shows an IGZO film formed using a sputtering target with a molecular ratio of 1:1:1. In 29(A), IGZO(1:3:4) has an atomic ratio of In, Ga, and Zn of 1. IGZO film formed using a sputtering target with a ratio of 1:3:4. In IGZO (1:3:6), the atomic ratio of In, Ga, and Zn is 1:3:6. This shows an IGZO film formed using a sputtering target. IGZO(1:6:8) is a sputtered layer with an atomic ratio of In, Ga, and Zn of 1:6:8. 28(A) to 31(A) show IGZO films formed using a GaN target. ), the dashed line indicates the interface between the copper film and the IGZO film.

[0411] In the channel region of a transistor, the concentration of copper (Cu), which affects the electrical characteristics, is 1 ×10 18 atoms / cm 3 That's all.

[0412] As shown in FIG. 28(A), in the sample A1, the copper (Cu) concentration is 1×10 18 at oms / cm 3 The region is a region 30 nm from the interface between the copper film and the IGZO film toward the substrate side.

[0413] On the other hand, as shown in FIG. 29(A), in the sample A2, the copper (Cu) concentration is 1×10 1 8 atoms / cm 3 The area is 10 nm from the interface between the copper film and the IGZO film on the substrate side. be.

[0414] As shown in FIG. 30A, in the sample A3, the concentration of copper (Cu) was 1×10 1 8 atoms / cm 3 The area is 10 nm from the interface between the copper film and the IGZO film on the substrate side. be.

[0415] As shown in FIG. 31A, in the sample A4, the copper (Cu) concentration is 1×10 1 8 atoms / cm 3 The area is 10 nm from the interface between the copper film and the IGZO film on the substrate side. be.

[0416] Based on the above, we have decided to use IGZO film (1:1:1), IGZO film (1:3:4), and IGZO First, an O film (1:3:6) or an IGZO film (1:6:8) is deposited, and then a copper film is deposited on top of it. This prevents copper (Cu) from diffusing from the copper film into the IGZO film (1:1:1). can be done.

[0417] In addition, as shown in FIG. 28(B) to FIG. 31(B), in the IGZO film included in each sample, A peak is observed at 2θ of approximately 31°. This peak indicates the (009) plane. This shows that the IGZO film in each sample is a c-axis oriented film. That is, the IGZO films included in the samples A1 to A4 are CAAC-OS films and CA It is found to be AC ​​oxide.

Claims

1. A first conductive film that functions as a gate electrode of a transistor; a first nitride insulating film having a region located above the first conductive film; a first oxide insulating film having a region located above the first nitride insulating film; an oxide semiconductor film having a region in contact with an upper surface of the first oxide insulating film and a region overlapping with the first conductive film with the first nitride insulating film and the first oxide insulating film interposed therebetween; an oxide film having a region in contact with a top surface of the oxide semiconductor film and a region overlapping with the first conductive film with the first nitride insulating film, the first oxide insulating film, and the oxide semiconductor film interposed therebetween; a second conductive film having a region in contact with a top surface of the oxide film and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive film having a region in contact with an upper surface of the oxide film and functioning as the other of the source electrode and the drain electrode of the transistor; a second oxide insulating film having a region in contact with an upper surface of the oxide film, a region in contact with an upper surface of the second conductive film, and a region in contact with an upper surface of the third conductive film; a second nitride insulating film having a region located above the second oxide insulating film; a fourth conductive film having a region located above the second nitride insulating film and functioning as a pixel electrode; the fourth conductive film is electrically connected to the third conductive film, each of the second conductive film and the third conductive film has a laminated structure including a copper film; each of the first nitride insulating film and the second nitride insulating film includes silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide; each of the first oxide insulating film and the second oxide insulating film contains silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, gallium oxide, or a metal oxide containing Ga and Zn; each of the oxide semiconductor film and the oxide film contains In, Ga, and Zn; When the atomic ratio of In to Ga to Zn in the oxide film is In:Ga:Zn=x 1 :y 1 :z 1 (atomic ratio) and the atomic ratio of In to Ga to Zn in the oxide semiconductor film is In:Ga:Zn=x 2 :y 2 :z 2 (atomic ratio), y 1 / x 1 is larger than y 2 / x 2 , In the oxide film, y 1 is greater than x 1 ; the oxide semiconductor film has a crystalline portion in which a plurality of spots are observed within a ring-shaped region by nanobeam electron diffraction; the oxide film has a non-single crystal structure and has a crystal portion oriented along the c-axis; Display device.

2. A first conductive film that functions as a gate electrode of a transistor; a first nitride insulating film having a region located above the first conductive film; a first oxide insulating film having a region located above the first nitride insulating film; an oxide semiconductor film having a region in contact with an upper surface of the first oxide insulating film and a region overlapping with the first conductive film with the first nitride insulating film and the first oxide insulating film interposed therebetween; an oxide film having a region in contact with a top surface of the oxide semiconductor film and a region overlapping with the first conductive film with the first nitride insulating film, the first oxide insulating film, and the oxide semiconductor film interposed therebetween; a second conductive film having a region in contact with a top surface of the oxide film and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive film having a region in contact with an upper surface of the oxide film and functioning as the other of the source electrode and the drain electrode of the transistor; a second oxide insulating film having a region in contact with an upper surface of the oxide film, a region in contact with an upper surface of the second conductive film, and a region in contact with an upper surface of the third conductive film; a second nitride insulating film having a region located above the second oxide insulating film; a fourth conductive film having a region located above the second nitride insulating film and functioning as a pixel electrode; the fourth conductive film is electrically connected to the third conductive film, each of the second conductive film and the third conductive film has a laminated structure including a copper film; each of the first nitride insulating film and the second nitride insulating film includes silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide; each of the first oxide insulating film and the second oxide insulating film contains silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, gallium oxide, or a metal oxide containing Ga and Zn; each of the oxide semiconductor film and the oxide film contains In, Ga, and Zn; When the atomic ratio of In to Ga to Zn in the oxide film is In:Ga:Zn=x 1 :y 1 :z 1 (atomic ratio) and the atomic ratio of In to Ga to Zn in the oxide semiconductor film is In:Ga:Zn=x 2 :y 2 :z 2 (atomic ratio), y 1 / x 1 is larger than y 2 / x 2 , In the oxide film, y 1 is greater than x 1 ; In the oxide semiconductor film, y 2 is equal to or greater than x 2 ; the oxide semiconductor film has a crystalline portion in which a plurality of spots are observed within a ring-shaped region by nanobeam electron diffraction; the oxide film has a non-single crystal structure and has a crystal portion oriented along the c-axis; Display device.

3. A first conductive film that functions as a gate electrode of a transistor; a first nitride insulating film having a region located above the first conductive film; a first oxide insulating film having a region located above the first nitride insulating film; an oxide semiconductor film having a region in contact with an upper surface of the first oxide insulating film and a region overlapping with the first conductive film with the first nitride insulating film and the first oxide insulating film interposed therebetween; an oxide film having a region in contact with a top surface of the oxide semiconductor film and a region overlapping with the first conductive film with the first nitride insulating film, the first oxide insulating film, and the oxide semiconductor film interposed therebetween; a second conductive film having a region in contact with a top surface of the oxide film and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive film having a region in contact with an upper surface of the oxide film and functioning as the other of the source electrode and the drain electrode of the transistor; a second oxide insulating film having a region in contact with an upper surface of the oxide film, a region in contact with an upper surface of the second conductive film, and a region in contact with an upper surface of the third conductive film; a second nitride insulating film having a region located above the second oxide insulating film; a fourth conductive film having a region located above the second nitride insulating film and having a function as a pixel electrode and a function as one electrode of a capacitance element; the fourth conductive film is electrically connected to the third conductive film, each of the second conductive film and the third conductive film has a laminated structure including a copper film; each of the first nitride insulating film and the second nitride insulating film includes silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide; each of the first oxide insulating film and the second oxide insulating film contains silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, gallium oxide, or a metal oxide containing Ga and Zn; each of the oxide semiconductor film and the oxide film contains In, Ga, and Zn; When the atomic ratio of In to Ga to Zn in the oxide film is In:Ga:Zn=x 1 :y 1 :z 1 (atomic ratio) and the atomic ratio of In to Ga to Zn in the oxide semiconductor film is In:Ga:Zn=x 2 :y 2 :z 2 (atomic ratio), y 1 / x 1 is larger than y 2 / x 2 , In the oxide film, y 1 is greater than x 1 ; the oxide semiconductor film has a crystalline portion in which a plurality of spots are observed within a ring-shaped region by nanobeam electron diffraction; the oxide film has a non-single crystal structure and has a crystal portion oriented along a c-axis, a fifth conductive film having a region located below the fourth conductive film and functioning as the other electrode of the capacitor element; the fifth conductive film contains indium tin oxide; Display device.

4. A first conductive film that functions as a gate electrode of a transistor; a first nitride insulating film having a region located above the first conductive film; a first oxide insulating film having a region located above the first nitride insulating film; an oxide semiconductor film having a region in contact with an upper surface of the first oxide insulating film and a region overlapping with the first conductive film with the first nitride insulating film and the first oxide insulating film interposed therebetween; an oxide film having a region in contact with a top surface of the oxide semiconductor film and a region overlapping with the first conductive film with the first nitride insulating film, the first oxide insulating film, and the oxide semiconductor film interposed therebetween; a second conductive film having a region in contact with a top surface of the oxide film and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive film having a region in contact with an upper surface of the oxide film and functioning as the other of the source electrode and the drain electrode of the transistor; a second oxide insulating film having a region in contact with an upper surface of the oxide film, a region in contact with an upper surface of the second conductive film, and a region in contact with an upper surface of the third conductive film; a second nitride insulating film having a region located above the second oxide insulating film; a fourth conductive film having a region located above the second nitride insulating film and having a function as a pixel electrode and a function as one electrode of a capacitance element; the fourth conductive film is electrically connected to the third conductive film, each of the second conductive film and the third conductive film has a laminated structure including a copper film; each of the first nitride insulating film and the second nitride insulating film includes silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide; each of the first oxide insulating film and the second oxide insulating film contains silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, gallium oxide, or a metal oxide containing Ga and Zn; each of the oxide semiconductor film and the oxide film contains In, Ga, and Zn; When the atomic ratio of In to Ga to Zn in the oxide film is In:Ga:Zn=x 1 :y 1 :z 1 (atomic ratio) and the atomic ratio of In to Ga to Zn in the oxide semiconductor film is In:Ga:Zn=x 2 :y 2 :z 2 (atomic ratio), y 1 / x 1 is larger than y 2 / x 2 , In the oxide film, y 1 is greater than x 1 ; In the oxide semiconductor film, y 2 is equal to or greater than x 2 ; the oxide semiconductor film has a crystalline portion in which a plurality of spots are observed within a ring-shaped region by nanobeam electron diffraction; the oxide film has a non-single crystal structure and has a crystal portion oriented along a c-axis, a fifth conductive film having a region located below the fourth conductive film and functioning as the other electrode of the capacitor element; the fifth conductive film contains indium tin oxide; Display device.

5. A first conductive film that functions as a gate electrode of a transistor; a first nitride insulating film having a region located above the first conductive film; a first oxide insulating film having a region located above the first nitride insulating film; an oxide semiconductor film having a region in contact with an upper surface of the first oxide insulating film and a region overlapping with the first conductive film with the first nitride insulating film and the first oxide insulating film interposed therebetween; an oxide film having a region in contact with a top surface of the oxide semiconductor film and a region overlapping with the first conductive film with the first nitride insulating film, the first oxide insulating film, and the oxide semiconductor film interposed therebetween; a second conductive film having a region in contact with a top surface of the oxide film and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive film having a region in contact with an upper surface of the oxide film and functioning as the other of the source electrode and the drain electrode of the transistor; a second oxide insulating film having a region in contact with an upper surface of the oxide film, a region in contact with an upper surface of the second conductive film, and a region in contact with an upper surface of the third conductive film; a second nitride insulating film having a region located above the second oxide insulating film; a fourth conductive film having a region located above the second nitride insulating film and functioning as a pixel electrode; the fourth conductive film is electrically connected to the third conductive film, each of the second conductive film and the third conductive film has a laminated structure including a copper film; each of the first nitride insulating film and the second nitride insulating film includes silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide; each of the first oxide insulating film and the second oxide insulating film contains silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, gallium oxide, or a metal oxide containing Ga and Zn; each of the oxide semiconductor film and the oxide film contains In, Ga, and Zn; an atomic ratio of Ga to In in the oxide film is larger than an atomic ratio of Ga to In in the oxide semiconductor film; In the oxide film, the atomic ratio of Ga is larger than the atomic ratio of In, the oxide semiconductor film has a crystalline portion in which a plurality of spots are observed within a ring-shaped region by nanobeam electron diffraction; the oxide film has a non-single crystal structure and has a crystal portion oriented along the c-axis; Display device.

6. A first conductive film that functions as a gate electrode of a transistor; a first nitride insulating film having a region located above the first conductive film; a first oxide insulating film having a region located above the first nitride insulating film; an oxide semiconductor film having a region in contact with an upper surface of the first oxide insulating film and a region overlapping with the first conductive film with the first nitride insulating film and the first oxide insulating film interposed therebetween; an oxide film having a region in contact with a top surface of the oxide semiconductor film and a region overlapping with the first conductive film with the first nitride insulating film, the first oxide insulating film, and the oxide semiconductor film interposed therebetween; a second conductive film having a region in contact with a top surface of the oxide film and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive film having a region in contact with an upper surface of the oxide film and functioning as the other of the source electrode and the drain electrode of the transistor; a second oxide insulating film having a region in contact with an upper surface of the oxide film, a region in contact with an upper surface of the second conductive film, and a region in contact with an upper surface of the third conductive film; a second nitride insulating film having a region located above the second oxide insulating film; a fourth conductive film having a region located above the second nitride insulating film and functioning as a pixel electrode; the fourth conductive film is electrically connected to the third conductive film, each of the second conductive film and the third conductive film has a laminated structure including a copper film; each of the first nitride insulating film and the second nitride insulating film includes silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide; each of the first oxide insulating film and the second oxide insulating film contains silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, gallium oxide, or a metal oxide containing Ga and Zn; each of the oxide semiconductor film and the oxide film contains In, Ga, and Zn; an atomic ratio of Ga to In in the oxide film is larger than an atomic ratio of Ga to In in the oxide semiconductor film; In the oxide film, the atomic ratio of Ga is larger than the atomic ratio of In, in the oxide semiconductor film, an atomic ratio of Ga is equal to or greater than an atomic ratio of In, the oxide semiconductor film has a crystalline portion in which a plurality of spots are observed within a ring-shaped region by nanobeam electron diffraction; the oxide film has a non-single crystal structure and has a crystal portion oriented along the c-axis; Display device.

7. A first conductive film that functions as a gate electrode of a transistor; a first nitride insulating film having a region located above the first conductive film; a first oxide insulating film having a region located above the first nitride insulating film; an oxide semiconductor film having a region in contact with an upper surface of the first oxide insulating film and a region overlapping with the first conductive film with the first nitride insulating film and the first oxide insulating film interposed therebetween; an oxide film having a region in contact with a top surface of the oxide semiconductor film and a region overlapping with the first conductive film with the first nitride insulating film, the first oxide insulating film, and the oxide semiconductor film interposed therebetween; a second conductive film having a region in contact with a top surface of the oxide film and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive film having a region in contact with an upper surface of the oxide film and functioning as the other of the source electrode and the drain electrode of the transistor; a second oxide insulating film having a region in contact with an upper surface of the oxide film, a region in contact with an upper surface of the second conductive film, and a region in contact with an upper surface of the third conductive film; a second nitride insulating film having a region located above the second oxide insulating film; a fourth conductive film having a region located above the second nitride insulating film and having a function as a pixel electrode and a function as one electrode of a capacitance element; the fourth conductive film is electrically connected to the third conductive film, each of the second conductive film and the third conductive film has a laminated structure including a copper film; each of the first nitride insulating film and the second nitride insulating film includes silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide; each of the first oxide insulating film and the second oxide insulating film contains silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, gallium oxide, or a metal oxide containing Ga and Zn; each of the oxide semiconductor film and the oxide film contains In, Ga, and Zn; an atomic ratio of Ga to In in the oxide film is larger than an atomic ratio of Ga to In in the oxide semiconductor film; In the oxide film, the atomic ratio of Ga is larger than the atomic ratio of In, the oxide semiconductor film has a crystalline portion in which a plurality of spots are observed within a ring-shaped region by nanobeam electron diffraction; the oxide film has a non-single crystal structure and has a crystal portion oriented along a c-axis, a fifth conductive film having a region located below the fourth conductive film and functioning as the other electrode of the capacitor element; the fifth conductive film contains indium tin oxide; Display device.

8. A first conductive film that functions as a gate electrode of a transistor; a first nitride insulating film having a region located above the first conductive film; a first oxide insulating film having a region located above the first nitride insulating film; an oxide semiconductor film having a region in contact with an upper surface of the first oxide insulating film and a region overlapping with the first conductive film with the first nitride insulating film and the first oxide insulating film interposed therebetween; an oxide film having a region in contact with a top surface of the oxide semiconductor film and a region overlapping with the first conductive film with the first nitride insulating film, the first oxide insulating film, and the oxide semiconductor film interposed therebetween; a second conductive film having a region in contact with a top surface of the oxide film and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive film having a region in contact with an upper surface of the oxide film and functioning as the other of the source electrode and the drain electrode of the transistor; a second oxide insulating film having a region in contact with an upper surface of the oxide film, a region in contact with an upper surface of the second conductive film, and a region in contact with an upper surface of the third conductive film; a second nitride insulating film having a region located above the second oxide insulating film; a fourth conductive film having a region located above the second nitride insulating film and having a function as a pixel electrode and a function as one electrode of a capacitance element; the fourth conductive film is electrically connected to the third conductive film, each of the second conductive film and the third conductive film has a laminated structure including a copper film; each of the first nitride insulating film and the second nitride insulating film includes silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide; each of the first oxide insulating film and the second oxide insulating film contains silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, gallium oxide, or a metal oxide containing Ga and Zn; each of the oxide semiconductor film and the oxide film contains In, Ga, and Zn; an atomic ratio of Ga to In in the oxide film is larger than an atomic ratio of Ga to In in the oxide semiconductor film; In the oxide film, the atomic ratio of Ga is larger than the atomic ratio of In, in the oxide semiconductor film, an atomic ratio of Ga is equal to or greater than an atomic ratio of In, the oxide semiconductor film has a crystalline portion in which a plurality of spots are observed within a ring-shaped region by nanobeam electron diffraction; the oxide film has a non-single crystal structure and has a crystal portion oriented along a c-axis, a fifth conductive film having a region located below the fourth conductive film and functioning as the other electrode of the capacitor element; the fifth conductive film contains indium tin oxide; Display device.

9. In any one of claims 3, 4, 7 and 8, the fourth conductive film has a region in contact with an upper surface of the second nitride insulating film, the second nitride insulating film has a region in contact with an upper surface of the fifth conductive film; Display device.

10. In any one of claims 1 to 9, the oxide semiconductor film has a crystal part with a thickness of 1 nm to 10 nm. Display device.

11. In any one of claims 1 to 10, the y 1 / x 1 is 1.5 times or more larger than the y 2 / x 2 ; Display device.

12. In any one of claims 1 to 10, the y 1 / x 1 is at least twice as large as the y 2 / x 2 ; Display device.

13. In any one of claims 1 to 10, the y 1 / x 1 is three times or more larger than the y 2 / x 2 ; Display device.

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