Display device

Abstract

To measure the luminance deterioration of a light-emitting element.SOLUTION: A pixel circuit includes a light-emitting element, a power source line that applies a power source voltage to feed current in the light-emitting element, a driving transistor that controls an amount of emission current to the light-emitting element in image display, a gate connected to one end of the light-emitting element, and a sense transistor that applies a source voltage to a sense line and constitutes a part of a sense circuit. The driving transistor controls the sense current from the power source line to the light-emitting element in order to measure the voltage at one end of the light-emitting element. The sense transistor applies the source voltage in a state in which the sense current is applied to the light-emitting element, to the sense line. A measurement circuit determines the voltage of the light-emitting element on the basis of the output of the sense line.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to display devices, and more particularly to measuring the luminance degradation of light-emitting elements. [Background technology]

[0002] OLED (Organic Light-Emitting Diode) elements are current-driven self-luminous elements that do not require a backlight, and have the advantages of low power consumption, a wide viewing angle, and a high contrast ratio, making them promising for the development of flat panel displays.

[0003] In light-emitting elements such as OLED elements, irreversible characteristic changes occur that affect the lighting lifespan. Specifically, problems such as burn-in or afterimages, where traces of a fixed display are constantly visible, occur. One example of a method for eliminating or reducing this problem is to compensate for the luminance degradation of the OLED elements. This method estimates the degree of degradation of each OLED element, and performs light emission control to correct the luminance according to the degree of degradation. This makes it possible to reduce the luminance difference between pixels caused by the degradation of the OLED elements. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent Application Publication No. 2022 / 0114960 [Patent Document 2] US Patent Application Publication No. 2019 / 0279566 [Patent Document 3] U.S. Patent Application Publication No. 2011 / 0164011 Summary of the Invention [Problem to be solved by the invention]

[0005] The luminance degradation of the light-emitting element can be estimated from the change in the current-voltage characteristics of the light-emitting element. One example of luminance degradation measurement is to supply a constant current from an external current source to the OLED element via a sense line outside the image display period (at startup or during the blanking period) and measure the voltage at the monitor point (OLED anode) in the pixel.

[0006] Since it takes time to charge the line capacitance of the sense line, if the sense current supplied is small, a long time is required for measurement. Increasing the sense current shortens the time, but the voltage drop of the selection switch transistor increases, making it difficult to perform normal measurement. If the channel width of the selection switch transistor is increased to avoid this, the pixel layout becomes more difficult. [Means for solving the problem]

[0007] A display device according to one embodiment of the present disclosure includes a plurality of pixel circuits on a substrate, a sense line on the substrate, and a measurement circuit, each pixel circuit of the plurality of pixel circuits includes a light-emitting element, a first power supply line that provides a power supply voltage for flowing current to the light-emitting element, a drive transistor that controls the amount of light-emitting current to the light-emitting element, a sense transistor having a gate electrode connected to one end of the light-emitting element, a second power supply line connected to a drain electrode of the sense transistor, and a first switch transistor connected between a source electrode of the sense transistor and the sense line, the sense transistor, the first power supply, and the second power supply line are included in a sense circuit, the drive transistor controls a sense current from the first power supply line to the light-emitting element in order to measure a voltage at one end of the light-emitting element, the sense transistor provides a source voltage to the sense line when the sense current is provided to the light-emitting element, and the measurement circuit determines the voltage of the light-emitting element based on an output of the sense line. Effect of the Invention

[0008] According to one aspect of the present disclosure, it is possible to quickly and accurately measure the luminance degradation of a light-emitting element. [Brief description of the drawings]

[0009] [Figure 1] 2A and 2B show schematic configuration examples of a display panel included in an OLED display device. [Diagram 2] 2 shows a schematic diagram of a configuration example of a pixel circuit and a circuit for measuring deterioration of an OLED element in the pixel circuit. [Diagram 3] 2A and 2B show schematic configuration examples of a display panel included in an OLED display device. [Figure 4] 1 shows an example of a circuit configuration for measuring degradation of an OLED element, including a CDS circuit. [Diagram 5] 11 is a timing chart showing changes over time of several control signals when reading out a reference signal. [Figure 6] 4 shows the ON / OFF states of transistors in the pixel circuit and the CDS circuit during a period PR1. [Figure 7] 11 is a timing chart showing changes over time of several control signals when reading out a reference signal. [Figure 8] 4 shows the ON / OFF states of the transistors in the pixel circuit and the CDS circuit in a period PR2. [Figure 9] The time variations of the signals S2, Em, SSS, Φa, and Φb are shown. [Figure 10] 5 shows a control timing chart of the 7T1C pixel circuit and the CDS circuit shown in FIG. 4 when the pulse width of the signal Em is set to 5H. [Figure 11] 1 illustrates an example of a pixel circuit to which the OLED element degradation measurement according to an embodiment of the present specification can be applied. [Figure 12] 12 shows a timing chart of control signals for measuring an anode voltage in the pixel circuit shown in FIG. [Figure 13] 1 illustrates an example of a pixel circuit to which the OLED element degradation measurement according to an embodiment of the present specification can be applied. [Figure 14] 14 shows a timing chart of control signals for measuring an anode voltage in the pixel circuit shown in FIG. [Figure 15]1 shows a configuration example in which the sense line is divided into upper and lower parts to reduce the sense line capacitance. [Figure 16] In this configuration example, each pixel circuit column is divided into a pixel circuit group consisting of odd-numbered pixel circuits and a pixel circuit group consisting of even-numbered pixel circuits, and these are connected to different sense lines. [Figure 17] The following shows the results of a simulation using the Monte Carlo method to calculate the changes in the sense line voltage and the data signal voltage of the output of the CDS circuit at different threshold voltages Vth of the sense transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the embodiment is merely an example for implementing the present disclosure and does not limit the technical scope of the present disclosure.

[0011] A display device according to an embodiment of the present specification measures the luminance degradation of a light-emitting element. The luminance degradation of a light-emitting element can be estimated from a change in the current-voltage characteristics of the light-emitting element. An example of the luminance degradation measurement is to supply a constant current to an OLED element via a sense line outside the image display period (at start-up or during a blanking period) and measure the voltage of a monitor point in a pixel (the OLED anode in the example described below).

[0012] Since it takes time to charge the line capacitance of the sense line, if the sense current supplied is small, a long time is required for measurement. Increasing the sense current shortens the time, but the voltage drop of the selection switch transistor increases, making it difficult to perform normal measurement. If the channel width of the selection switch transistor is increased to avoid this, the pixel layout becomes more difficult.

[0013] In one embodiment of the present disclosure, a sense current for measuring the voltage of a light-emitting element is generated from a power supply line that supplies a power supply voltage used in a pixel circuit, and is supplied to the light-emitting element. A circuit for reading out the voltage of the light-emitting element includes a sense circuit made up of a source follower circuit. The sense circuit includes a sense transistor having a gate connected to a monitor point. The source of the sense transistor is connected to the sense line directly or via a switch transistor, and a constant current is applied to the sense line.

[0014] Since the sense current is generated within the pixel circuit, the effect of the sense line capacitance on the time constant is small even if the sense current is low, and measurement can be performed in a short time. In addition, since the monitor voltage is input to the gate of the sense transistor, no current flows and a voltage drop in the sense transistor can be avoided. An embodiment of the present disclosure further uses a correlated double sampling (CDS) circuit to measure the voltage of the light-emitting element. This makes it possible to effectively correct the threshold voltage Vth variation of the sense transistor. <First embodiment> [Display panel configuration]

[0015] A display device according to an embodiment of the present specification will be described. In order to make the description easier to understand, the dimensions and shapes of the objects shown in the drawings may be exaggerated. In the following, an OLED display device will be described as an example of the display device. The characteristic measurement of the light-emitting element of the present disclosure can be applied to a current-driven light-emitting element different from an OLED element, for example, an inorganic LED element.

[0016] Fig. 1 shows a schematic configuration example of a display panel 100 included in an OLED display device. The OLED display device 10 includes a display area 125 consisting of a plurality of pixel circuits 210 arranged on an insulating substrate. In Fig. 1, one pixel circuit is indicated by reference numeral 210 as an example. Drive circuits for the pixel circuits 210 are arranged around the display area 125. Specifically, display vertical scanning circuits 131A and 131B, a sense signal vertical scanning circuit 132, a horizontal scanning circuit 133, and a data line driving circuit 134 are arranged.

[0017] 1, the sense signal vertical scanning circuit 132 is disposed on the left side of the display area 125, and the display vertical scanning circuits 131A and 131B are disposed on the right side of the display area 125. The horizontal scanning circuit 133 is disposed above the display area 125, and the data line driving circuit 134 is disposed below the display area 125.

[0018] The pixel circuit 210 includes an OLED element (light-emitting element) and a TFT (Thin Film Transistor) circuit for controlling the light emission or measuring deterioration. In the configuration example of FIG. 1, the display area 125 is composed of M pixel circuit rows each composed of a plurality of pixel circuits 210 arranged along the X-axis. The pixel circuit rows are arranged along the Y-axis. The pixel circuit rows are pixel circuit lines. For example, the pixel circuits constituting each pixel circuit row are connected to one or more common selection lines (control lines) and are controlled at the same timing.

[0019] Moreover, the display area 125 is configured with N pixel circuit columns, each of which is configured with pixel circuits 210 arranged along the Y axis. The pixel circuit columns are arranged along the X axis. The layout of the pixel circuits 210 can be determined arbitrarily depending on the design. A pixel row or a pixel column is a pixel line. The pixel circuits constituting each pixel circuit column are connected to, for example, the same data line, and a data signal is written from the same data line to sequentially selected pixel circuits.

[0020] The OLED element of each pixel circuit 210 emits light of a specific color. For example, the light emission color of all pixel circuits 210 may be white, or as illustrated in FIG. 1, each pixel circuit 210 may emit light of any of the colors red, green, or blue. In the example illustrated in FIG. 1, each pixel circuit column includes an OLED element of a common color. The pixel circuits 210 constituting the display area 125 display an image according to image data from the outside.

[0021] The display vertical scanning circuits 131A and 131B write data signals for image display to the pixel circuits 210 and output a plurality of selection signals for pixel circuit rows for turning light emission ON / OFF. For ease of illustration, scanning lines for transmitting selection signals from the display vertical scanning circuits 131A and 131B to the pixel circuits 210 of the pixel circuit rows are omitted in Fig. 1. The scanning lines are connected to terminals of the display vertical scanning circuit 131A or 131B and one or a plurality of pixel circuit rows.

[0022] The data line driving circuit 134 outputs a data signal that specifies the light emission brightness of the OLED element according to the grayscale level of the display image (frame) to the pixel circuit row selected for image display. For ease of illustration, data lines that transmit data signals from the data line driving circuit 134 to the pixel circuits 210 selected in the pixel circuit column are omitted in Fig. 1. The data lines are connected to the terminals of the data line driving circuit 134 and the pixel circuit column.

[0023] Each pixel circuit row is connected to a common sense scan line SS extending along the X-axis. In Fig. 1, one sense scan line is indicated by the symbol SS as an example. The sense scan line SS is driven by a sense signal vertical scanning circuit 132. The sense signal vertical scanning circuit 132 outputs a selection signal for the pixel circuit row for measuring deterioration of the OLED element of the pixel circuit 210. Each pixel circuit 210 includes a selection switch transistor M9, which is turned ON / OFF in response to the selection signal transmitted by the sense scan line SS.

[0024] The horizontal scanning circuit 133 outputs a selection signal for a pixel circuit column to measure deterioration of the OLED element of the pixel circuit 210. The selection signal turns on a selected selection switch transistor M10. The transistor M10 is connected to one sense line SL extending along the Y axis, and the sense line SL is connected to each of the transistors M9 (pixel circuits 210) in one pixel column. In FIG. 1, one transistor is designated by the symbol M10 as an example.

[0025] The sense lines SL transmit sense signals indicating the degree of deterioration of the selected OLED elements. The horizontal scanning circuit 133 selects the sense lines SL from which to capture the sense signals, i.e., the pixel columns. In FIG. 1, one sense line is indicated by the symbol SL as an example.

[0026] In the configuration example of FIG. 1, each terminal of the horizontal scanning circuit 133 is connected to the transistors M10 of three pixel columns, red, blue, and green, and these pixel columns are selected simultaneously. The transistors M10 of the pixel columns of each color are connected to a transmission line to a common output terminal 101. There are three output terminals 101 that output signals of the red, blue, and green pixel circuits. In FIG. 1, one output terminal is indicated by the reference numeral 101 as an example. The transistor M10 selects a sense line SL that is conductive with each output terminal 101 and outputs the signal. A sense signal that indicates deterioration of the OLED element and is read from the sense line SL is transmitted from the output terminal 101 to an external control circuit. Note that a circuit including the external control circuit and the drive circuit of the display panel may be called a control drive circuit. [OLED element degradation measurement]

[0027] The pixel circuit 210 includes an OLED element, and controls the luminance of the OLED element by controlling the current supplied to the anode electrode of the OLED element. Fig. 2 shows a schematic configuration example of the pixel circuit 210 and a circuit for measuring the deterioration of the OLED element in the pixel circuit.

[0028] The pixel circuit 210 includes an OLED element E1, nine thin film transistors (TFTs) M1 to M9, and a storage capacitor Cst. The pixel circuit 210 controls the emission of the OLED element E1 and also operates to measure deterioration of the OLED element E1 in the pixel circuit 210. The deterioration measurement measures the current-voltage characteristics of the OLED element E1. In this example, the transistors M1 to M9 are P-type, and the transistors other than the transistor M3 are switch transistors.

[0029] The transistor M3 is a drive transistor that controls the amount of current to the OLED element E1. The drive transistor M3 controls the amount of current provided to the OLED element E1 from the power supply line VDDL that provides the anode power supply voltage VDD according to the voltage held by the storage capacitor Cst. The cathode of the OLED element E1 is connected to the power supply line that provides the cathode power supply voltage VEE. The storage capacitor Cst holds the gate-source voltage (also simply called the gate voltage) of the transistor M3.

[0030] The transistors M1 and M6 control whether or not the OLED element E1 emits light. The transistor M1 turns on / off the current supply from the anode power line VDDL to the drive transistor M3. The transistor M6 turns on / off the current supply from the drive transistor M3 to the OLED element E1. The transistors M1 and M6 are each controlled by a light emission control signal Em from the display vertical scanning circuit 131A or 131B.

[0031] The transistor M5 controls whether or not a reference voltage is supplied to the gate voltage of the drive transistor M3. When the transistor M5 is turned on by a selection signal S1 from the display vertical scanning circuit 131A or 131B, it supplies a reference voltage Vref from a reference power line to the gate of the drive transistor M3. The reference voltage Vref is a constant voltage that is lower than the power supply voltage VDD, for example, equal to or higher than the power supply voltage VEE.

[0032] The transistor M2 is a selection transistor for selecting the pixel circuit 210 to which a data signal is supplied. The gate voltage of the transistor M2 is controlled by a selection signal S2 from the display vertical scanning circuit 131A or 131B. When the selection transistor M2 is ON, it supplies a data signal Vdata from the data line to the gate (storage capacitance Cst) of the drive transistor M3.

[0033] In this example, the selection transistor M2 (source and drain) is connected between the data line and the source of the drive transistor M3. Furthermore, the transistor M4 (source and drain) is connected between the drain and gate of the drive transistor M3. The transistor M4 operates to compensate for variations in the threshold voltage of the drive transistor M3. A data signal from the data line 105 is applied to the storage capacitor Cst via the selection transistor M2, the drive transistor M3, and the transistor M4, which are ON. The storage capacitor Cst holds a voltage obtained by adding the threshold voltage Vth of the drive transistor M3 to the data signal.

[0034] The transistor M7 controls whether or not a reset voltage Vrst is supplied to the anode of the OLED element E1. When the transistor M7 is turned on by a selection signal S2 from the display vertical scanning circuit 131A or 131B, the reset voltage Vrst is applied to the anode of the OLED element E1 from the reset power line. The reset voltage Vrst is a constant voltage that is lower than the power supply voltage VDD, for example, equal to or higher than the power supply voltage VEE.

[0035] The transistor M8 is a sense TFT for measuring the anode voltage of the OLED element E1 in order to measure the deterioration of the OLED element E1. The gate of the transistor M8 is connected to a sense node between the anode of the OLED element E1 and the transistor M6, and is given the anode voltage of the OLED element E1. In the deterioration measurement of the OLED element E1, the anode voltage is represented by Vf.

[0036] As shown in Fig. 2, a sense current SC for measuring deterioration of the OLED element E1 is applied from a power supply line VDDL via transistors M1, M3, and M6. The amount of the sense current SC is a predetermined value. The path of the sense current SC is the same as the current path to the OLED element E1 in normal image display. This reduces the parasitic capacitance on the path of the sense current, and shortens the time required for measuring deterioration.

[0037] A reference voltage Vref is applied to the drain of transistor M8, and the source is connected to the drain of transistor M9. The source of transistor M9 is connected to a sense line SL. The gate of transistor M9 is connected to a sense scan line SS and is controlled by a selection signal SSS from a sense signal vertical scanning circuit 132. The supply line of the reference voltage Vref, transistor M8, and transistor M9 are arranged for each pixel to constitute a sense circuit 310.

[0038] The sense line SL has a sense line capacitance (parasitic capacitance) Cp. The drain of the transistor M10 is connected to the sense line SL, and the source is connected to the output terminal 101. The gate of the transistor M10 is controlled by a selection signal SSC from the horizontal scanning circuit 133. The transistors M9 and M10P are switches that select the pixel circuit 210 that measures the characteristics of the OLED element E1.

[0039] The control circuit 300 is installed, for example, outside the display panel 100. The control circuit 300 generates a data signal for displaying an image corresponding to the image data in the display area 125 from image data from the outside, and controls the drive circuits 131A, 131B, and 134. The control circuit 300 controls the sense signal vertical scanning circuit 132 to measure the OLED element E1, and further acquires a signal indicating the characteristics of the OLED element E1 via the sense line SL. The control circuit 300 determines a data signal to be provided to the pixel circuit 210 in accordance with the OLED element E1.

[0040] The control circuit 300 performs degradation measurement of the OLED element E1. The degradation measurement is performed, for example, in a mode different from normal image display. The degradation measurement may be performed, for example, in response to a user's instruction, or may be automatically performed by the control circuit 300 after startup and before the start of normal display according to video data.

[0041] The control circuit 300 measures the voltage VOUT output from the output terminal 101 via the sense line SL. In the deterioration measurement of the OLED element E1, after a data signal for deterioration measurement is written to the storage capacitance Cst, the transistors M1, M6, M8, M9, and M10 are turned ON and the transistors M2, M4, M5, and M7 are turned OFF.

[0042] A predetermined sense current SC flows from a power supply line VDDL to the OLED element E1, and the anode voltage of the OLED element E1 is represented by Vf. In this embodiment, the anode voltage Vf of the OLED element E1 is measured using a sense circuit 310. This makes it possible to reduce the delay and the measurement time even when the sense current is small.

[0043] A reference voltage Vref lower than the power supply voltage VDD is applied to the drain of the transistor M8. The control circuit 300 supplies a constant current Is, which is substantially determined by the resistor RL, the power supply voltage VDD, and the reference voltage Vref, to the sense line SL. The anode of the OLED element E1 is connected to the gate of the transistor M8. The source of the transistor M8 is connected to the drain of the transistor M9. The source voltage of the transistor M8 is (Vf-Vth), where Vth is the threshold voltage of the transistor M8. The sense voltage VOUT is (Vf-Vth+Ron×Is), which is the source voltage of the transistor M8 plus a voltage drop (Ron×Is) due to the product of the on-resistance Ron and the constant current Is of the transistor M9. The circuit configuration of the constant current source to the sense line is arbitrary and is not limited to this example.

[0044] Since transistors M8 and M9 are arranged for each pixel circuit, the sense voltage VOUT may vary between pixel circuits due to the influence of the threshold voltage Vth of transistor M8 and the on-resistance Ron of transistor M9. The column selection switch transistor M10 is arranged on the periphery of the display area 125, allowing the channel width to be large, so that the voltage drop due to the on-resistance is sufficiently low and the variation between columns is negligible.

[0045] The input / output gain G of the sense circuit 310 is defined by the ratio of the output voltage (sense voltage) VOUT and the input voltage VIN (anode voltage Vf) of the sense circuit 310. That is, G = (VIN-Vth+Ron×Is) / VIN 2, when the transistor is P-type, VIN is negative, Vth is negative, and Ron×Is is positive, so the input / output gain G is less than 1. When the transistor is N-type, VIN is positive, Vth is positive, and Ron×Is is negative, so G is similarly less than 1.

[0046] As a method of correcting the variations, for example, the control circuit 300 stores in memory the value of the sense voltage VOUT before deterioration of each pixel circuit 210 (each OLED element E1) and calculates the difference between the sense voltage in the measurement after deterioration, thereby reducing the influence of the threshold voltage Vth and the on-resistance Ron on the deterioration measurement. Note that if the threshold voltage does not substantially affect the deterioration measurement or the variations between pixel circuits can be ignored, correction of the deterioration measurement result is not necessary.

[0047] Alternatively, the control circuit 300 can eliminate the influence of variations by storing information on the input / output gain G of each sense circuit 310 in a memory and correcting the measured value of the sense voltage VOUT of each pixel. <Second embodiment>

[0048] Another embodiment of the degradation measurement of the OLED element will be described below. In the following, the differences from the first embodiment will be mainly described. In this embodiment, in addition to the source follower circuit, a correlated double sampling (CDS) circuit is used for degradation measurement of the OLED element to correct the sense voltage VOUT. As described above, the sense voltage VOUT is affected by the threshold voltage of the sense transistor and the on-resistance Ron of the transistor M9. The CDS circuit performs the correction with an analog voltage when the signal is acquired. This eliminates the need for the control circuit 300 to store an initial value in advance, and also makes it possible to correct the change over time in the threshold voltage Vth and the on-resistance Ron of the transistor M9.

[0049] FIG. 3 is a schematic diagram showing an example of the configuration of a display panel 100 included in an OLED display device. A CDS circuit 320 is added to the configuration of the display panel shown in FIG. 1. The CDS circuit 320 is arranged for each sense line. That is, each CDS circuit 320 is arranged between each sense line SL and the transistor M10. In this way, by arranging the CDS circuit 320 on the display panel 100, more accurate measurement is possible and implementation in the control circuit 300 is not required. Note that one CDS circuit may perform correction for multiple sense lines.

[0050] 4 shows an example of a circuit configuration for measuring deterioration of an OLED element E1, including a CDS circuit 320. Compared to the circuit configuration example shown in FIG. 2, a CDS circuit 320 is added. Also, a resistor RL that provides a constant current to the sense line SL is disposed on an insulating substrate of the display panel 100. Note that some components on the display panel 100, such as the VDD wiring of the source follower circuit, the resistor RL, and the transmission lines of the signals Φa and Φb, are omitted in FIG. 3.

[0051] 3, the CDS circuit 320 is configured on an insulating substrate of the display panel 100. When processing a signal containing variation (noise), the CDS circuit 320 samples the unknown signal and a reference signal and takes the difference between them to eliminate noise correlated with the unknown signal. In order for the CDS circuit 320 to remove variations in the threshold voltage Vth of the sense transistor M8 and the on-resistance Ron of the transistor M9, it is necessary to prepare a reference signal that includes these variations.

[0052] Although a known signal can be used as the reference signal, this embodiment uses the reset voltage Vrst applied to the anode of the OLED element E1, which makes it possible to efficiently supply the reference signal without preparing new wiring or a power supply for supplying the reference signal.

[0053] 4, the CDS circuit 320 includes capacitors Ca and Cb and switch transistors M21 to M24. In this example, the transistors M21 to M24 are P-type thin film transistors. The capacitor Ca, transistors M22, and M23 are connected in series in this order from the sense line SL to the output terminal 101. One end of the capacitor Ca is connected to the sense line SL, and the other end is connected to one of the source / drain of the transistor M22.

[0054] The other of the source or drain of the transistor M22 is connected to one of the source or drain of the transistor M23. The other of the source or drain of the transistor M23 is connected to the output terminal 101. A selection signal Φb is provided to the gate of the transistor M22 from the control circuit 300 or the horizontal scanning circuit 133, and a selection signal SSC is provided to the gate of the transistor M23 from the horizontal scanning circuit 133.

[0055] One of the source and drain of the transistor M21 is connected to a node between the capacitor Ca and the transistor M22, and a constant voltage Vc is applied to the other. Vc is a voltage between VDD and VEE. One of the source and drain of the transistor M24 is connected to a node between the transistor M22 and the transistor M23, and a ground voltage GND is applied to the other. The ground voltage GND is a constant voltage that is lower than the power supply voltage VDD, for example, equal to or higher than the power supply voltage VEE. A selection signal Φa is applied to the gates of the transistors M21 and M24 from the control circuit 300 or the horizontal scanning circuit 133. One end of the capacitor Cb is connected to a node between the transistor M22 and the transistor M23, and a reference voltage Vref2 is applied to the other end. The reference voltage Vref2 is a constant voltage that is lower than the power supply voltage VDD, for example, equal to or higher than the power supply voltage VEE.

[0056] In measuring the degradation of the OLED element E1, a signal obtained by multiplying the anode voltage Vf of the OLED element E1 by the input / output gain G of the sense circuit 310 is input to the CDS circuit 320, and a signal VOUT is output in which the variation contained in the input / output gain G, i.e., the variation in the threshold voltage Vth of the transistor M8 and the on-resistance Ron of the transistor M9, has been cancelled.

[0057] An example of the operation of degradation measurement using the CDS circuit 320 will be described below. The CDS circuit 320 samples (reads) a reference signal (Vrst×G) in a state where a reset voltage Vrst (reference voltage) is applied to the anode of the OLED element E1, and samples (reads) a measurement signal (unknown signal) (Vf×G) when a sense current SC is supplied. Then, it outputs a signal VOUT indicating the difference between them.

[0058] Fig. 5 is a timing chart showing the time variations of several control signals in the readout of the reference signal. Specifically, Fig. 5 shows the time variations of signals Em(N), S1(N), S2(N), Φa(N), Φb(N), and SSS(N). N indicates the signal for the Nth pixel circuit row.

[0059] At time T1, the signal Em(N) changes from the L level to the H level, the signal S1(N) changes from the H level to the L level, and the signal S2 maintains the H level. The signal Φa(N) maintains the H level, the signal Φb(N) maintains the H level, and the signal SSS(N) maintains the H level.

[0060] Since the signal Em(N) changes to H level, the transistors M1 and M6 are turned OFF. Since the signal S1(N) changes to L level, the transistor M5 is turned ON. Since the signal S2 maintains H level, the transistors M2, M4, and M7 are maintained OFF. That is, no sense current flows in the pixel circuit, and the reference voltage Vref is applied to the gate of the transistor M3. Furthermore, since the signals Φa(N), Φb(N), and SSS(N) maintain H level, the transistors M9, M21, M22, and M24 are OFF. The transistor M23 is also OFF.

[0061] Next, at time T2, 1H after time T1, signal Em(N) maintains the H level, signal S1(N) changes from the L level to the H level, and signal S2 changes from the H level to the L level. Signal Φa(N) changes from the H level to the L level, signal Φb(N) maintains the H level, and signal SSS(N) changes from the H level to the L level.

[0062] Since the signal Em(N) maintains the H level, the transistors M1 and M6 are OFF. Since the signal S1(N) changes to the H level, the transistor M5 is turned OFF. Since the signal S2 changes to the L level, the transistors M2, M4, and M7 are turned ON. In other words, no sense current flows in the pixel circuit, and a data signal for providing the sense current SC to the storage capacitance Cst is written. In addition, a reset voltage Vrst is applied to the anode of the OLED element E1.

[0063] Furthermore, since the signals Φa(N) and SSS(N) change to the L level, the transistors M21, M24 and M9 are turned ON. Since the signal Φb(N) maintains the H level, the transistor M22 is OFF. A voltage (Vrst×G) is applied to one side of the capacitance Ca, and a voltage Vc is applied to the other side. The ground voltage and the reference voltage Vref2 are applied to both ends of the capacitance Cb. The transistor M23 is OFF.

[0064] The level of each signal is maintained from time T2 to time T3. In this 1H period PR1, the CDS circuit 320 reads out the reference signal (Vrst×G). That is, in the period PR1, the signals Em(N), S1(N), and Φb(N) are at the H level, and the signals S2(N), Φa(N), and SSS(N) are at the L level.

[0065] 6 shows the ON / OFF states of the transistors in the pixel circuit 210 and the CDS circuit 320 during a period PR1. Since the signals Em(N), S1(N), and Φb(N) are at the H level, the P-type switch transistors controlled by these signals are OFF. In other words, the transistors M1, M6, M5, and M22 are OFF.

[0066] Since the signals S2(N), Φa(N) and SSS(N) are at the L level, the P-type switch transistors controlled by them are ON. That is, the transistors M2, M4, M7, M9, M21 and M24 are ON. The transistor M23 is OFF.

[0067] In this period PR1, the sense line SL outputs a reference signal (Vrst×G). In the CDS circuit 320, the node voltage between the capacitance Ca and the transistor M22 is Vc. This is because the transistor M21 is ON and the transistor M22 is OFF.

[0068] Next, the reading of the unknown measurement signal will be described. FIG. 7 is a timing chart showing the time variations of several control signals in the reading of the reference signal. Specifically, FIG. 7 shows the time variations of signals Em(N), S1(N), S2(N), Φa(N), Φb(N), and SSS(N). The time variations of these signals are the same as in FIG. 5.

[0069] During a period PR2 of 1H from the end time T3 of the period PR1 to time T4, the CDS circuit 320 reads out the measurement signal (Vf×G). At time T3, the signal Em(N) changes from H level to L level, the signal S1(N) maintains the H level, and the signal S2 changes from L level to H level. The signal Φa(N) changes from L level to H level, the signal Φb(N) changes from H level to L level, and the signal SSS(N) maintains the L level.

[0070] Since the signal Em(N) changes to the L level, the transistors M1 and M6 are turned ON. Since the signal S1(N) maintains the H level, the transistor M5 remains OFF. Since the signal S2 changes to the H level, the transistors M2, M4, and M7 are turned OFF. That is, a sense current according to the holding voltage of the holding capacitance Cst flows in the pixel circuit.

[0071] Furthermore, since the signal Φa changes to H level, the transistors M21 and M24 are turned OFF. Since the signal Φb(N) changes to L level, the transistor M22 is turned ON. Since the signal SSS maintains the L level, the transistor M9 remains ON. A voltage (Vf×G) is applied to one side of the capacitance Ca, and the other side is conductive with the capacitance Cb.

[0072] Therefore, in the period PR2, the signals S1(N), S2(N) and Φa(N) are at H level, and the signals Em(N), Φb(N) and SSS(N) are at L level. Fig. 8 shows the ON / OFF state of the transistors in the pixel circuit 210 and the CDS circuit 320 in the period PR2. Since the signals S1(N), S2(N) and Φa(N) are at H level, the P-type switch transistors controlled by them are OFF. In other words, the transistors M5, M2, M4, M7, M22 and M24 are OFF.

[0073] Since the signals Em(N), Φb(N) and SSS(N) are at the L level, the P-type switch transistors controlled by them are ON. That is, the transistors M1, M6, M9 and M22 are ON. The transistor M23 is ON.

[0074] During this period PR2, the sense line SL outputs a measurement signal (Vf×G). Due to the presence of the capacitance Ca, only the change in voltage (AC component) is transmitted, so a voltage with the threshold voltage Vth of the transistor M8 cancelled out is output to the capacitance Cb. Specifically, the voltage of the capacitance Cb is (Vc+(Vf×G)-(Vrst×G)=Vc+Vf-Vrst). Here, the voltages Vc and Vrst are known. This voltage (Vc+Vf-Vrst) is the final output voltage VOUT.

[0075] At time T4, the signal Em(N) maintains the L level, the signal S1(N) maintains the H level, and the signal S2 maintains the H level. The signal Φa(N) maintains the H level, the signal Φb(N) changes from the L level to the H level, and the signal SSS(N) changes from the L level to the H level.

[0076] The description of the control of the transistors of the pixel circuit 210 for measuring the deterioration of the OLED element E1 applies to the description of the control for normal image display. That is, instead of writing the data signal that determines the sense current, a data signal for image display is written to the storage capacitance Cst. Also, during the reset period of the anode voltage of the OLED element E1, a reference signal for CDS is read out, and during a part of the subsequent light emission period, a measurement signal is read out. In this way, an efficient circuit and control are realized by controlling the switch transistors (not including the transistor M9) in the pixel circuit that are ON / OFF controlled during normal image display at the same timing for image display and for measuring the deterioration of the OLED element.

[0077] The change over time of the control signals will be further described. Fig. 9 shows the change over time of the signals S2, Em, SSS, Φa, and Φb. The variable in () of each signal indicates the pixel circuit row, and (N) indicates that it is a signal of the Nth pixel circuit row. Fig. 9 does not show the signal S1, but as described with reference to Figs. 5 and 7, it changes in the same way at a timing 1H earlier than the signal S2. In Fig. 9, periods PR1 and PR2 respectively indicate periods for measuring the deterioration of the OLED element E1 in the Nth pixel circuit row.

[0078] Fig. 9 shows a control timing chart of the 7T1C pixel circuit 210 and the CDS circuit 320 shown in Fig. 4 when the pulse width (H level period) of the signal Em is 2H. The pulse width (L level period) of the signals S1 and S2 is 1H. The pulse width (L level period) of the signal SSS is 2H, and the pulse widths of Φa and Φb are 1H. This timing allows the OLED element E1 to be measured at the fastest speed.

[0079] As described above, the reset voltage Vrst of the OLED element E1 is read as a reference voltage for correcting the threshold voltage Vth of the transistor M8 of the sense circuit 310. The signal Φa (clamp signal) of the CDS circuit 320 is synchronized with the signal S2 for resetting the anode of the OLED element E1.

[0080] Next, a predetermined sense current SC is supplied to the OLED element E1 from the pixel circuit, and the anode voltage Vf is read at the timing when light emission starts. The signal Φb (sampling signal) of the CDS circuit 320 is synchronized with the signal S2 of the next pixel circuit row (N+1).

[0081] By using this driving method to perform raster display with the reference current, the reset voltage Vrst and the anode voltage Vf are sampled twice and input to the CDS circuit 320, thereby making it possible to obtain a signal in which the gain variation of the sense circuit 310 has been cancelled.

[0082] Measuring the voltage Vrst and the voltage Vf each requires 1H, so a total of 2H is required. Therefore, the selection signal Em has a 2H pulse width. Therefore, the OLED element E1 is measured every other pixel circuit row. Odd-numbered rows and even-numbered rows are measured in two frame periods, respectively, to obtain measurement data for all rows. This operation completes the measurement of one pixel circuit column. This measurement is repeated for the number of pixel circuit columns to complete the measurement of all pixel circuits.

[0083] Here, we will show a trial calculation of the measurement time. Let's assume that the display area of ​​a full HD monitor is 1920H x 1080V. We assume that the output is multiplexed in RGB and measured at a frame frequency of 60Hz. The measurement time for all pixels can be calculated as follows: Total pixel measurement time = 2 x 16.7 ms x 1920 = 64.1 s

[0084] This figure is approximately 500 times faster than the conventional method of supplying sense current from an external current source.

[0085] Fig. 10 shows a control timing chart of the 7T1C pixel circuit 210 and the CDS circuit 320 shown in Fig. 4 when the pulse width (H level period) of the signal Em is 5H. When the signal Em has a width of 5H, the sense line SL is occupied for 5H per pixel, so that the OLED element is measured every 5 rows. The pulse width (L level period) of the signals S1 and S2 is 1H. The pulse width (L level period) of the signal SSS is 5H, and the pulse width (L level period) of Φa and Φb is 1H.

[0086] Assume that the display area of ​​full HD is composed of 1920H x 1080V, the output is multiplexed with RGB, and the measurement is performed at a frame frequency of 60Hz. The measurement time for all pixels can be calculated as follows: Total pixel measurement time = 5 x 16.7 ms x 1920 = 160.3 s

[0087] Although the measurement time is longer than in the method in which the pulse width is 2H, the method of the present embodiment can thus accommodate any pulse width of the signal Em. <Pixel Circuit of Other Embodiments>

[0088] 11 shows an example of a pixel circuit to which the OLED element degradation measurement of one embodiment of this specification can be applied. The pixel circuit has a 4T1C configuration, and all transistors are N-type thin film transistors. The transistors of the CDS circuit are also N-type thin film transistors. The relationship between the constant voltages VDD, VEE, Vrst, and Vref is the same as in the first embodiment, except that the polarities are inverted.

[0089] The transistor N1 is a drive transistor that controls the amount of light-emitting current to the OLED element E1. Between the gate of the transistor N1 and the cathode of the OLED element E1, the storage capacitors Cst1 and Cst2 are arranged in series. The gate of the transistor N1 is connected to the drain of the transistor N3 and the source / drain of the transistor N2. The gate of the transistor N3 is controlled by a signal S3, and a reference voltage Vref is applied to the gate of the transistor N1 via the transistor N3.

[0090] The gate of the transistor N2 is controlled by a signal S2, and a data signal Vdata is applied to the gate of the transistor N1, that is, to the storage capacitors Cst1 and Cst2, via the transistor N2.

[0091] The drain of the transistor N4 is connected to the anode of the OLED element E1, and the source of the transistor N4 is supplied with a reset voltage Vrst. The reset voltage Vrst is supplied to the anode of the OLED element E1 via the transistor N4. The gate of the transistor N4 is controlled by a signal S1.

[0092] The transistor N5 is a sense transistor for measuring the anode voltage of the OLED element E1. The gate of the transistor N5 is connected to the anode of the OLED element E1, and the power supply voltage VDD is applied to the drain. The sense line SL is connected to the source of the transistor N5 via the transistor N6. The gate of the transistor N6 is controlled by a signal SSS. The transistors N5 and N6 are included in a source follower circuit for measuring the anode voltage.

[0093] Fig. 12 shows a timing chart of control signals for measuring the anode voltage in the pixel circuit shown in Fig. 11. In this example, similar to the second embodiment, in the period in which a reset voltage is applied to the anode voltage of the OLED element E1, a reference signal (Vrst x G) for CDS is read out, and further, a measurement signal (Vf x G) is read out with a sense current flowing through the OLED element E1. The reading of the measurement signal is included in the light emission period in normal image display. Note that, similar to the first embodiment, measurement without using CDS is possible for this pixel circuit as well.

[0094] 12, in a period PR1 of 1H, the CDS circuit reads out a reference signal (Vrst×G). In the period PR1, the signals S1(N), S3(N), SSS(N), and Φa(N) are at H level. The signals S2(N) and Φb(N) are at L level. Since the signal S1(N) is at H level, a reset voltage is applied to the anode of the OLED element E1. Furthermore, since the signal SSS(N) is at H level, the reference signal (Vrst×G) is read out from the sense line SL.

[0095] In a 1H period PR2, 2H after the period PR1, the CDS circuit reads out an unknown measurement signal (Vf×G). In the period PR2, the signals S1(N), S2(N), S3(N), and Φa(N) are at L level. The signals SSS(N) and Φb(N) are at H level. In this state, a sense current flows from the power supply line VDDL through the OLED element E1, and its anode voltage is Vf. The measurement signal (Vf×G) is read out from the sense line SL.

[0096] The time changes of the signals S1(N), S2(N), and S3(N) described with reference to FIG. 12 are similar to those in normal image display. Instead of the data signal that determines the sense current, a data signal that determines the luminance for image display is written to the storage capacitors Cst1 and Cst2. In this way, if there is an anode reset period of the OLED element in the control of the pixel circuit in image display, the OLED element can be efficiently measured. Note that the constant voltage used for the reference signal may be a voltage different from the reset voltage Vrst. Also, as in the first embodiment, the measurement may be performed using a method other than CDS.

[0097] FIG. 13 shows an example of a pixel circuit to which the OLED element degradation measurement according to an embodiment of this specification can be applied. The pixel circuit has a 6T1C configuration, and all transistors are P-type thin film transistors. The relationship between the constant voltages VDD, VEE, Vrst, and Vref is the same as in the first embodiment. The pixel circuit shown in FIG. 13 has a configuration in which the transistor M5 is removed from the pixel circuit shown in FIG. 2.

[0098] The signals controlling the pixel circuit shown in Fig. 13 are different from the control signals of the pixel circuit shown in Fig. 2. Specifically, the gate of transistor M1 is controlled by signal Em1, the gate of transistor M6 is controlled by signal Em2, the gate of transistor M4 is controlled by signal S1, and the gates of transistors M2 and M7 are controlled by signal S2.

[0099] Fig. 14 shows a timing chart of control signals for measuring the anode voltage in the pixel circuit shown in Fig. 13. In this example, similar to the second embodiment, in the period in which a reset voltage is applied to the anode voltage of the OLED element E1, a reference signal (Vrst x G) for CDS is read out, and further, a measurement signal (Vf x G) is read out with a sense current flowing through the OLED element E1. The reading of the measurement signal is included in the light emission period in normal image display. Note that, similar to the first embodiment, measurement without using CDS is possible for this pixel circuit as well.

[0100] The pulse width (L level period) of signal S1(N) is 2H, and the pulse width (L level period) of signal S2(N) is 1H. The pulse width (H level period) of signal Em1(N) is 2H, and the pulse width (H level period) of signal Em2(N) is 1H. The pulse width (L level period) of signal SSS(N) is 2H, and the pulse width (L level period) of signals Φa(N) and Φb(N) is 1H.

[0101] 14, in a period PR1 of 1H, the CDS circuit 320 reads out a reference signal (Vrst×G). In the period PR1, the signals S1(N), S2(N), SSS(N), and Φa(N) are at L level. The signals Em1(N), Em2(N), and Φb(N) are at H level. Since the signal S2(N) is at H level, the transistor M7 is ON, and a reset voltage is applied to the anode of the OLED element E1. Since the signals Em1(N) and Em2(N) are at H level, the transistors M1 and M6 are OFF, and no sense current flows. The reference signal (Vrst×G) is read out from the sense line SL.

[0102] In a period PR2 of 1H immediately following the period PR1, the CDS circuit 320 reads out an unknown measurement signal (Vf-Vth). In the period PR2, the signals S1(N), S2(N), SSS(N), and Φa(N) are at H level. The signals Em1(N), Em2(N), and Φb(N) are at L level. In this state, a sense current flows from the power supply line VDDL through the OLED element E1, and the anode voltage is Vf. A measurement signal (Vf×G) is read out from the sense line SL.

[0103] The time changes of the signals S1(N), S2(N), Em1(N), and Em2(N) described with reference to FIG. 14 are similar to those in normal image display. Instead of the data signal that determines the sense current, a data signal that determines the luminance for image display is written to the storage capacitance Cst. In this way, if there is an anode reset period of the OLED element in the control of the pixel circuit in image display, it becomes possible to efficiently measure the OLED element. Note that the constant voltage used for the reference signal may be a voltage different from the reset voltage Vrst. Also, as in the first embodiment, the measurement may be performed using a method other than CDS. <Circuit layout of other embodiments>

[0104] Below, we will explain some examples of circuit layouts on the display panel 100. Fig. 15 shows a configuration example in which the sense line is divided into upper and lower parts to reduce the sense line capacitance. By reducing the sense line capacitance, it is possible to shorten the time required to read out a signal via the sense line.

[0105] In the configuration example shown in FIG. 15, the pixel circuits in each pixel circuit column are divided into two pixel circuit groups, and each pixel circuit group is composed of consecutive pixel circuits. For example, the number of pixel circuits in each pixel circuit group is the same. These numbers may be different. In FIG. 15, the pixel circuits are divided into an upper pixel circuit group and a lower pixel circuit group. The number of divided pixel circuit groups may be three or more. Each pixel circuit 210 in the upper pixel circuit group is connected to a sense line SLA. On the other hand, each pixel circuit 210 in the lower pixel circuit group is connected to a sense line SLB. The sense lines SLA and SLB are separated. In FIG. 15, one upper sense line is indicated by the symbol SLA, and one lower sense line is indicated by the symbol SLB as an example. The length of the sense lines SLA and SLB is shorter than the length of the pixel circuit column, and is approximately half.

[0106] The sense line SLA is connected to a CDS circuit 320A arranged on the upper side of the display area 125. A CDS circuit 320A is arranged for each sense line SLA. A switch transistor M10A is arranged between each CDS circuit 320A and the output terminal 101A. In FIG. 15, as an example, one upper CDS circuit is designated by the symbol 320A, and one upper transistor is designated by the symbol M10A.

[0107] The CDS circuits 320A of pixel circuits of the same color are connected to the same output terminal 101A, and the CDS circuit 320A that is conductive with the output terminal 101A is switched by a switch transistor M10A. The ON / OFF of the switch transistor M10A is controlled by a horizontal scanning circuit 133A arranged above the display area 125.

[0108] The sense line SLB is connected to a CDS circuit 320B arranged below the display area 125. A CDS circuit 320B is arranged for each sense line SLB. A switch transistor M10B is arranged between each CDS circuit 320B and the output terminal 101B. In FIG. 15, as an example, one lower CDS circuit is indicated by the reference symbol 320B, and one lower transistor is indicated by the reference symbol M10B.

[0109] The CDS circuits 320B of pixel circuits of the same color are connected to the same output terminal 101B, and the CDS circuit 320B that is conductive with the output terminal 101B is switched by a switch transistor M10B. The ON / OFF of the switch transistor M10B is controlled by a horizontal scanning circuit 133B arranged below the display area 125. Note that the data line driving circuit 134 is omitted in FIG.

[0110] In the configuration example shown in FIG. 16, each pixel circuit column is divided into two pixel circuit groups, each of which is connected to a different sense line. Specifically, each pixel circuit column is divided into a pixel circuit group consisting of odd-numbered pixel circuits and a pixel circuit group consisting of even-numbered pixel circuits. By reducing the number of pixel circuits connected to one sense line, the capacity of the path through which the sense signal flows can be reduced, and the time required to read out the signal can be shortened. The number of divided pixel circuit groups may be three or more.

[0111] 16, sense lines SLO and SLE are arranged for each pixel circuit column. One sense line is indicated by the symbol SLO or SLE as an example. The sense line SLO is connected to the odd-numbered pixel circuits of the corresponding pixel circuit column, and the sense line SLE is connected to the even-numbered pixel circuits of the corresponding pixel circuit column.

[0112] Each sense line SLO is connected to a CDS circuit 320O. The CDS circuit 320O processes the reference signal and the measurement signal transmitted by the sense line SLO. The output of the CDS circuit 320O is connected to a switch transistor M10O. The CDS circuit 320O and the switch transistor M10O are arranged for each sense line SLO.

[0113] Each sense line SLE is connected to a CDS circuit 320E. The CDS circuit 320E processes the reference signal and the measurement signal transmitted by the sense line SLE. The output of the CDS circuit 320E is connected to a switch transistor M10E. The CDS circuit 320E and the switch transistor M10E are arranged for each sense line SLE.

[0114] Signals on the sense lines SLO of the same color are output from a common output terminal (not shown) via a CDS circuit 320O and a switch transistor M10O. One CDS circuit 320O is selected by the switch transistor M10O, and its signal is output. Signals on the sense lines SLE of the same color are output from a common output terminal (not shown) via a CDS circuit 320E and a switch transistor M10E. One CDS circuit 320E is selected by the switch transistor M10E, and its signal is output.

[0115] FIG. 17 shows the results of a simulation in which the voltage of the sense line and the output of the CDS circuit are calculated with respect to the data signal voltage at different threshold voltages Vth of the sense transistor using the Monte Carlo method.

[0116] In the graph of Fig. 17, the horizontal axis represents the data signal voltage corresponding to the amount of sense current, and the vertical axis represents the voltage value. Line 501 represents the anode voltage Vf of the OLED element. Lines 502 represent the voltage of the sense line at different threshold voltages Vth of the sense transistor. Line 503 represents the output voltage at different threshold voltages Vth of the sense transistor. As shown in Fig. 17, the variation in threshold voltage Vth is effectively eliminated at the output of the CDS circuit.

[0117] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. A person skilled in the art can easily change, add, or convert each element of the above embodiments within the scope of the present disclosure. It is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. [Explanation of symbols]

[0118] 210 Pixel circuit 310 Sense Circuit 320 CDS circuit M8 Sense transistor SL Sense Line SC Sense Current

Claims

1. A display device, comprising: a plurality of pixel circuits on a substrate; a sense line on the substrate; A measurement circuit; Including, Each pixel circuit of the plurality of pixel circuits comprises: A light-emitting element; a first power supply line for applying a power supply voltage for causing a current to flow through the light emitting element; a driving transistor for controlling an amount of light-emitting current to the light-emitting element; a sense transistor having a gate electrode connected to one end of the light emitting element; a second power line connected to the drain electrode of the sense transistor; a first switch transistor connected between a source electrode of the sense transistor and the sense line; Including, the sense transistor, the first switch transistor, the sense line, and the second power supply line are included in a sense circuit; The driving transistor controls a sense current from the first power line to the light emitting element in order to measure a voltage at one end of the light emitting element; the sense transistor applies a source voltage to the sense line in a state in which the sense current is applied to the light emitting element; the measurement circuit determines a voltage of the light-emitting element based on an output of the sense line; Display device.

2. The display device according to claim 1 , The measurement circuit includes: Holding information on input / output gains of the sense circuit; correcting the output of the sense line based on the information of the input / output gain; Display device.

3. The display device according to claim 1 , Further, a correlated double sampling circuit is included, The correlated double sampling circuit comprises: A reference signal is acquired through the sense line while a reference voltage is applied to one end of the light emitting element; receiving an unknown signal through the sense line while the sense current is being applied to the light emitting element; outputting a difference signal between the reference signal and the unknown signal; the measurement circuit determines a voltage of the light emitting element based on an output from the correlated double sampling circuit; Display device.

4. The display device according to claim 3, the correlated double sampling circuit is disposed on the substrate; Display device.

5. The display device according to claim 3, the pixel circuit includes a second switch transistor that supplies a reset voltage to one terminal of the light emitting element during image display; using the reset voltage as the reference voltage; Display device.

6. The display device according to claim 3, The pixel circuit controls the transistor for measuring the light emitting element at the same control timing as a control timing of a transistor that is turned ON / OFF for displaying an image. Display device.

7. The display device according to claim 1 , a plurality of sense lines on the substrate, the sense lines including the sense lines; the plurality of pixel circuits constitute a plurality of pixel circuit columns, Each pixel circuit column of the plurality of pixel circuit columns is divided into two pixel circuit groups; The two pixel circuit groups each include a series of pixel circuits, The two pixel circuit groups are connected to different sense lines. Display device.

8. The display device according to claim 1 , a plurality of sense lines on the substrate, the sense lines including the sense lines; the plurality of pixel circuits constitute a plurality of pixel circuit columns, Each pixel circuit column of the plurality of pixel circuit columns is divided into two pixel circuit groups; one of the two pixel circuit groups is composed of odd-numbered pixel circuits, and the other of the two pixel circuit groups is composed of even-numbered pixel circuits; The two pixel circuit groups are connected to different sense lines. Display device.

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