Display device and method for controlling display

Abstract

To improve the refresh rate.SOLUTION: A display device includes: a display unit in which plural pixels are arranged: and a display control unit for making the update frequency of pixels belonging to a first region of the pixels arranged in the display unit higher than the update frequency of pixels belonging to a second region.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present disclosure relates to a display device and a display control method. [Background technology]

[0002] In recent years, a technology called foveated rendering has been developed for virtual reality (VR) display devices such as head mounted displays (HMDs). Foveated rendering generates a spatial distribution of resolution when displaying data on a display unit such as an organic electroluminescence (EL) display or a liquid crystal display, such that the area where the user's gaze is focused is displayed at high resolution and the surrounding area is displayed at low resolution.

[0003] Such foveated rendering makes it possible to reduce the load on a graphics processing unit (GPU) in a display device equipped with a display unit while displaying a high-definition image in the center of the user's field of view. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-525248 A [Patent Document 2] International Publication No. 2022 / 181212 [Patent Document 3] JP 2019-507380 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in general, there is a problem that there is a certain limit to how much the refresh rate can be improved in a display device. For example, when the above-mentioned foveated rendering is performed, although the rendering range is limited, the pixels on the entire display are updated every frame. Therefore, the time required for rewriting every frame is not shortened, and the refresh rate does not improve.

[0006] On the other hand, increasing the refresh rate and smoothing the movement of the image can improve the sense of immersion of the user viewing the displayed image and prevent motion sickness, so there is a demand for increasing the refresh rate.

[0007] The present disclosure has been made in view of the above, and has an object to provide a display device and a display control method that can improve the refresh rate. [Means for solving the problem]

[0008] According to one aspect of the present disclosure, a display device has a display section in which a plurality of pixels are arranged, and a display control section that sets the update frequency of pixels belonging to a first region among the pixels arranged in the display section to be higher than the update frequency of pixels belonging to a second region. Effect of the Invention

[0009] According to the display device of the present disclosure, the refresh rate can be improved. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram showing a configuration of a display device according to an embodiment. [Diagram 2] FIG. 2 is a block diagram showing a configuration of the gate driver. [Diagram 3] FIG. 3 is a block diagram showing the configuration of the source driver. [Figure 4] FIG. 4 is a diagram showing an example of a circuit configuration of a pixel. [Diagram 5] FIG. 5 is a diagram illustrating a display control method according to an embodiment. [Figure 6] FIG. 6 is a diagram illustrating a display control method according to an embodiment. [Figure 7] FIG. 7 is a diagram illustrating another display control method. [Figure 8] FIG. 8 is a diagram showing a modified example of the circuit configuration of a pixel. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment according to the present disclosure will be described with reference to the accompanying drawings. The embodiment described below is merely an example, and should not be construed as being limited by this description.

[0012] Fig. 1 is a block diagram showing a configuration of a display device 100 according to an embodiment. The display device 100 may be, for example, an organic EL display, a liquid crystal display, a plasma display, or an LED (Light Emitting Diode) display, and receives and displays display data from an image generating device (not shown). The display device 100 shown in Fig. 1 includes a display unit 110, a gate driver 120, a source driver 130, and a timing controller 140.

[0013] The display unit 110 includes a pixel array in which a plurality of pixels 115 are arranged two-dimensionally in row and column directions, and displays an image according to display data by emitting light from each pixel 115. Each pixel 115 of the display unit 110 holds a voltage according to the display data for each frame, and emits light with a luminance according to the held voltage.

[0014] The gate driver 120 applies a gate voltage to the pixel array of the display unit 110, row by row, and causes the pixels 115 to which the gate voltage has been applied to hold a data voltage corresponding to the display data. At this time, the gate driver 120 applies the gate voltage with different pulse periods (times) to a focus area of ​​the display unit 110 where the user's gaze is focused and a peripheral area around the focus area, according to control from the timing controller 140. Specifically, the gate driver 120 applies a gate voltage with a normal pulse period to the pixels 115 in a row including the focus area, and applies a gate voltage with a short pulse period, i.e., a high frequency, to the pixels 115 in a row not including the focus area so that a TFT (Thin Film Transistor) cannot follow the voltage.

[0015] The source driver 130 supplies a data voltage according to display data to each column of the pixel array of the display unit 110, and holds the voltage in the capacitor of the pixel 115. At this time, the source driver 130, under the control of the timing controller 140, supplies the data voltage to the pixels 115 belonging to the region of interest to overwrite the voltage held in the capacitor, and does not supply the data voltage to the pixels 115 belonging to the peripheral region to maintain the voltage held in the capacitor.

[0016] When the display data and the attention area information are input, the timing controller 140 outputs a data signal for causing each pixel 115 to emit light at a luminance corresponding to the display data to the source driver 130, and outputs a set signal indicating the update timing of each pixel 115 to the gate driver 120 and the source driver 130. Specifically, the timing controller 140 has a synchronization control unit 141 and a data control unit 142.

[0017] The synchronization control unit 141 generates a set signal with a variable frequency that indicates the update timing of the pixels 115 for each row, and outputs the set signal to the gate driver 120 and the source driver 130. Specifically, the synchronization control unit 141 generates set signals with different frequencies for rows that include a region of interest in the display unit 110 and rows that do not include a region of interest, and outputs the set signals to the gate driver 120 and the source driver 130.

[0018] That is, the synchronization control unit 141 sets the set signal corresponding to the row including the attention area to a normal frequency so that the gate voltage is applied at a speed that the TFT of each pixel 115 can follow. On the other hand, the synchronization control unit 141 sets the set signal corresponding to the row not including the attention area to a frequency higher than the normal frequency so that the gate voltage is applied at a speed that the TFT of each pixel 115 cannot follow. As a result, for the row including the attention area, the voltage held in the capacitor of the pixel 115 to which the gate voltage is applied is overwritten. Also, for the row not including the attention area, since the TFT cannot follow even if the gate voltage is applied, the voltage held in the capacitor is maintained without being overwritten. In other words, for the row not including the attention area, the update of the pixel 115 can be skipped, and the rewrite time for one frame can be shortened.

[0019] The data control unit 142 generates a data signal specifying the luminance of each pixel 115 so that each pixel 115 emits light corresponding to the display data, and outputs the data signal to the source driver 130. The data control unit 142 also generates an overwrite signal that instructs the pixel 115 belonging to the region of interest to be overwritten and the pixel 115 belonging to the peripheral region not to be overwritten, and outputs the overwrite signal to the source driver 130.

[0020] That is, the data control unit 142 generates a data signal specifying the luminance of the pixel 115 for each row including the attention area, and outputs it to the source driver 130. The data control unit 142 also generates an overwrite signal instructing to overwrite the pixel 115 belonging to the attention area among the pixels 115 in the row including the attention area and not to overwrite the pixel 115 belonging to the peripheral area, and outputs it to the source driver 130. As a result, in the row including the attention area, the pixel 115 belonging to the attention area is updated according to the display data, while the pixel 115 belonging to the peripheral area is not updated. Therefore, the update frequency of the attention area can be made higher than that of the peripheral area, and the refresh rate of the attention area can be artificially made higher than that of the peripheral area.

[0021] 2 is a block diagram showing a configuration of a gate driver 120 according to an embodiment. The gate driver 120 shown in FIG.

[0022] The shift register 121 receives a set signal output from the timing controller 140, and generates a pulse signal for applying a gate voltage to each row of the display unit 110 according to the timing indicated by the set signal.

[0023] The level shifter 122 adjusts the level of the pulse signal generated in the shift register 121 and outputs a gate voltage.

[0024] The buffer 123 temporarily holds the gate voltage output from the level shifter 122, and applies the gate voltage in sequence to each row of the pixel array of the display unit 110 according to the timing indicated by the set signal. That is, the buffer 123 applies the gate voltage at a normal frequency to rows including the region of interest, and applies the gate voltage at a frequency higher than normal to rows including only the peripheral region that does not include the region of interest.

[0025] With the gate driver 120 configured as above, a gate voltage is applied to the pixels 115 in the rows that do not include the region of interest but only the peripheral region at a speed that the TFTs of the pixels 115 cannot keep up with, and no updating of the pixels 115 occurs. As a result, the updating of the pixels 115 in the rows that only include the peripheral region can be skipped, and the rewriting time for one frame can be shortened.

[0026] 3 is a block diagram showing a configuration of a source driver 130 according to an embodiment. The source driver 130 shown in FIG. 3 includes a shift register 131, a register 132, a shift register 133, a register 134, a latch 135, a level shifter 136, a DAC (Digital Analog Converter) 137, and a buffer 138.

[0027] The shift register 131 receives a set signal output from the timing controller 140, and generates a pulse signal for supplying a data voltage to the pixels 115 of each row of the display unit 110 according to the timing indicated by the set signal.

[0028] The register 132 acquires a data signal that specifies the luminance of the pixels 115 for each row including the region of interest, and holds the acquired data signal in association with each column of the pixels 115. Then, the register 132 outputs the data signal to the latch 135 for each row in response to a pulse signal generated in the shift register 131.

[0029] The shift register 133 receives a set signal output from the timing controller 140, and generates a pulse signal for controlling overwriting of the pixels 115 in each row of the display unit 110 according to the timing indicated by the set signal.

[0030] The register 134 acquires an overwrite signal that controls whether or not to overwrite the pixels 115 for each row including the region of interest, and stores the acquired overwrite signal in association with each column of the pixels 115. Then, the register 134 outputs the overwrite signal to the latch 135 for each row in response to a pulse signal generated in the shift register 133.

[0031] The latch 135 acquires data signals of the pixels 115 belonging to the region of interest from the register 132 in accordance with the overwrite signal output from the register 134. That is, the latch 135 acquires data signals corresponding to the pixels 115 in the region of interest to be overwritten from among the data signals for one row output from the register 132.

[0032] The level shifter 136 adjusts the level of the data signal acquired by the latch 135, and outputs a voltage signal to be supplied to the pixels 115 belonging to the region of interest. That is, the level shifter 136 outputs to the DAC 137 a voltage signal according to the luminance of each pixel 115 belonging to the region of interest.

[0033] The DAC 137 performs digital-to-analog conversion on the voltage signal output from the level shifter 136, and outputs a data voltage to be supplied to each of the pixels 115 belonging to the region of interest.

[0034] Buffer 138 temporarily holds the data voltage output from DAC 137, and supplies the data voltage to pixels 115 in one row at a time of display unit 110 in accordance with the timing indicated by the set signal. That is, buffer 138 supplies the data voltage to pixels 115 belonging to the region of interest among pixels 115 in a row including the region of interest, and does not supply the data voltage to pixels 115 belonging to the peripheral region.

[0035] When the source driver 130 configured as above supplies a data voltage to the pixels 115 in a row including the region of interest, the data voltage is supplied only to the pixels 115 that belong to the region of interest, and the data voltage is not supplied to the pixels 115 that belong to the peripheral region. As a result, it is possible to update the pixels 115 that belong to the region of interest while preventing the pixels 115 that belong to the peripheral region from being updated.

[0036] Fig. 4 is a diagram showing an example of a circuit configuration of a pixel 115 of the display unit 110. Fig. 4 shows the circuit configuration of one pixel 115 arranged in the display unit 110. As shown in Fig. 4, the pixel 115 has a TFT 151, a capacitor 152, a TFT 153, and an OLED (Organic Light-Emitting Diode) 154.

[0037] In such a pixel 115, when a gate voltage is applied from the gate driver 120 to the TFT 151 and the TFT 151 is turned on so as to be conductive, a data voltage supplied from the source driver 130 is transmitted to the capacitor 152. That is, in the pixel 115 in the row including the attention area, the TFT 151 is turned on by the application of a gate voltage and transmits the data voltage to the capacitor 152. At this time, for the pixels 115 belonging to the attention area among the pixels 115 in the row including the attention area, the data voltage is supplied from the source driver 130, so that the voltage held in the capacitor 152 is overwritten by the data voltage. In contrast, for the pixels 115 belonging to the peripheral area among the pixels 115 in the row including the attention area, the data voltage is not supplied from the source driver 130, so that the voltage held in the capacitor 152 is not overwritten.

[0038] The source driver 130 may also include a circuit that enables sensing and recovery of the data voltage. The source driver 130 may sense the data voltage of the pixels 115 in the row including the region of interest that belong to the peripheral region, and may recover the voltage held in the capacitor 152. This makes it possible to suppress a decrease in luminance due to a voltage drop in the pixels 115 that belong to the peripheral region. At this time, a prediction formula may be used to shorten the sensing time.

[0039] Furthermore, for pixels 115 in a row including the region of interest that belong to the peripheral region, data voltages may be overwritten in the same manner as for pixels 115 that belong to the region of interest. In this case, the data voltages overwritten on pixels 115 that belong to the peripheral region may be data voltages that have been calculated in the past and supplied to pixels 115. In this way, data voltages that have been output in the past can be stored and the same data voltages can be output as necessary, reducing the calculation load.

[0040] On the other hand, in pixels 115 in rows not including the region of interest, the gate voltage is applied to the TFT 151 at high speed, causing the TFT 151 to immediately turn off before fully turning on. As a result, the voltage held in the capacitor 152 is not overwritten by the data voltage supplied from the source driver 130, and the capacitor 152 maintains the existing voltage.

[0041] When no gate voltage is applied to the TFT 151, the TFT 153 is turned on by the voltage held by the capacitor 152, and the OLED 154 emits light by a current from the power supply voltage (VDD). The luminance of the light emitted by the OLED 154 corresponds to the voltage held by the capacitor 152, that is, the data voltage based on the display data. As a result, the display data is displayed on the display unit 110 in which the pixels 115 are arranged.

[0042] Next, a display control method using the display device 100 configured as described above will be described with reference to Figures 5 and 6. Figure 5 is a diagram for explaining a specific example of application of a gate voltage to pixels 115 of the display unit 110, and Figure 6 is a diagram for explaining a specific example of supply of a data voltage to pixels 115 of the display unit 110.

[0043] The display unit 110 according to the present embodiment is divided into an attention area where the user's gaze is concentrated and a peripheral area around the attention area. Here, for example, as shown in FIG. 5(a), the display unit 110 is divided into a third area which is the attention area, and first, second, fourth, and fifth areas which are peripheral areas around the third area. Note that attention area information indicating the position of the attention area is calculated separately by estimation from information of the gaze tracking device or display contents, and is input to the timing controller 140 together with the display data. The shape of the third area which is the attention area is exemplified here as a rectangle, but may be any other shape.

[0044] In such a display unit 110, the row 210 constituting the first region and the row 230 constituting the fifth region do not include the region of interest, whereas the row 220 constituting the second, third, and fourth regions includes the third region, which is the region of interest. For this reason, the set signal that controls the timing of application of the gate voltage to each row has a high-frequency signal in sections 215 and 235 corresponding to the rows 210 and 230, and has a normal frequency signal in section 225 corresponding to the row 220, as shown in FIG. 5(b), for example. Each of the rows 210, 220, and 230 includes one or more rows of pixels 115, and the set signal has an on signal section corresponding to each row of the pixels 115. However, a gate in panel (GIP), which is a gate driver circuit formed on the panel by a TFT process, may be used to turn on multiple rows simultaneously.

[0045] As a result of such a set signal being output from the timing controller 140 to the gate driver 120, a gate voltage is applied to the TFTs 151 of the pixels 115 in the rows 210 and 230 at high speed, and the TFTs 151 are unable to keep up and do not fully turn on. As a result, the voltages held in the capacitors 152 of the pixels 115 in the rows 210 and 230 are not overwritten, and rewriting of these rows 210 and 230 can be skipped, thereby shortening the time required to rewrite one frame.

[0046] On the other hand, since the gate voltage is applied to the TFTs 151 of the pixels 115 in row 220 at the normal speed, the TFTs 151 are turned on and the voltage held in the capacitors 152 can be overwritten. Since row 220 includes the third region, which is the region of interest, and the second and fourth regions, which are peripheral regions, the source driver 130 controls the supply of data voltage to each column, thereby controlling whether or not the voltage held in the capacitors 152 is overwritten.

[0047] 6(a), the second region is made up of columns 240 of rows 220, the third region is made up of columns 250 of rows 220, and the fourth region is made up of columns 260 of rows 220. When a gate voltage is applied to such rows 220, an overwrite signal is input to the source driver 130 to overwrite the voltage held in the capacitor 152 only for the third region, which is the region of interest.

[0048] As a first example, the overwrite signal has a signal indicating overwrite off in sections 245 and 265 corresponding to columns 240 and 260, and a signal indicating continuous overwrite on in section 255 corresponding to column 250, as shown in Fig. 6(b), for example. Furthermore, the data signal for supplying a data voltage to each pixel 115 in row 220 has a no-signal section in sections 245 and 265 corresponding to columns 240 and 260, and a signal specifying the brightness of each pixel 115 in section 255 corresponding to column 250, as shown in Fig. 6(c), for example.

[0049] 7(a), the overwrite signal has signals indicating overwrite off in sections 245 and 265 corresponding to columns 240 and 260, and has a signal discretely indicating overwrite on in section 255 corresponding to column 250. Also, the data signal for supplying a data voltage to each pixel 115 in row 220 has no-signal sections in sections 245 and 265 corresponding to columns 240 and 260, and has a signal that specifies the brightness of each pixel 115 in synchronization with the overwrite signal in section 255 corresponding to column 250, as shown in FIG.

[0050] As a result of such overwrite signals and data signals being output from the timing controller 140 to the source driver 130, the voltages held in the capacitors 152 of the pixels 115 in the second and fourth regions located in the columns 240 and 260 are maintained without being overwritten. Then, a data voltage corresponding to the data signal in the section 255 is supplied to the pixels 115 in the third region located in the column 250, and the voltages held in the capacitors 152 are overwritten. As a result, in the row 220, the pixels 115 in the second and fourth regions, which are the peripheral regions, are not updated, and only the pixels 115 in the third region, which is the attention region, are updated. In other words, the attention region can be updated more frequently than the peripheral regions, and the refresh rate of the attention region can be artificially increased compared to the peripheral regions.

[0051] Furthermore, according to the overwrite signal and data signal of the first example, strict synchronization between the overwrite signal and the data signal is not required, and the pixels 115 to be updated can be controlled by the timing of the data signal. Also, according to the overwrite signal and data signal of the second example, the spatial distribution of the pixels 115 to be updated can be adjusted by overwriting the voltage, and the resolution of the region of interest in the updated image can be controlled.

[0052] 5 to 7, the display control for updating only the pixels 115 belonging to the third region, which is the region of interest, and not updating the pixels 115 belonging to the first, second, fourth, and fifth regions, which are the peripheral regions, is repeatedly executed for each frame. By updating the pixels 115 of all regions including the peripheral regions for frames at a predetermined cycle, it is possible to display an immersive image in which the region of interest is updated more frequently than the peripheral regions.

[0053] Depending on the pixel circuit used, the luminance drop in the surrounding area during the update interval of the pixels 115 in all areas may be large, causing the surrounding area to be perceived as dark. In this case, the amount of luminance drop corresponding to the update frequency may be calculated in advance, and the pixels 115 in the surrounding area may be updated to display the image at a luminance that includes the amount of luminance drop. This makes it possible to suppress the perceived drop in luminance in the pixels 115 in all areas, and to make the entire image perceived at a desired brightness.

[0054] When the amount of luminance reduction is added as described above, the amount of luminance reduction may differ between the second and fourth peripheral regions and the first and second peripheral regions. However, by calculating the amount of luminance reduction according to the update frequency of each region in advance, the reduction in perceived luminance can be suppressed in the pixels 115 of all regions. Furthermore, the amount of luminance reduction may differ depending on the distance from the gate driver 120 or the source driver 130. However, by calculating the amount of luminance reduction according to the update frequency at the position of each pixel 115 in advance, the reduction in perceived luminance can be suppressed in the pixels 115 of all regions. Note that such correction of the reduction in luminance utilizes a visual characteristic called the "Talbot-Plateau Law" that the perceived luminance of a flashing light is equivalent to the luminance of a stationary light, which is equal to the time integral of the luminance in the corresponding time interval.

[0055] As described above, according to this embodiment, the frequency of the set signal that controls the timing of applying the gate voltage to each row of the pixel array is made variable, and the set signal for the row that does not include the attention area where the gaze is concentrated is made high frequency. Therefore, in the pixels of the row that does not include the attention area, the TFT does not follow the gate voltage, and the voltage held in the capacitor is not rewritten. As a result, the update of the pixels of the row that does not include the attention area can be skipped, shortening the rewrite time of one frame and improving the refresh rate.

[0056] In the above embodiment, the gate driver 120 controls the updating of the pixels 115 row by row, but a gate-in-panel (GIP) may be used to simultaneously control the updating of the pixels 115 in a plurality of rows. That is, for a row including a region of interest, the updating of the pixels 115 in a plurality of rows may be simultaneously executed, and for a row not including a region of interest, the updating of the pixels 115 in a plurality of rows may be simultaneously skipped. This reduces the resolution of the display to be updated, thereby reducing the load of the calculation process in the GPU and timing controller 140 and further improving the display update speed of the display unit 110.

[0057] In the above embodiment, the overwrite signal is input to the source driver 130 to control whether or not to overwrite the region of interest and the surrounding region, but it is also possible to control whether or not to overwrite the region of interest and the surrounding region by inputting the overwrite signal to each pixel 115. An example of the circuit configuration of such a pixel 115 is shown in Figure 8. In Figure 8, the same parts as in Figure 4 are given the same reference numerals.

[0058] 8 has a configuration in which a TFT 161 is added to the pixel 115 shown in Fig. 4. An overwrite signal is input to the gate terminal of the TFT 161, and the TFT 161 is switched between a conductive state and a non-conductive state. That is, in the pixel 115 belonging to the region of interest, the overwrite signal causes the TFT 161 to be in a conductive state, and a gate voltage is applied to the TFT 151. On the other hand, in the pixel 115 belonging to the peripheral region, the overwrite signal causes the TFT 161 to be in a non-conductive state, and no gate voltage is applied to the TFT 151.

[0059] This makes it possible to control whether or not to apply a gate voltage to the TFT 151 for each column, even for pixels 115 in the same row, and to control whether or not to overwrite the voltage held in the capacitor 152 with a data voltage. [Explanation of symbols]

[0060] 100 display device 110 Display section 115 pixels 120 Gate Driver 121, 131, 133 Shift Registers 122, 136 Level shifter 123, 138 Buffer 130 Source Driver 132, 134 Registers 135 Latch 137 DAC 140 Timing Controller 141 Synchronization control section 142 Data Control Section 151, 153, 161 TFT 152 Capacitor 154 OLED

Claims

1. A display unit in which a plurality of pixels are arranged; a display control unit that sets an update frequency of pixels belonging to a first region among pixels arranged on the display unit higher than an update frequency of pixels belonging to a second region; A display device having the above configuration.

2. The display control unit is The update frequency of pixels belonging to a first region on which the gaze of a user viewing the display unit is concentrated is made higher than the update frequency of pixels belonging to a second region located around the first region. The display device according to claim 1 .

3. The pixel is a first transistor that, when in a conductive state, transmits a data voltage corresponding to a luminance for each pixel to update the pixel; The display control unit is a gate driver that applies a gate voltage to pixels of each row of the display unit so as to switch the first transistor to a conductive state; a timing controller that outputs a frequency-variable set signal to the gate driver and applies a gate voltage to a row that does not include the first region at a higher speed than to a row that includes the first region. The display device according to claim 1 .

4. The display control unit is The pixel array further includes a source driver that supplies the data voltage to pixels included in the first region and does not supply the data voltage to pixels included in the second region. The display device according to claim 3 .

5. The pixel is The pixel circuit further includes a second transistor that is switched between a conductive state and a non-conductive state by an overwrite signal that indicates whether or not the pixel is to be updated, and that applies a gate voltage from the gate driver to the first transistor when the second transistor is in a conductive state. The display device according to claim 3 .

6. The display control unit is Controlling the updating of pixels in multiple rows of the display simultaneously The display device according to claim 1 .

7. A display control method for controlling a display on a display unit in which a plurality of pixels are arranged, comprising: Among the pixels arranged on the display unit, pixels belonging to a first region are updated more frequently than pixels belonging to a second region. A display control method comprising:

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