Display device

Abstract

To provide a display device that can minimize a bezel area.SOLUTION: A display device comprises: a display panel that includes a plurality of pixels and includes a substrate having a first area disposed at a center and a second area surrounding the first area; a data driving portion that supplies a data signal to the pixels through data lines; and a gate driving portion that includes a plurality of stages to supply a gate signal to the pixels through gate lines. Each of the plurality of stages included in the gate driving portion is disposed on a gate area that at least partially overlaps the first area and the second area. The plurality of pixels include a plurality of first pixels disposed on the first area and a plurality of second pixels disposed on the second area, the first pixels are disposed in the first area at a first pixel density, and the second pixels are disposed in the second area at a second pixel density lower than the first pixel density.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a display device. [Background technology]

[0002] As we enter the information age, the field of displays that visually represent electrical information signals has been rapidly developing, and in response to this, a variety of display devices with excellent performance such as thinness, light weight, and low power consumption have been developed. Examples of such display devices include liquid crystal display devices (LCDs) and organic light emitting display devices (OLEDs).

[0003] Display devices are now used in a wide variety of applications, including not only computer monitors and TVs but also personal portable devices. Research is currently underway into display devices that have a large display area while being reduced in volume and weight.

[0004] In recent years, display devices that are manufactured by forming a display unit, wiring, etc. on a flexible substrate such as plastic, which is a flexible material, and are capable of expanding and contracting in specific directions and being changed into various shapes, have been attracting attention as the next generation of display devices. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device capable of minimizing a bezel area.

[0006] Another object of the present invention is to provide a display device capable of changing an outer region.

[0007] The object of the present invention is not limited to the above-mentioned objects, and other objects not mentioned herein will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] In order to solve the above-mentioned problems, a display device according to an embodiment of the present invention may include a display panel including a substrate including a first region and a second region surrounding the first region, a data driver for supplying data signals to the pixels through data lines, and a gate driver including a plurality of stages for supplying gate signals to the pixels through gate lines. Each of the stages included in the gate driver may be disposed on a gate region at least partially overlapping the first region and the second region, and the plurality of pixels may include a plurality of first pixels disposed on the first region and a plurality of second pixels disposed on the second region, the first pixels may be disposed at a first pixel density in the first region, and the second pixels may be disposed at a second pixel density smaller than the first pixel density in the second region.

[0009] Further details of the embodiments are included in the detailed description and the drawings.

[0010] In the display device according to the embodiment of the present invention, a gate region in which various elements constituting a gate driver are arranged may be arranged to overlap at least a part of a display region (first region, second region) in which various elements constituting pixels are arranged. That is, since the gate driver is arranged and formed in a Gate In Array (GIA) manner on the gate region, a bezel area of ​​the display device may be minimized.

[0011] In addition, in the case of a display device according to an embodiment of the present invention, a first region which is a central region and a second region which is an outer region surrounding the first region may be included, and second pixels arranged in the second region may be arranged at a lower pixel density than first pixels arranged in the first region. Thus, the display device may be deformed in the second region which is the outer region, and the second region which is the outer region may be configured to have a curved surface.

[0012] The effects of the present invention are not limited to the above-mentioned examples, and various other effects are included within the scope of the present invention. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a plan view showing a display device according to an embodiment of the present invention. [Figure 2a] 2 is a cross-sectional view showing an example taken along line II' shown in FIG. 1. [Figure 2b] 2 is a cross-sectional view showing an example taken along the line II-II' shown in FIG. 1. [Diagram 3] 2 is a diagram for explaining an example of the arrangement relationship of first pixels arranged on a first region of the display device of FIG. 1. FIG. [Figure 4] 1. FIG. 4 is a diagram for explaining an example of the arrangement relationship of second pixels arranged on a second region of the display device of FIG. [Diagram 5] FIG. 1 is a plan view showing a display device according to an embodiment of the present invention. [Figure 6] 6 is a diagram showing an example of a gate driver disposed on a gate region of the display device of FIG. 5. FIG. [Figure 7] 6 is a cross-sectional view illustrating an example of a display panel included in the display device of FIG. 5. [Figure 8] 6 is an enlarged view showing an example in which a portion of the first sub-region, the second sub-region, the fifth sub-region, the sixth sub-region, the seventh sub-region, and the eighth sub-region in FIG. 5 is enlarged. [Figure 9a] 6 is an enlarged view showing an example in which a part of the third sub-region and the fourth sub-region of FIG. 5 is enlarged. [Figure 9b]6 is an enlarged view showing another example in which a part of the third sub-region and the fourth sub-region of FIG. 5 is enlarged. FIG. [Figure 10] 6 is a cross-sectional view showing an example taken along line III-III' shown in FIG. 5. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The advantages and features of the present invention, and the methods for achieving them, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms. The embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the present invention of the scope of the invention. The present invention is only defined by the scope of the claims.

[0015] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, and the present invention is not limited to the illustrated matters. The same reference symbols refer to the same components throughout the specification. In addition, when describing the present invention, if it is determined that a detailed description of related known technology may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When "includes," "has," "is made," etc. are used in the present invention, other parts may be added since "only" is not used. When a component is expressed in the singular, it includes the plural unless otherwise explicitly stated.

[0016] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0017] Furthermore, when the term "connected" or "coupled" is used, unless "immediately" or "directly" is used, it can include being "connected" or "coupled" through one or more other components located between the two components.

[0018] In addition, although the terms "first", "second" and the like are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, the first component referred to below may be the second component within the technical concept of the present invention.

[0019] Like reference numbers refer to like elements throughout the specification.

[0020] The area and thickness of each component shown in the drawings are shown for convenience of explanation, and the present invention is not necessarily limited to the area and thickness of the components shown.

[0021] The respective features of the various embodiments of the present invention may be partially or fully combined or combined with each other, and may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0022] Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0023] FIG. 1 is a plan view showing a display device according to an embodiment of the present invention.

[0024] FIG. 2a is a cross-sectional view showing an example taken along line II' shown in FIG.

[0025] FIG. 2b is a cross-sectional view showing an example taken along line II-II' shown in FIG.

[0026] Meanwhile, FIG. 1 may be a diagram showing the front surface of a display device 1000 according to an embodiment of the present invention.

[0027] Although FIG. 1 illustrates a case in which the display device 1000 is embodied in the form of a smartphone, this is not limited thereto, and the display device 1000 may be embodied in various electronic devices (e.g., a smart watch, a tablet PC, etc.).

[0028] Meanwhile, in FIGS. 1, 2a, and 2b, for convenience of explanation, only a window WD among the components included in the display device 1000 is shown.

[0029] Referring to FIG. 1, a display device 1000 according to an embodiment of the present invention may include a display panel DP (see FIG. 7) and a window WD covering the display panel DP (see FIG. 7).

[0030] The display device 1000 can display an image through a display surface. Here, the display surface can be defined as an area on which an image is displayed. The display device 1000 can include a display panel DP (see FIG. 5), which can include a plurality of pixels for displaying an image.

[0031] Meanwhile, the display surface on which the image is displayed may be parallel to a plane defined by a first directional axis (e.g., an axis extending in a first direction DR1) and a second directional axis (e.g., an axis extending in a second direction DR2). The normal direction of the display surface, i.e., the thickness direction of the display device 1000, may be defined as a third direction DR3. In general, the first directional axis is known as the x-direction, the second directional axis is known as the y-direction, and the third directional axis is known as the z-direction.

[0032] The front (or top) and rear (or bottom) of each member or unit of the display device 1000 described below may be divided along a third direction DR3. However, the first to third directions DR1, DR2, and DR3 shown in this specification are merely examples, and the first to third directions DR1, DR2, and DR3 are relative concepts and may be converted to other directions. In the following, for convenience of explanation, the first to third directions DR1, DR2, and DR3 will each be referred to by the same reference numerals.

[0033] Meanwhile, in this specification, the expression "overlapped" means that two components are overlapped in the thickness direction of the display device 1000 (ie, the third direction DR3), unless otherwise defined.

[0034] Meanwhile, the display surface of the display device 1000 may be used not only as an area for displaying an image but also as an area for recognizing a user's touch input (e.g., a sensing area, a touch area). In this case, the display device 1000 may further include a touch sensor. According to an embodiment, the area for recognizing a user's touch input may correspond to the above-mentioned display surface and may be superimposed on at least a portion of the display surface.

[0035] 1, the display device 1000 is shown to have a rounded shape at a corner where one long side and one short side intersect, but this is merely an example and the shape of the display device 1000 is not limited thereto. For example, the display device 1000 may have an angular shape at a corner where one long side and one short side intersect.

[0036] In one embodiment, the display device 1000 may include a display surface in which the central region is flat and the outer region (e.g., edge region) is curved. For example, the front surface of the display device 1000 may be set as the display surface.

[0037] More specifically, the display device 1000 may include a first region A1 and a second region A2 excluding the first region A1. For example, the second region A2 may be defined as a region surrounding the first region A1. Meanwhile, the first region A1 may occupy most of the area of ​​the display surface.

[0038] In one embodiment, the second region A2 may include a left region, a right region, a lower region, an upper region, and a corner region of the first region A1. For example, the second region A2 may include a first sub-region A2a (e.g., a left region) adjacent to one side of the first region A1 along the first direction DR1, a second sub-region A2b (e.g., a right region) adjacent to the other side of the first region A1 along the first direction DR1, a third sub-region A2c (e.g., a lower region) adjacent to one side of the first region A1 along the second direction DR2, a fourth sub-region A2d (e.g., an upper region) adjacent to one side of the first region A1 along the second direction DR2, and a first sub-region A2e (e.g., a corner region). The sub-regions A2a and A2b may include a fifth sub-region A2e (e.g., a first corner region) between the first sub-region A2a and A2c, a sixth sub-region A2f (e.g., a second corner region) between the first sub-region A2a and A2c, a seventh sub-region A2g (e.g., a third corner region) between the second sub-region A2b and A2c, and an eighth sub-region A2h (e.g., a fourth corner region) between the second sub-region A2b and A2c.

[0039] Depending on the embodiment, the first region A1 may be a region corresponding to the central region of the display device 1000 and may be flat, and the second region A2 (e.g., the first to eighth sub-regions A2a to A2h) may be a region corresponding to the outer region (edge ​​region) of the display device 1000 and may be curved.

[0040] For example, referring to FIG. 2a and FIG. 2b, the first sub-region A2a and the second sub-region A2b may have a curved surface warped along a direction substantially parallel to the first direction DR1 (e.g., a first strain direction). Also, as shown in FIG. 2b, the third sub-region A2c and the fourth sub-region A2d may have a curved surface warped along a direction substantially parallel to the second direction DR2 (e.g., a second strain direction). Meanwhile, although not shown in FIG. 2a and FIG. 2b, each of the fifth to eighth sub-regions A2e to A2h may have a curved surface warped along the first direction DR1 and the second direction DR2 (e.g., the first strain direction and the second strain direction). The first direction DR1 may be parallel to the major axis of the display device 1000, and the second direction DR2 may be parallel to the minor axis of the display device 1000.

[0041] In one embodiment, the display device 1000, for example, the portions of the display panel DP (see FIG. 5) included in the display device 1000 corresponding to the first to eighth sub-regions A2a to A2h, may have the property of being able to warp or stretch. For example, the display device 1000, for example, the portions of the display panel DP (see FIG. 5) included in the display device 1000 corresponding to the first to eighth sub-regions A2a to A2h may have not only flexibility but also stretchability. Thus, the display device 1000 corresponding to the first to eighth sub-regions A2a to A2h may be designed to have a curved surface type in the corresponding regions since the shape of the display device 1000 may be freely deformed.

[0042] This will be described in more detail with reference to FIG. 5 and subsequent figures.

[0043] FIG. 3 is a diagram for explaining an example of the arrangement relationship of first pixels arranged on the first region of the display device of FIG.

[0044] FIG. 4 is a diagram for explaining an example of the arrangement relationship of second pixels arranged on the second region of the display device of FIG.

[0045] 1, 2a, 2b, 3 and 4, the display device 1000 may include a first region A1 and a second region A2. As described with reference to Figs. 1, 2a and 2b, the first region A1 may be a region corresponding to a central region of the display device 1000 and may have a flat type, and the second region A2 may be a region corresponding to an outer region (edge ​​region) of the display device 1000 and may have a curved type.

[0046] The display device 1000 may include a plurality of first pixels PX1 arranged in the first region A1 and a plurality of second pixels PX2 arranged in the second region A2. Meanwhile, each of the first pixels PX1 and the second pixels PX2 may include at least one sub-pixel selected from a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. In some cases, at least a portion of the first pixels PX1 and the second pixels PX2 may further include a white sub-pixel (not shown).

[0047] According to an embodiment, the light emitting efficiency of the light emitting element may be determined according to the colors of the sub-pixels R, G, and B. In consideration of this, the sizes of the sub-pixels R, G, and B may be determined according to the colors.

[0048] For example, among the subpixels R, G, and B, the blue subpixel B may be the largest and the green subpixel G may be the smallest, but this is merely an example and the embodiments of the present invention are not limited thereto.

[0049] In one embodiment, the display device 1000 may have different pixel densities in different regions.

[0050] For example, the display device 1000 may include a plurality of first pixels PX1 arranged on a first region A1 and a plurality of second pixels PX2 arranged on a second region A2. Here, the first pixels PX1 may be arranged on the first region A1 at a first pixel density, and the second pixels PX2 may be arranged on the second region A2 at a second pixel density smaller than the first pixel density.

[0051] Here, the pixel density may be defined as the total area of ​​the portion where the pixels are actually arranged relative to the total area of ​​the corresponding region, or may be defined as the total area of ​​the pixels included in a preset unit area. Here, the area where each pixel is arranged may be the area of ​​the light emitting surface of the light emitting element included in each pixel. For example, when the pixel includes an organic light emitting element, the pixel area may be the area of ​​the anode electrode exposed between the pixel defining films, or the area of ​​the light emitting layer.

[0052] More specifically, as shown in FIGS. 3 and 4, a unit area UA having the same size may be defined in each of the first area A1 and the second area A2.

[0053] Here, the first pixels PX1 arranged in the first region A1 may be arranged at a relatively high first pixel density based on the unit area UA. For example, the first pixels PX1 may be arranged at a high PPI in the first region A1. Thus, a high-resolution image may be displayed in the first region A1, which occupies most of the area of ​​the display surface and corresponds to the central region.

[0054] Also, the second pixels PX2 arranged on the second region A2 may be arranged at a relatively small second pixel density based on the unit area UA. Here, the second pixel density may be smaller than the first pixel density, for example, the first pixel density may be eight times the second pixel density, but this is merely an example and the embodiment of the present invention is not limited thereto. For example, the second pixels PX2 of the second region A2 may be arranged at a PPI lower than the PPI of the first pixels PX1 of the first region A1.

[0055] Here, as described above, the second region A2 is an outer region (edge ​​region) and may have a curved surface type warped along the strain direction. For example, the substrate of the display device 1000 is made of a ductile substrate, and a plurality of rigid plate patterns are arranged on the substrate at a distance from each other. In the unit area UA of the second region A2, the second pixel PX2 is arranged on the rigid plate pattern, and in the region where the second pixel PX2 is not arranged, a connecting wire having a bent shape is arranged, and the display device 1000 may be stretchable in the second region A2. Therefore, the display device 1000 may have a curved surface type shape warped along the strain direction in the second region A2.

[0056] FIG. 5 is a plan view showing a display device according to an embodiment of the present invention.

[0057] FIG. 6 is a diagram showing an example of a gate driver disposed on the gate region of the display device of FIG.

[0058] Meanwhile, in order to avoid redundant explanations, the following description will focus on content that does not overlap with the content described with reference to Figures 1 to 4, and parts that are not specifically described will follow the above-mentioned embodiments, with the same numbers indicating the same components and similar numbers indicating similar components.

[0059] 5, a display device 1000 according to an embodiment of the present invention may include a display panel DP, a plurality of pixels PX, a gate driver GD, and a data driver DD. In one embodiment, the display device 1000 may further include a printed circuit board PCB.

[0060] As described above, the display device 1000 may include a first region A1 and a second region A2. For example, the display panel DP of the display device 1000 may include a substrate in the first region A1 and the second region A2. Here, the first region A1 and the second region A2 may be defined as a display region.

[0061] Each pixel PX (e.g., the first pixel PX1 in the first region A1 and / or the second pixel PX2 in the second region A2) may include a display element and various driving elements for driving the display element. For example, the various driving elements may include at least one thin film transistor (TFT) and a capacitor. Also, each pixel PX may be connected to various wirings. For example, each pixel PX may be connected to various wirings such as a gate wiring (e.g., a scan signal wiring or an emission signal wiring), a data wiring, a power supply voltage wiring, etc.

[0062] The display panel DP may also include a gate region GIA. The gate region GIA may overlap at least a part of the first region A1 and at least a part of the second region A2. For example, a plurality of gate regions GIA each extending along the second direction DR2 and spaced apart from each other along the first direction DR1 may be arranged to overlap with parts of the first region A1 and the second region A2 (e.g., the third and fourth sub-regions A2c, A2d).

[0063] Meanwhile, in FIG. 5, the display panel DP is shown to include five gate areas GIA, but this is merely an example and the embodiment of the present invention is not limited thereto.

[0064] A gate driver GD may be disposed on the gate region GIA. For example, the gate driver GD may be formed in a gate in array manner on the gate region GIA overlapping at least a portion of the first region A1 and the second region A2. For example, the gate driver GD may be disposed on the same layer as the layer on the display panel DP on which the pixels PX are disposed, or may be disposed on a different layer depending on the embodiment. This may minimize the bezel of the display device 1000.

[0065] 6, a scan driver 200 for supplying a scan signal to the pixel PX and an emission driver 300 for supplying an emission control signal to the pixel PX may be disposed on the gate area GIA. The scan driver 200 may include a first scan driver 210, SC1 for supplying a first scan signal to the pixel PX, a second scan driver 220, SC2 for supplying a second scan signal to the pixel PX, a third scan driver 230, SC3 for supplying a third scan signal to the pixel PX, and a fourth scan driver 240, SC4 for supplying a fourth scan signal to the pixel PX.

[0066] For example, on the gate area GIA, components included in the first scan driver 210 (e.g., transistors, capacitors, various connecting signal wirings, etc.), components included in the second scan driver 220 (e.g., transistors, capacitors, various connecting signal wirings, etc.), components included in the third scan driver 230 (e.g., transistors, capacitors, various connecting signal wirings, etc.), components included in the fourth scan driver 240 (e.g., transistors, capacitors, various connecting signal wirings, etc.), and components included in the light emitting driver 300 (e.g., transistors, capacitors, various connecting signal wirings, etc.) may be arranged.

[0067] In addition, a power supply line PL for providing a low potential voltage VSS to the pixel PX may also be disposed on the gate region GIA. In this manner, the power supply line PL for providing the low potential voltage VSS may be disposed overlapping the first area A1 and the second area A2, which are the display areas, thereby minimizing the bezel of the display device 1000.

[0068] 5, the printed circuit board PCB can transmit signals and voltages for driving the display elements from a controller to the display elements. Thus, the printed circuit board PCB can also be referred to as a driver board. A controller such as an IC chip, a circuit unit, etc. can be attached to the printed circuit board PCB. In addition, a memory, a processor, etc. can be attached to the printed circuit board PCB.

[0069] The data driver DD may provide data signals to the pixels PX disposed in the first region A1 and / or the second region A2. For example, the data driver DD may provide data signals to the pixels PX through data lines.

[0070] In one embodiment, the data driver DD is configured in the form of an IC chip (Integrated Circuit Chip) and may be referred to as a data integrated circuit. The data driver DD may be implemented in a COF (Chip on Film) format, a COB (Chip on Board) format, a COG (Chip on Glass) format, a TCP (Tape Carrier Package) format, etc.

[0071] In the following, a specific cross-sectional structure of the display panel DP will be described with reference to FIG.

[0072] FIG. 7 is a cross-sectional view that illustrates an example of a display panel included in the display device of FIG.

[0073] 5 to 7, at least one transistor TR1, TR2 and a light emitting element LD may be disposed on a substrate SUB.

[0074] Meanwhile, the first transistor TR1 among the transistors disposed on the substrate SUB may be a polysilicon semiconductor transistor. For example, the first transistor TR1 may be a p-type MOSFET transistor (PMOS transistor) including a polysilicon semiconductor layer formed through a low temperature poly-silicon (LTPS) process as an active layer (channel).

[0075] Among the transistors disposed on the substrate SUB, the second transistor TR2 may be an oxide semiconductor transistor. For example, the second transistor TR2 may be an n-type MOSFET transistor (NMOS transistor) including an oxide semiconductor layer as an active layer (channel).

[0076] The substrate SUB is a base substrate of the display panel DP and may be a substantially transparent light-transmitting substrate. The substrate SUB may be a flexible substrate made of a plastic material. Here, the flexible property may be interpreted as being bendable, unbreakable, rollable, foldable, etc.

[0077] For example, the substrate SUB may include plastic, in which case the substrate SUB may also be referred to as a plastic film or a plastic substrate. For example, the substrate SUB may include at least one selected from the group consisting of polyester-based polymers, silicon-based polymers, acrylic-based polymers, polyolefin-based polymers, and polymers thereof. As an example, the substrate SUB may include polyimide (PI).

[0078] On the other hand, if the substrate SUB contains polyimide (PI), moisture may penetrate the substrate SUB made of polyimide (PI) and progress to the thin film transistors and other components contained in the pixel PX, reducing the reliability of the pixel PX and thereby reducing the performance of the display device 1000.

[0079] Thus, in one embodiment, the substrate SUB may include a double polyimide (PI). Also, the substrate SUB may further include an inorganic film formed between the two polyimides (PI), thereby blocking moisture components from penetrating through the lower polyimide (PI), thereby improving the reliability of product performance. Also, the inorganic film formed between the two polyimides (PI) may block charges charged in the lower polyimide (PI), thereby improving the reliability of product performance.

[0080] For example, as shown in FIG. 7, the substrate SUB may include a first sub-substrate SUBa including polyimide (PI), a second sub-substrate SUBb disposed on the first sub-substrate SUBa and including an inorganic insulating material, and a third sub-substrate SUBc disposed on the second sub-substrate SUBb and including polyimide (PI).

[0081] The inorganic insulating material contained in the second sub-substrate SUBb is silicon nitride (SiN x ) or silicon oxide (SiO x ) or multiple layers thereof. However, this is merely an example, and the embodiment of the present invention is not limited thereto. For example, the inorganic insulating material included in the second sub-substrate SUBb may be silicon oxide (SiO x For example, the inorganic insulating material included in the second sub-substrate SUBb may include silicon dioxide (Silica or Silicon Dioxide: SiO2). As another example, the inorganic insulating material included in the second sub-substrate SUBb may include silicon dioxide (SiO2) and silicon nitride (SiN x ) bilayer.

[0082] Meanwhile, although not separately shown in FIG. 7, a backplate and a metal plate may be further disposed under the substrate SUB.

[0083] A pattern layer 120 may be disposed on the substrate SUB. The pattern layer 120 supports the pixels PX, the gate drivers GD, and the connecting wires, and may include a plurality of plate patterns and a plurality of line patterns disposed on the second region A2. The pattern layer 120 will be described in more detail with reference to FIGS. 8 to 10.

[0084] On the substrate SUB (or patterned layer 120) a shielding metal layer may be arranged which includes at least one shielding metal pattern BSM.

[0085] The shielding metal pattern BSM included in the shielding metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0086] Depending on the embodiment, the shielding metal pattern BSM may be defined as a component included in the first transistor TR1. For example, the shielding metal pattern BSM may constitute a lower gate electrode of the first transistor TR1.

[0087] The first buffer layer BUF1 may be disposed on the substrate SUB (or the pattern layer 120). For example, the first buffer layer BUF1 may be disposed on the substrate SUB (or the pattern layer 120) to cover the shielding metal pattern BSM.

[0088] In one embodiment, the first buffer layer BUF1 may include a multi-buffer layer BUF1a disposed on the substrate SUB (or the patterned layer 120) and an active buffer layer BUF1b disposed on the multi-buffer layer BUF1a.

[0089] The first transistor TR1 may be disposed on the first buffer layer BUF1. The first transistor TR1 may include a first semiconductor pattern ACT1, a first gate electrode G1, a source electrode SE1, and a drain electrode DE1. Depending on the embodiment, as described above, the first transistor TR1 may further include a shielding metal pattern BSM disposed between the first buffer layer BUF1 and the substrate SUB.

[0090] A first semiconductor layer including at least one first semiconductor pattern ACT1 may be disposed on the first buffer layer BUF1.

[0091] For example, in the first semiconductor layer, a first semiconductor pattern ACT1 included in a first transistor TR1 may be disposed on a first buffer layer BUF1. The first semiconductor pattern ACT1 may include a first region S1 (or a source electrode, a source region), a second region D1 (or a drain electrode, a drain region), and a channel region A1 therebetween. As described above, the first semiconductor pattern ACT1 may include a polysilicon semiconductor layer formed through a low temperature poly-silicon (LTPS) process.

[0092] A first gate insulating layer GI1 may be disposed on the first semiconductor layer, e.g., the first semiconductor pattern ACT1. For example, the first gate insulating layer GI1 may be disposed to cover the first semiconductor layer, e.g., the first semiconductor pattern ACT1, and may insulate the first semiconductor pattern ACT1 and the first gate electrode G1 of the first transistor TR1.

[0093] For example, the first gate insulating layer GI1 is made of silicon nitride (SiN x ) or silicon oxide (SiO x ) or multiple layers thereof, but is not limited thereto.

[0094] A first conductive layer GAT1 may be disposed on the first gate insulating layer GI1. The first conductive layer GAT1 may constitute at least a part of a light emission control line for providing a light emission control signal to the pixel PX, a scan line for providing a scan signal, and a power supply line for providing various power supply voltages. Here, when the first conductive layer GAT1 constitutes at least a part of a power supply line for providing a power supply voltage, the first conductive layer GAT1 may be made of a highly conductive material such as a metal or a conductive oxide. For example, the first conductive layer GAT1 may be a single layer or a multilayer including aluminum (Al), copper (Cu), titanium (Ti), etc. In some embodiments, the first conductive layer GAT1 may be made of a triple layer of titanium, aluminum, and titanium (Ti / Al / Ti) sequentially arranged. However, the first conductive layer GAT1 is not limited to this, and the first conductive layer GAT1 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0095] In the first conductive layer GAT1, a first gate electrode G1 of a first transistor TR1 constituting at least a part of a light emission control line or a scan line can be disposed on the first gate insulating layer GI1.

[0096] The first gate electrode G1 of the first transistor TR1 may be disposed to at least partially overlap the first semiconductor pattern ACT1.

[0097] A first insulating layer ILD1 may be disposed on the first conductive layer GAT1, for example, the first gate electrode G1 of the first transistor TR1. For example, the first insulating layer ILD1 may be disposed to cover the first conductive layer GAT1, for example, the first gate electrode G1 of the first transistor TR1.

[0098] The first insulating layer ILD1 is made of silicon nitride (SiN x ) or silicon oxide (SiO x ) or multiple layers thereof, but is not limited thereto.

[0099] A second conductive layer TM1 may be disposed on the first insulating layer ILD1. The second conductive layer TM1 may include molybdenum (Mo), copper (Cu), titanium (Ti), etc., and may be a single layer or multiple layers.

[0100] A second insulating layer ILD2 may be disposed on the second conductive layer TM1. For example, the second insulating layer ILD2 may be disposed to cover the second conductive layer TM1.

[0101] The first insulating layer ILD1 is made of silicon nitride (SiN x ) or silicon oxide (SiO x ) or multiple layers thereof, but is not limited thereto.

[0102] A third conductive layer TM2 may be disposed on the second insulating layer ILD2. The third conductive layer TM2 may include molybdenum (Mo), copper (Cu), titanium (Ti), etc., and may be a single layer or multiple layers.

[0103] For example, in the third conductive layer TM2, the first source electrode SE1 and the first drain electrode DE1 of the first transistor TR1 may be disposed on the second insulating layer ILD2. In the third conductive layer TM2, the first source electrode SE1 of the first transistor TR1 may contact the first region S1 of the first semiconductor pattern ACT1 through a contact hole penetrating the second insulating layer ILD2, the first insulating layer ILD1, and the first gate insulating layer GI1, and in the third conductive layer TM2, the first drain electrode DE1 of the first transistor TR1 may contact the second region D1 of the first semiconductor pattern ACT1 through a contact hole penetrating the second insulating layer ILD2, the first insulating layer ILD1, and the first gate insulating layer GI1.

[0104] A third insulating layer ILD3 may be disposed on the third conductive layer TM2, for example, on the first source electrode SE1 and the first drain electrode DE1 of the first transistor TR1. For example, the third insulating layer ILD3 may be disposed to cover the third conductive layer TM2.

[0105] The third insulating layer ILD3 is made of silicon nitride (SiN x ) or silicon oxide (SiO x ) or multiple layers thereof, but is not limited thereto.

[0106] A second buffer layer BUF2 may be disposed on the third insulating layer ILD3.

[0107] The second buffer layer BUF2 is made of silicon nitride (SiN x ) or silicon oxide (SiO x ) or multiple layers thereof, but is not limited thereto.

[0108] A second semiconductor layer including at least one second semiconductor pattern ACT2 may be disposed on the second buffer layer BUF2.

[0109] For example, in the second semiconductor layer, the second semiconductor pattern ACT2 included in the second transistor TR2 may be disposed on the second buffer layer BUF2. The second semiconductor pattern ACT2 may include a first region S2 (or a source electrode, a source region), a second region D2 (or a drain electrode, a drain region), and a channel region A2 therebetween. As described above, the second semiconductor pattern ACT2 may include an oxide semiconductor layer.

[0110] A second gate insulating layer GI2 may be disposed on the second semiconductor layer, for example, the second semiconductor pattern ACT2. The second gate insulating layer GI2 may be formed of silicon nitride (SiN x ) or silicon oxide (SiO x ) or multiple layers thereof, but is not limited thereto.

[0111] A fourth conductive layer GAT2 may be disposed on the second gate insulating layer GI2. The fourth conductive layer GAT2 may include molybdenum (Mo), copper (Cu), titanium (Ti), etc., and may be a single layer or multiple layers.

[0112] For example, in the fourth conductive layer GAT2, the second gate electrode G2 of the second transistor TR2 constituting at least a part of the scan line can be disposed on the second gate insulating layer GI2.

[0113] The second gate electrode G2 of the second transistor TR2 may be disposed to at least partially overlap the second semiconductor pattern ACT2.

[0114] A fourth insulating layer ILD4 may be disposed on the fourth conductive layer GAT2, for example, the second gate electrode G2 of the second transistor TR2. For example, the fourth insulating layer ILD4 may be disposed to cover the fourth conductive layer GAT2, for example, the second gate electrode G2 of the second transistor TR2.

[0115] A fifth conductive layer SD1 may be disposed on the fourth insulating layer ILD4. The fifth conductive layer SD1 may constitute at least a portion of a power supply wiring that provides a power supply voltage. Here, since the fifth conductive layer SD1 constitutes at least a portion of the power supply wiring that provides a power supply voltage, the fifth conductive layer SD1 may be formed of a highly conductive material such as a metal or a conductive oxide. For example, the fifth conductive layer SD1 may be formed as a single layer or multiple layers including aluminum (Al), copper (Cu), titanium (Ti), etc. In some embodiments, the fifth conductive layer SD1 may be formed as a triple layer of titanium, aluminum, and titanium (Ti / Al / Ti) that are sequentially arranged. However, the fifth conductive layer SD1 is not limited thereto, and the fifth conductive layer SD1 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0116] Also, at least a portion of the fifth conductive layer SD1 may function as a connecting electrode. For example, at least a portion of the fifth conductive layer SD1 may be connected to the source electrode SE1 and / or the drain electrode DE1 of the first transistor TR1 in the third conductive layer TM2 through a contact hole penetrating the fourth insulating layer ILD4, the second gate insulating layer GI2, the second buffer layer BUF2, and the third insulating layer ILD3, or may be in contact with a portion of the fourth conductive layer GAT2 through a contact hole penetrating the fourth insulating layer ILD4.

[0117] Also, at least a part of the fifth conductive layer SD1 may constitute the second source electrode SE2 and the second drain electrode DE2 of the second transistor TR2. For example, in the fifth conductive layer SD1, the second source electrode SE2 of the second transistor TR2 may contact the first region S2 of the second semiconductor pattern ACT2 through a contact hole penetrating the fourth insulating layer ILD4 and the second gate insulating layer GI2, and the second drain electrode DE2 of the second transistor TR2 in the fifth conductive layer SD1 may contact the second region D2 of the second semiconductor pattern ACT2 through a contact hole penetrating the fourth insulating layer ILD4 and the second gate insulating layer GI2.

[0118] In one embodiment, at least a portion of the fifth conductive layer SD1 may constitute a clock line CLK that provides a clock signal to the gate driver GD arranged on the gate area GIA of the display panel DP described with reference to Figures 5 and 6. For example, at least a portion of the fifth conductive layer SD1 may constitute a clock line CLK that transmits a clock signal that is an input signal of each stage included in the gate driver GD (e.g., the scan driver 200 and / or the light emission driver 300) arranged on the gate area GIA. As an example, the clock line CLK that transmits the clock signal in the fifth conductive layer SD1 may be electrically connected to each stage (e.g., at least a portion of the transistors constituting each stage) of the gate driver GD through a line jumping structure.

[0119] A first planarization layer PNL1 may be disposed on the fifth conductive layer SD1. The first planarization layer PNL1 may be an organic layer for planarizing the upper portion and protecting components disposed below. For example, the first planarization layer PNL1 may include an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0120] A sixth conductive layer SD2 may be disposed on the first planarization layer PNL1.

[0121] The sixth conductive layer SD2 may constitute at least a part of a data wiring for providing a data signal to the pixel PX or a power wiring for providing a high potential power supply voltage VDD. Here, since the sixth conductive layer SD2 constitutes at least a part of a power wiring for providing a power supply voltage, the sixth conductive layer SD2 may be made of a highly conductive material such as a metal or a conductive oxide. For example, the sixth conductive layer SD2 may be a single layer or a multilayer including aluminum (Al), copper (Cu), titanium (Ti), etc. In some embodiments, the sixth conductive layer SD2 may be a triple layer of titanium, aluminum, and titanium (Ti / Al / Ti) arranged in sequence. However, the sixth conductive layer SD2 is not limited thereto, and the sixth conductive layer SD2 may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0122] In addition, at least a portion of the sixth conductive layer SD2 may function as a connecting electrode. For example, at least a portion of the sixth conductive layer SD2 may be connected to at least a portion of the fifth conductive layer SD1 through a contact hole penetrating the first planarization layer PNL1.

[0123] A second planarization layer PNL2 may be disposed on the sixth conductive layer SD2. The second planarization layer PNL2 may be an organic layer for planarizing the upper portion and protecting components disposed below. For example, the second planarization layer PNL2 may include an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0124] A seventh conductive layer SD3 may be disposed on the second planarization layer PNL2. The seventh conductive layer SD3 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0125] In one embodiment, at least a part of the seventh conductive layer SD3 can function as a shielding pattern SM. For example, as described above, at least a part of the fifth conductive layer SD1 constitutes at least a part of the clock wiring CLK that transmits a clock signal to the gate driver GD, so that signal interference may occur between the clock wiring CLK and the anode electrode AND of the light emitting element LD located above the fifth conductive layer SD1. In this case, the voltage of the anode electrode AND of the light emitting element LD may become unstable, and the display quality of the desired pixel PX may be reduced. As a result, in the case of the display device 1000 according to the embodiment of the present invention, the seventh conductive layer SD3 disposed above the second planarization layer PNL2 functions as a shielding pattern SM that performs signal shielding between at least a part of the fifth conductive layer SD1 (e.g., the clock wiring CLK) and the anode electrode AND of the light emitting element LD, thereby improving the display quality.

[0126] According to an embodiment, for the shielding function, the shielding pattern SM in the seventh conductive layer SD3 may have a width greater than the width of the anode electrode AND of the light emitting element LD.

[0127] In addition, at least a portion of the seventh conductive layer SD3 may be connected to at least a portion of the sixth conductive layer SD2 through a contact hole penetrating the second planarization layer PNL2.

[0128] A third planarization layer PNL3 may be disposed on the seventh conductive layer SD3. The third planarization layer PNL3 may be an organic layer for planarizing the upper portion and protecting components disposed below. For example, the third planarization layer PNL3 may include an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0129] The light emitting element LD may be disposed on the third planarization layer PNL3. The light emitting element LD may include an anode electrode AND (or a first electrode), a cathode electrode CAD (or a second electrode), and an emission layer EML formed therebetween.

[0130] The anode electrode AND may be disposed on the third planarization layer PNL3.

[0131] Meanwhile, when the display device 1000 is a top emission type in which light emitted from the light emitting element LD is emitted to the top of the substrate SUB on which the light emitting element LD is disposed, the anode electrode AND may further include a transparent conductive layer and a reflective layer on the transparent conductive layer. The transparent conductive layer may be made of a transparent conductive oxide such as ITO or IZO, and the reflective layer may include silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof.

[0132] The bank layer BNK can be arranged to cover at least a part of the anode electrode AND, and can leave the remaining part of the anode electrode AND open. For example, the bank layer BNK can be arranged to leave a part corresponding to the light-emitting area of ​​the pixel PX open. This allows a part of the anode electrode AND to be exposed by the open part of the bank layer BNK.

[0133] The bank layer BNK is made of silicon nitride (SiN x ), silicon oxide (SiO x The insulating material may include, but is not limited to, inorganic insulating materials such as benzocyclobutene-based resin, acrylic resin, or imide-based resin.

[0134] An emitting layer EML may be disposed on the front surface of the pixel PX on the upper surface of the bank layer BNK and the anode electrode AND, while the opened portion of the bank layer BNK may allow a part of the emitting layer EML to contact the exposed part of the anode electrode AND.

[0135] Depending on the embodiment, the light emitting layer EML may include multiple organic films.

[0136] A cathode electrode CAD may be disposed on the emitting layer EML. For example, the cathode electrode CAD may be disposed on the front surface of the pixel PX.

[0137] The anode electrode AND, the light emitting layer EML, and the cathode electrode CAD may form a light emitting element LD.

[0138] Meanwhile, the spacer SPC may be for preventing the screen mask and the substrate from directly contacting each other during the deposition of the emitting layer EML. The spacer SPC may be disposed on the bank layer BNK, and may be applied so that the emitting layer EML and the cathode electrode CAD pass over the spacer SPC disposed inside the display area AA.

[0139] According to an embodiment, the light emitting layer EML and / or the cathode electrode CAD may not extend beyond the spacer SPC. Since the spacer SPC is disposed only on a part of the bank layer BNK inside the display area AA, the cathode electrode CAD may have a structure in which it covers and is connected to the entire display area AA even if the cathode electrode CAD does not extend beyond the spacer SPC.

[0140] An encapsulation layer may be disposed on the light emitting element LD. For example, the encapsulation layer may include a first inorganic encapsulation layer PAS1, a first organic encapsulation layer PCL1 on the first inorganic encapsulation layer PAS1, a second inorganic encapsulation layer PAS2 on the first organic encapsulation layer PCL1, a second organic encapsulation layer PCL2 on the second inorganic encapsulation layer PAS2, and a third inorganic encapsulation layer PAS3 on the second organic encapsulation layer PCL2. The first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 may function to block the penetration of moisture and oxygen. For example, the first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 may be made of an inorganic material such as silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. The first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 may be formed by a chemical vapor deposition process or an atomic layer deposition process.

[0141] The first organic encapsulation layer PCL1 may be disposed between the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2, and the second organic encapsulation layer PCL2 may be disposed between the second inorganic encapsulation layer PAS2 and the third inorganic encapsulation layer PAS3. The first organic encapsulation layer PCL1 and the second organic encapsulation layer PCL2 may be formed to a relatively large thickness compared to the first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and / or the third inorganic encapsulation layer PAS3 so as to adsorb and / or block particles that may be generated during the manufacturing process. The first organic encapsulation layer PCL1 and the second organic encapsulation layer PCL2 may be made of an organic material such as silicon oxycarbonate (SiOCz) acrylic or epoxy-based resin. The first organic encapsulation layer PCL1 and the second organic encapsulation layer PCL2 may be formed by a coating process, for example, an inkjet coating process or a slit coating process.

[0142] FIG. 8 is an enlarged view showing an example in which a part of the first sub-region, the second sub-region, the fifth sub-region, the sixth sub-region, the seventh sub-region, and the eighth sub-region in FIG. 5 is enlarged.

[0143] FIG. 9a is an enlarged view showing an example in which a part of the third sub-region and the fourth sub-region in FIG. 5 is enlarged.

[0144] FIG. 9b is an enlarged view showing another example in which a part of the third sub-region and the fourth sub-region in FIG. 5 is enlarged.

[0145] On the other hand, Figure 8 is an enlarged view showing an example of a plan view of a portion of one of the first sub-region A2a, the second sub-region A2b, the fifth sub-region A2e, the sixth sub-region A2f, the seventh sub-region A2g, and the eighth sub-region A2h, Figure 9a is an enlarged view showing an example of a plan view of a portion of one of the third sub-region A2c and the fourth sub-region A2d, and Figure 9b is an enlarged view showing another example of a plan view of a portion of one of the third sub-region A2c and the fourth sub-region A2d.

[0146] 1, 3, 4, 5 to 9a, a display device 1000 according to an embodiment of the present invention may include a substrate SUB, a pattern layer 120, a plurality of pixels PX, a gate driver GD, and a data driver DD.

[0147] As described above, the substrate SUB is the base material of the display panel DP, and is a substrate for supporting and protecting the various components of the display device 1000.

[0148] The substrate SUB may be a ductile substrate capable of reversibly expanding and contracting. Accordingly, the substrate SUB may also be called a stretchable substrate, an elastic substrate, an elongated substrate, a ductile substrate, or a flexible substrate. The modulus of elasticity of the substrate SUB may range from several MPa to several hundred MPa. The ductile breaking rate of the substrate SUB may be 100% or more. Here, the ductile breaking rate refers to the elongation rate at which the object being stretched breaks or cracks.

[0149] A pattern layer 120 may be disposed on the substrate SUB. In one embodiment, the pattern layer 120 may support the pixels PX, the gate drivers GD, and the connecting lines 181, 182, 183, and 184 disposed on the second region A2.

[0150] In one embodiment, the pattern layer 120 may include a plurality of first plate patterns 121, a plurality of second plate patterns 122, a plurality of first wiring patterns 123, and a plurality of second wiring patterns 124 arranged in the second region A2.

[0151] The first plate pattern 121 may be disposed on the second region A2 of the substrate SUB. For example, the first plate pattern 121 may be disposed on the upper portions of the first to eighth sub-regions A2a to A2h of the substrate SUB. Also, as shown in Fig. 5, Fig. 8 and Fig. 9a, a plurality of second pixels PX2 including a plurality of sub-pixels SPX (e.g., the sub-pixels R, G and B described with reference to Fig. 4) may be disposed on the first plate pattern 121.

[0152] The first plate patterns 121 may be spaced apart from one another and disposed on the second region A2 of the substrate SUB. For example, as shown in Figures 8 and 9a, the first plate patterns 121 may be disposed in a matrix form on the second region A2 of the substrate SUB, but this is merely an example and the embodiment of the present invention is not limited thereto.

[0153] The second plate pattern 122 may be disposed on the second region A2 of the substrate SUB. For example, the second plate pattern 122 may be disposed on the upper portions of the third and fourth sub-regions A2c and A2d of the substrate SUB. Also, as shown in Figures 5 and 9a, the gate driver GD may be disposed on the second plate pattern 122. For example, various transistors, capacitors, and signal wirings constituting the gate driver GD may be disposed on the second plate pattern 122.

[0154] The second plate patterns 122 may be spaced apart from each other and disposed on a portion (e.g., the third and fourth sub-regions A2c, A2d) of the second region A2 of the substrate SUB. For example, as shown in Fig. 9a, the second plate patterns 122 may be disposed in a matrix form on the third and fourth sub-regions A2c, A2d of the substrate SUB, but this is merely an example and the embodiment of the present invention is not limited thereto.

[0155] For example, in the second region A2, on the third and fourth sub-regions A2c and A2d, the first plate pattern 121 and the second plate pattern 122 may be integrally formed.

[0156] Specifically, referring to Fig. 9b further, the pattern layer 120_1 may include a plurality of plate patterns 121_1 disposed on the third and fourth sub-regions A2c, A2d. The plurality of plate patterns 121_1 may be spaced apart from each other and disposed on the third and fourth sub-regions A2c, A2d in the second region A2 of the substrate SUB. For example, as shown in Fig. 9b, each of the plurality of plate patterns 121_1 may extend along a first direction DR1 on the third and fourth sub-regions A2c, A2d of the substrate SUB, and the plurality of plate patterns 121_1 may be spaced apart from each other along a second direction DR2.

[0157] In addition, a plurality of second pixels PX2 including a plurality of sub-pixels SPX (e.g., sub-pixels R, G, B described with reference to FIG. 4) and a gate driver GD (e.g., various transistors, capacitors, signal wiring, etc. constituting the gate driver GD) may be arranged on the plurality of plate patterns 121_1. For example, in the third and fourth sub-regions A2c and A2d, the gate driver GD (e.g., various transistors, capacitors, signal wiring, etc. constituting the gate driver GD) may be arranged on the plate pattern 121_1 corresponding to the gate region GIA, and the second pixel PX2 may be arranged on the plate pattern 121_1 corresponding to the remaining region except the gate region GIA in the third and fourth sub-regions A2c and A2d. The plate pattern 121_1 may be regarded as a first plate pattern 121 and a second plate pattern 122 integrally formed.

[0158] 9a, the first wiring pattern 123 may be disposed on the second region A2 of the substrate SUB. For example, the first wiring pattern 123 may be disposed on each of the first to eighth sub-regions A2a to A2h of the substrate SUB.

[0159] The first wiring pattern 123 is disposed on the second region A2 and is a pattern that connects adjacent first plate patterns 121, and may be referred to as a first connecting pattern. That is, at least one first wiring pattern 123 may be disposed between the first plate patterns 121.

[0160] In one embodiment, referring to FIG. 8 and FIG. 9a, each of the first wiring patterns 123 may have a bent shape. For example, the first wiring patterns 123 may have a sine wave shape. However, this is merely an example, and the shape of the first wiring patterns 123 is not limited thereto. For example, each of the first wiring patterns 123 may have a zigzag shape. As another example, each of the first wiring patterns 123 may have various shapes, such as a plurality of diamond-shaped substrates connected at their vertices and extending. Thus, the number and shape of the first wiring patterns 123 shown in FIG. 8 and FIG. 9a are merely an example, and the number and shape of the first wiring patterns 123 may be variously changed according to design.

[0161] Also, connecting wires 181, 182, and 183 may be disposed on the first wiring patterns 123. The first wiring patterns 123 may serve as a substrate supporting the connecting wires (eg, SD3(CL) in FIG. 10).

[0162] The second wiring pattern 124 may be disposed on the second region A2 of the substrate SUB. For example, the second wiring pattern 124 may be disposed on the upper portions of the third and fourth sub-regions A2c and A2d of the substrate SUB.

[0163] The second wiring pattern 124 is disposed on the second region A2 and is a pattern that connects adjacent second plate patterns 122, and may be referred to as a second connecting pattern. That is, at least one second wiring pattern 124 may be disposed between the second plate patterns 122.

[0164] In one embodiment, referring to FIG. 9a, each of the second wiring patterns 124 may have a bent shape. For example, the second wiring patterns 124 may have a sine wave shape. However, this is merely an example, and the shape of the second wiring patterns 124 is not limited thereto. For example, each of the second wiring patterns 124 may have a zigzag shape. As another example, each of the second wiring patterns 124 may have various shapes, such as a plurality of diamond-shaped substrates connected at their vertices and extending. Thus, the number and shape of the second wiring patterns 124 shown in FIG. 9a are merely an example, and the number and shape of the second wiring patterns 124 may be variously changed according to design.

[0165] In addition, the fourth connecting wires 184 may be disposed on the upper portions of the second wiring patterns 124. The second wiring patterns 124 may serve as a substrate supporting the fourth connecting wires 184.

[0166] In one embodiment, each of the first plate pattern 121, the second plate pattern 122, the first wiring pattern 123, and the second wiring pattern 124 may be a rigid pattern. For example, each of the first plate pattern 121, the second plate pattern 122, the first wiring pattern 123, and the second wiring pattern 124 may be rigid compared to the substrate SUB. Therefore, the modulus of elasticity of each of the first plate pattern 121, the second plate pattern 122, the first wiring pattern 123, and the second wiring pattern 124 may be higher than the modulus of elasticity of the substrate SUB. The modulus of elasticity is a parameter indicating the ratio of deformation to stress applied to the substrate, and when the modulus of elasticity is relatively high, the hardness may be relatively high. As a result, first plate pattern 121, second plate pattern 122, first wiring pattern 123, and second wiring pattern 124 may also be referred to as first to fourth rigidity patterns, respectively. For example, the elastic modulus of each of first plate pattern 121, second plate pattern 122, first wiring pattern 123, and second wiring pattern 124 may be 1000 times or more higher than the elastic modulus of substrate SUB, but this is merely an example and the embodiment of the present invention is not limited thereto.

[0167] In an embodiment, each of the first plate pattern 121, the second plate pattern 122, the first wiring pattern 123, and the second wiring pattern 124 may include a plastic material having lower flexibility than the substrate SUB. For example, each of the first plate pattern 121, the second plate pattern 122, the first wiring pattern 123, and the second wiring pattern 124 may include at least one material selected from the group consisting of polyimide (PI), polyacrylate, and polyacetate.

[0168] According to an embodiment, first plate pattern 121, second plate pattern 122, first wiring pattern 123, and second wiring pattern 124 may be made of the same material, but are not limited thereto and may be made of different materials. When first plate pattern 121, second plate pattern 122, first wiring pattern 123, and second wiring pattern 124 are made of the same material, first plate pattern 121, second plate pattern 122, first wiring pattern 123, and second wiring pattern 124 may be integrally formed.

[0169] In one embodiment, as shown in FIG. 8, in the first, second, fifth, sixth, seventh and eighth sub-regions A2a, A2b, A2e, A2f, A2g and A2h, a first connecting wire 181 extending along a first direction DR1 and a second connecting wire 182 extending along a second direction DR2 may be arranged on the first wiring pattern 123.

[0170] Here, each of the first connecting wire 181 and the second connecting wire 182 may be a connecting wire that connects second pixels PX2 arranged on the top of each of the first plate patterns 121 spaced apart from each other on the first, second, fifth, sixth, seventh and eighth sub-regions A2a, A2b, A2e, A2f, A2g and A2h.

[0171] Also, in one embodiment, as shown in FIG. 9a, in the third and fourth sub-regions A2c and A2d, a third connecting wire 183 extending along the second direction DR2 and a fourth connecting wire 184 extending along the second direction DR2 may be arranged on the first wiring pattern 123.

[0172] Here, the third connecting wires 183 may be connecting wires that connect the second pixels PX2 disposed on the first plate patterns 121 spaced apart from each other in the third and fourth sub-regions A2c and A2d.

[0173] Also, the fourth connection wire 184 may be a connection wire that connects the gate drivers GD disposed on the second plate patterns 122 spaced apart from each other in the third and fourth sub-regions A2c and A2d.

[0174] The sub-pixel SPX may be connected to a plurality of connecting lines 181, 182, and 183.

[0175] For example, sub-pixels SPX included in second pixel PX2 arranged on the first, second, fifth, sixth, seventh and eighth sub-regions A2a, A2b, A2e, A2f, A2g and A2h in the second region A2 may be electrically connected to a first connecting line 181 extending along the second direction DR2 and a second connecting line 182 extending along the first direction DR1.

[0176] As another example, the sub-pixel SPX included in the second pixel PX2 arranged on the third and fourth sub-regions A2c and A2d in the second region A2 may be electrically connected to a third connecting line 183 extending along the second direction DR2.

[0177] In one embodiment, the connecting lines 181, 182, and 183 connected to the subpixels SPX may include various lines such as a gate line (e.g., a scan signal line or a light emission control line), a data line, a high potential voltage line, a low potential voltage line, and an initialization voltage line.

[0178] Meanwhile, as described above, the gate driver GD is disposed on the upper portion of the second plate pattern 122 on the gate area GIA and can supply gate signals to the pixels PX (e.g., the first pixel PX1 and the second pixel PX2). Also, as shown in Fig. 5 and Fig. 9a, the gate area GIA can be disposed to overlap with a portion of the first area A1 and the second area A2 (e.g., the third and fourth sub-areas A2c, A2d).

[0179] The gate driver GD includes a plurality of stages formed on each of the second plate patterns 122, and the stages included in the gate driver GD may be electrically connected to each other through a plurality of gate connection lines. Thus, a gate signal output from any one stage may be transmitted to another stage. Each stage may sequentially supply gate signals to a plurality of pixels PX (e.g., the first pixel PX1 or the second pixel PX2) connected to the respective stage.

[0180] In addition, the gate driver GD may be connected to the fourth connecting line 184 .

[0181] For example, the gate driver GD (e.g., a stage included in the gate driver GD) arranged on the third and fourth sub-regions A2c, A2d in the second region A2 may be electrically connected to a fourth connecting wire 184 extending along the second direction DR2.

[0182] FIG. 10 is a cross-sectional view showing an example taken along line III-III' shown in FIG.

[0183] Meanwhile, in order to avoid redundant explanations, the following description will focus on content that does not overlap with the content described with reference to Figures 1 to 9b, and parts that are not specifically described will follow the above-mentioned embodiments, with the same numbers indicating the same components and similar numbers indicating similar components.

[0184] 10, a cross-sectional structure of the display device 1000 is shown in a second region A2 (e.g., a third sub-region A2c), a connection region CA, and a driving region DA. Here, the driving region DA may correspond to a region where the data driver DD and the like are arranged, and the connection region CA may refer to a region between the display panel DP and the data driver DD.

[0185] 5 to 10, a pattern layer 120 and various insulating layers (e.g., first and second buffer layers BUF1, BUF2, first and second gate insulating layers GI1, GI2, first to fourth insulating layers ILD1 to ILD4, first to third planarization layers PNL1 to PNL3, etc.) may be arranged on a substrate SUB.

[0186] In addition, the transistors TR1, TR2, the light-emitting element LD, and the sealing layer (e.g., the first to third inorganic sealing layers PAS1, PAS2, PAS3, the first and second organic sealing layers PCL1, PCL2) may be disposed on the substrate SUB or the second region A2 of the pattern layer 120, for example, the third sub-region A2c shown in FIG. 10. For example, the transistors TR1, TR2, the light-emitting element LD, and the sealing layer (e.g., the first to third inorganic sealing layers PAS1, PAS2, PAS3, the first and second organic sealing layers PCL1, PCL2) may be disposed on the plate pattern PP in the pattern layer 120. Meanwhile, the plate pattern PP shown in FIG. 10 may be the plate patterns 121, 121_1, 122 described with reference to FIGS. 8, 9a, and 9b.

[0187] In addition, a data driver DD may be disposed on the driving region DA of the substrate SUB or the pattern layer 120, and a connection signal line CL connecting the display panel DP and the data driver DD may be disposed on the connection region CA of the substrate SUB or the pattern layer 120. For example, a data driver DD may be disposed on a plate pattern PP disposed in the driving region DA of the pattern layer 120, and a connection signal line CL connecting the display panel DP and the data driver DD may be disposed on a wiring pattern LP disposed on the connection region CA of the pattern layer 120. Meanwhile, the wiring pattern LP shown in Fig. 10 may be the wiring patterns 123 and 124 described with reference to Figs. 8, 9a, and 9b.

[0188] In one embodiment, at least a portion of the seventh conductive layer SD3 disposed on the second planarization layer PNL2 may be disposed extending from the second region A2 (e.g., the third sub-region A2c) to the coupling region CA and the driving region DA, while at least a portion of the seventh conductive layer SD3 (e.g., the coupling signal line CL) may be disposed on the pattern layer 120 (e.g., the wiring pattern LP) so as to directly contact the pattern layer 120 (e.g., the wiring pattern LP) on the coupling region CA.

[0189] As described above, in the display device according to the embodiment of the present invention, the gate region in which various elements constituting the gate driver are arranged may be arranged to overlap at least a part of the display region (first region, second region) in which various elements constituting the pixels are arranged. That is, since the gate driver is arranged and formed on the gate region in a Gate In Array (GIA) manner, the bezel area of ​​the display device may be minimized.

[0190] In addition, in the case of a display device according to an embodiment of the present invention, a first region which is a central region and a second region which is an outer region surrounding the first region may be included, and second pixels arranged in the second region may be arranged at a lower pixel density than first pixels arranged in the first region. Thus, the display device may be deformed in the second region which is the outer region, and the second region which is the outer region may be configured to have a curved surface.

[0191] Display devices according to various embodiments of the present invention can be described as follows.

[0192] In order to solve the above-mentioned problems, a display device according to an embodiment of the present invention may include a display panel including a substrate including a first region and a second region surrounding the first region, a data driver for supplying data signals to the pixels through data lines, and a gate driver including a plurality of stages for supplying gate signals to the pixels through gate lines. Each of the stages included in the gate driver may be disposed on a gate region at least partially overlapping the first region and the second region, and the plurality of pixels may include a plurality of first pixels disposed on the first region and a plurality of second pixels disposed on the second region, the first pixels may be disposed at a first pixel density in the first region, and the second pixels may be disposed at a second pixel density smaller than the first pixel density in the second region.

[0193] In one embodiment, the second region may include a first sub-region adjacent to one side of the first region along the first direction, a second sub-region adjacent to the other side of the first region along the first direction, a third sub-region adjacent to one side of the first region along a second direction different from the first direction, a fourth sub-region adjacent to the other side of the first region along the second direction, a fifth sub-region between the first sub-region and the third sub-region, a sixth sub-region between the first sub-region and the fourth sub-region, a seventh sub-region between the second sub-region and the third sub-region, and an eighth sub-region between the second sub-region and the fourth sub-region.

[0194] In one embodiment, the display device may further include a pattern layer disposed on the second region of the substrate, the pattern layer including a plurality of first plate patterns, a plurality of second plate patterns, a plurality of first wiring patterns, and a plurality of second wiring patterns.

[0195] In one embodiment, in the first, second, fifth, sixth, seventh and eighth sub-regions, the plurality of first plate patterns may be arranged spaced apart from each other, and the plurality of first wiring patterns may connect adjacent first plate patterns to each other.

[0196] In one embodiment, the display device further includes a plurality of connecting wires arranged on the plurality of first wiring patterns, and in the first, second, fifth, sixth, seventh and eighth sub-regions, each of the plurality of second pixels is arranged on top of each of the plurality of first plate patterns, and each of the plurality of connecting wires is arranged on top of each of the plurality of first wiring patterns to connect the second pixels.

[0197] In one embodiment, in the third and fourth sub-regions, the first plate patterns may be arranged spaced apart from each other, and the first wiring patterns may connect adjacent first plate patterns along a second direction.

[0198] In one embodiment, the display device further includes a plurality of connecting wires arranged on the plurality of first wiring patterns, and in the third and fourth sub-regions, each of the plurality of second pixels is arranged on top of each of the plurality of first plate patterns, and each of the plurality of connecting wires is arranged on top of each of the plurality of first wiring patterns to connect the second pixels.

[0199] In one embodiment, in the third and fourth sub-regions, the second plate patterns may be arranged spaced apart from each other, and the second wiring patterns may connect adjacent second plate patterns along a second direction.

[0200] In one embodiment, the display device further includes a plurality of connecting wires arranged on the plurality of second wiring patterns, and in the third and fourth sub-regions, each of the plurality of stages included in the gate driver is arranged on top of each of the plurality of second plate patterns, and each of the plurality of connecting wires is arranged on top of each of the plurality of second wiring patterns to connect the stages.

[0201] In one embodiment, the gate region may overlap the first region, the third sub-region and the fourth sub-region.

[0202] In an embodiment, the plurality of second plate patterns and the plurality of second wiring patterns may be disposed to overlap the gate region.

[0203] In an embodiment, the display device may further include a power supply wiring disposed on the gate region and providing a low potential power supply voltage to the pixel.

[0204] In one embodiment, the display panel may include a first buffer layer disposed on the substrate, a first semiconductor layer disposed on the first buffer layer and including a first semiconductor pattern of a first transistor, a first gate insulating layer disposed on the first semiconductor layer, a first conductive layer disposed on the first gate insulating layer and including a first gate electrode of the first transistor, a first insulating layer disposed on the first conductive layer, a second conductive layer disposed on the first insulating layer, a second insulating layer disposed on the second conductive layer, a third conductive layer disposed on the second insulating layer and including a first source electrode and a first drain electrode of the first transistor, and a third insulating layer disposed on the third conductive layer.

[0205] In one embodiment, the display panel may further include a second buffer layer disposed on the third insulating layer, a second semiconductor layer disposed on the second buffer layer and including a second semiconductor pattern of a second transistor, a second gate insulating layer disposed on the second semiconductor layer, a fourth conductive layer disposed on the second gate insulating layer and including a second gate electrode of the second transistor, a fourth insulating layer disposed on the fourth conductive layer, and a fifth conductive layer disposed on the fourth insulating layer and including a second source electrode and a second drain electrode of the second transistor.

[0206] In an embodiment, the fifth conductive layer may further include the clock wiring.

[0207] In one embodiment, the display panel may further include a first planarization layer disposed on the fifth conductive layer, a sixth conductive layer disposed on the first planarization layer, a second planarization layer disposed on the sixth conductive layer, and a seventh conductive layer disposed on the second planarization layer.

[0208] In one embodiment, the substrate may further include a driving region in which the data driving unit is arranged and a connection region between the second region and the driving region, and the seventh conductive layer may be arranged to extend from the second region to the connection region and the driving region.

[0209] In one embodiment, the seventh conductive layer may be in direct contact with the substrate on the coupling region.

[0210] In one embodiment, the display panel may further include a light emitting element disposed on the seventh conductive layer and an encapsulation layer disposed on the light emitting element. The encapsulation layer may include a first inorganic encapsulation layer disposed on the light emitting element, a first organic encapsulation layer disposed on the first inorganic encapsulation layer, a second inorganic encapsulation layer disposed on the first organic encapsulation layer, a second organic encapsulation layer disposed on the second inorganic encapsulation layer, and a third inorganic encapsulation layer disposed on the second organic encapsulation layer.

[0211] In an embodiment, the display panel may include a light emitting element, a clock wiring for providing a clock signal to the gate driver, and a shielding pattern disposed between the light emitting element and the clock wiring.

[0212] In one embodiment, the display device may further include a plurality of first plate patterns disposed in the second region, and the second pixel may be disposed on at least a portion of the plurality of first plate patterns.

[0213] In one embodiment, each of the plurality of gate regions may extend along a first direction of the display device, and the plurality of gate regions may be spaced apart from each other along a second direction perpendicular to the first direction of the display device.

[0214] In one embodiment, the second region may include a plurality of sub-regions, each of which may be disposed adjacent to both sides of the first region.

[0215] In one embodiment, the first plate pattern may be disposed in each of the plurality of sub-regions.

[0216] In an embodiment, the display device may further include second plate patterns disposed in some regions of the plurality of sub-regions facing upper, lower, left and right sides of the first region.

[0217] In one embodiment, the gate driver may be disposed on the second plate pattern; and the second plate pattern may be disposed between the first plate patterns.

[0218] In one embodiment, the first plate pattern and the second plate pattern may be integrally arranged in some sub-regions among a plurality of sub-regions that are not arranged on the top, bottom, left, or right sides of the first region, extend in a second direction parallel to the top and bottom of the first region, and be spaced apart from each other in a first direction perpendicular to the second direction.

[0219] In an embodiment, the display device may further include at least one first wiring pattern disposed in the second region and connecting adjacent first plate patterns.

[0220] In an embodiment, the display device may further include at least one second wiring pattern disposed in the second region and connecting adjacent second plate patterns.

[0221] In an embodiment, the display device may further include at least one first wiring pattern and at least one second wiring pattern serving as a substrate supporting the connecting wires.

[0222] In one embodiment, the display device further includes a first conductive layer and a second conductive layer located on a layer between the first pixel and the second pixel; at least a portion of the first conductive layer may form a bent connecting wiring.

[0223] In one embodiment, at least a portion of the first conductive layer forming the interconnect may be disposed immediately above the wiring pattern, which is the substrate.

[0224] In one embodiment, the display device may be arranged such that at least a portion of the first conductive layer forms a shielding pattern.

[0225] In one embodiment, the display device is such that the shielding pattern is disposed between at least a portion of the third conductive layer, which is a clock wiring, and the anode of the pixel; the shielding pattern may have a width greater than that of the anode of the pixel.

[0226] Although the embodiments of the present invention have been described in more detail, the present invention is not necessarily limited to these embodiments, and various modifications can be made within the scope of the technical idea of ​​the present invention. Therefore, the embodiments disclosed in the present invention are for illustration purposes, not for limiting the technical idea of ​​the present invention, and the scope of the technical idea of ​​the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not limiting. The scope of protection of the present invention should be interpreted according to the following claims, and all technical ideas within the scope equivalent thereto should be interpreted as being included in the scope of the present invention.

Claims

1. a display panel including a plurality of pixels arranged on a substrate including a first region arranged at the center of the display device and a second region surrounding the first region; a data driver for supplying data signals to the pixels through data lines; a gate driver including a plurality of stages for supplying gate signals to the pixels through gate lines; Each of the stages included in the gate driver is disposed on one of a plurality of gate regions at least partially overlapping the first region and the second region, the plurality of pixels includes a plurality of first pixels arranged on the first region and a plurality of second pixels arranged on the second region, A display device, wherein the first pixels are arranged in the first region at a first pixel density, and the second pixels are arranged in the second region at a second pixel density smaller than the first pixel density.

2. Further comprising a plurality of first plate patterns disposed in the second region; The display device according to claim 1 , wherein the second pixel is disposed on at least a portion of the plurality of first plate patterns.

3. 2. The display device of claim 1, wherein each of the gate regions extends along a first direction of the display device, and the gate regions are spaced apart from each other along a second direction perpendicular to the first direction of the display device.

4. The display device according to claim 2 , wherein the second region includes a plurality of sub-regions, each of the plurality of sub-regions being disposed adjacent to one side of the first region.

5. The display device according to claim 4 , wherein the first plate pattern is disposed in each of the plurality of sub-regions.

6. The display device of claim 4 , further comprising second plate patterns arranged in some of the sub-regions facing upper, lower, left and right sides of the first region among the plurality of sub-regions.

7. the gate driver is disposed on the second plate pattern, The display device according to claim 6 , wherein the second plate patterns are disposed between the first plate patterns.

8. The first plate pattern and the second plate pattern are Among the plurality of sub-regions, the first region is integrally disposed in some of the sub-regions facing the upper, lower, left, and right sides of the first region, The display device of claim 6 , wherein the first regions extend in a second direction parallel to the top and bottom of the first region and are spaced apart from each other in a first direction perpendicular to the second direction.

9. The display device of claim 2 , further comprising at least one first wiring pattern disposed in the second region and connecting adjacent first plate patterns to each other.

10. The display device of claim 9 , further comprising at least one second wiring pattern disposed in the second region and connecting adjacent second plate patterns to each other.

11. The display device of claim 1 , further comprising at least one first wiring pattern and at least one second wiring pattern serving as a substrate for supporting the interconnection lines.

12. a first conductive layer and a second conductive layer located on a layer between the first pixel and the second pixel; The display device according to claim 11 , wherein at least a portion of the first conductive layer forms a bent interconnection line.

13. The display device according to claim 12 , wherein at least a portion of the first conductive layer forming the connecting wiring is disposed immediately above the wiring pattern that serves as the substrate.

14. The display device of claim 12 , wherein at least a portion of the first conductive layer is arranged to form a shielding pattern.

15. The shielding pattern is disposed between at least a portion of the third conductive layer, which is a clock wiring, and the anode of the pixel; and The display device of claim 14 , wherein the shielding pattern has a width greater than the anode of the pixel.

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