Display device, apparatus for manufacturing thereof and wearable electronic device

Abstract

To provide a display device, an apparatus for manufacturing thereof, and a wearable electronic device.SOLUTION: A display device includes a first sub-pixel, and a second sub-pixel located adjacent to the first sub-pixel. Each of the first and the second sub-pixels may include: a first electrode; a pixel defining layer on the first electrode; a first emission component on the pixel defining layer and configured to emit light; a first intermediate layer on the first emission component; a second emission component on the first intermediate layer and configured to emit light; and a second electrode on the second emission component. A trench may be formed by recessing at least a portion of the pixel defining layer in a boundary area between the first sub-pixel and the second sub-pixel. The first intermediate layer may be interrupted over the trench. The second emission component may completely cover the first intermediate layer over the trench.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to a display device, a manufacturing apparatus thereof, and a wearable electronic device. [Background technology]

[0002] 2. Description of the Related Art In recent years, as interest in information displays has increased, research and development into display devices has been continuously carried out. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Pat. No. 1,161,0954 [Patent Document 2] US Patent Application Publication No. 2022 / 0077257 [Patent Document 3] U.S. Pat. No. 1,134,983 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention can provide a display device, a manufacturing apparatus thereof, and a wearable electronic device with improved reliability. [Means for solving the problem]

[0005] A display device according to an embodiment may include a first sub-pixel and a second sub-pixel disposed adjacent to each other. Each of the first and second sub-pixels may include a first electrode, a pixel defining film disposed on the first electrode, a first light emitting portion disposed on the pixel defining film and emitting light, a first intermediate layer disposed on the first light emitting portion, a second light emitting portion disposed on the first intermediate layer and emitting light, and a second electrode disposed on the second light emitting portion. A trench may be formed by at least a portion of the pixel defining film being recessed in a boundary region between the first sub-pixel and the second sub-pixel. The first intermediate layer may be interrupted on the trench. The second light emitting portion may completely cover the first intermediate layer on the trench.

[0006] In the embodiment, the first intermediate layer may include a material having a higher charge conductivity than the first and second light emitting parts and may have electrical conductivity.

[0007] In an embodiment, the first intermediate layer and the second electrode may be electrically insulated from each other.

[0008] In the embodiment, the pixel defining layer may include a first surface and a second surface facing each other across the trench, and a third surface connecting the first surface and the second surface. The first surface may form a first sidewall of the trench, the second surface may form a second sidewall of the trench, and the third surface may form a bottom surface of the trench.

[0009] In an embodiment, an end of the second light-emitting portion on the first and second side walls is adjacent to the bottom surface more than an end of the first intermediate layer, and the second light-emitting portion can completely cover the first intermediate layer on the first and second side walls.

[0010] In the embodiment, the first light emitting portion may be disconnected within the trench, and the second light emitting portion of the first sub-pixel and the second light emitting portion of the second sub-pixel may be connected to each other.

[0011] In the embodiment, each of the first and second sub-pixels may further include a third light emitting portion disposed between the first electrode and the first light emitting portion and emitting light, and a second intermediate layer disposed between the third light emitting portion and the first light emitting portion. The second intermediate layer may be interrupted on the trench. The first light emitting portion may completely cover the second intermediate layer on the trench.

[0012] In the embodiment, the second intermediate layer may have conductivity by including a material having a higher charge conductivity than the first light emitting part, the second light emitting part, and the third light emitting part. The first intermediate layer, the second intermediate layer, and the second electrode may be electrically insulated from each other.

[0013] In an embodiment, on the first and second side walls, an end of the second light emitting portion may be closer to the bottom surface than an end of the first intermediate layer, and an end of the first light emitting portion may be closer to the bottom surface than an end of the second intermediate layer. On the first and second side walls, the second light emitting portion may completely cover the first intermediate layer, and the first light emitting portion may completely cover the second intermediate layer.

[0014] In the embodiment, the third light emitting portion and the first light emitting portion may be separated from each other within the trench, and the second light emitting portion of the first sub-pixel and the second light emitting portion of the second sub-pixel may be connected to each other.

[0015] In the embodiment, the trench may include a void surrounded by the first light emitting portion, the second light emitting portion, and the third light emitting portion.

[0016] In the embodiment, the distance between the first intermediate layer and the second electrode may be larger than the distance between the first intermediate layer and the second intermediate layer.

[0017] In the embodiment, the first light-emitting portion may include a first hole transport portion, a first light-emitting layer, and a first electron transport portion. The second light-emitting portion may include a second hole transport portion, a second light-emitting layer, and a second electron transport portion. The third light-emitting portion may include a third hole transport portion, a third light-emitting layer, and a third electron transport portion.

[0018] In the embodiment, each of the first and second sub-pixels may further include a substrate disposed under the first electrode, a pixel circuit layer disposed between the substrate and the first electrode and including at least one transistor electrically connected to the first electrode, a planarization layer disposed between the pixel circuit layer and the first electrode, and a sealing layer disposed on the second electrode. The trench may pass through at least a portion of the planarization layer.

[0019] In an apparatus for manufacturing a display device according to an embodiment, the display device may include a first sub-pixel and a second sub-pixel each including a pixel defining layer, a first light emitting portion, a first intermediate layer, a second light emitting portion, and a second electrode sequentially arranged on a first electrode, and a trench formed by recessing a portion of the pixel defining layer in a boundary region between the first and second sub-pixels. The apparatus may include a first deposition chamber for forming the first intermediate layer on the pixel defining layer, and a second deposition chamber for forming each of the first and second light emitting portions on the pixel defining layer.

[0020] In an embodiment, the first deposition chamber may include a first nozzle unit configured to inject a deposition material for the first intermediate layer, and a first angle limiting member connected to the first nozzle unit to limit an incident angle of the deposition material. The second deposition chamber may include a second nozzle unit configured to inject deposition materials for the first and second light emitting units, and a second angle limiting member connected to the second nozzle unit to limit an incident angle of the deposition material.

[0021] In an embodiment, a deposition material of the first intermediate layer and each of the deposition materials of the first and second light emitting portions may be incident on the pixel defining layer at different incident angles.

[0022] In the embodiment, the first intermediate layer may include a material having a higher charge conductivity than the first and second light emitting parts and may have electrical conductivity.

[0023] In an embodiment, the first angle limiting member may cause the deposition material of the first intermediate layer to be incident on the pixel defining layer at a low incident angle, and the second angle limiting member may cause the deposition material of each of the first and second light emitting parts to be incident on the pixel defining layer at a high incident angle.

[0024] In the embodiment, each of the first and second sub-pixels may further include a second intermediate layer having the conductivity and disposed between the second light-emitting portion and the second electrode, and a third light-emitting portion disposed between the second intermediate layer and the second electrode.

[0025] In the embodiment, the first deposition chamber may inject a deposition material for the second intermediate layer onto the second light emitting unit, and the second deposition chamber may inject a deposition material for the third light emitting unit onto the second intermediate layer.

[0026] In an embodiment, the deposition material of the second intermediate layer and the deposition material of the third light emitting portion may be incident at different incident angles.

[0027] A wearable electronic device according to an embodiment may include a display panel and a lens disposed on the display panel. The display panel may include first and second sub-pixels disposed adjacent to each other. Each of the first and second sub-pixels may include a first electrode, a pixel defining film disposed on the first electrode, a first light emitting portion disposed on the pixel defining film and emitting light, a first intermediate layer disposed on the first light emitting portion, a second light emitting portion disposed on the first intermediate layer and emitting light, and a second electrode disposed on the second light emitting portion.

[0028] In an embodiment, a trench may be formed by recessing at least a portion of the pixel defining layer in a boundary region between the first sub-pixel and the second sub-pixel. The first intermediate layer may be interrupted on the trench. The second light emitting portion may completely cover the first intermediate layer on the trench.

[0029] In the embodiment, each of the first and second sub-pixels may further include a third light emitting portion disposed between the first electrode and the first light emitting portion and emitting light, and a second intermediate layer disposed between the third light emitting portion and the first light emitting portion. The third light emitting portion and the second intermediate layer may be disconnected on the trench. The first light emitting portion may completely cover the second intermediate layer on the trench. Effect of the Invention

[0030] According to an embodiment, the incidence angle (or deposition angle) between layers constituting a light emitting structure arranged on a trench may be varied to prevent short circuits between conductive layers including a material having a relatively high charge conductivity (or charge mobility) among the layers, thereby improving the reliability of the display device.

[0031] In addition, according to an embodiment, the conductive intermediate layer (or charge generation layer) may be interrupted on the trench formed in the boundary region between adjacent sub-pixels, thereby reducing or preventing current from flowing through the intermediate layer to the adjacent sub-pixel.

[0032] The effects of the embodiments are not limited to those exemplified above, and various other effects may be included in this specification. [Brief description of the drawings]

[0033] [Figure 1] 1 is a schematic plan view showing a display device according to an embodiment. [Diagram 2] 2 is a schematic exploded perspective view showing a part of the display panel of FIG. 1. [Diagram 3] FIG. 3 is a schematic plan view illustrating one embodiment of the pixel of FIG. 2. [Figure 4] FIG. 4 is a schematic cross-sectional view taken along line I-I' in FIG. [Diagram 5] 5 is a schematic cross-sectional view showing an embodiment of a light emitting structure included in one of the first to third light emitting elements of FIG. 4. [Figure 6] 5 is a schematic cross-sectional view showing another embodiment of a light emitting structure included in one of the first to third light emitting elements of FIG. 4. [Figure 7a] 5 is a schematic cross-sectional view showing an enlarged portion of the display device of FIG. 4. [Figure 7b] 5 is a schematic cross-sectional view showing an enlarged portion of the display device of FIG. 4. [Figure 7c] 5 is a schematic cross-sectional view showing an enlarged portion of the display device of FIG. 4. [Figure 8] FIG. 7b is an enlarged schematic diagram of the EA portion of FIG. 7a. [Figure 9] FIG. 1 is a schematic diagram showing an embodiment of a manufacturing apparatus for a display device. [Figure 10] FIG. 10 is a schematic diagram showing a first deposition source in FIG. [Figure 11] FIG. 10 is a schematic diagram showing a second deposition source in FIG. [Figure 12] 11 shows a simulation result showing deposition behavior according to an incidence angle of a light emitting structure disposed on a trench. [Figure 13] FIG. 1 is a schematic block diagram illustrating an embodiment of a display system. [Figure 14] FIG. 14 is a schematic perspective view showing an application example of the display system of FIG. [Figure 15] 15 is a schematic diagram showing the head-mounted display device of FIG. 14 worn by a user. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Please note that in the following description, only parts necessary for understanding the operation of the present invention will be described, and descriptions of other parts will be omitted so as not to make the gist of the present invention unclear. In addition, the present invention is not limited to the embodiments described herein, and may be embodied in other forms. However, the embodiments described herein are provided in detail to the extent that those skilled in the art to which the present invention pertains can easily implement the technical scope of the present invention.

[0035] Throughout this specification, a part being "connected" to another part includes not only the case of being "directly connected" to another part, but also the case of being "indirectly connected" to another part through another element therebetween. The terms used herein are for describing a particular embodiment, and are not intended to limit the present invention. Throughout this specification, a part "comprises" a certain component, unless otherwise specified to the contrary, means that it can further include the other component, not excluding the other component. "At least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Here, "and / or" includes all combinations of one or more of the corresponding configurations.

[0036] Here, the terms "first", "second", etc. may be used to describe various components, but the components are not limited to these terms. These terms are used to distinguish one component from another. Thus, the first component can refer to the second component within a range that does not deviate from the contents disclosed herein.

[0037] Spatially relative terms such as "below," "above," and the like may be used for purposes of description, thereby describing the relationship of one element or feature to another element or feature as shown in the figures. Spatially relative terms are intended to include different orientations during use, operation, and / or manufacture in addition to the orientation depicted in the figures. For example, if a device shown in the figures were turned upside down, an element depicted as being "below" another element or feature would be in an orientation "above" the other element or feature. Thus, in one embodiment, "below" can include both an orientation of above and below. Additionally, a device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative terms used herein should be interpreted accordingly.

[0038] Various embodiments are described with reference to drawings that illustrate idealized embodiments. As such, it is to be expected that the shapes may vary depending on, for example, tolerances and / or manufacturing techniques. Thus, the embodiments disclosed herein should not be construed as limited to the particular shapes shown, but should be construed to include, for example, variations in shapes that result from manufacturing. As such, the drawings may not depict the actual shape of a region of a device, and the embodiments are not limited thereto.

[0039] 1 is a schematic plan view showing a display device DD according to an embodiment of the present invention, in which the structure of the display device DD, for example a display panel DP included in the display device DD, is simply shown with a display area DA in which an image is displayed as the center for convenience.

[0040] 1, the display panel DP may include a display area DA and a non-display area NDA. The display panel DP may display an image through the display area DA. The non-display area NDA may be disposed around the display area DA.

[0041] The display panel DP may include a substrate SUB, sub-pixels SP, and pads PD.

[0042] When the display panel DP is used as a display screen for a head mounted display device (HMD), a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, or the like, the display panel DP may be located very close to the user's eyes. In this case, a relatively high integration density of the sub-pixels SP may be required. In order to increase the integration density of the sub-pixels SP, a silicon substrate (or a silicon wafer) may be provided as the substrate SUB, but is not limited thereto. The silicon substrate may have the sub-pixels SP and / or the display panel DP formed on the substrate SUB. A display device DD including a display panel DP formed on the substrate SUB, which is a silicon substrate, may be referred to as an OLEDoS (OLED on Silicon) display device.

[0043] The sub-pixels SP may be disposed in a display area DA on a substrate SUB. The sub-pixels SP may be arranged in a matrix shape along a first direction DR1 and a second direction DR2 intersecting the first direction DR1, but the arrangement of the sub-pixels SP is not limited thereto. For example, the sub-pixels SP may be arranged in a zigzag shape along the first direction DR1 and the second direction DR2. The first direction DR1 may be the row direction, and the second direction DR2 may be the column direction.

[0044] Two or more of the sub-pixels SP can form one pixel PXL.

[0045] Components for controlling the sub-pixels SP may be disposed in the non-display area NDA on the substrate SUB. For example, wiring electrically connected to the sub-pixels SP may be disposed in the non-display area NDA. The wiring may include, for example, gate lines, data lines, etc.

[0046] A driving unit electrically connected to the sub-pixels SP for driving the sub-pixels SP may be arranged (or integrated) in the non-display area NDA of the display panel DP. A pad PD may be arranged in the non-display area NDA on the substrate SUB. The pad PD may be electrically connected to the sub-pixels SP via wiring. For example, the pad PD may be electrically connected to the sub-pixels SP via a data line.

[0047] The pads PD can interface the display panel DP to other components of the display device DD. In an embodiment, voltages and signals required for operation of the components included in the display panel DP may be provided from a driver (or driver integrated circuit) via the pads PD. For example, data lines may be electrically connected to the driver via the pads PD.

[0048] In an embodiment, the circuit board may be electrically connected to the pads PD using a conductive adhesive member such as an anisotropic conductive film. The circuit board may be a flexible circuit board or a flexible film made of a flexible material. The driving unit may be mounted on the circuit board and electrically connected to the pads PD.

[0049] In an embodiment, the display area DA may have various shapes. The display area DA may be a closed loop including straight and / or curved sides. For example, the display area DA may be a polygon, a circle, a semicircle, an ellipse, etc., but is not limited thereto.

[0050] In an embodiment, the display panel DP may have a flat display surface. Depending on the embodiment, the display panel DP may have an at least partially round display surface. In an embodiment, the display panel DP may be bendable, foldable or rollable. In this case, the display panel DP and / or the substrate SUB may comprise a material having flexible properties.

[0051] Fig. 2 is a schematic exploded perspective view showing a portion of the display panel of Fig. 1. For clarity and conciseness, Fig. 2 shows only a schematic view of the portions of the display panel DP corresponding to two pixels PXL1 and PXL2 of the pixels PXL of Fig. 1. The portions of the display panel DP corresponding to the remaining pixels may be similarly configured.

[0052] 2, each of the first and second pixels PXL1 and PXL2 may include, but is not limited to, first to third sub-pixels SP1, SP2, and SP3. Depending on the embodiment, each of the first and second pixels PXL1 and PXL2 may include four sub-pixels or two sub-pixels.

[0053] 2, the first to third sub-pixels SP1, SP2, and SP3 are shown to have a rectangular shape and the same size when viewed from a third direction DR3 intersecting the first and second directions DR1 and DR2, but are not limited thereto. Depending on the embodiment, the first to third sub-pixels SP1, SP2, and SP3 may be modified to have various shapes.

[0054] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, a sealing layer TFE, an optical functional layer OFL, an overcoat layer OC, and a cover window CW.

[0055] In an embodiment, the substrate SUB may include a silicon wafer substrate formed using a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon-germanium. The substrate SUB may be provided from a bulk wafer, an epitaxial layer, a silicon on insulator (SOI) layer, a semiconductor on insulator (SeOI) layer, or the like. In another embodiment, the substrate SUB may include a glass substrate. In yet another embodiment, the substrate SUB may include a polyimide (PI) substrate.

[0056] A pixel circuit layer PCL may be disposed on a substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and a conductive pattern disposed between the insulating layer. The conductive pattern of the pixel circuit layer PCL may function as at least a part of a circuit element, wiring, etc. The conductive pattern may include, but is not limited to, copper.

[0057] The circuit element may include subpixel circuits of the first to third subpixels SP1, SP2, and SP3. The subpixel circuits may include a transistor and one or more capacitors. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode superimposed on the semiconductor portion. In an embodiment, when a silicon substrate is provided as the substrate SUB, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. Depending on the embodiment, when a glass substrate or a PI substrate is provided as the substrate SUB, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other on a plane defined by the first and second directions DR1 and DR2. For example, each capacitor may include electrodes spaced apart from each other in a third direction DR3 with an insulating layer sandwiched therebetween.

[0058] The wiring of the pixel circuit layer PCL may include signal lines connected to the first to third sub-pixels SP1, SP2, and SP3, respectively, such as gate lines, emission control lines, data lines, etc. Depending on the embodiment, the wiring may further include a power supply voltage wiring.

[0059] The light emitting element layer LDL may include an anode electrode AE, a pixel defining layer PDL, a light emitting structure EMS, and a cathode electrode CE.

[0060] The anode electrode AE ​​(or the first electrode) may be disposed on the pixel circuit layer PCL. The anode electrode AE ​​may be in contact with a circuit element of the pixel circuit layer PCL. The anode electrode AE ​​may include, but is not limited to, an opaque conductive material that can reflect light.

[0061] A pixel defining film PDL may be disposed on the anode electrode AE. The pixel defining film PDL may include an opening OP exposing a portion of each of the anode electrodes AE. The opening OP of the pixel defining film PDL may be understood as a light emitting region corresponding to each of the first to third sub-pixels SP1, SP2, and SP3.

[0062] In an embodiment, the pixel-defining membrane PDL may include an inorganic material. In this case, the pixel-defining membrane PDL may include a plurality of stacked inorganic insulating layers. For example, the pixel-defining membrane PDL may include silicon oxide (SiO x ) and silicon nitride (SiN x Depending on the embodiment, the pixel defining layer PDL may include an organic material. However, the material of the pixel defining layer PDL is not limited to the above embodiment.

[0063] The light emitting structure EMS may be disposed on the anode electrode AE ​​(or the first electrode) exposed by the opening OP of the pixel definition film PDL. The light emitting structure EMS may include, but is not limited to, a light emitting layer configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes.

[0064] In the embodiment, the light emitting structure EMS may fill the opening OP of the pixel defining layer PDL and be entirely disposed on the upper part of the pixel defining layer PDL. That is, the light emitting structure EMS may extend across the first to third sub-pixels SP1, SP2, and SP3. In this case, at least a part of a layer in the light emitting structure EMS may be cut or bent in a boundary region between the first to third sub-pixels SP1, SP2, and SP3. However, the present invention is not limited thereto, and depending on the embodiment, the parts of the light emitting structure EMS corresponding to the first to third sub-pixels SP1, SP2, and SP3 may be separated from each other and disposed in the opening OP of the corresponding pixel defining layer PDL.

[0065] A cathode electrode CE (or a second electrode) may be disposed on the light emitting structure EMS. The cathode electrode CE may extend across the first to third sub-pixels SP1, SP2, and SP3. The cathode electrode CE may be provided as a common electrode for the first to third sub-pixels SP1, SP2, and SP3.

[0066] The cathode electrode CE may be a thin metal layer having a thickness sufficient to transmit light emitted from the light emitting structure EMS. The cathode electrode CE may be formed of a metal material or a transparent conductive material so as to have a relatively thin thickness. In an embodiment, the cathode electrode CE may include at least one of a variety of transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. In another embodiment, the cathode electrode CE may include at least one of magnesium, silver, and mixtures thereof. However, the material of the cathode electrode CE is not limited to the above embodiment.

[0067] Any one of the anode electrodes AE, a portion of the light emitting structure EMS overlapping therewith, and a portion of the cathode electrode CE overlapping therewith may be understood as constituting one light emitting element. That is, each of the light emitting elements of the first to third sub-pixels SP1, SP2, and SP3 may include one anode electrode AE ​​(or a first electrode), a portion of the light emitting structure EMS overlapping therewith, and a portion of the cathode electrode CE (or a second electrode) overlapping therewith. In each of the first to third sub-pixels SP1, SP2, and SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE are transported into the light emitting layer of the light emitting structure EMS to form excitons, and when the excitons transition from the excited state to the ground state, light may be generated. The luminance of the light may be determined according to the amount of current flowing through the light emitting layer. The wavelength range of the generated light may be determined according to the configuration of the light emitting layer.

[0068] An encapsulation layer TFE may be disposed on the cathode electrode CE. The encapsulation layer TFE may cover the light emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE may be configured to prevent oxygen and / or moisture from penetrating into the light emitting element layer LDL. In the embodiment, the encapsulation layer TFE may include a structure in which one or more inorganic films and one or more organic films are alternately stacked. For example, the inorganic film may be silicon nitride, silicon oxide, or silicon oxynitride (SiO x N yFor example, the organic film may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimides resin, an unsaturated polyesters resin, a polyphenylenes resin, a polyphenylenesulfides resin, or benzocyclobutene (BCB). However, the materials of the organic film and the inorganic film of the sealing layer TFE are not limited thereto.

[0069] In order to improve the sealing efficiency of the sealing layer TFE, the sealing layer TFE is made of aluminum oxide (AlO x The thin film containing aluminum oxide may be located on the upper surface of the sealing layer TFE facing the optical function layer OFL and / or on the lower surface of the sealing layer TFE facing the light emitting element layer LDL.

[0070] The thin film including aluminum oxide may be formed by, but is not limited to, an atomic layer deposition (ALD) method. The encapsulation layer TFE may further include a thin film formed of at least one of various materials suitable for improving encapsulation efficiency.

[0071] The optical functional layer OFL may be disposed on the encapsulation layer TFE. The optical functional layer OFL may include a color filter layer CFL and a lens array LA.

[0072] The color filter layer CFL may be disposed between the encapsulation layer TFE and the lens array LA. The color filter layer CFL may be configured to filter the light emitted from the light emitting structure EMS to selectively output light of a wavelength range or color corresponding to each sub-pixel. The color filter layer CFL may include color filters CF corresponding to the first to third sub-pixels SP1, SP2, and SP3, respectively. Each of the color filters CF may pass light of a wavelength range corresponding to the corresponding sub-pixel. For example, the color filter CF corresponding to the first sub-pixel SP1 may pass red light, the color filter CF corresponding to the second sub-pixel SP2 may pass green light, and the color filter CF corresponding to the third sub-pixel SP3 may pass blue light. At least a part of the color filters CF may be omitted depending on the light emitted from the light emitting structure EMS of each sub-pixel.

[0073] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first to third sub-pixels SP1, SP2, and SP3, respectively. Each of the lenses LS may improve light output efficiency by outputting light emitted from the light emitting structure EMS to an intended path. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a higher refractive index than the overcoat layer OC. In the embodiment, the lens LS may include an organic material. For example, the lens LS may include, but is not limited to, an acrylate material.

[0074] In the embodiment, at least a part of the color filters CF of the color filter layer CFL and at least a part of the lenses LS of the lens array LA may be shifted in a direction parallel to the plane defined by the first and second directions DR1 and DR2, compared with the apertures OP of the pixel definition film PDL. Specifically, in the central region of the display area DA, the centers of the color filters CF and the lenses LS may be aligned or overlapped with the centers of the corresponding apertures OP of the pixel definition film PDL when viewed from the third direction DR3. For example, in the central region of the display area DA, the apertures OP of the pixel definition film PDL may be completely overlapped with the color filters CF of the color filter layer CFL and the lenses LS of the lens array LA. In the region of the display area DA adjacent to the non-display area NDA, the centers of the color filters CF and the lenses LS may be shifted in the planar direction. For example, in the region of the display area DA adjacent to the non-display area NDA, the apertures OP of the pixel definition film PDL may be partially overlapped with the color filters CF of the color filter layer CFL and the lenses LS of the lens array LA. As a result, the light emitted from the light emitting structure EMS at the center of the display area DA can be efficiently output in the normal direction of the display surface, and the light emitted from the light emitting structure EMS at the periphery of the display area DA can be efficiently output in a direction inclined at a predetermined angle with respect to the normal direction of the display surface.

[0075] The overcoat layer OC may be disposed on the lens array LA. The overcoat layer OC may cover the optical function layer OFL, the encapsulation layer TFE, the light emitting structure EMS, and / or the pixel circuit layer PCL. The overcoat layer OC may include various materials suitable for protecting the layers below it from foreign substances such as dust and moisture. For example, the overcoat layer OC may include at least one of an inorganic insulating film and an organic insulating film. For example, the overcoat layer OC may include, but is not limited to, epoxy. The overcoat layer OC may have a lower refractive index than the lens array LA.

[0076] A cover window CW may be disposed on the overcoat layer OC. The cover window CW may be configured to protect the layers underneath. The cover window CW may have a higher refractive index than the overcoat layer OC. The cover window CW may include, but is not limited to, glass. Depending on the embodiment, the cover window CW may be an encapsulation glass configured to protect the components disposed underneath. Depending on the embodiment, the cover window CW may be omitted.

[0077] Figure 3 is a schematic plan view showing one embodiment of the pixels of Figure 2. For clarity and conciseness, Figure 3 shows only a first pixel PXL1 of the first and second pixels PXL1 and PXL2 of Figure 2. The remaining pixels may have a configuration (or structure) substantially identical to or similar to that of the first pixel PXL1.

[0078] Referring to FIG. 3, the first pixel PXL1 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 arranged along a first direction DR1.

[0079] The first subpixel SP1 may include a first light-emitting region EMA1 and a non-light-emitting region NEA around the first light-emitting region EMA1. The second subpixel SP2 may include a second light-emitting region EMA2 and a non-light-emitting region NEA around the second light-emitting region EMA2. The third subpixel SP3 may include a third light-emitting region EMA3 and a non-light-emitting region NEA around the third light-emitting region EMA3.

[0080] The first light emitting region EMA1 may be a region where light is emitted from a portion of the light emitting structure EMS (see FIG. 4) corresponding to the first sub-pixel SP1. The second light emitting region EMA2 may be a region where light is emitted from a portion of the light emitting structure EMS corresponding to the second sub-pixel SP2. The third light emitting region EMA3 may be a region where light is emitted from a portion of the light emitting structure EMS corresponding to the third sub-pixel SP3. As described with reference to FIG. 2, each light emitting region can be understood as an opening OP (see FIG. 2) of the pixel defining layer PDL (see FIG. 2) corresponding to each of the first to third sub-pixels SP1 to SP3.

[0081] The first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may have substantially the same area, but are not limited to this. Depending on the embodiment, the second subpixel SP2 may have a larger area than the first subpixel SP1, and the third subpixel SP3 may have a larger area than the second subpixel SP2.

[0082] The first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may have a polygonal shape. For example, but not limited to, the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may have a rectangular or hexagonal shape. Depending on the embodiment, the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may have a circular shape, a semi-elliptical shape, etc.

[0083] 3 is an example, and embodiments are not limited thereto. Each pixel includes two or more subpixels, and the subpixels may be arranged in various ways, each of the subpixels may have various shapes, and each of the light-emitting areas of the subpixels may also have various shapes.

[0084] FIG. 4 is a schematic cross-sectional view taken along line I-I' in FIG.

[0085] 3 and 4, the first pixel PXL1 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3.

[0086] Each of the first to third sub-pixels SP1 to SP3 may include a substrate SUB and a pixel circuit layer PCL disposed on the substrate SUB.

[0087] The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. For example, the substrate SUB may include silicon, germanium, and / or silicon-germanium.

[0088] The pixel circuit layer PCL may be disposed on a substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements of the first to third sub-pixels SP1 to SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 of the first sub-pixel SP1, a transistor T_SP2 of the second sub-pixel SP2, and a transistor T_SP3 of the third sub-pixel SP3. The transistor T_SP1 of the first sub-pixel SP1 may be one of the transistors included in the sub-pixel circuit of the first sub-pixel SP1, the transistor T_SP2 of the second sub-pixel SP2 may be one of the transistors included in the sub-pixel circuit of the second sub-pixel SP2, and the transistor T_SP3 of the third sub-pixel SP3 may be one of the transistors included in the sub-pixel circuit of the third sub-pixel SP3. In FIG. 4, for clarity and conciseness, one of the transistors of each sub-pixel is shown, and the remaining circuit elements are omitted.

[0089] The transistor T_SP1 of the first sub-pixel SP1 may include a source region SRA, a drain region DRA, and a gate electrode GE.

[0090] The source region SRA and the drain region DRA may be disposed in a substrate SUB. A well WL formed through an ion implantation process may be disposed in the substrate SUB, and the source region SRA and the drain region DRA may be disposed apart from each other in the well WL. A region between the source region SRA and the drain region DRA in the well WL may be defined as a channel region.

[0091] The gate electrode GE may overlap the channel region between the source region SRA and the drain region DRA and may be disposed in the pixel circuit layer PCL. The gate electrode GE may be separated from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE may include a conductive material.

[0092] The layers included in the pixel circuit layer PCL may include a conductive pattern disposed between insulating layers. The conductive pattern may include first and second conductive patterns CP1 and CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA via a drain connection part DRC that penetrates one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA via a source connection part SRC that penetrates one or more insulating layers.

[0093] By electrically connecting the gate electrode GE and the first and second conductive patterns CP1, CP2 to other circuit elements and / or wiring, the transistor T_SP1 of the first subpixel SP1 can be provided as one of the transistors constituting the subpixel circuit of the first subpixel SP1.

[0094] The transistor T_SP2 of the second sub-pixel SP2 and the transistor T_SP3 of the third sub-pixel SP3 may each be configured substantially similarly to the transistor T_SP1 of the first sub-pixel SP1.

[0095] As described above, the substrate SUB and the pixel circuit layer PCL may include circuit elements for each of the first to third sub-pixels SP1 to SP3.

[0096] A via layer VIAL may be disposed on the pixel circuit layer PCL. The via layer VIAL may cover the pixel circuit layer PCL and have an overall flat surface. The via layer VIAL may be configured to flatten steps on the pixel circuit layer PCL. The via layer VIAL may include at least one of silicon oxide, silicon nitride, and silicon carbonitride (SiCN), but is not limited thereto.

[0097] A light emitting element layer LDL may be disposed on the via layer VIAL. The light emitting element layer LDL may include first to third reflective electrodes RE1, RE2, and RE3, a planarization layer PLNL, first to third anode electrodes AE1, AE2, and AE3, a pixel defining layer PDL, a light emitting structure EMS, and a cathode electrode CE.

[0098] First to third reflective electrodes RE1 to RE3 may be arranged on the via layer VIAL in the first to third sub-pixels SP1 to SP3, respectively. For example, the first reflective electrode RE1 may be arranged on the via layer VIAL in the first sub-pixel SP1, the second reflective electrode RE2 may be arranged on the via layer VIAL in the second sub-pixel SP2, and the third reflective electrode RE3 may be arranged on the via layer VIAL in the third sub-pixel SP3. Each of the first to third reflective electrodes RE1 to RE3 can be in contact with a circuit element arranged in the pixel circuit layer PCL through a via penetrating the via layer VIAL.

[0099] The first to third reflective electrodes RE1 to RE3 may function as full mirrors that reflect light emitted from the light emitting structure EMS toward the display surface (or the cover window CW). The first to third reflective electrodes RE1 to RE3 may include a metal material suitable for reflecting light. For example, the first to third reflective electrodes RE1 to RE3 may include at least one of aluminum, silver, magnesium, platinum, palladium, gold, nickel, neodymium, iridium, chromium, and titanium, or may include at least one of an alloy of two or more materials selected therefrom, but the material of the first to third reflective electrodes RE1 to RE3 is not limited to the above embodiment.

[0100] Depending on the embodiment, a connection electrode may be disposed below each of the first to third reflective electrodes RE1 to RE3. The connection electrodes may be provided to improve the electrical connection characteristics between the corresponding reflective electrodes and the circuit elements of the pixel circuit layer PCL. The connection electrodes may be made up of multiple layers. For example, the multiple layers may include, but are not limited to, a laminated structure of titanium / titanium nitride (or titanium nitride) / tantalum nitride (or tantalum nitride), etc. Depending on the embodiment, the corresponding reflective electrodes may be disposed between the layers constituting the connection electrodes.

[0101] In the embodiment, a buffer pattern BFP may be disposed under at least one of the first to third reflective electrodes RE1 to RE3. For example, the buffer pattern BFP may be disposed between the first reflective electrode RE1 and the via layer VIAL. The buffer pattern BFP may include, but is not limited to, an inorganic material such as silicon carbon nitride. By disposing the buffer pattern BFP, the height of the corresponding reflective electrode in the third direction DR3 can be adjusted. For example, the buffer pattern BFP can adjust the height of the first reflective electrode RE1 between the first reflective electrode RE1 and the via layer VIAL.

[0102] The first to third reflective electrodes RE1 to RE3 can function as full mirrors, and the cathode electrode CE can function as a half mirror. The light emitted from the light emitting structure EMS can be amplified by at least partially traveling back and forth between the corresponding reflective electrode and the cathode electrode CE, and the amplified light can be output through the cathode electrode CE. In this way, the distance between each reflective electrode and the cathode electrode CE can be understood as a resonance distance for the light emitted from the light emitting layer of the corresponding light emitting structure EMS.

[0103] The first sub-pixel SP1 may have a shorter resonance distance than the other sub-pixels (e.g., the second and third sub-pixels SP2 and SP3) due to the buffer pattern BFP. The resonance distance adjusted in this manner may effectively and efficiently amplify light in a specific wavelength range (e.g., red). As a result, the first sub-pixel SP1 may effectively and efficiently output light in the corresponding wavelength range.

[0104] 4 shows that the buffer pattern BFP is provided in the first subpixel SP1 and not provided in the second and third subpixels SP2 and SP3, but the embodiment is not limited thereto. According to the embodiment, at least one of the second and third subpixels SP2 and SP3 may also be provided with a buffer pattern to adjust the resonance distance of at least one of the second and third subpixels SP2 and SP3. For example, when the first subpixel SP1 is a red subpixel, the second subpixel SP2 is a green subpixel, and the third subpixel SP3 is a blue subpixel, the distance between the first reflective electrode RE1 and the cathode electrode CE may be shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE, and the distance between the second reflective electrode RE2 and the cathode electrode CE may be shorter than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0105] A planarization layer PLNL may be provided to planarize steps between the first to third reflective electrodes RE1 to RE3. The planarization layer PLNL may be disposed on the via layer VIAL and the first to third reflective electrodes RE1 to RE3. The planarization layer PLNL entirely covers the first to third reflective electrodes RE1 to RE3 and the via layer VIAL, but may have a flat surface. Depending on the embodiment, the planarization layer PLNL may be omitted.

[0106] A first anode electrode AE1, a second anode electrode AE2, and a third anode electrode AE3 may be disposed on the planarization layer PLNL. For example, the first anode electrode AE1 may be disposed on the planarization layer PLNL so as to overlap with the first reflective electrode RE1, the second anode electrode AE2 may be disposed on the planarization layer PLNL so as to overlap with the second reflective electrode RE2, and the third anode electrode AE3 may be disposed on the planarization layer PLNL so as to overlap with the third reflective electrode RE3.

[0107] The first to third anode electrodes AE1 to AE3 may have shapes similar to the first to third light-emitting regions EMA1 to EMA3 in Fig. 3 when viewed from the third direction DR3. For example, the first anode electrode AE1 may have a shape similar to the first light-emitting region EMA1 when viewed from the third direction DR3, the second anode electrode AE2 may have a shape similar to the second light-emitting region EMA2 when viewed from the third direction DR3, and the third anode electrode AE3 may have a shape similar to the third light-emitting region EMA3 when viewed from the third direction DR3, but is not limited thereto.

[0108] Each of the first to third anode electrodes AE1 to AE3 may be electrically connected to a corresponding reflective electrode. For example, the first anode electrode AE1 may be electrically connected to the first reflective electrode RE1 through a first via VIA1 that penetrates the planarization layer PLNL. The second anode electrode AE2 may be electrically connected to the second reflective electrode RE2 through a second via VIA2 that penetrates the planarization layer PLNL. The third anode electrode AE3 may be electrically connected to the third reflective electrode RE3 through a third via VIA3 that penetrates the planarization layer PLNL.

[0109] The first to third anode electrodes AE1 to AE3 in the embodiment are made of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO xThe first to third anode electrodes AE1 to AE3 may include at least one of transparent conductive materials such as titanium nitride, indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc. However, the material of the first to third anode electrodes AE1 to AE3 is not limited thereto. For example, the first to third anode electrodes AE1 to AE3 may include titanium nitride.

[0110] An insulating layer may be further provided to adjust the height of one or more of the first to third anode electrodes AE1 to AE3. The insulating layer may be disposed between one or more of the first to third anode electrodes AE1 to AE3 and the corresponding electrode. In this case, the planarizing layer PLNL and / or the buffer pattern BFP may be omitted.

[0111] A pixel defining film PDL may be disposed on portions of the first to third anode electrodes AE1 to AE3 and the planarizing layer PLNL. The pixel defining film PDL may include openings OP exposing portions of the first to third anode electrodes AE1 to AE3. The openings OP of the pixel defining film PDL may define light emitting regions of the first to third sub-pixels SP1 to SP3. The pixel defining film PDL is disposed in the non-light emitting area NEA (see FIG. 3 ) and may define the first light emitting area EMA1, the second light emitting area EMA2, and the third light emitting area EMA3 described with reference to FIG. 3 .

[0112] In the embodiment, the pixel defining layer PDL may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers may include at least one of silicon oxide and silicon nitride. For example, the pixel defining layer PDL may include first to third inorganic insulating layers stacked in order, and the first to third inorganic insulating layers may include silicon nitride, silicon oxide, and silicon nitride, respectively. However, the material of the pixel defining layer PDL is not limited to the above embodiment.

[0113] A separator SPR may be provided in the boundary region BDA between adjacent sub-pixels. The separator SPR may cause a discontinuity in the light emitting structure EMS in the boundary region BDA. For example, the separator SPR may cause the light emitting structure EMS to bend or break in the boundary region BDA.

[0114] The separator SPR may be provided in or on the pixel definition film PDL. The pixel definition film PDL may include one or more trenches TRCH1, TRCH2 as the separator SPR in the boundary region BDA. In an embodiment, the one or more trenches TRCH1, TRCH2 may be formed penetrating the pixel definition film PDL and partially penetrating the planarization layer PLNL. In another embodiment, the one or more trenches TRCH1, TRCH2 may be formed penetrating the pixel definition film PDL and the planarization layer PLNL and partially penetrating the via layer VIAL. In yet another embodiment, the one or more trenches TRCH1, TRCH2 may at least partially penetrating the planarization layer PLNL and / or the via layer VIAL, and a part of the pixel definition film PDL may be disposed in the one or more trenches TRCH1, TRCH2. In yet another embodiment, the one or more trenches TRCH1, TRCH2 may be formed partially penetrating the pixel definition film PDL.

[0115] 4 shows that two trenches TRCH1 and TRCH2 are located in the boundary region BDA between the sub-pixels, but is not limited thereto. For example, a separator SPR including one trench may be provided inside and / or on the pixel definition film PDL in the boundary region BDA. Also, a separator SPR including three or more trenches may be provided inside and / or on the pixel definition film PDL in the boundary region BDA.

[0116] The first and second trenches TRCH1 and TRCH2 may form discontinuous portions, such as a first void VD1 and a second void VD2, in the boundary region BDA in the light emitting structure EMS. A portion of a plurality of layers (or components included in the light emitting structure EMS) stacked in the light emitting structure EMS may be cut or bent by the first and second voids VD1 and VD2. For example, at least one charge generation layer included in the light emitting structure EMS may be cut by the first and second voids VD1 and VD2. In this manner, the light emitting structures EMS included in the first to third sub-pixels SP1 to SP3 may be at least partially separated by the first and second trenches TRCH1 and TRCH2.

[0117] 4 shows that the first and second voids VD1 and VD2 are formed in the light emitting structure EMS in the boundary area BDA, but is not limited thereto. For example, a concave valley may be formed in the light emitting structure EMS in the boundary area BDA. The shapes of discontinuous parts formed in the light emitting structure EMS, for example, the first and second voids VD1 and VD2, may be variously changed according to the shapes of the first and second trenches TRCH1 and TRCH2.

[0118] In the embodiment, the light emitting structure EMS may be formed by a process such as vacuum deposition, inkjet printing, etc. In this case, the same material as a part of the components included in the light emitting structure EMS may be located on the bottom surfaces of the first and second trenches TRCH1 and TRCH2 adjacent to the via layer VIAL.

[0119] The separator SPR may be provided in various modified forms so that the light emitting structure EMS may have a discontinuous portion in the boundary region BDA. In an embodiment, an additional inorganic insulating pattern may be provided on the pixel defining layer PDL in the boundary region BDA without the first and second trenches TRCH1 and TRCH2. The width of the uppermost inorganic insulating pattern among the additionally stacked inorganic insulating patterns may be larger than the width of the inorganic insulating pattern disposed immediately below it. For example, in the boundary region BDA, the first to third inorganic insulating patterns are sequentially stacked on the pixel defining layer PDL, and the uppermost third inorganic insulating pattern may have a width larger than that of the second inorganic insulating pattern. In this case, the pixel defining layer PDL may have a "T"-shaped or "I"-shaped cross section in the boundary region BDA. Depending on the shape of the pixel defining layer PDL, a plurality of layers included in the light emitting structure EMS may be at least partially cut or bent in the boundary region BDA.

[0120] The light emitting structure EMS may be disposed on the anode electrode AE ​​(see FIG. 2) (or the first electrode) exposed by the opening OP of the pixel defining layer PDL. The light emitting structure EMS fills the opening OP of the pixel defining layer PDL, but may be disposed over the entire first to third sub-pixels SP1 to SP3. As described above, the light emitting structure EMS may be at least partially cut or bent in the boundary region BDA by the separator SPR. This allows a current flowing from each of the first to third sub-pixels SP1 to SP3 to the adjacent sub-pixels through a layer included in the light emitting structure EMS during operation of the display panel DP (see FIG. 2). Therefore, the first, second and third light emitting elements LD1, LD2 and LD3 may operate with relatively high reliability.

[0121] The cathode electrode CE may be disposed on the light emitting structure EMS. The cathode electrode CE may be provided in common to the first to third sub-pixels SP1 to SP3. The cathode electrode CE may function as a half mirror that partially transmits and partially reflects light emitted from the light emitting structure EMS.

[0122] The first anode electrode AE1 (or the first electrode), a portion of the light emitting structure EMS overlapping the first anode electrode AE1, and a portion of the cathode electrode CE (or the second electrode) overlapping the first anode electrode AE1 may form a first light emitting element LD1. The second anode electrode AE2 (or the first electrode), a portion of the light emitting structure EMS overlapping the second anode electrode AE2, and a portion of the cathode electrode CE (or the second electrode) overlapping the second anode electrode AE2 may form a second light emitting element LD2. The third anode electrode AE3 (or the first electrode), a portion of the light emitting structure EMS overlapping the third anode electrode AE3, and a portion of the cathode electrode CE (or the second electrode) overlapping the third anode electrode AE3 may form a third light emitting element LD3.

[0123] A sealing layer TFE may be disposed on the cathode electrode CE. The sealing layer TFE can prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL.

[0124] An optical functional layer OFL may be disposed on the encapsulation layer TFE. In an embodiment, the optical functional layer OFL may be attached to the encapsulation layer TFE via an adhesive layer APL. For example, the optical functional layer OFL may be manufactured separately and attached to the encapsulation layer TFE via an adhesive layer APL. The adhesive layer APL may further function to protect the lower layers including the encapsulation layer TFE.

[0125] The optical function layer OFL may include a color filter layer CFL and a lens array LA.

[0126] The color filter layer CFL may include first to third color filters CF1 to CF3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. For example, the color filter layer CFL may include a first color filter CF1 corresponding to the first sub-pixel SP1, a second color filter CF2 corresponding to the second sub-pixel SP2, and a third color filter CF3 corresponding to the third sub-pixel SP3. The first to third color filters CF1 to CF3 can transmit light of different wavelength ranges. For example, the first color filter CF1 can transmit red light, the second color filter CF2 can transmit green light, and the third color filter CF3 can transmit blue light. In this case, the first sub-pixel SP1 may be a red sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, and the third sub-pixel SP3 may be a blue sub-pixel.

[0127] In an embodiment, the first to third color filters CF1 to CF3 may partially overlap each other in the border area BDA. In another embodiment, the first to third color filters CF1 to CF3 may be spaced apart from each other, and a black matrix may be provided between the spaced apart first to third color filters CF1 to CF3.

[0128] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include first to third lenses LS1 to LS3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. For example, the lens array LA may include a first lens LS1 corresponding to the first sub-pixel SP1, a second lens LS2 corresponding to the second sub-pixel SP2, and a third lens LS3 corresponding to the third sub-pixel SP3. The first to third lenses LS1 to LS3 output the light emitted from the first to third light-emitting elements LD1 to LD3, respectively, to intended paths, thereby improving the light output efficiency.

[0129] FIG. 5 is a schematic cross-sectional view showing an embodiment of a light emitting structure included in one of the first to third light emitting devices of FIG.

[0130] 4 and 5, the light emitting structure EMS may have a tandem structure in which the first and second light emitting units EU1 and EU2 are stacked. The light emitting structure EMS may be substantially similarly configured in each of the first to third light emitting elements LD1 to LD3 in FIG.

[0131] Each of the first and second light-emitting units EU1 and EU2 may include at least one light-emitting layer that generates light in response to an applied current. The first light-emitting unit EU1 may include a first light-emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light-emitting layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light-emitting unit EU2 may include a second light-emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light-emitting layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0132] Each of the first and second hole transport units HTU1 and HTU2 may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc., as necessary. The first and second hole transport units HTU1 and HTU2 may have the same structure or different structures.

[0133] Each of the first and second electron transport units ETU1 and ETU2 may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, etc. The first and second electron transport units ETU1 and ETU2 may have the same structure or different structures.

[0134] An intermediate layer (or a connection layer) that may be provided in the form of a charge generation layer CGL may be disposed between the first light emitting unit EU1 and the second light emitting unit EU2 to connect the first light emitting unit EU1 and the second light emitting unit EU2 to each other. Hereinafter, the charge generation layer CGL is referred to as an intermediate layer. In the embodiment, the intermediate layer CGL may have a stacked structure of a p-dopant layer and an n-dopant layer. For example, the p-dopant layer may include a p-type dopant such as HAT-CN, TCNQ, NDP-9, etc., and the n-dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof. However, the structure (or material) of the intermediate layer CGL is not limited to the above embodiment. In the embodiment, the intermediate layer CGL may have conductivity by including a material having a relatively high charge conductivity (or charge mobility) compared to the first and second light emitting units EU1 and EU2.

[0135] In the embodiment, the first light-emitting layer EML1 and the second light-emitting layer EML2 may generate light of different colors. The light emitted from the first light-emitting layer EML1 and the second light-emitting layer EML2 may be mixed and viewed as white light. For example, the first light-emitting layer EML1 may generate blue light, and the second light-emitting layer EML2 may include a structure in which a first sub-light-emitting layer configured to generate red light and a second sub-light-emitting layer configured to generate green light are stacked. In this case, a functional layer configured to transport holes and / or block electron transport may be further disposed between the first and second sub-light-emitting layers.

[0136] In other embodiments, the first light-emitting layer EML1 and the second light-emitting layer EML2 can produce light of the same color.

[0137] FIG. 6 is a schematic cross-sectional view showing another embodiment of a light emitting structure included in one of the first to third light emitting devices of FIG.

[0138] 4 and 6, the light emitting structure EMS' may have a tandem structure in which the first, second and third light emitting units EU1', EU2' and EU3' are stacked. The light emitting structure EMS' may be substantially similarly configured in each of the first to third light emitting elements LD1 to LD3 in FIG.

[0139] Each of the first to third light emitting units EU1' to EU3' may include a light emitting layer that generates light in response to an applied current. The first light emitting unit EU1' may include a first light emitting layer EML1', a first electron transport unit ETU1', and a first hole transport unit HTU1'. The first light emitting layer EML1' may be disposed between the first electron transport unit ETU1' and the first hole transport unit HTU1'. The second light emitting unit EU2' may include a second light emitting layer EML2', a second electron transport unit ETU2', and a second hole transport unit HTU2'. The second light emitting layer EML2' may be disposed between the second electron transport unit ETU2' and the second hole transport unit HTU2'. The third light emitting unit EU3' may include a third light emitting layer EML3', a third electron transport unit ETU3', and a third hole transport unit HTU3'. The third light emitting layer EML3' may be disposed between the third electron transport unit ETU3' and the third hole transport unit HTU3'.

[0140] Each of the first to third hole transport units HTU1' to HTU3' may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc. The first to third hole transport units HTU1' to HTU3' may have the same configuration or different configurations.

[0141] Each of the first to third electron transport units ETU1' to ETU3' may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, etc. The first to third electron transport units ETU1' to ETU3' may have the same configuration or different configurations.

[0142] The first intermediate layer CGL1' may be disposed between the first light emitting unit EU1' and the second light emitting unit EU2'. The second intermediate layer CGL2' may be disposed between the second light emitting unit EU2' and the third light emitting unit EU3'. In an embodiment, the first intermediate layer CGL1' and the second intermediate layer CGL2' may have conductivity by including a material having a relatively high charge conductivity (or charge mobility) compared to the first light emitting unit EU1', the second light emitting unit EU2', and the third light emitting unit EU3'.

[0143] In the embodiment, the first to third light emitting layers EML1' to EML3' may generate light of different colors. The light emitted from each of the first to third light emitting layers EML1' to EML3' may be mixed and viewed as white light. For example, the first light emitting layer EML1' may generate blue light, the second light emitting layer EML2' may generate green light, and the third light emitting layer EML3' may generate red light.

[0144] In another embodiment, two or more of the first to third light emitting layers EML1' to EML3' can generate light of the same color.

[0145] Unlike those shown in Figs. 5 and 6, the light emitting structure EMS of Fig. 4 may include one light emitting portion in each of the first to third light emitting elements LD1 to LD3. Here, the light emitting portions included in each of the first to third light emitting elements LD1 to LD3 may be configured to emit light of different colors. For example, the light emitting portion of the first light emitting element LD1 may emit red light, the light emitting portion of the second light emitting element LD2 may emit green light, and the light emitting portion of the third light emitting element LD3 may emit blue light. In this case, unlike that shown in Fig. 4, the light emitting portions of the first to third sub-pixels SP1 to SP3 may be separated from each other and disposed in the corresponding openings OP of the pixel defining film PDL. As described above, when the light emitting portion of the first sub-pixel SP1, the light emitting portion of the second sub-pixel SP2, and the light emitting portion of the third sub-pixel SP3 are separated from each other and disposed in the corresponding openings OP of the pixel defining film PDL, at least a part of the first to third color filters CF1 to CF3 may be omitted.

[0146] 7a to 7c are schematic cross-sectional views in which a part of the display device in FIG. 4 is enlarged, and FIG. 8 is a schematic view in which the EA portion in FIG. 7a is enlarged.

[0147] 7a to 7c show the light emitting structure EMS and the cathode electrode CE in a region (e.g., a boundary region between the first sub-pixel SP1 and the second sub-pixel SP2) including the first and second trenches TRCH1 and TRCH2, and further show the planarization layer PLNL, the pixel definition layer PDL, and the encapsulation layer TFE for clarity.

[0148] In Figs. 7a to 8, differences from the above-described embodiment will be mainly described to avoid duplication of explanation.

[0149] With reference to FIGS. 4 to 8, a pixel defining film PDL may be disposed on the planarizing layer PLNL.

[0150] The pixel defining layer PDL may include, but is not limited to, a first inorganic insulating layer PDL1 (or a first inorganic layer), a second inorganic insulating layer PDL2 (or a second inorganic layer), and a third inorganic insulating layer PDL3 (or a third inorganic layer) sequentially stacked along the third direction DR3. Depending on the embodiment, the pixel defining layer PDL may further include an additional inorganic insulating layer in addition to the above-mentioned inorganic insulating layers.

[0151] The first inorganic insulating layer PDL1 and the third inorganic insulating layer PDL3 may include silicon nitride, and the second inorganic insulating layer PDL2 may include silicon oxide. However, the materials of the first to third inorganic insulating layers PDL1, PDL2, and PDL3 are not limited to those in the above-mentioned embodiment. The pixel defining layer PDL including the first, second, and third inorganic insulating layers PDL1, PDL2, and PDL3 may have a stepped cross section in a region adjacent to the opening OP (see FIG. 4), but is not limited thereto. Depending on the embodiment, the pixel defining layer PDL may not have a stepped cross section in a region adjacent to the opening OP, as shown in FIG. 7b.

[0152] The trench TRCH may be located between the first subpixel SP1 and the second subpixel SP2. For example, the first trench TRCH1 and the second trench TRCH2 may be located in a boundary area BDA (see FIG. 4) (or a non-emitting area NEA) between the first subpixel SP1 and the second subpixel SP2.

[0153] Each of the first and second trenches TRCH1 and TRCH2 may include or be defined (or formed) by a portion through which at least a portion of the pixel defining layer PDL penetrates and a recessed portion of the planarization layer PLNL, as shown in FIG. 7a. The first and second trenches TRCH1 and TRCH2 may be formed by an etching method, for example, a dry etching method, but is not limited thereto. That is, each of the first and second trenches TRCH1 and TRCH2 may be formed by removing at least a portion of the pixel defining layer PDL and the planarization layer PLNL from an upper surface of the pixel defining layer PDL toward a lower surface of the planarization layer PLNL. Depending on the embodiment, each of the first and second trenches TRCH1 and TRCH2 may be formed by removing only a portion of the pixel defining layer PDL, as shown in FIG. 7b.

[0154] Each of the first and second trenches TRCH1 and TRCH2 may be arranged in a form surrounding the light emitting region of the corresponding subpixel in the boundary region BDA between the first subpixel SP1 and the second subpixel SP2, but is not limited thereto.

[0155] In the embodiment, the pixel definition film PDL and the planarization layer PLNL may include a first surface S1 and a second surface S2 that face each other in the first direction DR1 with the first and second trenches TRCH1 and TRCH2 in between. The pixel definition film PDL and the planarization layer PLNL may include a third surface S3 that connects the first surface S1 and the second surface S2. The first surface S1 may be a first sidewall of each of the first and second trenches TRCH1 and TRCH2, and the second surface S2 may be a second sidewall of each of the first and second trenches TRCH1 and TRCH2. The third surface S3 may be a bottom surface BT of each of the first and second trenches TRCH1 and TRCH2. Hereinafter, for convenience of explanation, the first surface S1 is referred to as the first sidewall of the trench TRCH, the second surface S2 is referred to as the second sidewall of the trench TRCH, and the third surface S3 is referred to as the bottom surface of the trench TRCH.

[0156] In the embodiment, the width W_T of the first and second trenches TRCH1 and TRCH2 may be, but is not limited to, 110 nm or more and 210 nm or less. The width W_T of each of the first and second trenches TRCH1 and TRCH2 may be 210 nm or less. The depth L_T of the first and second trenches TRCH1 and TRCH2 may be, but is not limited to, 2700 Å or more and 3300 Å or less. The depth L_T of the first and second trenches TRCH1 and TRCH2 may be 2000 Å or more. In the embodiment, the ratio of the width W_T to the depth L_T of each trench TRCH may be 1:3 or more. In the embodiment, the angle θ of each trench TRCH may be determined by the inclination of each of the first and second sidewalls S1 and S2 with respect to the bottom surface BT. The angle θ of each trench TRCH may be set to 80° or more and 90° or less so that the first and second intermediate layers CGL1, CGL2 of the structures arranged on the first and second sidewalls S1, S2 are interrupted within each trench TRCH.

[0157] The depth L_T and width W_T of each trench TRCH and the thicknesses of the first to third light emitting portions EU1, EU2, EU3 may be set in consideration of the disconnection of the first and second intermediate layers CGL1, CGL2 and the connection (and resonance distance) of the cathode electrode CE. For example, if the width W_T of each trench TRCH is greater than 210 nm, the cathode electrode CE may be disconnected due to a step due to the configuration disposed below the trench TRCH, and the sub-pixel may not operate normally.

[0158] A light emitting structure EMS may be disposed on the pixel defining layer PDL. The light emitting structure EMS may include a first light emitting portion EU1, a second light emitting portion EU2, and a third light emitting portion EU3. The light emitting structure EMS may be substantially similarly configured in each of the first, second, and third light emitting elements LD1, LD2, and LD3 described with reference to FIG. 4, but is not limited thereto. In an embodiment, the light emitting structure EMS may be formed by a vacuum deposition method.

[0159] The light emitting structure EMS may further include a first intermediate layer CGL1 and a second intermediate layer CGL2. The first intermediate layer CGL1 (or the first charge generation layer) may be disposed between the first light emitting unit EU1 and the second light emitting unit EU2, and the second intermediate layer CGL2 (or the second charge generation layer) may be disposed between the second light emitting unit EU2 and the third light emitting unit EU3.

[0160] In the embodiment, each of the first, second and third light emitting units EU1, EU2 and EU3 may include a light emitting layer that generates light in response to an applied current. The first light emitting unit EU1 may be the same as the first light emitting unit EU1' described with reference to Fig. 6, the second light emitting unit EU2 may be the same as the second light emitting unit EU2' described with reference to Fig. 6, and the third light emitting unit EU3 may be the same as the third light emitting unit EU3' described with reference to Fig. 6.

[0161] The first, second and third light emitting units EU1, EU2 and EU3 may include a charge transport unit, a light emitting layer, an electron transport unit and a buffer layer, each including a material having a relatively low charge conductivity (or charge mobility) compared to the first and second intermediate layers CGL1 and CGL2. For example, the first light emitting unit EU1 may include a first charge transport unit HTU1' (see FIG. 6), a first light emitting layer EML1' (see FIG. 6) and a first electron transport unit ETU1' (see FIG. 6) including a material having a relatively low charge conductivity (or charge mobility) compared to the first and second intermediate layers CGL1 and CGL2. The second light emitting unit EU2 may include a second charge transport unit HTU2' (see FIG. 6), a second light emitting layer EML2' (see FIG. 6) and a second electron transport unit ETU2' (see FIG. 6) including a material having a relatively low charge conductivity (or charge mobility) compared to the first and second intermediate layers CGL1 and CGL2. The third light emitting unit EU3 may include a third charge transport unit HTU3' (see FIG. 6), a third light emitting layer EML3' (see FIG. 6), and a third electron transport unit ETU3' (see FIG. 6) that include a material having a relatively low charge conductivity (or charge mobility) compared to the first and second intermediate layers CGL1 and CGL2.

[0162] In the embodiment, the first, second and third light emitting units EU1, EU2 and EU3 may include a material having a relatively higher insulating property than the first and second intermediate layers CGL1 and CGL2. In this case, even if the first, second and third light emitting units EU1, EU2 and EU3 are connected to each other on the trench TRCH, a current may not be transmitted to an adjacent sub-pixel.

[0163] The first light emitting portion EU1 and the second light emitting portion EU2 may include a disconnection portion (or an open portion) separated from each other in the first and second trenches TRCH1 and TRCH2. The disconnection portion may be defined as a cut portion where the first and second light emitting portions EU1 and EU2 are not continuously formed in the first and second trenches TRCH1 and TRCH2. In this case, the first light emitting portion EU1 of the first sub-pixel SP1 may be separated from the first light emitting portion EU1 of the second sub-pixel SP2, and the second light emitting portion EU2 of the first sub-pixel SP1 may be separated from the second light emitting portion EU2 of the second sub-pixel SP2.

[0164] In the embodiment, at least a part of the third light emitting unit EU3 of the first sub-pixel SP1 and at least a part of the third light emitting unit EU3 of the second sub-pixel SP2 may be disconnected in the first and second trenches TRCH1 and TRCH2. Specifically, the lower surfaces (e.g., a surface in contact with the second intermediate layer CGL2) of the third light emitting units EU3 of the adjacent sub-pixels may be disconnected in the first and second trenches TRCH1 and TRCH2, and the upper surfaces (e.g., a surface in contact with the cathode electrode CE) facing the lower surfaces in the third direction DR3 may be connected to each other. Thus, the third light emitting unit EU3 may not be disconnected in the first and second trenches TRCH1 and TRCH2. In this case, the third light emitting unit EU3 of the first sub-pixel SP1 and the third light emitting unit EU3 of the second sub-pixel SP2 may be connected.

[0165] Each of the first intermediate layer CGL1 and the second intermediate layer CGL2 can generate charges. The first intermediate layer CGL1 can connect the first light emitting unit EU1 and the second light emitting unit EU2, and the second intermediate layer CGL2 can connect the second light emitting unit EU2 and the third light emitting unit EU3. In an embodiment, the first and second intermediate layers CGL1 and CGL2 can have conductivity by including a material having a relatively high charge conductivity (or charge mobility) compared to the first, second and third light emitting units EU1, EU2 and EU3.

[0166] Each of the first and second intermediate layers CGL1, CGL2 may include a disconnected portion (or an open portion) on (or within) the first and second trenches TRCH1, TRCH2, similar to the first and second light emitting portions EU1, EU2. The disconnected portion may be defined as a portion where the first and second intermediate layers CGL1, CGL2 are not continuously formed in the first and second trenches TRCH1, TRCH2, respectively. That is, each of the first and second intermediate layers CGL1, CGL2 may be disconnected on the top of each of the first and second trenches TRCH1, TRCH2, respectively. In this case, the current flowing from one subpixel to another subpixel adjacent thereto through the first and second intermediate layers CGL1, CGL2 is reduced or prevented, and the subpixels may operate with high reliability. Furthermore, when the first and second intermediate layers CGL1, CGL2 are cut at the tops of the first and second trenches TRCH1, TRCH2, respectively, color mixing between adjacent subpixels is prevented, and each subpixel can emit light of the intended color.

[0167] In the embodiment, the light emitting structure EMS may include a first light emitting unit EU1, a first intermediate layer CGL1, a second light emitting unit EU2, a second intermediate layer CGL2, and a third light emitting unit EU3, which are sequentially stacked along the third direction DR3. The first light emitting unit EU1 may be disposed on a corresponding anode electrode AE ​​(see FIG. 2) (or a first electrode) and a pixel defining layer PDL, the first intermediate layer CGL1 may be disposed on the first light emitting unit EU1, the second light emitting unit EU2 may be disposed on the first intermediate layer CGL1, the second intermediate layer CGL2 may be disposed on the second light emitting unit EU2, and the third light emitting unit EU3 may be disposed on the second intermediate layer CGL2. A cathode electrode CE (or a second electrode) may be disposed on the third light emitting unit EU3.

[0168] The first intermediate layer CGL1 is located between the first light emitting portion EU1 and the second light emitting portion EU2 and can be covered by the second light emitting portion EU2. The second intermediate layer CGL2 is located between the second light emitting portion EU2 and the third light emitting portion EU3 and can be covered by the third light emitting portion EU3. When viewed in cross section, the first intermediate layer CGL1 and the second intermediate layer CGL2 can face each other with the second light emitting portion EU2 in between.

[0169] The first light emitting unit EU1 may be formed on the anode electrode AE ​​(or the first electrode) and the pixel defining layer PDL, and may also be formed on the first and second sidewalls S1 and S2 of the first and second trenches TRCH1 and TRCH2. At this time, in the first and second sidewalls S1 and S2, an end EP1 (hereinafter referred to as the "first end") of the first light emitting unit EU1 may be located adjacent to a bottom surface BT of the trench TRCH1 and may contact the bottom surface BT. Depending on the embodiment, the first light emitting unit EU1 may or may not be formed on the bottom surface BT of each trench TRCH. In the process of forming the first light emitting unit EU1, the position of the first end EP1 of the first light emitting unit EU1 on the first and second sidewalls S1 and S2 of each trench TRCH may be determined by adjusting the incidence angle (or injection angle) of the base material (or deposition material) of the first light emitting unit EU1.

[0170] The first intermediate layer CGL1 may be formed on the first light emitting unit EU1, and may also be formed on the first and second side walls S1 and S2 of each trench TRCH on the first light emitting unit EU1. An end EP2 (hereinafter referred to as "second end") of the first intermediate layer CGL1 may be located farther from the bottom surface BT of the trench TRCH than the first end EP1 of the first light emitting unit EU1. In the process of forming the first intermediate layer CGL1, the position of the second end EP2 of the first intermediate layer CGL1 on the first and second side walls S1 and S2 of each trench TRCH may be determined by adjusting the incidence angle (or injection angle) of the base material (or deposition material) of the first intermediate layer CGL1. In this case, the incidence angle of the base material of the first intermediate layer CGL1 may be different from the incidence angle of the base material of the first light emitting unit EU1. For example, the incidence angle of the base material of the first intermediate layer CGL1 may be set to be smaller than the incidence angle of the base material of the first light emitting unit EU1.

[0171] The second light emitting unit EU2 is formed on the first intermediate layer CGL1, and the first and second side walls S1, S2 of each trench TRCH may also be formed on the first intermediate layer CGL1. An end EP3 (hereinafter referred to as "third end") of the second light emitting unit EU2 may be located closer to the bottom surface BT of the trench TRCH than the second end EP2 of the first intermediate layer CGL1. In this case, as shown in FIG. 8, the second light emitting unit EU2 may be disposed relatively deeper than the first intermediate layer CGL1 in the trench TRCH. Thus, the first intermediate layer CGL1 may be covered by the second light emitting unit EU2 even in the trench TRCH. That is, the first intermediate layer CGL1 may be completely covered by the second light emitting unit EU2 up to the second end EP2. In the process of forming the second light emitting unit EU2, the position of the third end EP3 of the second light emitting unit EU2 on the first and second side walls S1, S2 of each trench TRCH may be determined by adjusting the incidence angle (or injection angle) of the base material (or deposition material) of the second light emitting unit EU2. In this case, the incidence angle of the base material of the second light emitting unit EU2 may be different from the incidence angle of the base material of the first intermediate layer CGL1. For example, the incidence angle of the base material of the second light emitting unit EU2 may be set to be larger than the incidence angle of the base material of the first intermediate layer CGL1. The incidence angle of the base material of the second light emitting unit EU2 may be the same as the incidence angle of the base material of the first light emitting unit EU1, but is not limited thereto.

[0172] The second intermediate layer CGL2 is formed on the second light emitting portion EU2, and may be formed on the first and second side walls S1, S2 of each trench TRCH on the second light emitting portion EU2. An end EP4 (hereinafter referred to as "fourth end") of the second intermediate layer CGL2 may be located farther from the bottom surface BT of the trench TRCH than the third end EP3 of the second light emitting portion EU2. In this case, as shown in FIG. 8, the second intermediate layer CGL2 is disposed relatively thinner than the second light emitting portion EU2 in the trench TRCH, and a part of the second intermediate layer CGL2 may be exposed to the outside. In the process of forming the second intermediate layer CGL2, the position of the fourth end EP4 of the second intermediate layer CGL2 on the first and second side walls S1, S2 of each trench TRCH may be determined by adjusting the incidence angle (or injection angle) of the base material (or deposition material) of the second intermediate layer CGL2. In this case, the incidence angle of the base material of the second intermediate layer CGL2 may be different from the incidence angle of the base material of the second light emitting portion EU2. For example, the incident angle of the base material of the second intermediate layer CGL2 may be set to be smaller than the incident angle of the base material of the second light emitting portion EU2. The injection angle of the base material of the second intermediate layer CGL2 may be the same as the injection angle of the base material of the first intermediate layer CGL1, but is not limited thereto.

[0173] The third light emitting unit EU3 is formed on the second intermediate layer CGL2, and the first and second side walls S1 and S2 of each trench TRCH may also be formed on the second intermediate layer CGL2. An end EP5 (hereinafter referred to as the "fifth end") of the third light emitting unit EU3 may be located closer to the bottom surface BT of the trench TRCH than the fourth end EP4 of the second intermediate layer CGL2. In this case, as shown in FIG. 8, the third light emitting unit EU3 may be disposed relatively deeper than the second intermediate layer CGL2 in the trench TRCH. Thus, the second intermediate layer CGL2 may be covered by the third light emitting unit EU3 even in the trench TRCH. That is, the second intermediate layer CGL2 may be completely covered by the third light emitting unit EU3 up to the fourth end EP4. The third light emitting unit EU3 may be disposed on a part of the second light emitting unit EU2 exposed to the outside. In the process of forming the third light emitting unit EU3, the position of the fifth end E5 of the third light emitting unit EU3 on the first and second side walls S1 and S2 of each trench TRCH may be determined by adjusting the incidence angle (or injection angle) of the base material (or deposition material) of the third light emitting unit EU3. In this case, the incidence angle of the base material of the third light emitting unit EU3 may be different from the incidence angles of the base materials of the first and second intermediate layers CGL1 and CGL2. For example, the incidence angle of the base material of the third light emitting unit EU3 may be set to be larger than the incidence angles of the first and second intermediate layers CGL1 and CGL2. The incidence angle of the base material of the third light emitting unit EU3 may be the same as the incidence angle of the base material of the first light emitting unit EU1 and / or the incidence angle of the base material of the second light emitting unit EU2, but is not limited thereto.

[0174] A cathode electrode CE may be disposed on the third light emitting unit EU3. The cathode electrode CE (or the second electrode) may be made of a metal containing a conductive material. In the embodiment, the thickness d of the third light emitting unit EU3 may be formed to be relatively thicker than the first and second light emitting units EU1, EU2. The thickness d of the third light emitting unit EU3 may be the distance between the second intermediate layer CGL2 and the cathode electrode CE. That is, the thickness d of the third light emitting unit EU3, which corresponds to the distance between the second intermediate layer CGL2 and the cathode electrode CE, may be greater than the distance between the first intermediate layer CGL1 and the second intermediate layer CGL2 (or the thickness of the second light emitting unit EU2). This is to prevent defects caused by shorting between the cathode electrode CE and the second intermediate layer CGL2 having conductivity including a material with high charge conductivity (or charge mobility), while preventing the cathode electrode CE from being disconnected due to steps of the components located thereunder (e.g., the second intermediate layer CGL2, the second light emitting unit EU2, the first intermediate layer CGL1, and the first light emitting unit EU1). That is, the third light emitting unit EU3 having a thick thickness d further secures the distance between the cathode electrode CE and the second intermediate layer CGL2, thereby preventing defects of shorting between the cathode electrode CE and the second intermediate layer CGL2. In addition, the third light emitting unit EU3 reduces the steps of the components located thereunder, improving the step coverage of the cathode electrode CE disposed on the third light emitting unit EU3, thereby preventing defects of the cathode electrode CE being disconnected on the trench TRCH.

[0175] In the embodiment, the thickness of the first and second light emitting units EU1 and EU2 in the third direction DR3 may be thinner than the thickness L_T of each of the first and second trenches TRCH1 and TRCH2. The thickness d of the third light emitting unit EU3 may be larger than the thickness L_T of each of the first and second trenches TRCH1 and TRCH2.

[0176] A void VD may be formed in each of the first and second trenches TRCH1 and TRCH2. The void VD may be the same as the first and second voids VD1 and VD2 described with reference to Fig. 4. The void VD may be surrounded by the first light emitting portion EU1, the second light emitting portion EU2, and the third light emitting portion EU3 in each trench TRCH.

[0177] According to the above-described embodiment, the first intermediate layer CGL1 (or the first charge generation layer) having conductivity including a material with relatively high charge conductivity (or charge mobility) among the layers constituting the light emitting structure EMS may be disconnected at the top of each trench TRCH and may be completely covered by the second light emitting unit EU2 up to its end (or the second end EP2) in the corresponding trench TRCH. Also, the second intermediate layer CGL2 (or the second charge generation layer) having conductivity including a material with relatively high charge conductivity (or charge mobility) may be disconnected at the top of each trench TRCH and may be completely covered by the third light emitting unit EU3 up to its end (or the fourth end EP4) in the corresponding trench TRCH. As a result, it is possible to reduce or prevent a short circuit between the first intermediate layer CGL1 and the second intermediate layer CGL2 having conductivity, thereby further improving the reliability of each sub-pixel.

[0178] According to the above-described embodiment, the first intermediate layer CGL1, the second intermediate layer CGL2, and the cathode electrode CE (or the second electrode) may be electrically insulated from each other.

[0179] In the above embodiment, the light emitting structure EMS has been described as having a tandem structure in which the first light emitting unit EU1, the second light emitting unit EU2, and the third light emitting unit EU3 are stacked, but is not limited thereto. Depending on the embodiment, the light emitting structure EMS may be configured as a tandem structure in which the first light emitting unit EU1 and the second light emitting unit EU2 are stacked as shown in FIG. 7c. In this case, the light emitting structure EMS may include a first intermediate layer CGL1 disposed between the first light emitting unit EU1 and the second light emitting unit EU2, similar to the light emitting structure EMS described with reference to FIG. 5. The first intermediate layer CGL1 may be the same as the intermediate layer CGL in FIG. 5.

[0180] Hereinafter, the light emitting structure EMS including the first and second light emitting units EU1 and EU2 and the first intermediate layer CGL1 will be described with reference to FIG. 7c.

[0181] Each of the first and second light emitting units EU1 and EU2 may include a light emitting layer that generates light in response to an applied current. The first light emitting unit EU1 may be the same as the first light emitting unit EU1 described with reference to Fig. 5, and the second light emitting unit EU2 may be the same as the second light emitting unit EU2 described with reference to Fig. 5. Each of the first and second light emitting units EU1 and EU2 may include a charge transport unit, a light emitting layer, an electron transport unit, a buffer layer, etc., including a material having a relatively lower charge conductivity than the first intermediate layer CGL1.

[0182] The first light emitting portion EU1 may include a disconnection portion separated from the first and second trenches TRCH1 and TRCH2. In this case, the first light emitting portion EU1 of the first sub-pixel SP1 may be separated from the first light emitting portion EU1 of the second sub-pixel SP2.

[0183] At least a part of the second light emitting portion EU2 of the first sub-pixel SP1 and at least a part of the second light emitting portion EU2 of the second sub-pixel SP2 may be disconnected in the first and second trenches TRCH1 and TRCH2. Specifically, the lower surfaces (e.g., surfaces in contact with the intermediate layer CGL) of the second light emitting portions EU2 of adjacent sub-pixels may be disconnected in the first and second trenches TRCH1 and TRCH2, and the upper surfaces (e.g., surfaces in contact with the cathode electrode CE) facing the lower surfaces in the third direction DR3 may be connected to each other. Thus, the second light emitting portion EU2 may not be disconnected in the first and second trenches TRCH1 and TRCH2. In this case, the second light emitting portion EU2 of the first sub-pixel SP1 and the second light emitting portion EU2 of the second sub-pixel SP2 may be connected.

[0184] The first intermediate layer CGL1 may generate charges. The first intermediate layer CGL1 may be the same as the intermediate layer CGL described with reference to FIG. 5. The first intermediate layer CGL1 may connect the first light emitting unit EU1 and the second light emitting unit EU2. The first intermediate layer CGL1 may be conductive by including a material having a relatively high charge conductivity. The first intermediate layer CGL1 may include a disconnection portion on (or within) the first and second trenches TRCH1 and TRCH2, similar to the first light emitting unit EU1. The first intermediate layer CGL1 may be cut at the top of each of the first and second trenches TRCH1 and TRCH2. In this case, a current flow from one sub-pixel to another sub-pixel adjacent thereto through the first intermediate layer CGL1 is reduced or prevented, and the sub-pixels may operate with high reliability. In addition, when the first intermediate layer CGL1 is cut at the top of each of the first and second trenches TRCH1 and TRCH2, color mixing between adjacent sub-pixels may be prevented.

[0185] The first intermediate layer CGL1 is formed on the first light emitting portion EU1, and may also be formed on the first light emitting portion EU1 on the first and second side walls S1 and S2 of each trench TRCH. On each trench TRCH, an end of the first intermediate layer CGL1 may be located farther from the bottom surface BT of the trench TRCH than the first light emitting portion EU1.

[0186] The second light emitting unit EU2 is formed on the first intermediate layer CGL1, and the first and second side walls S1, S2 of each trench TRCH may also be formed on the first intermediate layer CGL1. On each trench TRCH, an end of the second light emitting unit EU2 may be located closer to the bottom surface BT of the trench TRCH than an end of the first intermediate layer CGL1. In this case, the second light emitting unit EU2 may be disposed relatively deeper than the first intermediate layer CGL1 on the trench TRCH (or within the trench TRCH). Thus, the first intermediate layer CGL1 may be covered by the second light emitting unit EU2 even within the trench TRCH. That is, the first intermediate layer CGL1 may be completely covered by the second light emitting unit EU2 up to its end. The second light emitting unit EU2 may be disposed on a part of the first light emitting unit EU1 exposed to the outside.

[0187] A cathode electrode CE may be disposed on the second light emitting portion EU2. The cathode electrode CE (or the second electrode) may be made of a metal containing a conductive material.

[0188] A void VD may be formed in each of the first and second trenches TRCH1 and TRCH2. The void VD may be surrounded by the first light emitting portion EU1 and the second light emitting portion EU2 in each trench TRCH.

[0189] According to the above-described embodiment, the first intermediate layer CGL1 having conductivity including a material with relatively high charge conductivity (or charge mobility) among layers constituting the light emitting structure EMS may be interrupted at the top of each trench TRCH and may be completely covered by the second light emitting unit EU2 including a material with relatively low charge conductivity up to its end in the corresponding trench TRCH. In this case, the first intermediate layer CGL1 and the cathode electrode CE (or the second electrode) may be electrically insulated from each other. As a result, a defect caused by a short circuit between the first intermediate layer CGL1 and the cathode electrode CE may be reduced or prevented, and the reliability of each sub-pixel may be further improved.

[0190] Hereinafter, with reference to FIGS. 9 to 12, a method for forming a light emitting structure EMS on the first and second side walls S1 and S2 of the trench TRCH using the display device manufacturing apparatus 1 (see FIG. 9) will be described.

[0191] Fig. 9 is a schematic diagram showing one embodiment of the display device manufacturing apparatus 1, Fig. 10 is a schematic diagram showing the first deposition source 10 of Fig. 9, Fig. 11 is a schematic diagram showing the second deposition source 20 of Fig. 9, and Fig. 12 is a simulation result showing deposition behavior according to the incident angle of the configuration of the light emitting structure EMS formed on the trench TRCH. For convenience, in Fig. 9, the first deposition chamber CHM1 and the second deposition chamber CHM2 are shown to have the same structure.

[0192] 7a to 12, the display device manufacturing apparatus 1 may be a deposition apparatus for forming a light emitting structure EMS. Hereinafter, the display device manufacturing apparatus 1 will be referred to as a deposition apparatus.

[0193] The deposition apparatus 1 may include a first deposition chamber CHM1 and a second deposition chamber CHM2 separated from each other.

[0194] The first deposition chamber CHM1 may provide an enclosed space for depositing (or forming) the first and second intermediate layers CGL1 and CGL2, which are conductive and include a material having a relatively high charge conductivity among the components of the light emitting structure EMS, on the target substrate DS. Depending on the embodiment, the first deposition chamber CHM1 may provide an enclosed space for depositing (or forming) the cathode electrode CE (or the second electrode) including a conductive material on the target substrate DS. The second deposition chamber CHM2 may provide an enclosed space for depositing (or forming) the first, second, and third light emitting units EU1, EU2, and EU3, which include a material having a relatively low charge conductivity (or a low charge mobility) compared to the first and second intermediate layers CGL1 and CGL2 among the components of the light emitting structure EMS, on the target substrate DS. The insides of the first deposition chamber CHM1 and the second deposition chamber CHM2 may each be maintained at a reduced pressure atmosphere.

[0195] A moving plate MP, a first mask assembly MK1, and a first deposition source 10 may be disposed in an inner space of the first deposition chamber CHM1. A moving plate MP, a second mask assembly MK2, and a second deposition source 20 may be disposed in an inner space of the second deposition chamber CHM2. Each of the first and second deposition chambers CHM1 and CHM2 may include one or more gates GA. For example, the target substrate DS may enter and exit the corresponding chamber through the gate GA. For example, when the deposition material of the first intermediate layer CGL1 on the target substrate DS is completed in the first deposition chamber CHM1, the target substrate DS may be moved to the second deposition chamber CHM2 through the gate GA of the first deposition chamber CHM1. Also, when the deposition material of the second light emitting unit EU2 on the target substrate DS is completed in the second deposition chamber CHM2, the target substrate DS may be moved to the first deposition chamber CHM1 through the gate GA of the second deposition chamber CHM2.

[0196] The moving plate MP is capable of moving within the first and second deposition chambers CHM1, CHM2.

[0197] The first mask assembly MK1 is disposed between the target substrate DS and the first deposition source 10 and may overlap the target substrate DS. The first mask assembly MK1 may be supported by a support SU. A plurality of first openings OPN1 may be defined in the first mask assembly MK1. A deposition material injected in the first deposition chamber CHM1 may pass through the first openings OPN1 and be deposited on the target substrate DS.

[0198] The second mask assembly MK2 is disposed between the target substrate DS and the second deposition source 20 and may overlap the target substrate DS. The second mask assembly MK2 may be supported by a support SU. A plurality of second openings OPN2 may be defined in the second mask assembly MK2. The deposition material injected in the second deposition chamber CHM2 may pass through the second openings OPN2 and be deposited on the target substrate DS.

[0199] The first deposition source 10 is disposed under the first mask assembly MK1 and may contain a deposition material therein. The first deposition source 10 may vaporize or sublimate the deposition material contained therein and inject it onto a target substrate DS. At this time, the first deposition source 10 may contain a deposition material corresponding to a first intermediate layer CGL1, a deposition material corresponding to a second intermediate layer CGL2, and a deposition material corresponding to a cathode electrode CE separately from one another.

[0200] The first deposition source 10 may include a first body BO1 and a first angle limiting member AC1. The first body BO1 may include a crucible for accommodating a deposition material and a first nozzle NOZ1 for injecting the deposition material onto a target substrate DS. Each of the first nozzles NOZ1 may be defined with a first nozzle hole NOH1. The first deposition source 10 may include a first reflector RF1 for preventing heat from flowing upward from the first body BO1.

[0201] The first angle limiting member AC1 can limit a deposition area of ​​the deposition material sprayed toward the target substrate DS through the first nozzle NOZ1. The deposition material sprayed from the first body BO1 can have a radiation angle limited to a certain angle or less by the first angle limiting member AC1. As a result, the incidence angle of the deposition material to the target substrate DS during deposition in the deposition apparatus 1 can be limited to a certain angle or less, and patterning accuracy in film formation through the first mask assembly MK1 can be improved. The first angle limiting member AC1 may include a 1-1 angle limiting member AC1_1 and a 1-2 angle limiting member AC1_2 facing each other across the first nozzle NOZ1. The incidence angle of the deposition material (e.g., the deposition material corresponding to the first intermediate layer CGL1 and the deposition material corresponding to the second intermediate layer CGL2) sprayed onto the target substrate DS can be adjusted by adjusting the inclination angle of the 1-1 angle limiting member AC1_1 and the 1-2 angle limiting member AC1_2.

[0202] The second deposition source 20 is disposed below the second mask assembly MK2 and may contain a deposition material therein. The second deposition source 20 may vaporize or sublimate the deposition material contained therein and inject it onto the target substrate DS. At this time, the second deposition source 20 may contain the deposition material corresponding to the first light emitting unit EU1, the deposition material corresponding to the second light emitting unit EU2, and the deposition material corresponding to the third light emitting unit EU3 separately from one another.

[0203] The second deposition source 20 may include a second body BO2 and a second angle limiting member AC2. The second body BO2 may include a crucible for accommodating a deposition material and a second nozzle NOZ2 for spraying the deposition material onto the target substrate DS. A second nozzle hole NOH2 may be defined in each of the second nozzles NOZ2. The second deposition source 20 may include a second reflector RF2 for preventing heat from flowing upward from the second body BO2.

[0204] The second angle limiting member AC2 can limit a deposition area of ​​the deposition material sprayed toward the target substrate DS through the second nozzle NOZ2. The deposition material sprayed from the second body BO2 can have a radiation angle limited to a certain angle or less by the second angle limiting member AC2. As a result, the incidence angle of the deposition material to the target substrate DS during deposition in the deposition apparatus 1 can be limited to a certain angle or less, and patterning accuracy in film formation through the second mask assembly MK2 can be improved. The second angle limiting member AC2 may include a 2-1 angle limiting member AC2_1 and a 2-2 angle limiting member AC2_2 facing each other across the second nozzle NOZ2. The incidence angle of the deposition material sprayed to the target substrate DS can be adjusted by adjusting the inclination angle of the 2-1 angle limiting member AC2_1 and the 2-2 angle limiting member AC2_2.

[0205] In the embodiment, the inclination angle of the first angle limiting member AC1 and the inclination angle of the second angle limiting member AC2 may be different from each other. For example, but not limited to, the inclination angle of the second angle limiting member AC2 may be larger than the inclination angle of the first angle limiting member AC1. The inclination angles of the first angle limiting member AC1 and the second angle limiting member AC2 may be determined according to the incidence angle of the deposition material sprayed onto the corresponding target substrate DS.

[0206] Hereinafter, the degree of deposition of the light emitting structure EMS formed inside the trench TRCH according to the incidence angle will be described with reference to FIG.

[0207] In Fig. 12, the first and second angles of incidence may be determined within a range of 40° to 85°. For example, the first angle of incidence is 50° to 60°, and the second angle of incidence is 70° to 75°. The second angle of incidence may be a higher angle of incidence than the first angle of incidence. The first angle of incidence may be a lower angle of incidence than the second angle of incidence.

[0208] 12, Examples 1 to 6 are examples in which the inclination angles of the first and second angle limiting members AC1 and AC2 are adjusted so that the components (e.g., first light emitting portion EU1, first intermediate layer CGL1, second light emitting portion EU2, second intermediate layer CGL2, and third light emitting portion EU3) included in the light emitting structure EMS are incident on the pixel defining film PDL at the first incident angle (or low incident angle) when the light emitting structure EMS is formed on the pixel defining film PDL (or target substrate DS). Examples 7 to 12 are examples in which the inclination angles of the first and second angle limiting members AC1 and AC2 are adjusted so that the components (e.g., first light emitting portion EU1, first intermediate layer CGL1, second light emitting portion EU2, second intermediate layer CGL2, and third light emitting portion EU3) included in the light emitting structure EMS are incident on the pixel defining film PDL at the second incident angle (or high incident angle) when the light emitting structure EMS is formed on the pixel defining film PDL (or target substrate DS).

[0209] The width of the trench TRCH in Examples 1 and 7 is about 110 nm, the width of the trench TRCH in Examples 2 and 8 is about 130 nm, the width of the trench TRCH in Examples 3 and 9 is about 150 nm, the width of the trench TRCH in Examples 4 and 10 is about 170 nm, the width of the trench TRCH in Examples 5 and 11 is about 190 nm, and the width of the trench TRCH in Examples 6 and 12 is about 210 nm.

[0210] In Examples 1 to 12, the first light emitting unit EU1, the first intermediate layer CGL1, the second light emitting unit EU2, and the second intermediate layer CGL2 may be formed discontinuously on the trench TRCH, and the third light emitting unit EU3 may be formed continuously without being interrupted. Also, in Examples 1 to 12, a part of the lower surface of the third light emitting unit EU3 may be formed discontinuously on the trench TRCH, and its upper surface may be formed continuously without being interrupted.

[0211] In the first to twelfth embodiments, the ends of the first light emitting unit EU1 may be located on the first and second side walls S1 and S2 of the trench TRCH. The first light emitting unit EU1 may also be located on the bottom surface BT of the trench TRCH.

[0212] On the trench TRCH, an end of each of the first intermediate layers CGL1 in Examples 1 to 6 is located farther from the bottom surface BT of the trench TRCH than an end of each of the first intermediate layers CGL1 in Examples 7 to 12. This confirms that the first intermediate layer CGL1 in each of Examples 7 to 12 incident on the pixel defining layer PDL at the second incident angle (or high incident angle) can be formed deeper toward the first and second side walls S1 and S2 of the trench TRCH than the first intermediate layer CGL1 in each of Examples 1 to 6 incident on the pixel defining layer PDL at the first incident angle (or low incident angle).

[0213] On the trench TRCH, the end of each of the second light emitting units EU2 in Examples 1 to 6 is located farther from the bottom surface BT of the trench TRCH than the end of each of the second light emitting units EU2 in Examples 7 to 12. This confirms that the second light emitting units EU2 in each of Examples 7 to 12 incident on the first intermediate layer CGL1 at the second incident angle (or high incident angle) can be formed deeper toward the first and second side walls S1, S2 of the trench TRCH than the second light emitting units EU2 in each of Examples 1 to 6 incident on the first intermediate layer CGL1 at the first incident angle (or low incident angle).

[0214] On the trench TRCH, the end of each of the second intermediate layers CGL2 in Examples 1 to 6 is located farther from the bottom surface BT of the trench TRCH than the end of each of the second intermediate layers CGL2 in Examples 7 to 12. This confirms that the second intermediate layer CGL2 in each of Examples 7 to 12 incident on the second light emitting portion EU2 at the second incident angle (or high incident angle) can be formed deeper toward the first and second side walls S1, S2 of the trench TRCH than the second intermediate layer CGL2 in each of Examples 1 to 6 incident on the second light emitting portion EU2 at the first incident angle (or low incident angle).

[0215] On the trench TRCH, a part of the lower surface of each of the third light emitting units EU3 of Examples 1 to 12 is disconnected, and the upper surface thereof is not disconnected. As a result, on the trench TRCH, each of the third light emitting units EU3 of Examples 1 to 12 covers the end portion of the second intermediate layer CGL2 while grading the step caused by the configuration disposed on the lower portion thereof.

[0216] In the above embodiment, in order to prevent a defect in which the first and second intermediate layers CGL1 and CGL2, which include a material having a relatively high charge conductivity and have conductivity, are shorted on the trench TRCH, the first and second intermediate layers CGL1 and CGL2 are incident on the pixel defining layer PDL at a first incident angle (or a low incident angle), and the first to third light emitting units EU1, EU2, and EU3, which are disposed on the first and second intermediate layers CGL1 and CGL2 and include a material having a relatively low charge conductivity compared to the first and second intermediate layers CGL1 and CGL2, are incident on the pixel defining layer PDL at a second incident angle (or a high incident angle), in accordance with the simulation result of FIG. 12. In this case, on the first and second side walls S1 and S2 of the trench TRCH, the end EP2 (see FIG. 8) of the first intermediate layer CGL1 is located farther from the bottom surface BT of the trench TRCH than the end EP3 (see FIG. 8) of the second light emitting unit EU2, and may be completely covered by the second light emitting unit EU2. In addition, on the first and second side walls S1, S2 of the trench TRCH, the end EP4 (see FIG. 8) of the second intermediate layer CGL2 is located farther from the bottom surface BT of the trench TRCH than the end EP5 (see FIG. 8) of the third light emitting portion EU3, and can be completely covered by the third light emitting portion EU3. This prevents a short circuit between the first intermediate layer CGL1 and the second intermediate layer CGL2, which are conductive inside the trench TRCH, and allows the sub-pixel to operate with high reliability, thereby improving the reliability of the display device DD (see FIG. 1).

[0217] In addition, in the above-described embodiment, the incidence angles of the first and second intermediate layers CGL1 and CGL2 and the incidence angles of the first to third light emitting units EU1, EU2, and EU3 can be easily adjusted by adjusting the inclination angles of the first and second angle limiting members AC1 and AC2 of the deposition apparatus 1. As a result, it is possible to prevent short circuit defects between the conductive first intermediate layer CGL1 and the second intermediate layer CGL2 by adjusting the incidence angles of the first light emitting unit EU1, the first intermediate layer CGL1, the second light emitting unit EU2, the second intermediate layer CGL2, and the third light emitting unit EU3 included in the light emitting structure EMS without a separate additional process. As a result, it is possible to further improve the manufacturing efficiency of the display device.

[0218] Hereinafter, application fields of the display device according to the embodiment will be described with reference to FIGS.

[0219] FIG. 13 is a schematic block diagram illustrating an embodiment of a display system 1000.

[0220] Referring to FIG. 13, a display system 1000 may include a processor 1100 and one or more display devices 1210,1220.

[0221] The processor 1100 can perform various tasks and calculations. In an embodiment, the processor 1100 may include an application processor, a graphic processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 can be connected to other components of the display system 1000 via a bus system to control them.

[0222] 13, a display system 1000 is shown including first and second display devices 1210, 1220. The processor 1100 may be connected to the first display device 1210 via a first channel CH1 and to the second display device 1220 via a second channel CH2.

[0223] The processor 1100 may transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210 via the first channel CH1. The first display device 1210 may display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 1210 may have the same configuration as the display device DD described with reference to FIG. 1.

[0224] The processor 1100 may transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220 via the second channel CH2. The second display device 1220 may display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 1220 may have the same configuration as the display device DD described with reference to FIG. 1.

[0225] The display system 1000 may include a computing system providing a video display function, such as a portable computer, a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation system, an ultra mobile personal computer (UMPC), etc. The display system 1000 may also include at least one of a head mounted display device (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0226] FIG. 14 is a schematic perspective view showing an application example of the display system of FIG.

[0227] 14, the display system 1000 of FIG. 13 may be applied to a head-mounted display device 2000. The head-mounted display device 2000 may be a wearable electronic device that can be worn on a user's head.

[0228] The head mounted display device 2000 may include a head mounted band 2100 and a display device housing case 2200. The head mounted band 2100 may be connected to the display device housing case 2200. The head mounted band 2100 may be connected to the display device housing case 2200. The head mounted band 2100 may include a horizontal band and / or a vertical band for fixing the head mounted display device 2000 to the user's head. The horizontal band may be configured to surround the side of the user's head, and the vertical band may be configured to surround the top of the user's head. However, the embodiment is not limited thereto. For example, the head mounted band 2100 may be embodied in the shape of a glasses frame, a helmet, or the like.

[0229] The display device housing case 2200 can house the first and second display devices 1210 and 1220 of Fig. 13. The display device housing case 2200 can further house the processor 1100 of Fig. 13.

[0230] FIG. 15 is a schematic diagram showing the head-mounted display device of FIG. 14 worn by a user.

[0231] 15, a first display panel DP1 of the first display device 1210 (see FIG. 14) and a second display panel DP2 of the second display device 1220 (see FIG. 14) are arranged in a head-mounted display device 2000. The head-mounted display device 2000 may further include one or more lenses LLNS, RLNS.

[0232] In the display device storage case 2200, the right-eye lens RLNS can be disposed between the first display panel DP1 and the right eye of the user. In the display device storage case 2200, the left-eye lens LLNS can be disposed between the second display panel DP2 and the left eye of the user.

[0233] An image output from the first display panel DP1 can be viewed by the user's right eye through the right-eye lens RLNS. The right-eye lens RLNS can refract light from the first display panel DP1 so that it faces the user's right eye. The right-eye lens RLNS can perform an optical function for adjusting the viewing distance between the first display panel DP1 and the user's right eye.

[0234] An image output from the second display panel DP2 can be viewed by the left eye of the user through the left eye lens LLNS. The left eye lens LLNS can refract light from the second display panel DP2 so that it faces the left eye of the user. The left eye lens LLNS can perform an optical function for adjusting the viewing distance between the second display panel DP2 and the left eye of the user.

[0235] In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a pancake-shaped cross section. In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including sub-regions having different optical properties. In this case, each display panel outputs an image corresponding to each sub-region of the multi-channel lens, and the output image can pass through the corresponding sub-region to be viewed by a user.

[0236] Although specific embodiments and application examples have been described above, other embodiments and modifications can be derived from the above description. Therefore, the technical scope of the present invention is not limited to this embodiment, but can extend to the appended claims, various obvious modifications, and equivalents. [Explanation of symbols]

[0237] DD display device DP display panel PXL Pixel SP subpixel SUB board PCL Pixel circuit layer LDL Light emitting device layer OFL optical functional layer OC overcoat layer CW Cover Window EMS Light-emitting Structure EU1, EU2, EU3 1st, 2nd, 3rd light emitting section CGL1, CGL2 First and second intermediate layers SPR Separator TRCH1, TRCH2 First and second trenches S1, S2 First and second side walls BT bottom PDL Pixel Defined Membrane VD Void EP1, EP2, EP3, EP4, EP5 1st, 2nd, 3rd, 4th, 5th end 1 Vapor deposition equipment 10, 20 First and second deposition sources AC1, AC2 First and second angle limiting members

Claims

1. a first sub-pixel and a second sub-pixel arranged adjacent to each other; Each of the first and second sub-pixels is A first electrode; a pixel defining layer disposed on the first electrode; a first light emitting portion disposed on the pixel defining film and configured to emit light; A first intermediate layer disposed on the first light emitting portion; a second light emitting portion disposed on the first intermediate layer and emitting light; a second electrode disposed on the second light emitting portion; a trench formed by recessing at least a portion of the pixel defining layer in a boundary region between the first sub-pixel and the second sub-pixel; the first intermediate layer is interrupted on the trench; The second light-emitting portion completely covers the first intermediate layer above the trench.

2. The display device of claim 1 , wherein the first intermediate layer is conductive and contains a material having a higher charge conductivity than the first and second light emitting parts.

3. The display device according to claim 2 , wherein the first intermediate layer and the second electrode are electrically insulated from each other.

4. the pixel defining layer includes a first surface and a second surface facing each other across the trench, and a third surface connecting the first surface and the second surface; The display device of claim 2 , wherein the first surface constitutes a first sidewall of the trench, the second surface constitutes a second sidewall of the trench, and the third surface constitutes a bottom surface of the trench.

5. The display device of claim 4 , wherein an end of the second light-emitting portion on the first and second side walls is adjacent to the bottom surface more than an end of the first intermediate layer, and the second light-emitting portion completely covers the first intermediate layer on the first and second side walls.

6. The first light emitting portion is interrupted within the trench, The display device of claim 4 , wherein the second light emitting portion of the first sub-pixel and the second light emitting portion of the second sub-pixel are connected to each other.

7. Each of the first and second sub-pixels is a third light emitting portion disposed between the first electrode and the first light emitting portion and emitting light; A second intermediate layer disposed between the third light emitting portion and the first light emitting portion, The second intermediate layer is interrupted above the trench; The display device according to claim 4 , wherein the first light emitting portion completely covers the second intermediate layer above the trench.

8. the second intermediate layer includes a material having a higher charge conductivity than the first light emitting part, the second light emitting part, and the third light emitting part, and has electrical conductivity; The display device according to claim 7 , wherein the first intermediate layer, the second intermediate layer, and the second electrode are electrically insulated from each other.

9. On the first and second side walls, an end of the second light emitting portion is adjacent to the bottom surface with respect to an end of the first intermediate layer, and an end of the first light emitting portion is adjacent to the bottom surface with respect to an end of the second intermediate layer, The display device of claim 8 , wherein the second light-emitting portion completely covers the first intermediate layer on the first and second side walls, and the first light-emitting portion completely covers the second intermediate layer.

10. The third light emitting portion and the first light emitting portion are disconnected within the trench, The display device of claim 8 , wherein the second light emitting portion of the first sub-pixel and the second light emitting portion of the second sub-pixel are connected to each other.

11. The display device of claim 8 , wherein the trench includes a void surrounded by the first light emitting portion, the second light emitting portion, and the third light emitting portion.

12. The display device according to claim 8 , wherein a distance between the first intermediate layer and the second electrode is larger than a distance between the first intermediate layer and the second intermediate layer.

13. the first light emitting part includes a first hole transport part, a first light emitting layer, and a first electron transport part; the second light emitting part includes a second hole transport part, a second light emitting layer, and a second electron transport part; The display device of claim 7 , wherein the third light emitting part comprises a third hole transport part, a third light emitting layer, and a third electron transport part.

14. In a manufacturing apparatus for a display device, The display device includes a first sub-pixel and a second sub-pixel, each of which includes a pixel defining layer, a first emission portion, a first intermediate layer, a second emission portion, and a second electrode, which are sequentially disposed on a first electrode, and a trench formed by recessing a portion of the pixel defining layer in a boundary region between the first and second sub-pixels, The manufacturing apparatus includes: a first deposition chamber for forming the first intermediate layer on the pixel defining film; a second deposition chamber for forming the first and second light emitting units on the pixel defining layer, the first deposition chamber includes a first nozzle unit configured to inject a deposition material for the first intermediate layer, and a first angle limiting member configured to be connected to the first nozzle unit and limit an incidence angle of the deposition material, the second deposition chamber includes a second nozzle unit configured to inject deposition materials for the first and second light emitting units, and a second angle limiting member connected to the second nozzle unit to limit an incidence angle of the deposition materials, The deposition material of the first intermediate layer and the deposition materials of the first and second light emitting portions are incident on the pixel defining layer at different incident angles.

15. The apparatus of claim 14 , wherein the first intermediate layer contains a material having a higher charge conductivity than the first and second light emitting parts and has electrical conductivity.

16. the first angle limiting member causes the deposition material of the first intermediate layer to be incident on the pixel defining layer at a low incident angle; The apparatus of claim 15, wherein the second angle limiting member causes the deposition material of each of the first and second light emitting portions to be incident on the pixel defining layer at a high incident angle.

17. Each of the first and second sub-pixels further includes a second intermediate layer having the conductivity and disposed between the second light-emitting portion and the second electrode, and a third light-emitting portion disposed between the second intermediate layer and the second electrode, 16. The apparatus of claim 15, wherein the first deposition chamber injects the deposition material for the second intermediate layer onto the second light emitting unit, and the second deposition chamber injects the deposition material for the third light emitting unit onto the second intermediate layer.

18. The apparatus of claim 17 , wherein the deposition material of the second intermediate layer and the deposition material of the third light emitting portion are incident at different incident angles.

19. A display panel; a lens disposed on the display panel; the display panel includes first and second sub-pixels arranged adjacent to each other, Each of the first and second sub-pixels is A first electrode; a pixel defining layer disposed on the first electrode; a first light emitting portion disposed on the pixel defining film and configured to emit light; A first intermediate layer disposed on the first light emitting portion; a second light emitting portion disposed on the first intermediate layer and emitting light; a second electrode disposed on the second light emitting portion; a trench formed by recessing at least a portion of the pixel defining layer in a boundary region between the first sub-pixel and the second sub-pixel; the first intermediate layer is interrupted on the trench; A wearable electronic device, wherein the second light-emitting portion completely covers the first intermediate layer above the trench.

20. Each of the first and second sub-pixels is a third light emitting portion disposed between the first electrode and the first light emitting portion and emitting light; A second intermediate layer disposed between the third light emitting portion and the first light emitting portion, The third light emitting portion and the second intermediate layer are disconnected above the trench, The wearable electronic device of claim 19 , wherein the first light-emitting portion completely covers the second intermediate layer above the trench.

Images