Display device and manufacturing method for the same

Abstract

To suppress deterioration in display performance.SOLUTION: In an embodiment, a display device includes a substrate, a lower electrode disposed over the substrate, an inorganic insulating layer covering a peripheral part of the lower electrode, a partition wall having a lower part with conductivity disposed on the inorganic insulating layer and an upper part disposed on the lower part and projecting from a side surface of the lower part, an organic layer disposed on the lower electrode, and an upper electrode disposed on the organic layer in contact with the lower part. The organic layer includes a hole injection layer apart from the partition wall and in contact with the lower electrode, a first intermediate layer disposed on the hole injection layer and including a first light-emitting layer, a first charge generation layer disposed on the first intermediate layer apart from the partition wall, and a second intermediate layer disposed on the first charge generation layer and including a second light-emitting layer. The hole injection layer and the first charge generation layer are apart from each other and apart from the upper electrode.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] 1. Field of the Invention The present invention relates to a display device and a manufacturing method thereof. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have been put to practical use. This display element includes a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer that covers the lower electrode, and an upper electrode that covers the organic layer. In the process of manufacturing such display elements, a technique for suppressing deterioration in reliability is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-195677 A [Patent Document 2] JP 2004-207217 A [Patent Document 3] JP 2008-135325 A [Patent Document 4] JP 2009-32673 A [Patent Document 5] JP 2010-118191 A [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device capable of suppressing deterioration of display performance, and a manufacturing method thereof. [Means for solving the problem]

[0005] According to one embodiment, the display device comprises: a lower electrode disposed above the substrate; an inorganic insulating layer covering a peripheral portion of the lower electrode; a partition having a conductive lower portion disposed on the inorganic insulating layer and an upper portion disposed on the lower portion and protruding from a side surface of the lower portion; an organic layer disposed on the lower electrode; and an upper electrode disposed on the organic layer and in contact with the lower portion, wherein the organic layer has a hole injection layer spaced from the partition and in contact with the lower electrode, a first intermediate layer disposed on the hole injection layer and including a first light-emitting layer, a first charge generation layer spaced from the partition and disposed on the first intermediate layer, and a second intermediate layer disposed on the first charge generation layer and including a second light-emitting layer, and the hole injection layer and the first charge generation layer are spaced from each other and from the upper electrode.

[0006] According to one embodiment, the display device comprises: The present invention comprises a substrate, a lower electrode arranged above the substrate, an inorganic insulating layer covering a peripheral portion of the lower electrode, a partition having a conductive lower portion arranged on the inorganic insulating layer, and an upper portion arranged on the lower portion and protruding from a side of the lower portion, an organic layer arranged on the lower electrode, and an upper electrode arranged on the organic layer and in contact with the lower portion, wherein the organic layer has a hole injection layer spaced from the partition and in contact with the lower electrode, a first intermediate layer covering the hole injection layer and including a first light-emitting layer, a first charge generation layer spaced from the partition and arranged on the first intermediate layer, and a second intermediate layer covering the first intermediate layer and the first charge generation layer and including a second light-emitting layer.

[0007] According to one embodiment, a method for manufacturing a display device includes the steps of: a lower electrode is formed above a substrate; an inorganic insulating layer is formed to cover a peripheral portion of the lower electrode; a partition is formed having a lower portion located on the inorganic insulating layer and formed of a conductive material, and an upper portion located on the lower portion and protruding from a side surface of the lower portion; deposition is performed using the partition as a mask to form a laminated film including an organic layer and an upper electrode on the lower electrode; the organic layer has a hole injection layer, a first intermediate layer including a first light-emitting layer, a first charge generation layer, and a second intermediate layer including a second light-emitting layer, each of the hole injection layer and the first charge generation layer is formed from a material ejected from a first deposition source at a first deposition angle using the partition as a mask; each of the first intermediate layer and the second intermediate layer is formed from a material ejected from a second deposition source at a second deposition angle using the partition as a mask, and the second deposition angle is greater than the first deposition angle. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing an example of the configuration of a display device DSP. [Diagram 2] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG. [Figure 4] FIG. 4 is a diagram showing an example of the configuration of the display elements DE1 to DE3. [Diagram 5] FIG. 5 is a schematic cross-sectional view showing an example of the configuration of the organic layer OR. [Figure 6] FIG. 6 is a cross-sectional view of the organic layer OR shown in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view showing another example of the configuration of the organic layer OR. [Figure 8] FIG. 8 is a cross-sectional view of the organic layer OR shown in FIG. [Figure 9] FIG. 9 is a diagram for explaining a manufacturing method of the display device. [Figure 10] FIG. 10 is a diagram for explaining a manufacturing method of the display device. [Figure 11]FIG. 11 is a diagram for explaining a method for manufacturing the hole injection layer and the charge generation layer. [Figure 12] FIG. 12 is a diagram for explaining a method for manufacturing the intermediate layer. [Figure 13] FIG. 13 is a diagram for explaining a manufacturing method of the display device. [Figure 14] FIG. 14 is a diagram for explaining a manufacturing method of the display device. [Figure 15] FIG. 15 is a diagram for explaining a manufacturing method of the display device. [Figure 16] FIG. 16 is a diagram for explaining a manufacturing method of the display device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The embodiment will be described with reference to the drawings. The disclosure is merely an example, and those who are skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed explanations may be omitted as appropriate.

[0010] In addition, in the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. Viewing various elements parallel to the third direction Z is called a planar view.

[0011] The display device according to this embodiment is an organic electroluminescence display device having an organic light emitting diode (OLED) as a display element, and can be mounted on televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and the like.

[0012] FIG. 1 is a plan view showing an example of the configuration of a display device DSP.

[0013] The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA outside the display area DA, on an insulating substrate 10. The substrate 10 may be a glass substrate or a flexible resin substrate.

[0014] In this embodiment, the shape of the substrate 10 in a plan view is rectangular. However, the shape of the substrate 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0015] The display area DA includes a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y. The pixels PX include a plurality of subpixels SP. In one example, the pixel PX includes a subpixel SP1 of a first color, a subpixel SP2 of a second color, and a subpixel SP3 of a third color. The first color, the second color, and the third color are different from each other. The pixel PX may include a subpixel SP of another color, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0016] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements constituted by, for example, thin film transistors.

[0017] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element DE.

[0018] It should be noted that the configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0019] The display element DE is an organic light-emitting diode (OLED) as a light-emitting element, and may be called an organic EL element.

[0020] The peripheral area SA has a plurality of terminals TE arranged in one direction. In the illustrated example, the plurality of terminals TE are arranged along a first direction X. Each of the terminals TE extends in a second direction Y, but this is not limited thereto. For example, some of the plurality of terminals TE may extend in an oblique direction. Such a plurality of terminals TE are electrically connected to, for example, a flexible printed circuit board or an IC chip.

[0021] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3.

[0022] In the illustrated example, the subpixels SP2 and SP3 are aligned in the second direction Y. The subpixels SP1 and SP2 are aligned in the first direction X, and the subpixels SP1 and SP3 are aligned in the first direction X.

[0023] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and the subpixels SP3 are alternately arranged in the second direction Y, and a column in which a plurality of subpixels SP1 are arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0024] It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to the example in Fig. 2. As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0025] An insulating layer 5 and partition walls 6 are disposed in the display area DA. The insulating layer 5 has openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. The insulating layer 5 having these openings AP1, AP2, and AP3 may be referred to as a rib.

[0026] The partition wall 6 overlaps with the insulating layer 5 in a plan view. The partition wall 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. It can also be said that the partition wall 6 has openings in the subpixels SP1, SP2, and SP3, similar to the insulating layer 5. The partition wall 6 is conductive and is electrically connected to the terminal TE of the common potential among the multiple terminals TE shown in FIG. 1.

[0027] The sub-pixels SP1, SP2, and SP3 include display elements DE1, DE2, and DE3, respectively, as the display element DE.

[0028] The display element DE1 of the subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each of which overlaps with the aperture AP1. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 are surrounded by a partition wall 6 in a planar view. The peripheral portions of the lower electrode LE1, the organic layer OR1, and the upper electrode UE1 overlap with the insulating layer 5 in a planar view.

[0029] The display element DE2 of the subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each of which overlaps with the opening AP2. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 are surrounded by a partition wall 6 in a planar view. The peripheral portions of the lower electrode LE2, the organic layer OR2, and the upper electrode UE2 overlap with the insulating layer 5 in a planar view.

[0030] The display element DE3 of the subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each of which overlaps with the aperture AP3. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 are surrounded by a partition wall 6 in a planar view. The peripheral portions of the lower electrode LE3, the organic layer OR3, and the upper electrode UE3 overlap with the insulating layer 5 in a planar view.

[0031] In the illustrated example, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dashed lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed lines. Note that the outlines of the lower electrodes, organic layers, and upper electrodes illustrated in the drawings do not necessarily reflect the exact shapes.

[0032] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anodes of the display elements. The upper electrodes UE1, UE2, and UE3 correspond to the cathodes of the display elements or a common electrode, and are in contact with the partition walls 6.

[0033] In the illustrated example, the areas of the openings AP1, AP2, and AP3 are different from one another. The area of ​​the openings AP1 is larger than the area of ​​the openings AP2, and the area of ​​the openings AP2 is larger than the area of ​​the openings AP3. In other words, the area of ​​the lower electrode LE1 exposed from the opening AP1 is larger than the area of ​​the lower electrode LE2 exposed from the opening AP2, and the area of ​​the lower electrode LE2 exposed from the opening AP2 is larger than the area of ​​the lower electrode LE3 exposed from the opening AP3.

[0034] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG.

[0035] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in Fig. 1, and various wirings such as the scanning line GL, the signal line SL, and the power supply line PL. The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 is an organic insulating layer that flattens unevenness caused by the circuit layer 11.

[0036] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12 and are spaced apart from each other. The insulating layer 5 is an inorganic insulating layer and is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. An opening AP1 in the insulating layer 5 overlaps the lower electrode LE1, an opening AP2 overlaps the lower electrode LE2, and an opening AP3 overlaps the lower electrode LE3. The peripheries of the lower electrodes LE1, LE2, and LE3 are covered with the insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the subpixels SP1, SP2, and SP3 through contact holes provided in the insulating layer 12. The contact holes in the insulating layer 12 are omitted in FIG. 3.

[0037] The partition 6 includes a conductive lower portion 61 disposed on the insulating layer 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. Both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition 6 is called an overhang shape.

[0038] In the illustrated example, the lower portion 61 has a first conductive layer 63 disposed on the insulating layer 5 and a second conductive layer 64 disposed on the first conductive layer 63. For example, the first conductive layer 63 is formed to be thinner than the second conductive layer 64. In addition, in the illustrated example, both ends of the first conductive layer 63 protrude from the side surfaces of the second conductive layer 64. The upper portion 62 has a first thin film 65 disposed on the second conductive layer 64 and a second thin film 66 disposed on the first thin film 65. Both end portions of the first thin film 65 and the second thin film 66 protrude from the side surfaces of the second conductive layer 64.

[0039] The organic layer OR1 is in contact with the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed from the opening AP1, and has a peripheral portion located on the insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower portion 61.

[0040] The organic layer OR2 is in contact with the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed from the opening AP2, and has a peripheral portion located on the insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower portion 61.

[0041] The organic layer OR3 is in contact with the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed from the opening AP3, and has a peripheral portion located on the insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower portion 61.

[0042] In the illustrated example, subpixel SP1 has a cap layer CP1 and a sealing layer SE1, subpixel SP2 has a cap layer CP2 and a sealing layer SE2, and subpixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively. The cap layers CP1, CP2, and CP3 may be omitted.

[0043] The cap layer CP1 is disposed on the upper electrode UE1. The cap layer CP2 is disposed on the upper electrode UE2. The cap layer CP3 is disposed on the upper electrode UE3.

[0044] The sealing layer SE1 is disposed on the cap layer CP1, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP1. The sealing layer SE2 is disposed on the cap layer CP2, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP2. The sealing layer SE3 is disposed on the cap layer CP3, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP3.

[0045] In the illustrated example, parts of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 are located on the partition wall 6 around the subpixel SP1. These parts are separated from parts of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 located in the aperture AP1 (parts constituting the display element DE1). Similarly, portions of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 are located on the partition 6 surrounding the subpixel SP2, and these portions are spaced apart from portions of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 that are located in the opening AP2 (portions that constitute the display element DE2). Similarly, portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 are located on the partition 6 surrounding the subpixel SP3, and these portions are spaced apart from portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 that are located in the opening AP3 (portions that constitute the display element DE3).

[0046] In the following description, a multilayer body including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 is referred to as a laminate film FL1, a multilayer body including an organic layer OR2, an upper electrode UE2, and a cap layer CP2 is referred to as a laminate film FL2, and a multilayer body including an organic layer OR3, an upper electrode UE3, and a cap layer CP3 is referred to as a laminate film FL3.

[0047] Ends of the sealing layers SE1, SE2, and SE3 and ends of the stacked films FL1, FL2, and FL3 are located on the partition wall 6. In the illustrated example, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP2 are spaced apart from the stacked film FL2 and the sealing layer SE2 on the partition wall 6. In addition, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP3 are spaced apart from the stacked film FL3 and the sealing layer SE3 on the partition wall 6.

[0048] The partition 6 and the sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. The resin layer 13 is covered with a sealing layer 14. The sealing layer 14 is covered with a resin layer 15.

[0049] The insulating layer 5, the sealing layers SE1, SE2, SE3, and the sealing layer 14 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0050] The lower portion 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The first conductive layer 63 is formed of a titanium-based material such as titanium or a titanium compound. The second conductive layer 64 is formed of a material different from the first conductive layer 63 and the upper portion 62, and is formed of an aluminum-based material such as aluminum or an aluminum compound.

[0051] The upper portion 62 of the partition wall 6 is formed of, for example, a conductive material, but may be formed of an insulating material. The first thin film 65 is formed of, for example, a titanium-based material such as titanium or a titanium compound. The second thin film 66 is formed of, for example, an oxide conductive material such as indium tin oxide (ITO).

[0052] The lower electrodes LE1, LE2, and LE3 are multilayer structures including a transparent layer made of an oxide conductive material such as indium tin oxide (ITO) and a reflective layer made of a metal material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer structures including a reflective layer between a pair of transparent layers. The lower transparent layer functions as an adhesive layer that adheres to the insulating layer 12.

[0053] The organic layer OR1 includes an emitting layer EM1. The organic layer OR2 includes an emitting layer EM2. The organic layer OR3 includes an emitting layer EM3. The emitting layers EM1, EM2, and EM3 are formed of different materials. In one example, the emitting layer EM1 is formed of a material that emits light in a blue wavelength range, the emitting layer EM2 is formed of a material that emits light in a green wavelength range, and the emitting layer EM3 is formed of a material that emits light in a red wavelength range. In addition, each of the organic layers OR1, OR2, and OR3 includes a plurality of functional layers, such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, an electron injection layer, and a charge generation layer.

[0054] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0055] The cap layers CP1, CP2, and CP3 are multilayer structures made up of a plurality of thin films, all of which are transparent and have different refractive indices.

[0056] The illustrated circuit layer 11, insulating layer 12, insulating layer 5, resin layer 13, resin layer 15, and sealing layer 14 are disposed across the display area DA and the peripheral area SA.

[0057] FIG. 4 is a diagram showing an example of the configuration of the display elements DE1 to DE3. In this example, the lower electrode corresponds to the anode, and the upper electrode corresponds to the cathode.

[0058] The display element DE1 includes an organic layer OR1 between a lower electrode LE1 and an upper electrode UE1. In the organic layer OR1, the hole injection layer HIL1, the hole transport layer HTL11, the electron blocking layer EBL11, the emitting layer (first emitting layer) EM11, the hole blocking layer HBL11, the n-type charge generating layer nCGL1, the p-type charge generating layer pCGL1, the hole transport layer HTL12, the electron blocking layer EBL12, the emitting layer (second emitting layer) EM12, the hole blocking layer HBL12, the electron transport layer ETL1, and the electron injection layer EIL1 are laminated in this order.

[0059] The hole transport layers HTL11 and HTL12 can be formed of the same material. The electron blocking layers EBL11 and EBL12 can be formed of the same material. The light emitting layers EM11 and EM12 can be formed of the same material. The hole blocking layers HBL11 and HBL12 can be formed of the same material. The n-type charge generating layer nCGL1 is a functional layer that supplies electrons to the light emitting layer EM11, and is a layer doped with a metal such as lithium or ytterbium. The p-type charge generating layer pCGL1 is a functional layer that supplies holes to the light emitting layer EM12, and is made of a HAT material or the like. The cap layer CP1 including the first transparent layer TL11 and the second transparent layer TL12 is disposed on the upper electrode UE1. The sealing layer SE1 is disposed on the second transparent layer TL12.

[0060] The display element DE2 includes an organic layer OR2 between a lower electrode LE2 and an upper electrode UE2. In the organic layer OR2, the hole injection layer HIL2, the hole transport layer HTL21, the electron blocking layer EBL21, the light-emitting layer EM21, the hole blocking layer HBL21, the n-type charge generation layer nCGL2, the p-type charge generation layer pCGL2, the hole transport layer HTL22, the electron blocking layer EBL22, the light-emitting layer EM22, the hole blocking layer HBL22, the electron transport layer ETL2, and the electron injection layer EIL2 are laminated in this order.

[0061] The hole transport layers HTL21 and HTL22 can be formed of the same material. In one example, the thickness T21 of the hole transport layer HTL21 can be different from the thickness T11 of the hole transport layer HTL11, and the thickness T22 of the hole transport layer HTL22 can be different from the thickness T12 of the hole transport layer HTL12. The electron blocking layers EBL21 and EBL22 can be formed of the same material. The light emitting layers EM21 and EM22 can be made of the same material, which is different from the material of the light emitting layers EM11 and EM12. The hole blocking layers HBL21 and HBL22 can be formed of the same material. The n-type charge generating layer nCGL2 is a functional layer that supplies electrons to the light emitting layer EM21. The p-type charge generating layer pCGL2 is a functional layer that supplies holes to the light emitting layer EM22. The cap layer CP2 including the first transparent layer TL21 and the second transparent layer TL22 is disposed on the upper electrode UE2. The sealing layer SE2 is disposed on the second transparent layer TL22.

[0062] The display element DE3 includes an organic layer OR3 between a lower electrode LE3 and an upper electrode UE3. In the organic layer OR3, the hole injection layer HIL3, the hole transport layer HTL31, the electron blocking layer EBL31, the light-emitting layer EM31, the hole blocking layer HBL31, the n-type charge generation layer nCGL3, the p-type charge generation layer pCGL3, the hole transport layer HTL32, the electron blocking layer EBL32, the light-emitting layer EM32, the hole blocking layer HBL32, the electron transport layer ETL3, and the electron injection layer EIL3 are stacked in this order.

[0063] The hole transport layers HTL31 and HTL32 can be formed of the same material. In one example, the thickness T31 of the hole transport layer HTL31 can be different from the thickness T11 and the thickness T21, and the thickness T32 of the hole transport layer HTL32 can be different from the thickness T12 and the thickness T22. The electron blocking layers EBL31 and EBL32 can be formed of the same material. The light-emitting layers EM31 and EM32 can be formed of the same material. The material of the light-emitting layers EM31 and EM32 is different from the material of the light-emitting layers EM11 and EM12, and different from the material of the light-emitting layers EM21 and EM22. The hole blocking layers HBL31 and HBL32 can be formed of the same material. The n-type charge generating layer nCGL3 is a functional layer that supplies electrons to the light emitting layer EM31. The p-type charge generating layer pCGL3 is a functional layer that supplies holes to the light emitting layer EM32. The cap layer CP3 including the first transparent layer TL31 and the second transparent layer TL32 is disposed on the upper electrode UE3. The sealing layer SE3 is disposed on the second transparent layer TL32.

[0064] In this specification, the configuration of the display elements DE1 to DE3 shown in Fig. 4 is referred to as a tandem configuration. Such a tandem configuration improves current efficiency compared to a single configuration in which the organic layer OR has one light-emitting layer. In other words, at the same current density, the tandem configuration can achieve higher brightness than the single configuration. In addition, because of the improved light-emitting efficiency, the tandem configuration can achieve a longer life than the single configuration at the same brightness.

[0065] FIG. 5 is a schematic cross-sectional view showing an example of the configuration of the organic layer OR.

[0066] Here, a description will be given of a common structure of the display elements DE1 to DE3 shown in Fig. 4. In the figure, the lower electrode LE corresponds to the lower electrodes LE1, LE2, and LE3, the opening AP corresponds to the openings AP1, AP2, and AP3, the organic layers OR correspond to OR1, OR2, and OR3, and the upper electrodes UE correspond to UE1, UE2, and UE3.

[0067] The organic layer OR includes a hole injection layer HIL, a first intermediate layer M1, a first charge generation layer CGL1, and a second intermediate layer M2. The first intermediate layer M1 includes a hole transport layer HTL, an electron blocking layer EBL, a first emitting layer EML1, and a hole blocking layer HBL. The first charge generation layer CGL1 includes an n-type charge generation layer nCGL and a p-type charge generation layer pCGL. The second intermediate layer M2 includes a hole transport layer HTL, an electron blocking layer EBL, a second emitting layer EML2, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL.

[0068] The hole injection layer HIL is in contact with the lower electrode LE at the opening AP, extends over the insulating layer 5, and is spaced apart from the partition wall 6. An end of the hole injection layer HIL is located on the insulating layer 5 and immediately below the upper portion 62.

[0069] The first intermediate layer M1 is disposed on the hole injection layer HIL. In the illustrated example, the first intermediate layer M1 covers the hole injection layer HIL. That is, the first intermediate layer M1 covers an end of the hole injection layer HIL and contacts the insulating layer 5 between the hole injection layer HIL and the partition 6. The end of the first intermediate layer M1 is located on the insulating layer 5 and directly below the upper portion 62. In the illustrated example, the first intermediate layer M1 is spaced apart from the partition 6.

[0070] The first charge generation layer CGL1 is disposed on the first intermediate layer M1. The first charge generation layer CGL1 is separated from the partition wall 6 and from the hole injection layer HIL. An end of the first charge generation layer CGL1 is located on the first intermediate layer M1 and directly below the upper portion 62.

[0071] The second intermediate layer M2 is disposed on the first charge generation layer CGL1. In the illustrated example, the second intermediate layer M2 covers the first intermediate layer M1 and the first charge generation layer CGL1. That is, the second intermediate layer M2 covers the end of the first charge generation layer CGL1 and is in contact with the first intermediate layer M1. Furthermore, the second intermediate layer M2 covers the end of the first intermediate layer M1 and is in contact with the insulating layer 5 between the hole injection layer HIL and the partition 6. The end of the second intermediate layer M2 is located on the insulating layer 5 and directly below the upper portion 62. In the illustrated example, the second intermediate layer M2 is spaced apart from the partition 6.

[0072] The upper electrode UE is disposed on the second intermediate layer M2. The upper electrode UE is spaced apart from the hole injection layer HIL and the first charge generation layer CGL1. In the illustrated example, the upper electrode UE covers the second intermediate layer M2. That is, the upper electrode UE covers the end of the second intermediate layer M2 and contacts the lower portion 61 of the partition wall 6. In the illustrated example, the second intermediate layer M2 is spaced apart from the partition wall 6, and the upper electrode UE contacts the insulating layer 5 between the second intermediate layer M2 and the first conductive layer 63.

[0073] In this way, the hole injection layer HIL is covered with the first intermediate layer M1 and is separated from the upper electrode UE, and the first charge generation layer CGL1 is covered with the second intermediate layer M2 and is separated from the upper electrode UE, and the hole injection layer HIL and the first charge generation layer CGL1 are separated from each other. This suppresses carrier leakage through the hole injection layer HIL and the first charge generation layer CGL1. This suppresses the disturbance of the carrier injection balance inside the display element, and the desired display performance can be achieved.

[0074] FIG. 6 is a cross-sectional view of the organic layer OR shown in FIG.

[0075] In the first intermediate layer M1, the hole transport layer HTL is disposed on the hole injection layer HIL and covers the entire hole transport layer HIL including its ends. The electron blocking layer EBL is disposed on the hole transport layer HTL and covers the entire hole transport layer HTL including its ends. The first emissive layer EML1 is disposed on the electron blocking layer EBL and covers the entire electron blocking layer EBL including its ends. The hole blocking layer HBL is disposed on the first emissive layer EML1 and covers the entire first emissive layer EML1 including its ends.

[0076] In the first charge generation layer CGL1, the n-type charge generation layer nCGL is disposed on the hole blocking layer HBL. The p-type charge generation layer pCGL is disposed on the n-type charge generation layer nCGL. In the illustrated example, the p-type charge generation layer pCGL covers the entire n-type charge generation layer nCGL including its ends.

[0077] In the second intermediate layer M2, the hole transport layer HTL is disposed on the p-type charge generation layer pCGL and covers the entire p-type charge generation layer pCGL including its ends. The electron blocking layer EBL is disposed on the hole transport layer HTL and covers the entire hole transport layer HTL including its ends. The second emitting layer EML2 is disposed on the electron blocking layer EBL and covers the entire electron blocking layer EBL including its ends. The hole blocking layer HBL is disposed on the second emitting layer EML2 and covers the entire second emitting layer EML2 including its ends. The electron transport layer ETL is disposed on the hole blocking layer HBL and covers the entire hole blocking layer HBL including its ends. The electron injection layer EIL is disposed on the electron transport layer ETL and covers the entire electron transport layer ETL including its ends.

[0078] The upper electrode UE covers the electron injection layer EIL. In the illustrated example, a first intermediate layer M1 and a second intermediate layer M2 are interposed between the upper electrode UE and the hole injection layer HIL. A second intermediate layer M2 is interposed between the upper electrode UE and the first charge generation layer CGL1. A first intermediate layer M1 is interposed between the hole injection layer HIL and the first charge generation layer CGL1. This ensures electrical insulation between the hole injection layer HIL, the first charge generation layer CGL1, and the upper electrode UE.

[0079] Next, another configuration example will be described.

[0080] FIG. 7 is a schematic cross-sectional view showing another example of the configuration of the organic layer OR.

[0081] The configuration example shown in Fig. 7 differs from the configuration example shown in Fig. 5 in that the organic layer OR has a second charge generation layer CGL2 and a third intermediate layer M3 between the second intermediate layer M2 and the upper electrode UE. The configurations of the first intermediate layer M1 and the first charge generation layer CGL1 are the same as those in the example shown in Fig. 5.

[0082] The second intermediate layer M2 includes a hole transport layer HTL, an electron blocking layer EBL, a second emitting layer EML2, and a hole blocking layer HBL. The second charge generation layer CGL2 includes an n-type charge generation layer nCGL and a p-type charge generation layer pCGL. The third intermediate layer M3 includes a hole transport layer HTL, an electron blocking layer EBL, a third emitting layer EML3, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL.

[0083] The hole injection layer HIL is in contact with the lower electrode LE at the opening AP, extends onto the insulating layer 5 , and is spaced apart from the partition wall 6 .

[0084] The first intermediate layer M1 is disposed on the hole injection layer HIL. In the illustrated example, the first intermediate layer M1 covers the hole injection layer HIL and is spaced apart from the partition wall 6.

[0085] The first charge generation layer CGL1 is disposed on the first intermediate layer M1 and is spaced apart from the partition wall 6 and the hole injection layer HIL.

[0086] The second intermediate layer M2 is disposed on the first charge generation layer CGL1. In the illustrated example, the second intermediate layer M2 covers the first intermediate layer M1 and the first charge generation layer CGL1 and is spaced apart from the partition wall 6.

[0087] The second charge generation layer CGL2 is disposed on the second intermediate layer M2. The second charge generation layer CGL2 is separated from the partition wall 6, the hole injection layer HIL, and the first charge generation layer CGL1. An end of the second charge generation layer CGL2 is located on the second intermediate layer M2 and directly below the upper portion 62.

[0088] The third intermediate layer M3 is disposed on the second charge generation layer CGL2. In the illustrated example, the third intermediate layer M3 covers the second intermediate layer M2 and the second charge generation layer CGL2. That is, the third intermediate layer M3 covers an end of the second charge generation layer CGL2 and is in contact with the second intermediate layer M2. Furthermore, the third intermediate layer M3 covers an end of the second intermediate layer M2 and is in contact with the insulating layer 5 between the hole injection layer HIL and the partition 6. The end of the third intermediate layer M3 is located on the insulating layer 5 and directly below the upper portion 62. In the illustrated example, the third intermediate layer M3 is spaced apart from the partition 6.

[0089] The upper electrode UE is disposed on the third intermediate layer M3. The upper electrode UE is separated from all of the hole injection layer HIL, the first charge generation layer CGL1, and the second charge generation layer CGL2. In the illustrated example, the upper electrode UE covers the third intermediate layer M3. That is, the upper electrode UE covers the end of the third intermediate layer M3 and contacts the lower portion 61 of the partition wall 6. In the illustrated example, the third intermediate layer M3 is separated from the partition wall 6, and the upper electrode UE contacts the insulating layer 5 between the third intermediate layer M3 and the first conductive layer 63.

[0090] FIG. 8 is a cross-sectional view of the organic layer OR shown in FIG.

[0091] In the first intermediate layer M1, the hole transport layer HTL is disposed on the hole injection layer HIL and covers the entire hole transport layer HIL including its ends. The electron blocking layer EBL is disposed on the hole transport layer HTL and covers the entire hole transport layer HTL including its ends. The first emissive layer EML1 is disposed on the electron blocking layer EBL and covers the entire electron blocking layer EBL including its ends. The hole blocking layer HBL is disposed on the first emissive layer EML1 and covers the entire first emissive layer EML1 including its ends.

[0092] In the first charge generation layer CGL1, the n-type charge generation layer nCGL is disposed on the hole blocking layer HBL. The p-type charge generation layer pCGL is disposed on the n-type charge generation layer nCGL. In the illustrated example, the p-type charge generation layer pCGL covers the entire n-type charge generation layer nCGL including its ends.

[0093] In the second intermediate layer M2, the hole transport layer HTL is disposed on the p-type charge generation layer pCGL and covers the entire p-type charge generation layer pCGL including its ends. The electron blocking layer EBL is disposed on the hole transport layer HTL and covers the entire hole transport layer HTL including its ends. The second emitting layer EML2 is disposed on the electron blocking layer EBL and covers the entire electron blocking layer EBL including its ends. The hole blocking layer HBL is disposed on the second emitting layer EML2 and covers the entire second emitting layer EML2 including its ends.

[0094] In the second charge generation layer CGL2, the n-type charge generation layer nCGL is disposed on the hole blocking layer HBL. The p-type charge generation layer pCGL is disposed on the n-type charge generation layer nCGL. In the illustrated example, the p-type charge generation layer pCGL covers the entire n-type charge generation layer nCGL including its ends.

[0095] In the third intermediate layer M3, the hole transport layer HTL is disposed on the p-type charge generation layer pCGL and covers the entire p-type charge generation layer pCGL including its ends. The electron blocking layer EBL is disposed on the hole transport layer HTL and covers the entire hole transport layer HTL including its ends. The third emitting layer EML3 is disposed on the electron blocking layer EBL and covers the entire electron blocking layer EBL including its ends. The hole blocking layer HBL is disposed on the third emitting layer EML3 and covers the entire third emitting layer EML3 including its ends. The electron transport layer ETL is disposed on the hole blocking layer HBL and covers the entire hole blocking layer HBL including its ends. The electron injection layer EIL is disposed on the electron transport layer ETL and covers the entire electron transport layer ETL including its ends.

[0096] The upper electrode UE covers the electron injection layer EIL. In the illustrated example, a first intermediate layer M1, a second intermediate layer M2, and a third intermediate layer M3 are interposed between the upper electrode UE and the hole injection layer HIL. A second intermediate layer M2 and a third intermediate layer M3 are interposed between the upper electrode UE and the first charge generation layer CGL1. A third intermediate layer M3 is interposed between the upper electrode UE and the second charge generation layer CGL2. A first intermediate layer M1 is interposed between the hole injection layer HIL and the first charge generation layer CGL1. A second intermediate layer M2 is interposed between the first charge generation layer CGL1 and the second charge generation layer CGL2.

[0097] This ensures electrical insulation between the hole injection layer HIL, the first charge generation layer CGL1, the second charge generation layer CGL2, and the upper electrode UE, thereby providing the same effects as those of the above configuration example.

[0098] In the examples shown in FIGS. 7 and 8, the tandem configuration in which the organic layer OR has three light-emitting layers has been described, but the organic layer OR may have four or more light-emitting layers.

[0099] Next, a method for manufacturing the display device DSP will be described. Note that in each drawing for explaining the manufacturing method, illustration of the part below the insulating layer 12 is omitted.

[0100] First, a circuit layer 11 and an insulating layer 12 are formed on a substrate 10 across the display area DA and the peripheral area SA, and then, as shown in FIG. 9, a lower electrode LE1 of subpixel SP1, a lower electrode LE2 of subpixel SP2, and a lower electrode LE3 of subpixel SP3 are formed on the insulating layer 12. Thereafter, an insulating layer 5 is formed to cover the periphery of the lower electrodes LE1, LE2, and LE3. The insulating layer 5 is made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. Thereafter, a partition wall 6 is formed having a lower portion 61 located on the insulating layer 5 and an upper portion 62 located on the lower portion 61. The first conductive layer 63 of the lower portion 61 and the upper portion 62 protrude from a side surface of the second conductive layer 64 of the lower portion 61. The first conductive layer 63 is formed of a conductive material such as a titanium-based material, and the second conductive layer 64 is formed of a conductive material such as an aluminum-based material. The step of forming the openings AP1, AP2, and AP3 in the insulating layer 5 may be performed before or after the partition wall 6 is formed.

[0101] Next, the display element DE1 is formed.

[0102] First, as shown in FIG. 10, a laminated film FL1 including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 is formed. The process of forming the laminated film FL1 includes a process of forming an organic layer OR1 that contacts the lower electrode LE1 at the opening AP1, a process of forming an upper electrode UE1 that covers the organic layer OR1 and contacts the lower portion 61 of the partition wall 6, and a process of forming a cap layer CP1 located on the upper electrode UE1. The process of forming the organic layer OR1 also includes a process of forming a hole injection layer, a hole transport layer, an electron blocking layer, a plurality of light-emitting layers, a hole blocking layer, an electron transport layer, an electron injection layer, an n-type charge generation layer, and a p-type charge generation layer. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are each formed by deposition using the partition wall 6 as a mask. The laminated film FL1 is divided into a plurality of parts by the overhanging partition wall 6. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are continuously formed while maintaining a vacuum environment.

[0103] Then, an inorganic insulating material is deposited to form a sealing layer SE1 on the laminated film FL1. The sealing layer SE1 is formed by CVD (Chemical Vapor Deposition). The sealing layer SE1 continuously covers each of the divided portions of the laminated film FL1 and the partition walls 6.

[0104] Here, the steps of forming each layer of the organic layer OR will be described in more detail.

[0105] FIG. 11 is a diagram for explaining the process of forming the hole injection layer HIL, the n-type charge generation layer nCGL, and the p-type charge generation layer pCGL.

[0106] The first deposition source ES1 is configured to emit a material at a first deposition angle θ1. Here, the deposition angle is the spread angle of the material emitted from the deposition source. The deposition angle can be controlled by the shape of the nozzle from which the material is emitted, the shield surrounding the nozzle, and the like.

[0107] Materials for forming the hole injection layer HIL, the n-type charge generation layer nCGL, and the p-type charge generation layer pCGL are emitted from a first deposition source ES1 set at a first deposition angle θ1 as shown in the figure. The first deposition angle θ1 is set to a relatively small angle.

[0108] Therefore, for example, when a material for forming the hole injection layer HIL is ejected from the first deposition source ES1, the ejected material is blocked by the upper portion 62 in the vicinity of the partition 6 and reaches a position directly below the upper portion 62 and away from the partition 6. As a result, the area of ​​the hole injection layer HIL formed inside the region surrounded by the partition 6 is relatively small. In addition, the areas of the n-type charge generation layer nCGL and the p-type charge generation layer pCGL inside the partition 6 are also relatively small.

[0109] FIG. 12 is a diagram illustrating the process of forming the first intermediate layer M1, the second intermediate layer M2, and the third intermediate layer M3.

[0110] The second deposition source ES2 is configured to emit material at a second deposition angle θ2. The second deposition angle θ2 is larger than the first deposition angle θ1 (θ1<θ2) shown in FIG. 11. The materials for forming the first intermediate layer M1, the second intermediate layer M2, and the third intermediate layer M3 are emitted from the second deposition source ES2 set at the second deposition angle θ2 as shown in the figure.

[0111] Therefore, for example, when a material for forming the hole transport layer of the first intermediate layer M1 is ejected from the second deposition source ES2, the ejected material reaches a position immediately below the upper portion 62 and close to the partition 6. As a result, the area of ​​the hole transport layer HTL formed inside the region surrounded by the partition 6 is relatively large. Also, inside the partition 6, the areas of the first intermediate layer M1 including the hole transport layer HTL, the second intermediate layer M2, and the third intermediate layer M3 are larger than the areas of the hole injection layer HIL, the n-type charge generation layer nCGL, and the p-type charge generation layer pCGL. Therefore, the hole injection layer HIL, the n-type charge generation layer nCGL, and the p-type charge generation layer pCGL are covered by at least one of the first intermediate layer M1, the second intermediate layer M2, and the third intermediate layer M3.

[0112] 13, a resist RS patterned into a predetermined shape is formed on the sealing layer SE1. The resist RS overlaps the subpixel SP1 and a part of the partition wall 6 around it.

[0113] 14, etching is performed using the resist RS as a mask to sequentially remove the sealing layer SE1 and stacked film FL1 exposed from the resist RS. In this etching, after removing the sealing layer SE1 exposed from the resist RS, the cap layer CP1 exposed from the sealing layer SE1 is removed, and further, after removing the upper electrode UE1 exposed from the cap layer CP1, the organic layer OR1 exposed from the upper electrode UE1 is removed. As a result, the lower electrode LE2 of the subpixel SP2 and the lower electrode LE3 of the subpixel SP3 are exposed. Thereafter, the resist RS is removed, thereby forming a display element DE1 in the subpixel SP1.

[0114] Next, as shown in FIG. 15, a display element DE2 is formed. The procedure for forming the display element DE2 is the same as that for forming the display element DE1. That is, an organic layer OR2 including an emitting layer EM2, an upper electrode UE2, and a cap layer CP2 are formed in this order on the lower electrode LE2 to form a laminated film FL2. Then, a sealing layer SE2 is formed on the laminated film FL2. Then, a resist is formed on the sealing layer SE2, and the sealing layer SE2, the cap layer CP2, the upper electrode UE2, and the organic layer OR2 are patterned by etching using the resist as a mask. After this patterning, the resist is removed. As a result, a display element DE2 is formed in the subpixel SP2, and the lower electrode LE3 of the subpixel SP3 is exposed.

[0115] Next, as shown in FIG. 16, a display element DE3 is formed. The procedure for forming the display element DE3 is the same as that for forming the display element DE1. That is, an organic layer OR3 including an emitting layer EM3, an upper electrode UE3, and a cap layer CP3 are formed in this order on the lower electrode LE3 to form a laminated film FL3. Then, a sealing layer SE3 is formed on the laminated film FL3. Then, a resist is formed on the sealing layer SE3, and the sealing layer SE3, the cap layer CP3, the upper electrode UE3, and the organic layer OR3 are patterned by etching using the resist as a mask. After this patterning, the resist is removed. As a result, a display element DE3 is formed in the subpixel SP3.

[0116] Thereafter, the resin layer 13, the sealing layer 14, and the resin layer 15 shown in Fig. 3 are formed in this order, thereby completing the display device DSP.

[0117] In the above manufacturing process, it is assumed that display element DE1 is formed first, then display element DE2 is formed, and finally display element DE3 is formed, but the order of formation of display elements DE1, DE2, and DE3 is not limited to this example.

[0118] As described above, according to the present embodiment, it is possible to provide a display device capable of suppressing deterioration of display performance and a manufacturing method thereof.

[0119] All display devices and manufacturing methods thereof that can be implemented by a person skilled in the art through appropriate design modifications based on the display device and manufacturing method thereof described above as embodiments of the present invention are within the scope of the present invention as long as they include the gist of the present invention.

[0120] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of the above-mentioned embodiment, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0121] Furthermore, with regard to other effects and advantages brought about by the aspects described in the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately thought up by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0122] DSP: Display device PNL: Display panel 10...Substrate 5...Insulating layer AP1, AP2, AP3...Openings 6...Bulkhead 61...Lower 62...Upper SP1, SP2, SP3...Subpixels DE1, DE2, DE3...Display element (organic EL element) LE1, LE2, LE3...lower electrode UE1, UE2, UE3...upper electrode OR1, OR2, OR3…Organic layer HIL: Hole injection layer CGL1: First charge generation layer CGL2: Second charge generation layer M1...First intermediate layer M2...Second intermediate layer M3...Third intermediate layer

Claims

1. A substrate; a lower electrode disposed above the substrate; an inorganic insulating layer covering a peripheral portion of the lower electrode; a partition wall having a conductive lower portion disposed on the inorganic insulating layer and an upper portion disposed on the lower portion and protruding from a side surface of the lower portion; an organic layer disposed on the lower electrode; an upper electrode disposed over the organic layer and in contact with the lower portion; the organic layer includes a hole injection layer spaced apart from the partition wall and in contact with the lower electrode, a first intermediate layer disposed on the hole injection layer and including a first light-emitting layer, a first charge generation layer spaced apart from the partition wall and disposed on the first intermediate layer, and a second intermediate layer disposed on the first charge generation layer and including a second light-emitting layer, the hole injection layer and the first charge generation layer are spaced apart from each other and from the upper electrode; Display device.

2. The first intermediate layer and the second intermediate layer are in contact with each other. The display device according to claim 1 .

3. an end portion of the first intermediate layer is covered with the second intermediate layer; The display device according to claim 2 .

4. the first intermediate layer covers an end portion of the hole injection layer and is in contact with the inorganic insulating layer between the hole injection layer and the partition wall; The display device according to claim 1 .

5. the first intermediate layer has a hole transport layer disposed on the hole injection layer, an electron blocking layer disposed on the hole transport layer, the first light emitting layer disposed on the electron blocking layer, and a hole blocking layer disposed on the first light emitting layer; The hole transport layer covers an end of the hole injection layer. The display device according to claim 4.

6. the first charge generation layer has an n-type charge generation layer disposed on the hole blocking layer and a p-type charge generation layer disposed on the n-type charge generation layer; The display device according to claim 5 .

7. the second intermediate layer covers an end portion of the first charge generating layer and is in contact with the inorganic insulating layer between the hole injection layer and the partition wall; The display device according to claim 1 .

8. the second intermediate layer has a hole transport layer disposed on the first charge generating layer, an electron blocking layer disposed on the hole transport layer, the second light emitting layer disposed on the electron blocking layer, a hole blocking layer disposed on the second light emitting layer, an electron transport layer disposed on the hole blocking layer, and an electron injection layer disposed on the electron transport layer; the hole transport layer covers an edge of the first charge generation layer; The display device according to claim 7.

9. The upper electrode covers the electron injection layer. The display device according to claim 8.

10. the organic layer further includes a second charge generating layer disposed on the second intermediate layer and spaced apart from the partition wall, and a third intermediate layer disposed on the second charge generating layer and including a third light emitting layer, the hole injection layer, the first charge generation layer, and the second charge generation layer are spaced apart from each other and from the upper electrode; The display device according to claim 1 .

11. the third intermediate layer covers an end portion of the second charge generating layer and is in contact with the inorganic insulating layer between the hole injection layer and the partition wall; The display device according to claim 10.

12. the third intermediate layer has a hole transport layer disposed on the second charge generation layer, an electron blocking layer disposed on the hole transport layer, the third light emitting layer disposed on the electron blocking layer, a hole blocking layer disposed on the third light emitting layer, an electron transport layer disposed on the hole blocking layer, and an electron injection layer disposed on the electron transport layer; the hole transport layer covers an end of the second charge generating layer; The display device according to claim 11.

13. The upper electrode covers the electron injection layer. The display device according to claim 12.

14. an end of the hole injection layer and an end of the first charge generation layer are located directly below the upper portion; The display device according to claim 1 .

15. A substrate; a lower electrode disposed above the substrate; an inorganic insulating layer covering a peripheral portion of the lower electrode; a partition wall having a conductive lower portion disposed on the inorganic insulating layer and an upper portion disposed on the lower portion and protruding from a side surface of the lower portion; an organic layer disposed on the lower electrode; an upper electrode disposed over the organic layer and in contact with the lower portion; the organic layer includes a hole injection layer spaced apart from the partition wall and in contact with the lower electrode, a first intermediate layer covering the hole injection layer and including a first light-emitting layer, a first charge generation layer spaced apart from the partition wall and disposed on the first intermediate layer, and a second intermediate layer covering the first intermediate layer and the first charge generation layer and including a second light-emitting layer. Display device.

16. the first intermediate layer includes a hole transport layer covering the hole injection layer, an electron blocking layer covering the hole transport layer, the first light emitting layer covering the electron blocking layer, and a hole blocking layer covering the first light emitting layer, the first charge generating layer is disposed on the hole blocking layer; The display device according to claim 15.

17. the second intermediate layer includes a hole transport layer covering the first charge generation layer, an electron blocking layer covering the hole transport layer, the second light emitting layer covering the electron blocking layer, a hole blocking layer covering the second light emitting layer, an electron transport layer covering the hole blocking layer, and an electron injection layer covering the electron transport layer, The upper electrode covers the electron injection layer. The display device according to claim 15.

18. forming a lower electrode above the substrate; forming an inorganic insulating layer covering a peripheral portion of the lower electrode; forming a partition wall having a lower portion located on the inorganic insulating layer and made of a conductive material, and an upper portion located on the lower portion and protruding from a side surface of the lower portion; performing deposition using the partition as a mask to form a laminated film including an organic layer and an upper electrode on the lower electrode; the organic layer includes a hole injection layer, a first intermediate layer including a first light-emitting layer, a first charge generation layer, and a second intermediate layer including a second light-emitting layer; each of the hole injection layer and the first charge generation layer is formed from a material ejected from a first deposition source at a first deposition angle by using the partition wall as a mask; each of the first intermediate layer and the second intermediate layer is formed of a material emitted from a second deposition source at a second deposition angle by using the partition wall as a mask; The second deposition angle is greater than the first deposition angle. A method for manufacturing a display device.

19. Furthermore, after forming the laminated film, forming a sealing layer covering the laminated film and the partition wall using an inorganic insulating material; The method for manufacturing the display device according to claim 18 .

20. Furthermore, after forming the sealing layer, forming a patterned resist on the sealing layer; performing etching using the resist as a mask to sequentially remove the sealing layer and the laminated film exposed from the resist; The method for manufacturing the display device according to claim 19 .

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