Semiconductor device

Abstract

To provide a semiconductor device comprising a configuration that can sufficiently reduce parasitic capacitance between wirings.SOLUTION: In a thin-film transistor of a bottom gate structure using a lamination of a first layer obtained by oxidizing a part or all of a metal thin-film, and an oxide semiconductor layer, an oxide insulating layer serving as a channel protection layer being in contact with a part of the oxide semiconductor layer overlapped with a gate electrode layer is formed. At formation of the insulating layer, the oxide insulating layer covering a peripheral edge part (including a lateral face) of the lamination of the oxide semiconductor layer is formed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This generally refers to electro-optical devices such as display devices, semiconductor circuits, and electronic devices. be. [Background technology]

[0003] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates with insulating surfaces have been used The technology of constructing thin film transistors (TFTs) is attracting attention. It is widely used in electronic devices such as C and electro-optical devices, especially in switching of image display devices. Metal oxides exist in a wide variety of forms and are used for a wide range of purposes. Indium oxide is a well-known material that is needed for applications such as liquid crystal displays. It is used as a transparent electrode material.

[0004] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin-film transistors that use metal oxides as channel formation regions and that exhibit excellent semiconductor properties are already known. (Patent Document 1 and Patent Document 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0006] When multiple thin film transistors are fabricated on an insulating surface, for example, gate wiring, source wiring, At the intersection, there is a gate wiring and a gate line having a different potential. An insulating layer is provided between the source wirings, and the insulating layer serves as a dielectric to form a capacitance. The capacitance is also called the parasitic capacitance between wirings, and there is a risk that the signal waveform may become distorted. A large amount of raw capacitance can slow down signal transmission.

[0007] In addition, an increase in parasitic capacitance can cause crosstalk, which is when electrical signals leak between wiring, and can also lead to increased power consumption. This leads to increased power.

[0008] In an active matrix display device, the signal wiring for supplying a video signal is If a large parasitic capacitance is formed between the wiring or the electrode, the display quality may be deteriorated. There is.

[0009] Furthermore, when miniaturizing circuits, the distance between wirings becomes narrower, and the parasitic capacitance between wirings increases. There is a risk of this happening.

[0010] One embodiment of the present invention provides a semiconductor device having a structure capable of sufficiently reducing parasitic capacitance between wirings. One of the goals of the project is to

[0011] In addition, when a driver circuit is formed on an insulating surface, the operation of a thin film transistor used in the driver circuit A faster speed is preferable.

[0012] For example, the channel length (L) of a thin-film transistor can be shortened or the channel width (W) can be widened. However, shortening the channel length reduces the switching characteristics, e.g. For example, the on / off ratio becomes smaller. Also, if the channel width W is widened, the thin-film transistor However, this increases the capacity load on the star itself.

[0013] Semiconductor device having thin film transistors with stable electrical characteristics even when the channel length is short One of our goals is to provide

[0014] In addition, when forming a plurality of different circuits on an insulating surface, for example, a pixel portion and a driver circuit may be formed on the same substrate. When formed on a substrate, the thin film transistor used in the pixel portion must have excellent switching characteristics. For example, a large on-off ratio is required, and the thin film transistors used in the drive circuits Fast operation speed is required. In particular, the higher the resolution of the display device, Since the time it takes to write a display image is shortened, the thin-film transistors used in the driver circuits operate faster. It is preferable to use speed.

[0015] A semiconductor device that creates multiple types of circuits by fabricating multiple types of thin-film transistor structures on the same substrate. An object of the present invention is to provide a method for manufacturing a semiconductor device. [Means for solving the problem]

[0016] After forming a metal thin film on an insulating surface, an oxide semiconductor layer thicker than the metal thin film is laminated. Then, a part or the whole of the metal thin film is oxidized by performing an oxidation treatment such as a heat treatment. A first layer formed by oxidizing a part or the whole of a metal thin film and an oxide semiconductor layer are stacked on a thin film transistor. It is used as the semiconductor layer of a transistor.

[0017] Specifically, when multiple types of thin film transistors are fabricated on the same substrate, at least one A first layer formed by oxidizing a part or all of a metal thin film as a semiconductor layer of the thin film transistor of A stack of a gate insulating film and an oxide semiconductor layer is used.

[0018] In addition, a stack of a first layer formed by oxidizing a part or the whole of a metal thin film and an oxide semiconductor layer is used. In a bottom-gate thin film transistor, a gate electrode layer and an oxide semiconductor layer overlap each other. An oxide insulating layer is formed on the upper surface of the channel to serve as a channel protection layer. An oxide insulating layer is formed to cover the periphery (including the side surface) of the stack of oxide semiconductor layers.

[0019] The oxide insulating layer covering the periphery (including the side surface) of the stack of the oxide semiconductor layer is a gate electrode layer and The distance from the wiring layers (source wiring layer, capacitance wiring layer, etc.) formed above or around it is large. This reduces parasitic capacitance.

[0020] The oxide insulating layer covers an end portion of the first layer obtained by oxidizing a part or all of the metal thin film, The leakage current can be reduced.

[0021] The oxide insulating layer that covers the periphery of the stack of oxide semiconductor layers is formed in the same process as the channel protection layer. Therefore, the parasitic capacitance can be reduced without increasing the number of processes.

[0022] In addition, the oxide insulating layer covering the periphery (including the side surface) of the stack of oxide semiconductor layers reduces parasitic capacitance. This can reduce distortion of the signal waveform.

[0023] In order to reduce parasitic capacitance, it is necessary to use an oxide insulating layer with a small dielectric constant as the insulating layer between the wiring. It is preferred to use a border material.

[0024] By providing an oxide insulating layer that covers the periphery (including the side surface) of the oxide semiconductor layer, the parasitic capacitance This reduces the amount of charge as much as possible, enabling high-speed operation of thin-film transistors. The use of fast thin-film transistors allows for greater circuit integration.

[0025] One embodiment of the present invention disclosed in this specification is a first thin film transistor and a second thin film transistor. The first thin film transistor has a first gate electrode through a first gate insulating layer. a first oxide semiconductor layer and a second oxide semiconductor layer overlapping the second thin film transistor; The transistor is a third oxide semiconductor layer overlapping the second gate electrode layer through the second gate insulating layer. The laminate of the first oxide semiconductor layer and the second oxide semiconductor layer covers the periphery and the side surface. a solenoid that is in contact with the oxide insulating layer and electrically connects to the second oxide semiconductor layer on the oxide insulating layer; The semiconductor device has a source electrode layer and a drain electrode layer.

[0026] As the metal thin film, a material that becomes a semiconductor by oxidation treatment, such as indium, zinc, tin, molybdenum, etc. It is preferable to use tungsten or benzene. A first oxide semiconductor layer is formed, and a second oxide semiconductor layer is formed thereon. The first oxide semiconductor layer has a lower electrical resistivity than the second oxide semiconductor layer. In addition, the first oxide semiconductor layer has a thickness of 100 nm to the gate electrode. The thin film transistor is placed on the side with the shortest distance and is in contact with at least the gate insulating film. By producing a thin film transistor with excellent electrical properties (e.g., field effect mobility, etc.), A transistor can be realized.

[0027] The above configuration solves at least one of the above problems.

[0028] In addition, one embodiment of the present invention for realizing the above structure is to form a gate electrode layer, forming a gate insulating layer on the layer; forming a metal thin film on the gate insulating layer; and forming an oxide layer on the metal thin film. After forming a semiconductor layer and dehydrating or dehydrogenating the oxide semiconductor layer, The insulating layer 14 is formed of a metal oxide semiconductor layer 15, which is a metal oxide semiconductor layer 16 and is formed of a metal oxide semiconductor layer 17. The insulating layer 14 is formed of a metal oxide semiconductor layer 17 and is formed of a metal oxide semiconductor layer 18. An oxide insulating layer is formed to cover the periphery and side surfaces of the oxide semiconductor layer, and the metal thin film is oxidized. A source electrode layer and a drain electrode layer are formed on the oxide insulating layer, Method for manufacturing semiconductor device in which a drain electrode layer and a protective insulating layer in contact with an oxide semiconductor layer are formed It is law.

[0029] The metal thin film is formed by using a sputtering method, a vacuum deposition method, a coating method, or the like. The thickness of the thin film is set to be greater than 0 nm and less than 10 nm, preferably greater than 3 nm. A laminate of metal thin films may be used, the total thickness of which is 10 nm or less. By oxidizing at least a part of the film, it is possible to function as a thin film transistor and to obtain switching characteristics. In other words, the source electrode is oxidized to a degree that shows The current flowing between the source and drain electrodes remains almost constant, or the current flowing between the source and drain electrodes remains constant. The metal thin film is oxidized so that the electrodes are not in a conductive state. The edges and sides of the metal thin film are oxidized so that the drain electrode is not in a conductive state. An oxide insulating layer is provided covering the

[0030] In addition, the first oxide semiconductor layer finally obtained (i.e., an oxide semiconductor layer obtained by oxidizing a metal thin film) The average total thickness of the first oxide semiconductor layer and the second oxide semiconductor layer is set to 3 nm or more and 30 nm or less.

[0031] The second oxide semiconductor layer preferably contains at least one of the same elements as the metal thin film. If the second oxide semiconductor layer contains at least one of the same elements as the metal thin film, the same edging can be achieved. The second oxide semiconductor layer and the metal thin film are etched in the same process using an etching solution and etching gas. Since the above-mentioned can be removed by the above-mentioned method, the number of steps can be reduced.

[0032] The oxidation treatment is a heat treatment in either an oxygen-containing atmosphere or a nitrogen atmosphere (20 The temperature range is from 0°C to 600°C. Even in a nitrogen atmosphere, the metal thin film can be formed by heat treatment. The oxygen in the oxide semiconductor layer (second oxide semiconductor layer) formed on and in contact with the metal thin film is In this case, the presence of the metal thin film attracts oxygen from the second oxide semiconductor layer. In addition, oxygen vacancy regions can be formed in the second oxide semiconductor layer. The existence of the metal thin film can be prevented not only by heat treatment in an atmosphere but also by heating in an atmosphere containing oxygen. Due to the presence of the oxygen, oxygen is extracted from the second oxide semiconductor layer, and oxygen vacancies are formed in the second oxide semiconductor layer. By forming an oxygen vacancy region in the second oxide semiconductor layer, This can improve the field effect mobility. In some cases, the heat treatment may cause the interface with an oxide semiconductor layer formed thereon to become unclear. However, the oxide semiconductor layer on the gate insulating layer side, i.e., the lower layer of the oxide semiconductor layer, and the oxide semiconductor layer The upper layer shows different electrical properties.

[0033] The second oxide semiconductor layer is, for example, InMO3(ZnO). m (m>0) A thin film is formed, and a thin film transistor is manufactured using the thin film as an oxide semiconductor layer. In addition, M is one metal element selected from Ga, Fe, Ni, Mn, and Co, or a plurality of metal elements. For example, M can be Ga, Ga and Ni, or Ga and F. In addition, the above-mentioned metal elements other than Ga, such as Ga, may be included in the above-mentioned oxide semiconductor. In addition to the metal elements contained as M, Fe, Ni and other transition metal elements are also contained as impurity elements. In the present specification, the term "InM" refers to a transition metal. O3(ZnO) m In the oxide semiconductor layer having a structure represented by (m>0), M is Ga. The oxide semiconductor with the structure containing In-Ga-Zn-O is called the In-Ga-Zn-O oxide semiconductor, and the thin film of In It is also called Ga-Zn-O type non-single crystal film.

[0034] In addition to the above, metal oxides that can be used for the oxide semiconductor layer include In-Sn-Zn-O In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn -Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In- Metal oxides of O, Sn-O, and Zn-O can be used. The oxide semiconductor layer made of such a material may contain silicon oxide.

[0035] Heat treatment is performed under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.). In this case, the oxide semiconductor layer becomes oxygen-deficient and has low resistance, that is, becomes N-type ( N - Then, an oxide insulating film is formed in contact with the oxide semiconductor layer, and a heat treatment is performed after the formation. By performing heat treatment, the oxide semiconductor layer is made into an oxygen-excess state, and the resistance is increased, i.e., I In addition, solid-phase oxidation is performed to place the oxide semiconductor layer in an oxygen-excess state. This allows us to obtain thin film transistors with good electrical characteristics and high reliability. It is therefore possible to manufacture and provide a semiconductor device having the above-mentioned characteristics.

[0036] Dehydration or dehydrogenation is performed using inert gases such as nitrogen or noble gases (argon, helium, etc.). Heating in an atmosphere at 400°C or higher but lower than the strain point of the substrate, preferably 420°C or higher and 570°C or lower Heat treatment is performed to reduce impurities such as moisture contained in the oxide semiconductor layer.

[0037] The oxide semiconductor layer that has been dehydrated or dehydrogenated is Even when TDS was measured up to 450°C for the layer, two peaks of water and at least 300 The heat treatment conditions are set so that a peak that appears around 100 °C is not detected. The TDS test showed that the thin-film transistor using the oxide semiconductor layer that was dehydrogenated or dehydrogenated had a thermal conductivity of 45 Even when measurements are taken down to 0°C, the water peak that appears around 300°C is not detected.

[0038] Then, the temperature is lowered from the heating temperature T at which the oxide semiconductor layer is dehydrated or dehydrogenated. When dehydrating or dehydrogenating, the same furnace is used to prevent exposure to air, and water or It is important to prevent hydrogen from re-entering the oxide semiconductor. The body layer is made low resistance, i.e., N-type (N - After that, the oxide semiconductor is made high-resistance and made I-type. When a thin-film transistor is fabricated using a conductor layer, the threshold voltage value of the thin-film transistor can be programmed. A so-called normally-off switching element can be realized. The transistor gate voltage forms a channel at a positive threshold voltage as close as possible to 0V. It is desirable for a semiconductor device (display device) to have a threshold voltage value of a thin film transistor. If the gate voltage is negative, current flows between the source and drain electrodes even if the gate voltage is 0V. In an active matrix display device, The electrical characteristics of the thin-film transistors that make up the circuit are important, and these electrical characteristics determine the performance of the display device. In particular, the threshold voltage (Vth) is an important electrical characteristic of thin-film transistors. Even if the field effect mobility is high, the threshold voltage is high, or the threshold voltage is If the threshold voltage is high, it is difficult to control the circuit. In the case of a thin-film transistor with a large absolute value of the threshold voltage, when the driving voltage is low, The n-channel type cannot perform its switching function and may become a load. In the case of thin film transistors, a channel is formed only when a positive voltage is applied to the gate. A transistor that allows a drain current to flow out of the channel is desirable. There are transistors in which a channel does not form, and transistors in which a channel forms even under negative voltage conditions and the drain current is A flowing transistor is not suitable as a thin film transistor for use in a circuit.

[0039] In addition, the gas atmosphere used to lower the temperature from T is different from the gas atmosphere used to raise the temperature to T. A gas atmosphere may be switched to, for example, air in the same furnace where dehydration or dehydrogenation was performed. The inside of the furnace is filled with high-purity oxygen gas or N2O gas, ultra-dry air (dew point Cooling is performed by filling the container with water at a temperature of -40°C or less, preferably -60°C or less.

[0040] The moisture content in the film is reduced by a heat treatment for dehydration or dehydrogenation, and then the film is Cool slowly (or cool) in an atmosphere that is not prone to dew (dew point is -40°C or less, preferably -60°C or less). The oxide semiconductor film is used to improve the electrical characteristics of thin film transistors and to facilitate mass production. This will realize thin-film transistors that are both reliable and high performance.

[0041] In this specification, the method is carried out under an inert gas atmosphere of nitrogen or a rare gas (argon, helium, etc.). This heat treatment is called a heat treatment for dehydration or dehydrogenation. Dehydrogenation does not only mean that hydrogen is released as H2 by the hydrogenation process, but also means that H For convenience, this process is referred to as dehydration or dehydrogenation, which also includes the elimination of OH and other groups.

[0042] Heat treatment is performed under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.). In this case, the oxide semiconductor layer becomes oxygen-deficient and has low resistance, that is, becomes N-type ( N - To make something (e.g., convert it into something new).

[0043] In addition, the drain electrode layer overlaps with the oxygen-deficient high-resistance drain region (HRD). A resistance drain region is also formed. The oxygen-deficient high-resistance source region (HRS) overlaps the layer. e Source region) is formed.

[0044] Specifically, the carrier concentration in the high-resistance drain region is 1×10 18 / cm 3 Within the above range and the carrier concentration in the channel formation region is at least (1×10 18 / cm 3 Less than The carrier concentration in this specification is calculated from Hall effect measurements at room temperature. This refers to the carrier concentration value measured.

[0045] Then, at least a part of the stack of the dehydrated or dehydrogenated oxide semiconductor layers is heated to 1000° C. in an oxygen-excess atmosphere. By making the semiconductor into a high resistance state, the semiconductor is made into an I-type semiconductor, thereby forming a channel forming region. As a treatment for bringing a stack of dehydrated or dehydrogenated oxide semiconductor layers into an oxygen-excess state, The present invention relates to a method for forming an oxide insulating film in contact with a stack of a dehydrated or dehydrogenated oxide semiconductor layer by a sputtering method. or heat treatment after the formation of an oxide insulating film, or heat treatment in an atmosphere containing oxygen, Or heating in an inert gas atmosphere and then cooling in an oxygen atmosphere, ultra-dry air (dew point This is carried out by a cooling treatment to a temperature of -40°C or lower, preferably -60°C or lower.

[0046] In addition, at least a part of the stack of the dehydrated or dehydrogenated oxide semiconductor layers (gate electrode layers In order to make the area (the area overlapping with the area) into a channel formation region, the selective oxygen excess is It is also possible to make it highly resistive, i.e., I-type.

[0047] This allows the fabrication of a semiconductor device having thin film transistors with good electrical characteristics and high reliability. It will be possible to provide such information.

[0048] Note that a high-resistance drain region is formed in the oxide semiconductor layer overlapping with the drain electrode layer. This makes it possible to improve the reliability of the drive circuit. By forming a resistive drain region, the drain electrode layer, the high-resistance drain region, and the channel It is possible to form a structure in which the conductivity can be changed stepwise over the formation region. Therefore, when the drain electrode layer is connected to a wiring that supplies a high power supply potential VDD, Even if a high electric field is applied between the drain electrode layer and the drain electrode layer, the high resistance drain region acts as a buffer. This prevents a local high electric field from being applied, improving the breakdown voltage of the transistor. can be done.

[0049] In addition, a high resistance drain electrode layer (and a source electrode layer) is formed in the oxide semiconductor layer overlapping the drain electrode layer (and the source electrode layer). By forming a drain region (and a high resistance source region), the transistor It is possible to reduce the leakage current in the channel forming region. By forming a region, the lead of the transistor flowing between the drain electrode layer and the source electrode layer The drain electrode layer, the high-resistance drain region on the drain electrode layer side, and the channel The order is the panel formation region, the high resistance source region on the source electrode layer side, and the source electrode layer. In the channel formation region, current flows from the high-resistance drain region on the drain electrode layer side to the channel region. The leakage current is induced by the gate insulating layer and the channel formation region, which have high resistance when the transistor is off. The back channel (a region away from the gate electrode layer) can be concentrated near the interface. It is possible to reduce leakage current in the channel forming region (part of the surface).

[0050] In addition, a high resistance source region overlapping the source electrode layer and a high resistance drain region overlapping the drain electrode layer are The gate region overlaps a part of the gate electrode layer via the gate insulating layer, depending on the width of the gate electrode layer. As a result, the electric field intensity in the vicinity of the end portion of the drain electrode layer can be more effectively reduced.

[0051] In addition to liquid crystal display devices, display devices having a driving circuit include light-emitting devices using light-emitting elements. display devices, and display devices also called electronic paper using electrophoretic display elements. .

[0052] In a light-emitting display device using a light-emitting element, a pixel portion has a plurality of thin film transistors. In the elemental portion, the gate electrode of a thin film transistor and the source wiring of another transistor, The light emitting device has a portion for connecting a drain wiring. In the driving circuit, the gate electrode of the thin film transistor and the source The semiconductor device has a portion for connecting a wiring or a drain wiring.

[0053] In addition, the manufacturing cost of the semiconductor device can be reduced by fabricating the matrix circuit and the driver circuit on the same substrate. The driving circuit includes a circuit that prioritizes high-speed operation, such as a logic circuit. For such a circuit, a thin film transistor using a stack of a first oxide semiconductor layer and a second oxide semiconductor layer is used. The other circuits are configured using a single layer of the third oxide semiconductor layer. This allows circuits that prioritize high-speed operation, such as logic circuits, to have different thin structures from other circuits. A membrane transistor can be arranged.

[0054] In addition, since thin-film transistors are easily damaged by static electricity, etc., For the line, a protection circuit for protecting the thin film transistor in the pixel area can be provided on the same substrate. The protection circuit is preferably formed using a nonlinear element using an oxide semiconductor layer. It is nice.

[0055] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of steps or stacking. In addition, the specific names used in this specification are not intended to identify the invention. This does not indicate the Effect of the Invention

[0056] A semiconductor device including a thin film transistor having excellent electrical characteristics using a stacked oxide semiconductor layer is provided. The periphery and side surfaces of the stacked oxide semiconductor layers are covered with an oxide insulating layer, and a leakage current is reduced. Note that the oxide semiconductor layer is not necessarily formed on the oxide insulating layer. is formed in the same process as the oxide insulating layer that functions as a channel protective layer.

[0057] In addition, a thin film transistor having a stacked oxide semiconductor layer and a single-layer oxide semiconductor Thin film transistors having conductor layers can be fabricated to configure a variety of types of circuits. [Brief description of the drawings]

[0058] [Figure 1] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of the present invention. [Diagram 2] 1A to 1C are cross-sectional views showing a process of one embodiment of the present invention. [Diagram 3] FIG. 1 is a cross-sectional view showing one embodiment of the present invention. [Figure 4] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of the present invention. [Diagram 5] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 6] FIG. 1 is a cross-sectional view showing one embodiment of the present invention. [Figure 7] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views showing a process of one embodiment of the present invention. [Figure 9] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 10] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 11]1A to 1C are diagrams illustrating a semiconductor device. [Figure 12] 1A and 1B are diagrams illustrating a pixel equivalent circuit of a semiconductor device. [Figure 13] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 14] FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 15] 1A and 1B are a diagram illustrating a configuration of a signal line driver circuit and a timing chart illustrating the operation of the signal line driver circuit. [Figure 16] FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 17] 1A and 1B are a diagram illustrating a configuration of a shift register and a timing chart illustrating the operation of the shift register; [Figure 18] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 19] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 20] FIG. 1 is an external view showing an example of an electronic book. [Figure 21] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 22] FIG. 1 is an external view showing an example of a gaming machine. [Figure 23] FIG. 1 is an external view showing an example of a portable computer and a mobile phone. [Figure 24] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 25] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 26] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 27] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 28] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 29] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 30] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 31] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 32] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 33] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 34] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 35] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 36] 1A to 1C are diagrams illustrating a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0059] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. It is understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should be interpreted as being limited to the following description of the embodiment. In the configuration described below, parts having the same parts or similar functions are not included. The same reference numerals are used in common between different drawings for the corresponding parts, and the repeated explanations will be omitted.

[0060] (Embodiment 1) In this embodiment mode, a semiconductor device and a manufacturing method thereof will be described with reference to FIGS. This will be explained with reference to FIG.

[0061] FIG. 1A is a plan view of a channel-protective thin film transistor 448 disposed in a pixel. FIG. 1B is a cross-sectional view taken along line D1-D2 in FIG. 1A and a cross-sectional view taken along line D5 in FIG. FIG. 1C is a cross-sectional view taken along line D3-D4 in FIG. 1A. It is a cross-sectional view. Note that Fig. 2(E) is the same as Fig. 1(B).

[0062] The thin film transistor 448 disposed in the pixel is a channel protection type (also called a channel stop type). A gate electrode layer 421 is formed on a substrate 400 having an insulating surface. a, a gate insulating layer 402, a stacked oxide semiconductor layer 442 including a channel formation region 423, The oxide insulating layer 426a serving as a channel protective layer, the source electrode layer 425a, and the drain electrode layer 426b are The thin film transistor 448 is covered with an oxide insulating layer 426. a, a protective insulating layer 403 in contact with the source electrode layer 425a and the drain electrode layer 425b, and A drain electrode 402 and a planarization insulating layer 404 are stacked on the planarization insulating layer 404. A pixel electrode layer 427 is provided in contact with the electrode layer 425b. are spiritually connected.

[0063] Note that the stacked oxide semiconductor layer 442 is formed by stacking a metal thin film and an oxide semiconductor layer, and then depositing a metal thin film on the oxide semiconductor layer. Since the thin film is oxidized, depending on the materials of the metal thin film and the oxide semiconductor layer, Since there are no boundaries, the boundaries of the layers are shown herein as dotted lines.

[0064] The thin film transistor 448 for the pixel has a high resistance source region 424a and a high resistance drain region 4 24b, and a stack of an oxide semiconductor layer 442 including a channel formation region 423. A high-resistance source region 424a is formed in contact with the lower surface of the electrode layer 425a. A high-resistance drain region 424b is formed in contact with the lower surface of the inner electrode layer 425b. The transistor 448 has a highly resistive drain region or a highly resistive source region even when a high electric field is applied. The region acts as a buffer to prevent localized high electric fields from being applied, improving the breakdown voltage of the transistor. It is as follows.

[0065] The channel formation region of the thin film transistor 448 arranged in the pixel is formed of the stacked oxide semiconductor layer. Among the oxide insulating layer 426a, which is a channel protection layer, the gate electrode layer 4 The thin film transistor 448 is formed by the oxide insulating layer 426a. In order to protect the source electrode layer 425a and the drain electrode layer 425b, etching is performed. This can prevent the oxide semiconductor layer 442 from being etched in the process.

[0066] In addition, the thin film transistor 448 is a light-transmitting thin film transistor having a high aperture ratio. In order to realize a display device having such a structure, the source electrode layer 425a and the drain electrode layer 425b are A conductive film having the following structure is used.

[0067] In addition, a gate electrode layer 421a of the thin film transistor 448 is also formed using a light-transmitting conductive film. .

[0068] In addition, in the pixel where the thin film transistor 448 is arranged, a pixel electrode layer 427 or other The electrode layer (capacitor electrode layer, etc.) and wiring layer (capacitor wiring layer, etc.) are transparent to visible light. By using a conductive film having such a structure, a display device having a high aperture ratio can be realized. The oxide insulating layer 426a is also preferably formed using a film that transmits visible light.

[0069] In addition, it is preferable that the metal thin film is oxidized to become a film having transparency to visible light. Since the thin film is as thin as 10 nm or less, it is transparent to visible light, although this depends on the material.

[0070] In this specification, a film that is transparent to visible light has a visible light transmittance of 75 to 100 %, and if the film is conductive, it is also called a transparent conductive film. Also, a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or other electrodes A conductive film that is semi-transparent to visible light is used as a metal oxide for the wiring layer and other wiring layers. Translucent to visible light means that the transmittance of visible light is 50 to 75%. .

[0071] In addition, in order to reduce parasitic capacitance, the gate wiring and source wiring cross each other. Between the gate electrode layer 421b and the source electrode layer 425a, a gate insulating layer 402 and an oxide insulating layer Note that the oxide insulating layer 426b overlaps with the channel formation region 423. The oxide insulating layer 426a and the oxide insulating layer 426b in a region that does not overlap with the channel formation region 423 are different from each other. Although different reference numerals are used, the layers are made of the same material and are formed in the same process.

[0072] 2A to 2E, a thin film transistor 448 and a wiring cross-connection are formed on the same substrate. The process of manufacturing the difference part will be explained. In addition to the pixel part, the thin film transistor of the driver circuit will also be They may be formed on the same substrate in the same process.

[0073] First, a light-transmitting conductive film is formed on a substrate 400 having an insulating surface, and then a first photo Gate electrode layers 421a and 421b are formed by a lithography process. The gate electrode layers 421a and 421b are made of the same material having a light-transmitting property and are formed by the same first photolithography. In addition, when forming not only the pixel section but also the driving circuit, In the case where a capacitance is required for the driving circuit, a capacitance wiring layer is also formed for the driving circuit. The resist mask may be formed by an inkjet method. When this is formed, no photomask is used, and therefore manufacturing costs can be reduced.

[0074] In addition to a glass substrate, the substrate 400 may be a ceramic substrate, a quartz substrate, or a sapphire substrate. Alternatively, a substrate made of an insulating material such as silicon dioxide may be used. Alternatively, a substrate made of a crystallized glass may be used. do.

[0075] In addition, an insulating film serving as a base film is provided between the substrate 400 and the gate electrode layers 421a and 421b. The undercoat film has a function of preventing diffusion of impurity elements from the substrate 400. A silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film is used. The insulating film can be formed by a laminate structure.

[0076] The gate electrode layers 421a and 421b are formed of a conductive material that transmits visible light, e.g. For example, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al -Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Metal oxides of Al-Zn-O, In-O, Sn-O, and Zn-O can be used. The thickness of the gate electrode layer 421 is appropriately selected within the range of 50 nm to 300 nm. The metal oxide film formation method used in a and 421b is the sputtering method or the vacuum deposition method (electron beam evaporation). The method is arc discharge ion plating or spraying. When using the target deposition method, a target containing SiO2 of 2% by weight or more and 10% by weight or less is used. The conductive film is then coated with SiOx (X>0) which inhibits crystallization. Suppresses crystallization during the heat treatment for dehydration or dehydrogenation in the process. It is preferred.

[0077] Next, the gate insulating layer 402 is formed over the gate electrode layers 421a and 421b.

[0078] The gate insulating layer 402 is a silicon oxide layer formed by using a plasma CVD method, a sputtering method, or the like. , a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer, For example, the deposition gas is SiH4, oxygen, and nitrogen. A silicon oxynitride layer may be formed by plasma CVD. The thickness is 100 nm to 500 nm. In the case of a multilayer structure, the thickness is, for example, 50 nm to 2 A first gate insulating layer having a thickness of 000 nm or less, and a second gate insulating layer having a thickness of 5 nm or more and 300 nm or less on the first gate insulating layer. The second gate insulating layer has a thickness of 1 m or less.

[0079] In this embodiment, a silicon nitride layer having a thickness of 200 nm or less is formed by plasma CVD. The insulating layer 402 is a thin film.

[0080] Then, on the gate insulating layer 402, indium, zinc, tin, molybdenum, or tungsten is In addition, a thin metal film such as tin is formed. In addition, an alloy thin film or a laminated film of these is used. The metal thin film can be formed by sputtering, vacuum deposition, or coating. Here, an indium film is formed by deposition, preferably to a thickness of more than 0 nm and not more than 10 nm. The metal thin film is formed to a thickness of 3 nm to 5 nm. The oxide has a lower electrical resistivity than the oxide semiconductor layer that is formed later on the metal thin film. Depending on the material of the metal thin film and the film forming conditions, the surface of the gate insulating layer 402 may be A state where a part of the gate insulating layer 402 is exposed, instead of a film covering the surface, e.g., metal clusters In some cases, metals are dispersed in clusters. However, if the oxide semiconductor is formed by the subsequent oxidation process, the electrochemical migration of the thin film transistor is not expected. In addition, when metals are dispersed in clusters, the metal and The material is not limited to the above-mentioned materials, but aluminum, copper, etc. can be used. By forming a thin metal film of indium, we aim to improve the electrical characteristics of thin film transistors. Good too.

[0081] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is formed on the metal thin film. Even if a heat treatment for dehydration or dehydrogenation is performed after the formation of the oxide semiconductor film, the oxide semiconductor film In order to make the oxide semiconductor amorphous, it is preferable to make the film thickness as thin as 50 nm or less. By making the thickness of the oxide semiconductor film thin, the oxide semiconductor layer is crystallized when it is heated after being formed. This can prevent the item from being put away.

[0082] The oxide semiconductor film is an In-Ga-Zn-O non-single crystal film, an In-Sn-Zn-O film, or an In -Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al- Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, S In this embodiment, an In-Ga-Zn The film is formed by sputtering using a -O-based oxide semiconductor target. The film is heated under a rare gas (typically argon) atmosphere, under oxygen atmosphere, or under a rare gas (typically The film can be formed by sputtering under an atmosphere of argon and oxygen. When using the sputtering method, a target containing 2% to 10% by weight of SiO2 is used. The oxide semiconductor film is then formed to contain SiOx (X>0), which inhibits crystallization, and the oxide semiconductor film is then processed in the following steps. In order to prevent crystallization during the heat treatment for dehydration or dehydrogenation, is preferred.

[0083] The oxide semiconductor is preferably an oxide semiconductor containing In, more preferably an oxide semiconductor containing In and In order to make the oxide semiconductor layer i-type (intrinsic), It is advantageous to carry out a hydrogenation or dehydrogenation step.

[0084] Here, an oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O 3:ZnO=1:1:1[mol ratio], In:Ga:Zn=1:1:0.5[at ratio]) The distance between the substrate and the target was 100 mm, the pressure was 0.2 Pa, and the direct current (DC) was Power supply 0.5kW, argon and oxygen (argon:oxygen = 30sccm:20sccm acid The film is formed in an atmosphere with a nitrogen flow rate of 40%). Note that if a pulsed direct current (DC) power supply is used, This is preferable because it reduces the damage and makes the film thickness distribution uniform. In this embodiment, the oxide semiconductor film is formed of an I A 20 nm thick film was deposited by sputtering using an n-Ga-Zn-O oxide semiconductor target. An In-Ga-Zn-O based non-single crystal film is formed.

[0085] There are two types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used for depositing insulating films, while the DC sputtering method is mainly used for depositing metal films. It is used in.

[0086] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of films in the same chamber. It is also possible to form a film by discharging two or more materials at the same time.

[0087] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There is a sputtering apparatus that uses this method.

[0088] In addition, in a film formation method using a sputtering method, a target material and a sputtering gas component are mixed during film formation. Reactive sputtering is a method of forming thin films of compounds by chemically reacting them with each other, and There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0089] Next, the metal thin film and the oxide semiconductor film are stacked in a second photolithography process to form an island-like The metal layer 428 and the island-shaped oxide semiconductor layer 429 are processed. A resist mask for forming the oxide semiconductor layer 429 was formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask is not required. This reduces manufacturing costs.

[0090] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400° C. or higher and lower than the distortion point of the substrate, preferably 425° C. or higher. If the temperature is 425℃ or higher, the heat treatment time can be 1 hour or less. The heat treatment time is longer than one hour. The substrate is placed in an electric furnace, and the oxide semiconductor layer is subjected to a heat treatment in a nitrogen atmosphere. After that, the oxide semiconductor layer is not exposed to the air, and water and hydrogen are prevented from re-mixing into the oxide semiconductor layer. A conductor layer 442 is obtained. In this embodiment, the oxide semiconductor layer is dehydrated or dehydrogenated. The same furnace is used to heat the material from the heating temperature T to a temperature that is high enough to prevent water from entering again. The temperature is gradually cooled in a nitrogen atmosphere until it drops by 100°C or more below the temperature T. Also, the nitrogen atmosphere is limited. Dehydration or dehydrogenation is performed under a rare gas atmosphere such as helium, neon, or argon. Do the following.

[0091] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to keep the concentration of the ion exchange resin at 0.1 ppm or less.

[0092] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized and microcrystalline. In some cases, the film may be a crystalline or polycrystalline film.

[0093] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, the substrate is removed from the heating device after the first heat treatment. The substrate is then taken out and subjected to a photolithography process.

[0094] Alternatively, the metal layer 428 may be oxidized by the first heat treatment to become an oxide semiconductor layer. In addition, the first heat treatment is not limited to oxidizing the metal layer 428. Apart from the treatment, an oxidation treatment may be performed to oxidize the metal layer 428, e.g. After the oxide insulating film is formed by a sputtering method, oxidation treatment may be performed.

[0095] Next, an oxide insulating film 44 is formed over the gate insulating layer 402 and the oxide semiconductor layer by a sputtering method. Form 6 (see FIG. 2(A)).

[0096] Next, a resist mask is formed by a third photolithography process and selectively etched. Then, oxide insulating layers 426a and 426b are formed by etching, and the resist mask is then removed. At this stage, a region in contact with the oxide insulating layer is formed in the oxide semiconductor layer of the stack. Among the regions, the oxide insulating layer 426a overlaps with the gate electrode layer through the gate insulating layer. The overlapping region is a channel formation region. A region overlapping with the oxide insulating layer 426b is also formed.

[0097] The oxide insulating film is at least 1 nm thick and is formed by an oxide insulating method such as a sputtering method. The film can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed into the film. In this embodiment, a silicon oxide film having a thickness of 300 nm is deposited as an oxide insulating film by sputtering. The substrate temperature during the film formation may be set to a temperature between room temperature and 300° C. in this embodiment. The temperature is set at room temperature. The deposition of silicon oxide film by sputtering method is carried out using rare gas (typically argon). In an atmosphere of rare gas (typically argon) and oxygen, or in an atmosphere of rare gas (typically argon) and oxygen The target may be a silicon oxide target or a silicon target. For example, a silicon target can be used under an oxygen and nitrogen atmosphere. A silicon oxide film can be formed by sputtering. The oxide insulating film formed in contact with the substrate is resistant to moisture, hydrogen ions, and OH - Contains impurities such as First, an inorganic insulating film is used to block these substances from entering from the outside, typically an oxide film. A silicon film, a silicon nitride oxide film, an aluminum oxide film, an aluminum oxide nitride film, or the like is used. do.

[0098] Next, a second heat treatment (preferably The temperature is 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower (see FIG. 2(B)). For example, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. As a result of the treatment, an end portion of the oxide semiconductor layer 442 overlapping with the oxide insulating layer 426b and an end portion of the oxide semiconductor layer 442 overlapping with the oxide insulating layer 426c are A part of the oxide semiconductor layer 442 overlapping the edge layer 426a is heated in a state where the part is in contact with the oxide insulating layer. Note that when the second heat treatment is performed, the oxide semiconductor layer in the stack that does not overlap with the oxide insulating layer is removed. The oxide semiconductor layer 442 is heated in an exposed state. When heat treatment is performed under a nitrogen or inert gas atmosphere in this state, the oxide semiconductor layer 4 In the embodiment, the exposed high resistance (I-type) region in 42 can be made low resistance. The oxide insulating layer 426a can be formed in a channel formation region of the stacked oxide semiconductor layer 442. The layer is provided on and in contact with the region and functions as a channel protection layer.

[0099] Next, the gate insulating layer 402, the oxide insulating layers 426a and 426b, and the stacked oxide semiconductor After forming a light-transmitting conductive film on the conductive layer 442, a fourth photolithography process is performed. A resist mask is formed and selectively etched to form the source electrode layer 425a and The drain electrode layer 425b is formed (see FIG. 2C). The deposition methods include sputtering, vacuum deposition (electron beam deposition, etc.), and arc discharge ion plating. The conductive film is made of a material that is transparent to visible light. Conductive materials such as In-Sn-Zn-O, In-Al-Zn-O, Sn-Ga-Z nO system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn -Zn-O, Al-Zn-O, In-O, Sn-O, and Zn-O metal oxides The thickness of the film is appropriately selected within the range of 50 nm to 300 nm. When using a sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used. The conductive film is then formed by adding SiOx (X>0) which inhibits crystallization. It is preferable to suppress crystallization during a heat treatment carried out in a later step.

[0100] Note that a resist mask for forming the source electrode layer 425a and the drain electrode layer 425b is used. The resist mask may be formed by an inkjet method. Since no photomask is used, manufacturing costs can be reduced.

[0101] Next, the oxide insulating layers 426a and 426b, the source electrode layer 425a, and the drain electrode layer 42 A protective insulating layer 403 is formed on the insulating film 5b. In this embodiment, a nitriding method is used. The RF sputtering method is suitable for mass production, and is therefore used as a method for forming the protective insulating layer 403. The protective insulating layer 403 is preferably formed of a material that is resistant to moisture, hydrogen ions, and OH ions. - Contains impurities such as First, inorganic insulating films are used to block these substances from entering from the outside, and silicon nitride films and nitride films are used. Aluminum nitride film, silicon nitride oxide film, aluminum oxynitride film, etc. are used. The edge layer 403 is a light-transmitting insulating film.

[0102] Next, a planarization insulating layer 404 is formed over the protective insulating layer 403. Examples of such materials include polyimide, acrylic resin, benzocyclobutene resin, polyamide, and epoxy. In addition to the above organic materials, organic materials having heat resistance such as fluororesin can be used. Low dielectric constant materials (low-k materials), siloxane resins, PSG (phosphorus glass), BPSG (phosphorus boron glass) and the like can be used. Note that insulating films formed from these materials can be used. The planarization insulating layer 404 may be formed by stacking a plurality of layers.

[0103] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, the organic group may have a fluoro group. That's fine.

[0104] The method for forming the planarization insulating layer 404 is not particularly limited. Depending on the material, it may be a sputtering method, a SO G method, spin coating, dip, spray coating, droplet ejection method (inkjet method, screen Printing methods such as doctor knife, roll contact, etc. can be used. The coating can be performed using a coater, curtain coater, knife coater, or the like.

[0105] Next, a fifth photolithography step is performed to form a resist mask, and a planarization insulating layer 4 04, and the protective insulating layer 403 is etched to form a contact that reaches the drain electrode layer 425b. Then, a hole 441 is formed and the resist mask is removed (see FIG. 2(D)). As shown in FIG. 1, an oxide insulating layer 426b is provided below the contact hole. The amount of planarizing insulation removed is smaller than when there is no oxide insulating layer below the contact hole. The thickness of the edge layer can be made thin, and the etching time can be shortened. The depth of the contact hole 441 is smaller than that in the case where no oxide insulating layer is provided below the contact hole. In the region overlapping with the contact hole 441, In addition, the coverage of the light-transmitting conductive film can be improved. A contact hole reaching the gate electrode layer 421b is also formed by this etching. A resist mask for forming a contact hole reaching the drain electrode layer 425b is then applied. If the resist mask is formed by the inkjet method, the photoresist can be formed by the inkjet method. Since no mask is used, manufacturing costs can be reduced.

[0106] Next, a light-transmitting conductive film is formed. Indium (In2O3) and indium oxide tin oxide alloy (In2O3-SnO2, IT The conductive film is formed by sputtering or vacuum deposition. As another material for the conductive film, there is a nitrogen-containing Al-Zn-O-based non-single crystal film, i.e. Al-Zn- ON-based non-single crystal film, Zn-ON-based non-single crystal film, Sn-Zn-ON-based non-single crystal film The composition ratio (atomic %) of zinc in the Al-Zn-ON non-single crystal film is as follows: The composition ratio (atomic %) of aluminum in the non-single crystal film is 47 atomic % or less, and is larger than that in the non-single crystal film. The composition ratio (atomic %) of aluminum in the crystalline film is the same as the composition ratio (atomic %) of nitrogen in the non-single crystalline film. Etching of such materials is carried out with solutions based on hydrochloric acid. ITO etching tends to leave residues, so we used an oxidizer to improve the etching process. An indium zinc oxide alloy (In2O3-ZnO) may also be used.

[0107] The composition ratio of the light-transmitting conductive film is expressed in atomic percent. (EPMA:Electron Probe X-ray MicroAnalyzer ) will be used for the evaluation.

[0108] Next, a sixth photolithography process is performed to form a resist mask and to form a Then, unnecessary portions are removed to form a pixel electrode layer 427, and the resist mask is removed (FIG. 2( See E). ).

[0109] Through the above steps, a thin film transistor 448 and a side It is possible to fabricate wiring intersections with reduced parasitic capacitance. 8 is a high-resistance source region 424a, a high-resistance drain region 424b, and a channel forming region 423 and the oxide semiconductor layer 442. Therefore, the thin film transistor 448 has a high resistance drain region 424 even when a high electric field is applied. b or the high resistance source region 424a acts as a buffer to prevent a local high electric field from being applied, This configuration improves the withstand voltage of the transistor.

[0110] In addition, the storage capacitor formed by the capacitance wiring layer and the capacitance electrode with the gate insulating layer 402 as a dielectric is The thin film transistor 448 and the storage capacitor can be formed on the same substrate. The corresponding pixels are arranged in a matrix to form an active matrix display device. For the sake of convenience, this specification refers to such a substrate as an This is called an active matrix substrate.

[0111] In addition, a thin film transistor of a driver circuit can be provided on the same substrate. By forming a driving circuit and a pixel section, connection wiring for external signals input to the driving circuit This allows the semiconductor device to be made smaller and at a lower cost.

[0112] In addition, the oxide semiconductor layer 442 of the stack of the thin film transistor 448 for a pixel shown in FIG. The insulating layer 426b is overlapped with a first region 424c and a second region 424d at the periphery. The first region 424c, which is a peripheral portion of the stacked oxide semiconductor layer 442, and the second region 4 The region 24d is in the same oxygen-rich state as the channel formation region 423, and has a structure with a different potential nearby. When a wire or a stacked oxide semiconductor layer is arranged, leakage current and parasitic capacitance are reduced. It can be realized.

[0113] In addition, by providing the oxide insulating layer 426b, even if the metal thin film is not oxidized, The structure covers the sides of the metal thin film even when the source electrode layer and drain electrode layer are short-circuited. It is as follows.

[0114] In particular, in the driver circuit, the distance between multiple wirings and multiple oxide semiconductor layers is increased in order to achieve high integration. It is preferable that the first region 424c is narrowed by overlapping with the oxide insulating layer 426b. It is effective to provide the second region 424d to reduce leakage current and parasitic capacitance. In addition, when multiple thin film transistors are arranged in series or in parallel, The oxide semiconductor layer of the transistor is treated as an island, and each element is isolated by oxide insulation. A region overlapping with the oxide insulating layer 426b is used as an element isolation region. In this way, it is possible to arrange multiple thin film transistors in a small area. Therefore, the driver circuit can be highly integrated.

[0115] (Embodiment 2) In this embodiment mode, a pixel is formed on the same substrate using the thin film transistor described in Embodiment Mode 1. This shows an example in which a pixel portion and a driver circuit are formed to manufacture an active matrix type liquid crystal display device.

[0116] FIG. 3A shows an example of a cross-sectional structure of an active matrix substrate.

[0117] In the first embodiment, the thin film transistors and the wiring intersections of the pixel portion are illustrated. In this embodiment, in addition to the thin-film transistors and wiring intersections, the thin-film transistors of the drive circuits and the storage capacitors are The capacitor, gate wiring, and source wiring terminals are also illustrated and described. The terminal portion of the line can be formed by the same manufacturing process as that shown in Embodiment 1. In the display area of ​​the pixel section, the gate wiring, source wiring, and capacitance wiring layer are all The insulating film is formed of a light-transmitting conductive film, and a high aperture ratio is achieved.

[0118] In FIG. 3A, a thin film transistor 220 electrically connected to a pixel electrode layer 227 is A channel protection type thin film transistor is provided in a pixel portion. The thin film transistor 220 has the same structure as the thin film transistor 448 of the first embodiment. The width of the gate electrode layer in the channel length direction is equal to the width of the oxide semiconductor layer of the thin film transistor 220. Narrower than the width in the longitudinal direction of the panel.

[0119] A layer formed of the same material and process as the gate electrode layer of the thin film transistor 220. The capacitor wiring layer 230 is connected to the capacitor electrode 231 via the gate insulating layer 202 which serves as a dielectric. The capacitor electrode 231 is connected to the source of the thin film transistor 220. The second electrode layer is formed of the same light-transmitting material and in the same process as the source electrode layer or the drain electrode layer. Therefore, in addition to the thin film transistor 220 having a light transmitting property, each storage capacitor Since the transparent insulating film 10 also has light transmitting properties, the aperture ratio can be improved.

[0120] It is important for the storage capacitor to have light transmittance in order to improve the aperture ratio. In the following small LCD panels, the number of gate wirings is increased to improve the resolution of the displayed image. Even if the pixel size is reduced to achieve high resolution, a high aperture ratio can be achieved. By using a film having light transmitting properties as the constituent members of the thin film transistor 220 and the storage capacitor, To achieve a wide viewing angle, a high aperture ratio is achieved even when one pixel is divided into multiple sub-pixels. That is, even if a high density group of thin film transistors is arranged, a large aperture ratio can be obtained. For example, two to four pixels can be arranged in one pixel, and a sufficient area can be secured for the display area. When the device has four sub-pixels and a storage capacitor, the thin film transistor is transparent. In addition, each storage capacitor is transparent, so that the aperture ratio can be improved. do.

[0121] The storage capacitor is provided below the pixel electrode layer 227, and the capacitor electrode 231 is disposed below the pixel electrode layer 227. 27.

[0122] In this embodiment, a storage capacitor is formed using a capacitor electrode 231 and a capacitor wiring layer 230. However, the structure for forming the storage capacitor is not particularly limited. For example, The pixel electrode layer is not provided with a gate wiring of an adjacent pixel, a planarizing insulating layer, a protective insulating layer, and A storage capacitor may be formed by overlapping with a gate insulating layer interposed therebetween.

[0123] In addition, in FIG. 3A, the storage capacitor has a large capacitance, so the capacitance wiring and the capacitance electrode Only the gate insulating layer 202 is provided between the wirings, and the wiring intersections are provided with a gate insulating layer 202 to reduce parasitic capacitance. Between the gate electrode layer 421b and the wiring formed thereon, the gate insulating layer 202 and the oxide insulating layer 203 are formed. In the storage capacitor, a gate insulating layer is provided between the capacitor wiring and the capacitor electrode. In the case where only the oxide insulating layer 202 is used, the oxide insulating layer 266b is selectively removed by etching. Select the etching conditions or the material of the gate insulating layer so as to leave only the gate insulating layer 202. In this embodiment, the oxide insulating layer 266b is a silicon oxide film obtained by a sputtering method, and the gate Since the insulating layer 202 is a silicon nitride film obtained by the plasma CVD method, it can be selectively removed. Note that the oxide insulating layer 266b and the gate insulating layer 202 can be etched under the same etching conditions. When a removable material is used, a part of the gate insulating layer is thinned by etching. It is preferable that the thickness of the gate insulating layer is set so that at least the gate insulating layer remains and a capacitance can be formed. In order to increase the storage capacitance, it is preferable to reduce the thickness of the gate insulating layer. Therefore, the gate insulating layer on the capacitance wiring is thinned during the selective etching of the oxide insulating layer 266b. It may also be configured in such a manner that the

[0124] The thin film transistor 260 is a channel protection type thin film transistor provided in the driving circuit. The channel length L is shorter than that of the thin film transistor 220, and the operating speed is increased. The channel length of a channel protection type thin film transistor provided in the driver circuit is It is preferable that L is set to 0.1 μm or more and 2 μm or less. The width of the gate electrode layer 261 in the channel length direction is equal to the width of the channel of the oxide semiconductor layer of the thin film transistor 260. The end face of the gate electrode layer 261 is in contact with the gate insulating layer 202 and the oxide layer 203. The source electrode layer 265a or the drain electrode layer 265b is overlapped with the insulating layer 266b therebetween. .

[0125] In addition, the thin film transistor 260 is formed by forming an oxide semiconductor film after removing the metal thin film. The oxide semiconductor layer is a single layer, and the thickness of the oxide semiconductor layer is thinner than that of the thin film transistor 220. The oxide semiconductor layer of the thin film transistor 260 is In the case of a single layer, the metal thin film is selectively etched, so the acid of the thin film transistor 260 is Compared to the case where the compound semiconductor layers are laminated, the number of photomasks increases by one.

[0126] The thin film transistor 260 is formed by forming a gate electrode layer 261, a gate The source insulating layer 202, at least the channel forming region 263, the high resistance source region 264a, and and a high-resistance drain region 264b, a source electrode layer 265a, and a drain The drain electrode layer 265b is also formed on the oxide insulating layer 26 6a is provided.

[0127] In addition, the gate electrode layer of the thin film transistor 260 of the driving circuit is provided above the oxide semiconductor layer. In this case, the thin film transistor 264 may be electrically connected to the conductive layer 267. A contact for electrically connecting the drain electrode layer of the transistor 220 and the pixel electrode layer 227. Using the same photomask as the tact hole, the planarization insulating layer 204, the protective insulating layer 203, and the oxide The insulating layer 266b and the gate insulating layer 202 are selectively etched to form contact holes. Through this contact hole, the conductive layer 267 and the thin film transistor 26 of the driving circuit are 0 and gate electrode layer 261 are electrically connected.

[0128] The protective insulating layer 203 is made of an inorganic insulating film, such as a silicon nitride film, an aluminum nitride film, or a silicon nitride oxide film. A film made of aluminum oxynitride or the like is used. In this embodiment mode, a silicon nitride film is used.

[0129] In the thin film transistor 260, the width of the gate electrode layer 261 is smaller than the width of the oxide semiconductor layer. The oxide insulating layer 266b overlaps with a periphery of the oxide semiconductor layer. The oxide insulating layer 266b overlaps the gate electrode layer 261. The distance between the drain electrode layer 265b and the gate electrode layer 261 is increased, and This serves to reduce the parasitic capacitance formed between the oxide layer 261 and the gate electrode layer 262. The first region 264c and the second region 264d of the oxide semiconductor layer overlapping the oxide insulating layer 266b are The oxygen-rich state is the same as that of the channel formation region 263, and this reduces leakage current and parasitic capacitance. It also has a reducing function.

[0130] In addition, the size of LCD panels has exceeded 10 inches, reaching 60 inches and even 120 inches. In this case, the wiring resistance of the light-transmitting wiring may become a problem. It is preferable to use metal wiring to reduce wiring resistance. For example, as shown in FIG. The source electrode layer 265a and the drain electrode layer 265b are made of metal wiring (metal electrodes) such as Ti. do.

[0131] In this case, a metal electrode such as Ti is placed on the dehydrated or dehydrogenated oxide semiconductor layer. A source electrode layer and a drain electrode layer are formed, and a high resistance source region overlapping the source electrode layer is formed. A high-resistance drain region overlapping the drain electrode layer is formed, and a high-resistance source region and a high-resistance The region between the drain region becomes a channel forming region.

[0132] In order to reduce the wiring resistance, as shown in FIG. 3A, the source electrode layer 265a and the drain Auxiliary electrode layers 268a and 268b using metal electrodes with lower resistance are formed on the main electrode layer 265b. In this case, metal wiring (metal electrodes) is also formed, so that the process is more efficient than that of the first embodiment. The number of photomasks increases by one.

[0133] Source electrode layer 265a, drain electrode layer 265b, auxiliary electrode layers 268a, 268b, thin film The source electrode layer and the drain electrode layer of the transistor 220 are formed of a light-transmitting conductive film and a gold film. The metal conductive film is laminated and selectively etched by a photolithography process. The metal conductive film on the source electrode layer and the drain electrode layer of the film transistor 220 is removed.

[0134] During etching of the metal conductive film, the source electrode layer and the drain electrode layer of the thin film transistor 220 are The materials and etching conditions are appropriately adjusted so that the inner electrode layer is not removed.

[0135] For example, an alkaline etchant is used to selectively etch a metal conductive film. The material of the metal conductive film is selected from Al, Cr, Cu, Ta, Ti, Mo, and W. The above elements, or alloys containing the above elements, or alloy films of combinations of the above elements, etc. The metal conductive film may have a single layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a titanium film laminated on an aluminum film, A two-layer structure is used, a Ti film and an aluminum film are laminated on top of the Ti film. A three-layer structure is also available, in which a titanium film is formed on the aluminum. Ta (Ta), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Neodymium (N d) Scandium (Sc) and other elements, or a combination of elements, or alloy films Alternatively, a nitride film may be used.

[0136] In this embodiment, a Ti film is used as the metal conductive film, and the source electrode layer and the drain electrode layer are In-Sn-O oxide was used for the etching, and ammonia water (ammonia A mixture of water, hydrogen peroxide, and sodium hydroxide is used.

[0137] A drain electrode layer provided between the oxide semiconductor layer and the auxiliary electrode layer 268b made of a metal material. 265b is the low resistance drain region (LRN(Low Resistance N-type conductivity) area, LRD (Low Resistance Drai) n) region). The oxide semiconductor layer, the low-resistance drain region, the metal electrode By using the auxiliary electrode layer 268 having such a structure, the withstand voltage of the transistor can be further improved. Specifically, the carrier concentration in the low-resistance drain region is higher than that in the high-resistance drain region. area (HRD area), e.g., 1×1020 / cm 3 More than 1×10 21 / cm 3 It is preferable that the content is within the following range.

[0138] In addition, the gate wiring, source wiring, and capacitance wiring layer are provided in multiple lines according to the pixel density. In the terminal section, a first terminal electrode having the same potential as the gate line, a source line a second terminal electrode having the same potential as the capacitance wiring layer, a third terminal electrode having the same potential as the capacitance wiring layer, etc. are arranged in a row. The number of each terminal electrode may be any number. The implementer should make the appropriate decision.

[0139] In the terminal portion, the first terminal electrode having the same potential as the gate line is formed of the same light-transmitting material as the pixel electrode layer 227. The first terminal electrode can be formed of a material having a good thermal conductivity. The contact hole is electrically connected to the gate wiring. The pin electrically connects the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227. The same photomask as that used for the contact holes for connecting the semiconductor substrate to the semiconductor substrate is used to form the planarizing insulating layer 204 and the protective insulating layer 205. The edge layer 203 is selectively etched.

[0140] In addition, a second terminal electrode 255 having the same potential as the source wiring 254 and the auxiliary wiring 269 of the terminal portion The second terminal electrode layer 227 can be formed of the same light-transmitting material as the pixel electrode layer 227. The electrode 255 is electrically connected to the source wiring through a contact hole that reaches the source wiring 254. The source wiring 254 is connected to the source electrode layer 265a of the thin film transistor 260. On the other hand, the auxiliary wiring 269 is formed of the same material in the same process and has the same potential. 4 is a metal wiring using a metal material having a lower resistance than the metal wiring 260, and is an auxiliary electrode layer of the thin film transistor 260. It is formed from the same material and in the same process as 268a and 268b, and has the same potential.

[0141] The third terminal electrode having the same potential as the capacitance wiring layer 230 has the same light-transmitting property as the pixel electrode layer 227. In addition, the contact hole reaching the capacitance wiring layer 230 can be formed of a material having the above-mentioned properties. The contact hole 231 is electrically connected to the pixel electrode layer 227. The same photomask and process can be used to form the insulating film.

[0142] In addition, when an active matrix type liquid crystal display device is manufactured, A liquid crystal layer is provided between the substrate and the opposing substrate on which the opposing electrode is provided, and an active matrix The substrate and the counter substrate are fixed together. The counter electrode is electrically connected to the counter substrate. A common electrode is provided on the active matrix substrate, and a fourth terminal is electrically connected to the common electrode. The fourth terminal electrode is provided on the terminal portion. The fourth terminal electrode is connected to the common electrode at a fixed potential, for example, GND, 0 The fourth terminal electrode is a terminal for setting the pixel electrode layer 227 and the like. The insulating layer may be made of a material having the following properties:

[0143] Also, a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or other electrodes If the same material is used for the layers and other wiring layers, common sputter targets and common manufacturing equipment can be used. The cost of the material and the etchant (or This reduces the cost of etching gas, resulting in reduced manufacturing costs. It is possible.

[0144] In the structure of FIG. 3A, a photosensitive resin material is used as the planarization insulating layer 204. In this case, the step of forming a resist mask can be omitted.

[0145] FIG. 3(B) shows a cross-sectional structure that is partially different from that shown in FIG. 3(A). A) The absence of the planarization insulating layer 204 at the terminal portion and the structure of the thin film transistor of the driving circuit Since the same parts are the same except for the difference in the number of parts, the same reference numerals are used for the same parts, and detailed explanations of the same parts will be omitted. In FIG. 3B, a thin film transistor 270 using metal wiring is disposed. In addition, the terminal electrodes are formed using the same material and process as the metal wiring.

[0146] In the structure of FIG. 3B, a photosensitive resin material is used as the planarizing insulating layer 204. Therefore, the step of forming a resist mask is omitted. In the terminal portion, the planarization insulating layer 204 may not be present. The absence of a planarizing insulating layer facilitates good connection with the FPC.

[0147] The thin film transistor 270 is formed by forming a gate electrode layer 271, a gate The source insulating layer 202, at least the channel forming region 273, the high resistance source region 274a, and and a high-resistance drain region 274b, a source electrode layer 275a, and a drain The drain electrode layer 275b is also an oxide insulating layer 27 6a is provided.

[0148] In addition, the first region 274c and the second region 27 4d is in the same oxygen-excess state as the channel formation region 273, and is effective in reducing leakage current and reducing the parasitic capacitance. The protective insulating layer 203 also serves to reduce parasitic capacitance. The third region 274e is provided between the channel forming region 273 and the high resistance source region 274a. In addition, the fourth region 274f of the oxide semiconductor layer in contact with the protective insulating layer 203 is a channel region. The protective insulating layer 203 is provided between the drain formation region 273 and the high resistance drain region 274b. The third region 274e and the fourth region 274f of the oxide semiconductor layer, which are in contact with each other, are intended to reduce the off-state current. It is possible.

[0149] In addition, the channel protection type thin film transistor has a channel length L of the channel formation region that is shortened. In order to achieve this, the width of the oxide insulating layer is narrowed, and the source electrode layer and the drain electrode layer are formed on the narrow oxide insulating layer. If a thin oxide insulating layer is provided, there is a risk of short circuiting on the oxide insulating layer. The source electrode layer 275a and the drain electrode layer 275b are provided at ends separated from the edge layer 276a. This is the configuration.

[0150] When the metal conductive film is etched, the oxide semiconductor layer of the thin film transistor 270 is also removed. The materials and etching conditions are appropriately adjusted so that this does not occur.

[0151] In this embodiment, a Ti film is used as the metal conductive film, and an In-Ga- Zn-O oxide was used as the etchant, and ammonia water (ammonia, water, peroxide) was used. A mixture of hydrogen peroxide and water is used.

[0152] In addition, the gate electrode layer of the thin film transistor 270 of the driving circuit is provided above the oxide semiconductor layer. Alternatively, the insulating layer 275 may be electrically connected to the conductive layer 277 .

[0153] In addition, the second terminal electrode 257, which has the same potential as the source line 256 of the terminal portion, is connected to the pixel electrode layer 227. The source wiring is a metal wiring, and can be formed of a thin film. The source electrode layer 275a of the transistor 270 is formed of the same material and in the same process, and has the same potential. be.

[0154] In addition, thin film transistors are easily damaged by static electricity, etc. The protection circuit is preferably provided over the same substrate as the semiconductor device. It is preferable to use a nonlinear element. For example, the protection circuit is In this embodiment, a plurality of protection circuits are provided between the terminal and the signal line input terminal. A surge voltage is applied to the scanning lines, signal lines and capacitance bus lines due to static electricity or the like, and the pixel transistors are The protection circuit is designed to prevent the transistors from being destroyed. When a voltage is applied, the charge is released to the common wiring or the common wiring. The protection circuit is composed of a nonlinear element arranged in parallel with the scanning line. The elements and nonlinear elements may be two-terminal elements such as diodes or three-terminal elements such as transistors. For example, it can be formed in the same process as the thin film transistor 220 in the pixel portion. For example, by connecting the gate terminal and the drain terminal, it can be made to be similar to a diode. It is possible to give the following characteristics.

[0155] Note that the step of forming the planarization insulating layer 204 is omitted, and a structure without the planarization insulating layer 204 is used. In this case, the conductive layer 267, the conductive layer 277, the pixel electrode layer 227, the second terminal electrode The electrodes 255 and 257 are provided on and in contact with the protective insulating layer 203 .

[0156] This embodiment mode can be freely combined with the first embodiment mode.

[0157] (Embodiment 3) In this embodiment, one of the configurations of the terminal portion provided on the same substrate as the thin film transistor is In the second embodiment, an example of the terminal portion of the source line is shown. FIG. 1 shows a terminal portion of a source line and a terminal portion of a gate line having a different configuration from that of the second embodiment. In FIG. 4, the same parts as those in FIG. 3(A) or 3(B) are designated by the same reference numerals. explain.

[0158] FIG. 4(A1) and FIG. 4(A2) are a top view and a cross-sectional view, respectively, of a gate line terminal portion. FIG. 4(A1) corresponds to a cross-sectional view taken along line C1-C2 in FIG. 4(A2). In (A1), the conductive layer 225 formed on the protective insulating layer 203 functions as an input terminal. In FIG. 4(A1), the terminal portion is a gate electrode. The first terminal 221 is made of the same material as the layer 421b, and the second terminal 221 is made of the same material as the source line. a connection electrode layer 223 connected to the connection electrode layer 223, and an auxiliary electrode formed of a metal electrode material having a lower resistance than the connection electrode layer 223. The electrode layer 228 overlaps with the gate insulating layer 202 interposed therebetween, and is electrically connected to the conductive layer 225. In addition, when the connection electrode layer 223 has the structure shown in FIG. 3(B), a metal wiring material is used. This can be done.

[0159] Also, FIG. 4(B1) and FIG. 4(B2) show a source line terminal portion different from that shown in FIG. 3(B). 4(B1) shows a top view and a cross-sectional view of the source wiring terminal portion. This corresponds to a cross-sectional view taken along line C3-C4 in FIG. 4(B2). The conductive layer 225 formed on the insulating layer 203 is a connection terminal electrode that functions as an input terminal. In addition, in FIG. 4B1, the terminal portion is formed of the same material as the gate wiring. An electrode layer 226 is formed on the gate insulating layer 222 below the second terminal 222 that is electrically connected to the source line. The electrode layer 226 overlaps with the second terminal 222 through the layer 202. , the electrode layer 226 is set to a potential different from that of the second terminal 222, for example, floating, GND, or 0V. By setting the value to 0, it is possible to form a capacitance for noise countermeasures or a capacitance for static electricity countermeasures. In addition, a metal electrode material having a lower resistance than the second terminal 222 is provided on the second terminal 222. An auxiliary electrode layer 229 made of a material is laminated, and a contact formed in the protective insulating layer 203 is laminated. The second terminal 222 is electrically connected to the conductive layer 225 through a hole. In the case of the configuration shown in (B), a metal wiring material can be used.

[0160] A plurality of gate lines, source lines, and capacitance lines are provided according to the pixel density. In addition, in the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the source wiring, The terminal 2 and the third terminal of the same potential as the capacitance wiring are arranged in a row. The number of terminals may be any number and may be determined appropriately by the implementer.

[0161] This embodiment mode can be freely combined with embodiment mode 1 or 2.

[0162] (Embodiment 4) Here, in a liquid crystal display device in which a liquid crystal layer is sealed between a first substrate and a second substrate, A common connection portion is formed on the first substrate for electrically connecting to the counter electrode provided on the second substrate. In addition, a thin film transistor is formed as a switching element on the first substrate. The manufacturing process of the common connection portion is made common to the manufacturing process of the switching element of the pixel portion. This allows the formation of the film without complicating the process.

[0163] The common connection portion is disposed at a position overlapping a sealant for bonding the first substrate and the second substrate. The sealing material is electrically connected to the counter electrode via conductive particles contained therein. The common connection part is provided in a place where it does not overlap with the sealing material (excluding the pixel part), and the common connection part A paste containing conductive particles is provided separately from the sealing material so as to overlap the opposing electrode. A connection is made.

[0164] FIG. 5A is a cross-sectional view of a semiconductor device in which a thin film transistor and a common connection portion are fabricated on the same substrate. FIG.

[0165] In FIG. 5A, a thin film transistor 220 electrically connected to a pixel electrode layer 227 is A channel protection type thin film transistor is provided in a pixel portion. The thin film transistor 448 has the same structure as that of the thin film transistor 448 of the first embodiment.

[0166] FIG. 5B is a top view of an example of the common connection portion, and the dashed line C5-C6 in the figure is This corresponds to the cross section of the common connection part in FIG. 5(A). The same reference numerals will be used for the above parts in the following description.

[0167] The common potential line 205 is provided on the gate insulating layer 202 and is connected to the source of the thin film transistor 220. The common potential line 2 is made of the same material and in the same process as the source electrode layer and the drain electrode layer. On the 05, an auxiliary wiring 21 made of a metal wiring made of the same material and by the same process as the auxiliary electrode layer is provided. 0 is formed.

[0168] The common potential line 205 is covered with a protective insulating layer 203. The thin film transistor 202 has a plurality of openings at positions overlapping the line 205. The contact hole connecting the drain electrode layer 20 and the pixel electrode layer 227 is formed in the same process. It is manufactured.

[0169] In addition, since the area size is significantly different here, the contact hole in the pixel area and the common In FIG. 5(A), the pixel section and the common connection section are called the openings of the common connection section. For example, the length of the chain line C5-C6 of the common connection is 500 mm. The width of a thin-film transistor is less than 50 μm, and in fact is about 10 The area size is more than twice as large, but for ease of understanding, the pixel section and the common connection section are shown in Figure 5(A). The figures are illustrated at different scales.

[0170] The common electrode layer 206 is provided on the protective insulating layer 203, and the pixel electrode layer 227 of the pixel portion It is made of the same materials and in the same process.

[0171] In this way, the manufacturing process of the common connection portion is common to the manufacturing process of the switching element of the pixel portion. conduct.

[0172] A first substrate on which a pixel section and a common connection section are provided and a second substrate having a counter electrode are then Secure it in place using a sealant.

[0173] When the sealing material contains conductive particles, the sealing material and the common connection part are overlapped with each other. For example, in a small LCD panel, the diagonal corners of the pixel area are aligned. Two common connection parts are arranged overlapping the sealant. In addition, in large liquid crystal panels, Four or more common connections are disposed in overlapping relation with the sealant.

[0174] The common electrode layer 206 is an electrode that comes into contact with the conductive particles contained in the sealing material. The substrate is electrically connected to the counter electrode of the substrate.

[0175] When using the liquid crystal injection method, a pair of substrates are fixed with a sealant, and then liquid crystal is injected between the pair of substrates. In addition, when the liquid crystal dropping method is used, a sealant is applied to the second substrate or the first substrate. After drawing and dropping liquid crystal, the pair of substrates are bonded together under reduced pressure.

[0176] In this embodiment, an example of a common connection portion electrically connected to the counter electrode has been shown. Not limited to this, it is used for connecting parts to other wiring, connecting parts to external connection terminals, etc. It is possible.

[0177] FIG. 5(C) shows a cross-sectional structure that is partially different from that shown in FIG. 5(A). A) is a stack of oxide semiconductor layers overlapping the common electrode layer 206, and an oxide insulating layer covering the edge of the stack is provided. The configuration is the same except for the presence of a metal wiring as a common potential line. The same reference numerals are used in the following description, and detailed explanations of the same parts will be omitted.

[0178] The stacked oxide semiconductor layer 207 is provided on the gate insulating layer 202 and is a thin film transistor 2 The oxide semiconductor layer is formed of the same material and in the same process as the oxide semiconductor layer of the stack of 20. An oxide insulating layer 208 is formed to cover the oxide semiconductor layer 207. A common potential line 209 made of metal wiring is formed. The common potential line 209 made of metal wiring is As shown in FIG. 3B of the second embodiment, the source electrode layer of the thin film transistor of the driving circuit Alternatively, the drain electrode layer is formed in the same process.

[0179] The common electrode layer 206 is covered with a protective insulating layer 203, which is connected to a common potential The thin film transistor 207 has a plurality of openings at positions overlapping the line 209. The contact hole connecting the drain electrode layer 20 and the pixel electrode layer 227 is formed in the same process. It is manufactured.

[0180] The common potential line 209 is provided on the protective insulating layer 203 and is connected to the pixel electrode layer 227 of the pixel portion. It is made of the same materials and in the same process.

[0181] In this way, the manufacturing process of the common connection portion is common to the manufacturing process of the switching element of the pixel portion. In addition, the common potential line may be made of metal wiring to reduce the wiring resistance.

[0182] This embodiment mode can be freely combined with any one of the embodiment modes 1 to 3.

[0183] (Embodiment 5) In the first and second embodiments, an example in which the gate insulating layer is a single layer is shown. An example of lamination is shown below. In FIG. 6, the same part as in FIG. 3(A) or FIG. 3(B) is will be explained using the same reference numerals.

[0184] In FIG. 6A, a thin film transistor 280 is a channel-protected thin film transistor provided in a pixel. This is an example of a film transistor having two gate insulating layers and two oxide semiconductor layers. The thin film transistor 260 is a channel protection type thin film transistor provided in the driving circuit. The gate insulating layer is a single oxide semiconductor layer. The thin film transistor 260 shown in FIG. 6A is the same as the thin film transistor 260 shown in FIG. Therefore, the description will be omitted here.

[0185] In this embodiment, a first gate insulating layer 282a having a thickness of 50 nm or more and 200 nm or less, A second gate insulating layer 282b having a thickness of 50 nm to 300 nm is a stacked gate insulating layer. The first gate insulating layer 282a is a silicon nitride film or a nitride oxide film having a thickness of 100 nm. A silicon film is used. The second gate insulating layer 282b is a silicon oxide film having a thickness of 100 nm. A bare membrane is used.

[0186] In addition, the thin film transistor 280 includes a gate electrode layer 281, a first The first gate insulating layer 282a, the second gate insulating layer 282b, and at least the channel forming region 283, a high-resistance source region 284a, and a high-resistance drain region 284b. The semiconductor layer includes a source electrode layer 285a and a drain electrode layer 285b. A laminated oxide insulating layer 286a is provided in contact with the panel forming region 283. The first region 284c and the second region 284d of the stacked oxide semiconductor layer overlapping the layer 286b are The oxygen-rich state is the same as that of the channel formation region 283, and the leakage current is reduced and the parasitic capacitance is reduced. The pixel electrode layer 227 also functions to reduce the electric field generated by the drain electrode layer 285b. is connected to

[0187] The storage capacitor is provided below the pixel electrode layer 227, and the capacitor electrode 231 is disposed below the pixel electrode layer 227. 27.

[0188] In this embodiment, a storage capacitor is formed using a capacitor electrode 231 and a capacitor wiring layer 230. .

[0189] In addition, in FIG. 6A, the storage capacitor has a large capacitance, so the capacitance wiring and the capacitance electrode Only the gate insulating layer is provided between them.

[0190] In this embodiment, a silicon oxide film obtained by a sputtering method is used as the oxide insulating layer 286b. When removing the oxide insulating layer of the stack that overlaps the capacitance wiring layer 230, the second silicon oxide film is In this example, the gate insulating layer is also thinned by etching to form a third gate insulating layer 282c. The first gate insulating layer 282a is a silicon nitride film or a silicon oxynitride film, and is etched. It functions as an etching stopper to prevent etching damage to the gate electrode layer and substrate.

[0191] By making the third gate insulating layer 282c thin, it is possible to increase the storage capacitance. can.

[0192] FIG. 6B shows a cross-sectional structure that is partially different from that shown in FIG. 6A. In FIG. 6B, The thin film transistor 290 is a channel protection type thin film transistor provided in a pixel. In this example, the gate insulating layer is two layers, and is an example of a two-layer oxide semiconductor layer. The transistor 245 is a channel protection type thin film transistor provided in the driving circuit, and has a gate insulator. The thin film transistor shown in FIG. 6B has two insulating layers, and is an example of a single oxide semiconductor layer. The transistor 245 is a thin film transistor 260 shown in FIG. Since the structure is the same except that 8a and 268b are not provided, a description thereof will be omitted here. Like the thin film transistor 245, a transparent solenoid is used without providing an auxiliary electrode layer in the driver circuit. A structure including only the source electrode layer and the drain electrode layer may also be used.

[0193] In the thin film transistor 290 shown in FIG. 6B, the first and a second gate insulating layer 292b having a thickness of 1 nm to 50 nm. The first gate insulating layer 292a is a 100 nm thick oxide film. The second gate insulating layer 292b is a silicon nitride film having a thickness of 10 nm. A bare film or a silicon oxynitride film is used.

[0194] The thin film transistor 290 includes a gate electrode layer 291, a first insulating layer 292, a second insulating layer 293, a first insulating layer 294, a second insulating layer 295, a first insulating layer 296, a second insulating layer 297, a first insulating layer 298, a second insulating layer 299, a first insulating layer 291, a second insulating layer 299, a second insulating layer 291, a first insulating layer 292, a The first gate insulating layer 292a, the second gate insulating layer 292b, and at least the channel forming region 293, a high-resistance source region 294a, and a high-resistance drain region 294b. The semiconductor layer includes a source electrode layer 295a and a drain electrode layer 295b. An oxide insulating layer 296a is provided in contact with the panel formation region 293.

[0195] In addition, the first region 294c and the second region 294b of the stacked oxide semiconductor layer overlap with the oxide insulating layer 296b. The region 294d is in the same oxygen-excess state as the channel formation region 293, and the leakage current is reduced. In addition, the protective insulating layer 203 also functions to reduce the amount of oxidation of the laminated layer. The third region 294e of the compound semiconductor layer is a channel forming region 293 and a high resistance source region 294 a. In addition, the fourth region of the oxide semiconductor layer in contact with the protective insulating layer 203 The region 294f is provided between the channel formation region 293 and the high-resistance drain region 294b. The third region 294e and the fourth region 29 4f can reduce the off current.

[0196] The third region 294e and the fourth region 294f of the oxide semiconductor layer are made of a silicon nitride film or a nitride The protective insulating layer 203 is also in contact with the second gate insulating layer 292b which is a silicon oxide film. , hydrogen ions, oxygen ions, OH - It does not contain impurities such as The inorganic insulating film used is a silicon nitride film, an aluminum nitride film, a nitride oxide film, etc. A silicon film, an aluminum oxide nitride film, or the like is used.

[0197] In this embodiment, a silicon oxide film obtained by a sputtering method is used as the oxide insulating layer 296b. When removing the oxide insulating layer overlapping the capacitance wiring layer 230, a silicon nitride film or a nitriding oxide film is used. The oxide insulating layer is etched using the second gate insulating layer, which is a silicon oxide film, as an etching stopper. This is an example of

[0198] In addition, the channel protection type thin film transistor has a channel length L of the channel formation region that is shortened. In order to achieve this, the width of the oxide insulating layer is narrowed, and the source electrode layer and the drain electrode layer are formed on the narrow oxide insulating layer. If a thin oxide insulating layer is provided, there is a risk of short circuiting on the oxide insulating layer. The source electrode layer 295a and the drain electrode layer 295b are provided at ends separated from the edge layer 296a. This is the configuration.

[0199] This embodiment mode can be freely combined with any one of the embodiment modes 1 to 4.

[0200] (Embodiment 6) In this embodiment, a manufacturing process of a thin film transistor is partially different from that in Embodiment 1, as shown in FIG. 7 and 8 are the same as FIG. 1 and FIG. 2 except for some steps. Therefore, the same reference numerals are used for the same parts, and detailed descriptions of the same parts are omitted.

[0201] First, according to the first embodiment, a gate electrode layer, a gate insulating layer, a metal thin film, and an oxide film are formed on a substrate. Then, according to the first embodiment, an island-shaped metal layer 428 and an island-shaped An oxide semiconductor layer 429 is formed.

[0202] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400° C. or higher and lower than the distortion point of the substrate, preferably 425° C. or higher. If the temperature is 425℃ or higher, the heat treatment time can be 1 hour or less. The heat treatment time is longer than one hour. The substrate is placed in an electric furnace, and the oxide semiconductor layer is subjected to a heat treatment in a nitrogen atmosphere. After that, the oxide semiconductor layer is not exposed to the air, and water and hydrogen are prevented from re-mixing into the oxide semiconductor layer. A conductor layer 422 is obtained. After that, high-purity oxygen gas, high-purity N2O gas, or ultra-high-purity SiO2 gas is added to the same furnace. Cooling is performed by introducing dry air (dew point below -40°C, preferably below -60°C). Oxygen It is preferable that the gas or N2O gas does not contain water, hydrogen, etc. The purity of oxygen gas or N2O gas introduced into the device should be 6N (99.9999%) or higher. Preferably 7N (99.99999%) or more (i.e. impurities in oxygen gas or N2O gas) It is preferable to keep the concentration at 1 ppm or less, and preferably at 0.1 ppm or less.

[0203] After the first heat treatment for dehydration or dehydrogenation, the temperature is preferably 200° C. or higher and 400° C. or lower. Or heat treatment at a temperature between 200℃ and 300℃ in an oxygen gas or N2O gas atmosphere. The theory may also be carried out.

[0204] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, the substrate is removed from the heating device after the first heat treatment. The substrate is then taken out and subjected to a photolithography process.

[0205] By going through the above steps, the entire oxide semiconductor film is made into an oxygen-excess state, and thus a high resistance It converts it into type I, that is, into an anti-type I.

[0206] Alternatively, the metal layer 428 may be oxidized by the first heat treatment to become an oxide semiconductor layer. In addition, the first heat treatment is not limited to oxidizing the metal layer 428. Apart from the treatment, an oxidation treatment may be performed to oxidize the metal layer 428, e.g. After the oxide insulating film is formed by a sputtering method, oxidation treatment may be performed.

[0207] Next, an oxide insulating film is formed over the gate insulating layer 402 and the oxide semiconductor layer by a sputtering method. (See FIG. 8(A)).

[0208] Next, a resist mask is formed by a third photolithography process and selectively etched. Then, oxide insulating layers 426a and 426b are formed by etching, and the resist mask is then removed. (See FIG. 8(B)).

[0209] Next, the gate insulating layer 402, the oxide insulating layers 426a and 426b, and the stacked oxide semiconductor After forming a light-transmitting conductive film on the conductive layer 422, a fourth photolithography process is performed. A resist mask is formed and selectively etched to form the source electrode layer 425a and The drain electrode layer 425b is formed (see FIG. 8C).

[0210] Next, in order to reduce the variation in the electrical characteristics of the thin-film transistors, Alternatively, heat treatment (preferably at 150°C or higher and lower than 350°C) is performed under a nitrogen gas atmosphere. For example, a heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere.

[0211] Next, the oxide insulating layers 426a and 426b, the source electrode layer 425a, and the drain electrode layer 42 A protective insulating layer 403 is formed on 5b.

[0212] Next, a planarization insulating layer 404 is formed over the protective insulating layer 403 .

[0213] Next, a fifth photolithography step is performed to form a resist mask, and a planarization insulating layer 4 04, and the protective insulating layer 403 is etched to form a contact that reaches the drain electrode layer 425b. A cut hole 441 is formed, and the resist mask is removed (see FIG. 8(D)).

[0214] Next, a light-transmitting conductive film is formed.

[0215] Next, a sixth photolithography process is performed to form a resist mask and to form a Then, unnecessary portions are removed to form a pixel electrode layer 427, and the resist mask is removed (FIG. 8( See E). ).

[0216] Through the above steps, a thin film transistor 420 and a side Wire crossings with reduced raw capacitance can be created.

[0217] The pixel thin film transistor 420 is a stack of an oxide semiconductor layer 42 including a channel formation region. 2 is a channel-protected thin-film transistor including

[0218] FIG. 7A is a plan view of a channel-protected thin-film transistor 420 disposed in a pixel. 7(B) is a cross-sectional view taken along line D7-D8 in FIG. 7(A) and a cross-sectional view taken along line D7-D8 in FIG. 7(A) is a cross-sectional view taken along line D9-D10 in FIG. 8(E) is the same as FIG. 7(B).

[0219] This embodiment mode can be freely combined with any one of the embodiment modes 1 to 5.

[0220] (Embodiment 7) In this embodiment, a configuration of a storage capacitor different from that of the second embodiment is shown in FIG. FIG. 9(B) shows the same as FIG. 3(A) except for the configuration of the storage capacitor. Therefore, the same parts are designated by the same reference numerals, and detailed explanations of the same parts are omitted. 1A shows the cross-sectional structure of a thin film transistor 220 and a storage capacitor in a pixel portion.

[0221] FIG. 9A shows a pixel electrode layer 202 having a protective insulating layer 203 and a planarizing insulating layer 204 as dielectrics. 27 and a capacitance wiring layer 250 overlapping the pixel electrode layer 227 form a storage capacitance. The capacitance wiring layer 250 has the same light-transmitting property as the source electrode layer of the thin film transistor 220 in the pixel portion. Since the material has the same properties and is formed in the same process, the source wiring layer of the thin film transistor 220 The layout is such that there is no overlap.

[0222] In the storage capacitor shown in FIG. 9A, a pair of electrodes and a dielectric material are transparent, and the entire storage capacitor The body is translucent.

[0223] FIG. 9B shows an example of a storage capacitor configuration different from that shown in FIG. 9A. Since this is the same as 3(A) except for the difference in the storage capacitance, the same symbols are used for the same parts. Detailed explanations of the same parts will be omitted.

[0224] FIG. 9B shows a structure in which the dielectric is a gate insulating layer 202, a capacitance wiring layer 230, and the capacitance wiring layer 2 In this example, a storage capacitor is formed by laminating an oxide semiconductor layer 251 and a capacitor electrode 231 that overlap with the oxide semiconductor layer 30. In addition, the capacitance electrode 231 is laminated on the oxide semiconductor layer 251 in contact therewith, and a storage capacitance The oxide semiconductor layer 251 functions as one electrode of the thin film transistor 22. The oxide semiconductor layer 251 is formed in a process different from that of the oxide semiconductor layer 250. After that, an oxide semiconductor layer is formed on the capacitor wiring layer 230. Since the gate electrode layer of the transistor 220 is formed of the same material having the same light-transmitting property and in the same process, The layout is such that it does not overlap with the gate wiring layer of the film transistor 220. The electrode 231 is electrically connected to the pixel electrode layer 227 .

[0225] The storage capacitor shown in FIG. 9B also has a pair of electrodes and a dielectric material that are transparent, and the entire storage capacitor The body is translucent.

[0226] The storage capacitor shown in FIG. 9(A) and FIG. 9(B) has a light-transmitting property, and the number of gate wirings is In order to increase the resolution of displayed images, it is necessary to increase the capacity of the display even if the pixel size is reduced. It is possible to obtain a high aperture ratio.

[0227] This embodiment mode can be freely combined with other embodiment modes.

[0228] (Embodiment 8) In this embodiment, at least a part of the driver circuit and a thin film transistor to be disposed in the pixel portion are formed on the same substrate. An example of fabricating a transistor will be described below.

[0229] The thin film transistors to be disposed in the pixel portion are formed according to the first, second, fifth and sixth embodiments. In addition, since the thin film transistors shown in the first, second, fifth and sixth embodiments are n-channel TFTs, Among the driver circuits, a part of the driver circuit that can be configured with an n-channel TFT is The thin film transistor is formed on the same substrate.

[0230] An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, and a third scanning line driver circuit 5304 are provided on a substrate 5300. The pixel portion 5301 includes a signal line driver circuit 5303 and a signal line driver circuit 5304. is arranged extending from a signal line driver circuit 5304, and a plurality of scanning lines are arranged in a first scanning line driver circuit The first scanning line driver circuit 5302 and the second scanning line driver circuit 5303 are arranged to extend from each other. At the intersections of the signal lines and the display elements, pixels each having a display element are arranged in a matrix. In addition, the substrate 5300 of the display device is a flexible printed circuit (FPC). A timing control circuit 5305 (controller, control I / F) is connected to the timing control circuit 5305 via a connection part such as a C).

[0231] In FIG. 14A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The signal line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. This reduces the number of external components such as drive circuits, and therefore reduces costs. In addition, when a driving circuit is provided outside the substrate 5300, the wiring is extended to provide a connection portion. The number of connections can be reduced, and the reliability and yield can be improved.

[0232] The timing control circuit 5305 is, for example, A first scanning line driving circuit start signal (GSP1), a scanning line driving circuit clock signal (GCK1). The timing control circuit 5305 also supplies the second scanning line driving circuit For example, the second scanning line driver circuit start signal (GSP2) (start The signal line supplies the clock signal (GCK2) for the scanning line driver circuit. A start signal (SSP) for the signal line driver circuit and a clock for the signal line driver circuit are input to the driver circuit 5304. Clock signal (SCK), data for video signal (DATA) (also simply called video signal), Each clock signal is a multiple of the clock signal (LAT) with different periods. It may be a clock signal or may be supplied together with an inverted clock signal (CKB). The first scanning line driver circuit 5302 and the second scanning line driver circuit 53 It is possible to omit either 03 or 04.

[0233] In FIG. 14B, a circuit with a low driving frequency (for example, the first scanning line driving circuit 5302, The second scanning line driver circuit 5303) is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver The configuration in which the driving circuit 5304 is formed on a substrate different from that of the pixel portion 5301 is shown. Due to its structure, the field effect mobility is smaller than that of a transistor using a single crystal semiconductor. The driving circuit formed on the substrate 5300 can be configured by the thin film transistor. Therefore, it is possible to increase the size of the display device, reduce the cost, and improve the yield. do.

[0234] The thin film transistors shown in the first, second, fifth and sixth embodiments are n-channel TFTs. In FIG. 15(A) and FIG. 15(B), a signal line driver circuit is configured with an n-channel TFT. An example of the operation will be described.

[0235] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 includes switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each have a A plurality of thin film transistors 5603_1 to 5603_k (k is a natural number) are provided. The thin film transistors 5603_1 to 5603_k are N-channel TFTs. An example will be explained.

[0236] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are respectively connected to the wiring 5604_1 The second terminals of the thin film transistors 5603_1 to 5603_k are connected to are connected to the signal lines S1 to Sk, respectively. The gate of k is connected to the wiring 5605_1.

[0237] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , or high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_k in sequence.

[0238] The switching circuit 5602_1 includes wirings 5604_1 to 5604_k and signal lines S1 to Sk. The function of controlling the conduction state (conduction between the first terminal and the second terminal) with the wiring 5604_ The switches have a function of controlling whether or not potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. and the signal lines S1 to Sk, that is, the wirings 5604_1 to 5604_k The thin film transistor 56 has a function of supplying the potential to the signal lines S1 to Sk. Each of 03_1 to 5603_k has a function as a switch.

[0239] In addition, the wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal that

[0240] Next, the operation of the signal line driver circuit of FIG. 15(A) will be described with reference to the timing chart of FIG. 15(B). FIG. 15B shows signals Sout_1 to Sout_N and An example of Vdata_1 to Vdata_k is shown. These are examples of output signals of the shift register 5601, and signals Vdata_1 to Vdata _k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The selection period is divided into periods T1 to TN, for example. This is a period for writing video signal data (DATA) to the pixels belonging to the selected row. be.

[0241] In the drawings of the present embodiment, the signal waveforms of the components are not rounded for clarity. Therefore, the scale may not necessarily be limited to the actual scale. It should be noted that

[0242] During the period T1 to the period TN, the shift register 5601 outputs an H-level signal to the wiring 560 For example, in the period T1, the shift registers 5 601 outputs a high-level signal to the wiring 5605_1. Since 5603_1 to 5603_k are turned on, wiring 5604_1 to 5604_k and signal At this time, the wirings 5604_1 to 5604_k are in a conductive state. Data(S1)~Data(Sk) are input. Data(S1)~Data(Sk ) belong to a selected row via thin film transistors 5603_1 to 5603_k. In this way, during the periods T1 to TN, Then, the video signal data (DATA) is sent to the pixels in the selected row in order of k columns. It will be written.

[0243] As described above, video signal data (DATA) is written to the pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. A) is written to the pixels in multiple columns at a time, which allows the writing time to be extended. This makes it possible to prevent insufficient writing of video signal data (DATA).

[0244] The shift register 5601 and the switching circuit 5602 are the same as those in the first embodiment. It is possible to use a circuit composed of thin film transistors shown in 2, 5, and 6. In this case, the polarity of all the transistors in the shift register 5601 is set to N-channel type or The channel types can be configured with only one polarity.

[0245] Regarding one form of a shift register used as a part of a scanning line driver circuit and / or a signal line driver circuit, This will be described with reference to FIG. 16 and FIG. 17.

[0246] The configuration of the scanning line driver circuit will be described. The scanning line driver circuit has a shift register. In some cases, a level shifter, a buffer, etc. may be included. In the operation circuit, a clock signal (CLK) and a start pulse signal (S P) is input to generate a selection signal. The generated selection signal is buffered The signal is buffered and amplified at the 10th line and then supplied to the corresponding scanning line. The gate electrodes of the transistors are connected. must be turned on at the same time, so the buffer must be capable of passing a large current. is used.

[0247] The shift register includes a first pulse output circuit 10_1 to an N-th pulse output circuit 10_N ( N is a natural number of 3 or more (see FIG. 16(A)). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the register are A first clock signal CK1 is transmitted from a wiring 11, and a second clock signal CK2 is transmitted from a second wiring 12. , a third clock signal CK3 is output from a third wiring 13, and a fourth clock signal CK4 is output from a fourth wiring 14. In the first pulse output circuit 10_1, a signal CK4 is supplied from the fifth wiring 15. A start pulse SP1 (first start pulse) is input. In the pulse output circuit 10_n (n is a natural number between 2 and N), A signal from the previous stage (called the previous stage signal OUT(n-1)) is input. Also, the first pulse output A signal is input to the circuit 10_1 from a third pulse output circuit 10_3 which is two stages later. Similarly, in the n-th pulse output circuit 10_n in the second or subsequent stage, the (n+2)-th pulse output circuit in the second stage A signal from the output circuit 10_(n+2) (called the next stage signal OUT(n+2)) is input. Therefore, the pulse output circuit of each stage outputs a signal to the pulse output circuit of the next stage and / or the stage two stages before. A first output signal OUT(1)(SR) to OUT(N)(SR) for input to another circuit Second output signals OUT(1) to OUT(N) are outputted, which are electrically inputted to lines, etc. As shown in FIG. 16A, the last two stages of the shift register are connected to the rear stage signal O Since UT(n+2) is not input, for example, a second start pulse SP2, The third start pulse SP3 may be input to each of the first and second input terminals.

[0248] The clock signal (CK) goes between H and L levels (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are The four clock signals (CK4) are delayed by 1 / 4 of a period in sequence (i.e., 90 degrees from each other). In this embodiment, the first clock signal (CK1) to the fourth clock signal (CK2) are The clock signal (CK4) is used to control the driving of the pulse output circuit. The signal may be called GCK or SCK depending on the drive circuit to which it is input. I will explain as K.

[0249] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11 to It is electrically connected to any one of the fourth wirings 14. For example, in FIG. The first pulse output circuit 10_1 has a first input terminal 21 electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is The second pulse output circuit 10_2 is electrically connected to the third wiring 13. The first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13. The third input terminal 23 is electrically connected to the fourth wiring 14. There are.

[0250] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal The input terminal 25, the first output terminal 26, and the second output terminal 27 (see FIG. 16(B)). In the first pulse output circuit 10_1, a first clock signal is input to a first input terminal 21. A first clock signal CK1 is input to the first input terminal 22, a second clock signal CK2 is input to the third input terminal 23, and a third clock signal CK3 is input to the second input terminal 24. A third clock signal CK3 is input to the input terminal 23 of the second clock CLK1, and a start signal CK4 is input to the fourth input terminal 24 of the third clock CLK2. A pulse is input, the next stage signal OUT(3) is input to the fifth input terminal 25, and the first output A first output signal OUT(1)(SR) is output from a terminal 26, and a second output signal OUT(1)(SR) is output from a second output terminal 27. The second output signal OUT(1) is output.

[0251] The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are each a three-terminal thin-film transistor. In addition to transistors (also called TFTs: Thin Film Transistors), In this specification, a thin film transistor can be used. When the gate electrode has two gate electrodes through a semiconductor layer, the gate electrode below the semiconductor layer The gate electrode above the semiconductor layer is also called the upper gate electrode.

[0252] When an oxide semiconductor is used for a semiconductor layer including a channel formation region of a thin film transistor, The threshold voltage may shift to the negative or positive side depending on the process. Therefore, in a thin film transistor in which an oxide semiconductor is used for a semiconductor layer including a channel formation region, A configuration capable of controlling the threshold voltage is preferable. The threshold voltage of the thin film transistor 28 controls the potential of the upper and / or lower gate electrodes. By controlling the voltage, it is possible to control the voltage to a desired value.

[0253] Next, an example of a specific circuit configuration of the pulse output circuit shown in FIG. This is explained in (D).

[0254] The pulse output circuit shown in FIG. 16(D) includes a first transistor 31 to a thirteenth transistor. The first input terminal 21 to the fifth input terminal 25, In addition to the first output terminal 26 and the second output terminal 27, a power supply to which a first high power supply potential VDD is supplied is provided. A power supply line 51, a power supply line 52 to which a second high power supply potential VCC is supplied, and a power supply line 53 to which a low power supply potential VSS is supplied. A signal is supplied to the first transistor 31 to the thirteenth transistor 43 from a power supply line 53 connected to the The power supply potential is supplied to each of the power supply lines in FIG. The first power supply potential VDD is set to a potential equal to or higher than the second power supply potential VCC. The potential of the first clock signal (CK1) to the third power supply potential VSS is set to be higher than the third power supply potential VSS. The fourth clock signal (CK4) is a signal that alternates between H and L levels at regular intervals. When the power supply line 52 is at the H level, it is VDD, and when the power supply line 52 is at the L level, it is VSS. By making the power supply potential VCC lower than the power supply potential VDD of the power supply line 51, the operation is not affected. The potential applied to the gate electrode of the transistor can be kept low without causing a problem. This reduces the shift in the threshold voltage of the transistor and suppresses degradation. Among the transistors 31 to 43, the first transistor 31 and the sixth transistor The transistors 36 to 9 are the four-terminal thin-film transistors shown in FIG. It is preferable to use the first transistor 31 and the sixth transistor 28. The operation of the 36th to 9th transistors 39 is performed when one of the electrodes serving as the source or drain is connected to The potential of the node connected to the gate electrode must be switched by the control signal of the gate electrode. It is a transistor that responds quickly to the control signal input to the gate electrode (the on-current rises A transistor that can reduce malfunctions in the pulse output circuit by having a steep rise time. Therefore, the four-terminal thin film transistor 28 shown in FIG. The threshold voltage can be controlled by the above, and a pulse output circuit that can further reduce malfunctions can be obtained. It is possible.

[0255] In FIG. 16D, the first transistor 31 has a first terminal electrically connected to a power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39; (the lower gate electrode and the upper gate electrode) are electrically connected to the fourth input terminal 24. The second transistor 32 has a first terminal electrically connected to the power supply line 53 and a second terminal a gate electrode electrically connected to the first terminal of the ninth transistor 39 and a gate electrode electrically connected to the first terminal of the fourth transistor The third transistor 33 is electrically connected to the gate electrode of the first terminal The first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 has a first terminal electrically connected to the power supply line 53, The second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 is The first terminal is electrically connected to the power supply line 53, and the second terminal is connected to the gate of the second transistor 32. The electrode of the fourth transistor 34 is electrically connected to the gate electrode of the fourth transistor 34. The sixth transistor 36 has a first terminal electrically connected to the power supply line 52, and the second terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 33. The gate electrode of the transistor 34 is electrically connected to the gate electrode of the transistor 34. The seventh transistor (the gate electrode of the seventh transistor) is electrically connected to the fifth input terminal 25. The eighth transistor 37 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the eighth transistor 38. and a gate electrode (a lower gate electrode and an upper gate electrode) electrically connected to the second terminal of the is electrically connected to the third input terminal 23. The eighth transistor 38 is is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. and the gate electrodes (the lower gate electrode and the upper gate electrode) are connected to the second input terminal The ninth transistor 39 has a first terminal electrically connected to the first transistor 22. The second terminal is electrically connected to the second terminal of the second transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are connected to The gate electrodes (the lower gate electrode and the upper gate electrode) are electrically connected to the power supply line 52. The tenth transistor 40 has a first terminal electrically connected to the first input terminal 2. 1, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is electrically connected to the second terminal of the ninth transistor 39. 41 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the second output terminal 27. The gate electrodes of the second transistor 32 and the fourth transistor The twelfth transistor 42 is electrically connected to the gate electrode of the first terminal of the transistor 34. The first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the second output terminal 27. The gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) The thirteenth transistor 43 has a first terminal electrically connected to the power supply line 5 3, the second terminal is electrically connected to the first output terminal 26, and the gate electrode The seventh transistor 37 has a gate electrode (lower gate electrode and upper gate electrode) are electrically connected.

[0256] In FIG. 16D, the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 4 The connection point of the gate electrode of transistor 0 and the second terminal of transistor 939 is referred to as node A. In addition, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the transistor 38 and the gate electrode of the eleventh transistor 41 is node B. Let us assume that.

[0257] FIG. 17A shows the pulse output circuit described in FIG. 16D as a first pulse output circuit 10_ 1, the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26 and a signal input to or output from a second output terminal 27.

[0258] Specifically, a first clock signal CK1 is input to the first input terminal 21, and A second clock signal CK2 is input to the third input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A start pulse is input to the fourth input terminal 24, and a clock signal CK3 is input to the fifth input terminal The next stage signal OUT(3) is input to the first output terminal 25, and the first output signal OUT (1)(SR) is output, and the second output signal OUT(1) is output from the second output terminal 27. will be done.

[0259] A thin film transistor is defined as a transistor having at least three elements including a gate, a drain, and a source. A semiconductor device has a terminal and a channel region formed in a region overlapping with the gate. By controlling the gate potential, the drain and source are connected via the channel region. The current flowing between the source and drain can be controlled by the thin film transistor. Which is the source and which is the drain depends on the transistor structure and operating conditions, etc. Therefore, the regions that function as the source and drain are In some cases, the term "source" or "drain" is not used. In such cases, for example, They may be written as terminal or second terminal.

[0260] In FIG. 16(C) and FIG. 17(A), the node A is put into a floating state, and the boot A capacitor may be provided separately to perform a strap operation. To achieve this, a capacitor having one electrode electrically connected to the node B may be provided separately.

[0261] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. A shift register is a scanning line driver circuit. In this case, the period 61 in FIG. 17(B) corresponds to a vertical blanking period, and the period 62 corresponds to a gate selection period. do.

[0262] As shown in FIG. 17A, the ninth transistor has a gate to which the second power supply potential VCC is applied. By providing the transistor 39, the following can be achieved before and after the bootstrap operation: There are such advantages.

[0263] In the absence of the ninth transistor 39, the gate electrode of which is applied with the second power supply potential VCC, When the potential of the node A rises due to the base strap operation, the second transistor 31 The potential of the source terminal rises and becomes higher than the first power supply potential VDD. Then, the source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, between the gate and the source, between the gate and the drain In both cases, a large bias voltage is applied, which places a large stress on the transistor. Therefore, the ninth power supply potential VCC is applied to the gate electrode. By providing the transistor 39, the voltage of the node A is increased by the bootstrap operation. The potential of the second terminal of the first transistor 31 is increased, but the potential of the second terminal of the first transistor 31 is not increased. That is, by providing the ninth transistor 39, It is possible to reduce the value of the negative bias voltage applied between the gate and source of the transistor 31. Therefore, by using the circuit configuration of this embodiment, the first transistor 31 The negative bias voltage applied between the gate and source can also be reduced, reducing the stress-induced Deterioration of the first transistor 31 can be suppressed.

[0264] The ninth transistor 39 is provided at a position corresponding to the second gate of the first transistor 31. A terminal is connected between the terminal and the gate of the third transistor 33 via a first terminal and a second terminal. In addition, in the present embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scan line driver circuit. The resistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0265] Note that the semiconductor layers of the first to thirteenth transistors 31 to 43 are made of oxide semiconductor. By using a conductor, the off-current of a thin film transistor is reduced, and the on-current and the field effect It is possible to increase the mobility and reduce the degree of degradation, so that In addition, a transistor using an oxide semiconductor can be used in an amorphous Compared to transistors using base silicon, a high potential is applied to the gate electrode. The degree of deterioration of the transistor is small. Therefore, the power supply line that supplies the second power supply potential VCC The same operation can be obtained by supplying the first power supply potential VDD to the Since the number of lines can be reduced, the circuit can be made smaller.

[0266] The gate electrodes (lower gate electrode and upper gate electrode) of the seventh transistor 37 a clock signal provided by the third input terminal 23 to the gate of the eighth transistor 38; The input electrodes (lower gate electrode and upper gate electrode) are supplied with a second input terminal 22. The clock signal is applied to the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode). A clock signal is supplied to the gate electrode of the eighth transistor by the second input terminal 22. The third input terminal 23 is connected to the gate electrodes (lower gate electrode and upper gate electrode) of the gate electrode of the transistor 38. The same effect can be obtained by swapping the wiring so that the clock signal is supplied by In the shift register shown in FIG. The seventh transistor 37 is turned off and the eighth transistor 38 is turned on. The transistor 38 is on, then the seventh transistor 37 is off, and the eighth transistor By turning off the input terminal 38, the second input terminal 22 and the third input terminal 23 are The voltage drop at node B is generated by the gate of the seventh transistor 37. due to a drop in the potential of the gate electrode of the eighth transistor 38 and a drop in the potential of the gate electrode of the eighth transistor 39. On the other hand, in the shift register shown in FIG. The seventh transistor 37 and the eighth transistor 38 are both in an on state. 7 is on, the eighth transistor 38 is off, then the seventh transistor 37 is on. By turning off the eighth transistor 38, the second input terminal 22 and The drop in the potential of the node B caused by the drop in the potential of the third input terminal 23 is The number of times the potential of the gate electrode of the transistor 38 is decreased can be reduced to one time. The gate electrodes (lower gate electrode and upper gate electrode) of the seventh transistor 37 are connected to the third A clock signal is supplied from the input terminal of the eighth transistor 38 (the lower A clock signal is supplied from the second input terminal to the gate electrode and the upper gate electrode. If we assume the above relationship, the noise can be reduced by reducing the fluctuation of the potential of node B. Therefore, it is preferable.

[0267] In this manner, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during the period, the pulse output This makes it possible to suppress malfunction of the power circuit.

[0268] (Embodiment 9) A thin film transistor is manufactured, and the thin film transistor is used in a pixel portion and further in a driver circuit. It is possible to manufacture a semiconductor device (also called a display device) having a display function. The transistors and part or the entire driver circuit are integrated on the same substrate as the pixel section, An on-panel can be formed.

[0269] The display device includes a display element. The display element may be a liquid crystal element (also called a liquid crystal display element), a light-emitting A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element is a light-emitting element that emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. Also, electronic inks and other electronic devices A display medium in which the contrast changes due to thermal effects can also be applied.

[0270] The display device includes a panel in which a display element is sealed, and a controller for the panel. and a module in which an IC or the like including the above is mounted. In the process, the element substrate corresponds to one form before the display element is completed, and the element substrate is The element substrate is provided with a means for supplying a current to the display element in each of the plurality of pixels. The display element may be in a state where only the pixel electrodes of the display element are formed, or a conductive film that becomes the pixel electrodes may be formed. may be in a state after the formation of a film and before etching to form a pixel electrode, All forms apply.

[0271] In this specification, the term "display device" refers to an image display device, a display device, or an optical Also refers to connectors, such as FPC (Flexible Printed Circuit). inted circuit) or TAB (Tape Automated Bon ding tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or the display element is mounted with an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted.

[0272] The appearance and cross section of a liquid crystal display panel, which is one embodiment of a semiconductor device, will be described with reference to FIG. 10(A1) and 10(A2) show thin film transistors 4010 and 4011 and a liquid crystal display. The element 4013 is disposed between the first substrate 4001 and the second substrate 4006 by a sealant 4005. FIG. 10(B) is a plan view of the panel sealed by the above method. Equivalent to the cross-sectional view at -N.

[0273] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this manner, a sealant 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealant 4005, and a second substrate 4006. The liquid crystal layer 4008 is sealed together with the first substrate 4001. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0274] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, A wire bonding method, a TAB method, or the like can be used. FIG. 10A shows an example of mounting a signal line driver circuit 4003 by the COG method. This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0275] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 10B, the thin film transistor included in the pixel portion 4002 is A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 Insulating layers 4041a and 4041b are formed on the thin film transistors 4010 and 4011. 41b, 4042a, 4042b, 4020, and 4021 are provided.

[0276] The thin film transistors 4010 and 4011 are made of the oxide semiconductor shown in the first, second, fifth and sixth embodiments. A highly reliable thin film transistor including a dielectric layer can be applied. The transistor 4011 is the thin film transistor 26 shown in the first, second, fifth and sixth embodiments. 0, 245, 270, and the thin film transistor 4010 for the pixel is a thin film transistor 4 20, 448, 220, 280, and 290 can be used. The thin film transistors 4010 and 4011 are n-channel thin film transistors.

[0277] The oxide semiconductor layer of the thin film transistor 4011 for the driver circuit is A conductive layer 4040 is provided in a position overlapping with the channel formation region. By providing the gate insulating film at a position overlapping the channel formation region of the nitride semiconductor layer, In addition, the amount of change in the threshold voltage of the thin film transistor 4011 can be reduced. The conductive layer 4040 may have the same potential as the gate electrode layer of the thin film transistor 4011. The conductive layer may be different from the first gate electrode layer and may function as the second gate electrode layer. The potential of 4040 may be GND, 0V, or may be in a floating state.

[0278] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. A pixel electrode layer 4030, a counter electrode layer 4031, and a liquid crystal layer 4008 are formed on the liquid crystal layer 4006. The overlapping portion corresponds to a liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0279] The first substrate 4001 and the second substrate 4006 may be light-transmitting substrates. Glass, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Room can be used.

[0280] Also, 4035 is a columnar spacer obtained by selectively etching the insulating film. and the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 is controlled. A spherical spacer may be used. 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the opposing electrodes via conductive particles disposed between the pair of substrates. The electrode layer 4031 can be electrically connected to a common potential line. It is incorporated into material 4005.

[0281] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears in a relatively narrow temperature range, so it is necessary to improve the temperature range. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec. Since the liquid crystal display is optically isotropic, no alignment treatment is required, and the viewing angle dependency is small.

[0282] In addition to the transmission type liquid crystal display device, the present invention can also be applied to a semi-transmission type liquid crystal display device.

[0283] In addition, in a liquid crystal display device, a polarizing plate is provided on the outer side (the viewing side) of the substrate, and a colored layer and a display element are provided on the inner side. In the example shown, the polarizing plate is disposed on the inner side of the substrate. In addition, the laminated structure of the polarizing plate and the coloring layer is not limited to the present embodiment, and the materials and The conditions may be appropriately set according to the manufacturing process conditions. A light-shielding film that functions as a light-shielding film may be provided.

[0284] The thin film transistor 4011 includes an insulating layer 4041a functioning as a channel protection layer and an oxide An insulating layer 4041b is formed to cover the peripheral portion (including the side surface) of the laminate of the compound semiconductor layers. Similarly, the thin film transistor 4010 has an insulating layer 4042a which functions as a channel protective layer. An insulating layer 4042b is formed to cover the periphery (including the side surface) of the stack of oxide semiconductor layers. There are.

[0285] An insulating layer 4041 which is an oxide insulating layer covering the periphery (including the side surface) of the stack of oxide semiconductor layers b, 4042b are a gate electrode layer and a wiring layer (source wiring) formed above or around the gate electrode layer. This increases the distance between the insulation layer and the wiring layer (such as the wiring layer or the capacitance wiring layer) and reduces the parasitic capacitance. The layers 4041a, 4041b, 4042a, and 4042b are the oxide insulating layers shown in the first embodiment. The layers 426a and 426b may be formed using the same material and method. In order to reduce the surface irregularities, the insulating layer 4021 is covered with the insulating layer 4021, which functions as a planarizing insulating film. Here, the insulating layers 4041a, 4041b, 4042a, and 4042b are Using the first embodiment, a silicon oxide film is formed by sputtering.

[0286] In addition, an insulating layer 4020 is formed on the insulating layers 4041a, 4041b, 4042a, and 4042b. The insulating layer 4020 is formed using a material similar to that of the protective insulating layer 403 described in Embodiment 1. Here, the insulating layer 4020 is formed by a nitride film formed by RF sputtering. A silicon film is formed.

[0287] In addition, an insulating layer 4021 is formed as a planarization insulating film. The planarization insulating layer 404 may be formed using the same material and method as in the first embodiment. , acrylic resin, benzocyclobutene resin, polyamide, epoxy resin, etc. In addition to the above organic materials, low dielectric constant materials (L ow-k materials), siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron glass) In addition, a plurality of insulating films made of these materials can be laminated. In this way, the insulating layer 4021 may be formed.

[0288] In this embodiment, a plurality of thin film transistors in a pixel portion are surrounded by a nitride insulating film. The insulating layer 4020 and the gate insulating layer may be formed using a nitride insulating film as shown in FIG. In order to achieve this, an insulating layer 4020 is provided so as to surround at least the periphery of the pixel portion of the active matrix substrate. In this manufacturing process, the external In addition, when the semiconductor device is used as a display device, for example, Even after the design is completed, it can prevent moisture from entering from the outside for a long period of time, ensuring long-term reliability of the device. This can improve reliability.

[0289] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, the organic group may have a fluoro group. That's fine.

[0290] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife The baking process of the insulating layer 4021 and the annealing of the semiconductor layer can be performed by using a fcoater or the like. By using both, a semiconductor device can be manufactured efficiently.

[0291] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Transparent conductive materials such as indium zinc oxide and indium tin oxide doped with silicon oxide Materials can be used.

[0292] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer. The conductive composition may be used to form the conductive film. The pixel electrode thus fabricated has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity be 0.1 Ω·cm or less.

[0293] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0294] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials are applied to 002 via FPC4018.

[0295] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layers of the thin film transistors 4010 and 4011. The drain electrode layer is formed of the same conductive film as the drain electrode layer.

[0296] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. The electrodes are electrically connected to each other.

[0297] In FIG. 10, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. The embodiment is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. It may be implemented.

[0298] FIG. 19 shows a semiconductor device using a TFT substrate manufactured by the manufacturing method disclosed in this specification. 1 shows an example of a liquid crystal display module.

[0299] FIG. 19 shows an example of a liquid crystal display module, in which a substrate 2600 and an opposing substrate 2601 are made of a sealing material. 2602, and a pixel portion 2603 including a TFT and a display element including a liquid crystal layer are disposed between them. A color layer 2605 is provided to form a display area. - In the case of the RGB method, coloring corresponding to the colors red, green, and blue is required for display. A layer is provided for each pixel. The light source is a cold cathode fluorescent lamp 261. 0 and a reflector 2611, and the circuit board 2612 is a flexible wiring board 260 9 is connected to the wiring circuit section 2608 of the substrate 2600, and a control circuit, a power supply circuit, etc. In addition, a retardation plate is placed between the polarizing plate and the liquid crystal layer. It may be laminated in the form of a single layer.

[0300] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) irefringence mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0301] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0302] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0303] (Embodiment 10) An example of electronic paper will be shown as one mode of a semiconductor device.

[0304] Electronic paper is also called an electrophoretic display (electrophoretic display) and has the same properties as paper. The advantages are ease of reading, lower power consumption compared to other display devices, and the possibility of making them thin and lightweight. It has points.

[0305] Electrophoretic displays can take a variety of forms, but the first particle has a positive charge. A microcapsule containing a negatively charged second particle and a negatively charged second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particles and the second particles are different in color (colorless). (including

[0306] Thus, electrophoretic displays operate in such a way that materials with high dielectric constants migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect.

[0307] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. A color display is also possible by using a color filter or particles having a pigment.

[0308] In addition, the above microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. Display can be achieved by applying an electric field to the cell. An active matrix substrate obtained by thin film transistors can be used.

[0309] The first particles and the second particles in the microcapsules are made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of magnetochromic material, magnetophoretic material, and a composite material thereof. Just use it.

[0310] FIG. 18 shows an active matrix type electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the device is the thin film transistor shown in the embodiment mode 1. The thin film transistor can be fabricated in the same manner as the conventional thin film transistor, and is highly reliable, including an oxide semiconductor layer. The thin film transistors shown in the second, fifth and sixth embodiments are also used as the thin film transistor 581 of this embodiment. It can also be applied.

[0311] The electronic paper in FIG. 18 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. A potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying information by controlling the orientation of spherical particles caused by the generation of light.

[0312] The thin film transistor 581 formed on the substrate 580 is a bottom-gate thin film transistor. The thin film transistor 581 is covered with an insulating film 583 that is in contact with the semiconductor layer. The first electrode layer 587 and the insulating layer 585 are formed as a source electrode layer or a drain electrode layer. The first electrode layer 587 is formed on the substrate 596 and is electrically connected to the first electrode layer 587 through the opening. Between the second electrode layer 588 and the black area 590a and the white area 590b, A spherical particle 589 is provided that includes a cavity 594 that is filled with a liquid, the spherical particle The periphery of the electrode 589 is filled with a filler 595 such as a resin. The second electrode layer 588 corresponds to a thin film transistor. The transistor 581 is electrically connected to a common potential line provided on the same substrate. The second electrode layer 588 and the common electrode layer 589 are connected to each other through conductive particles disposed between the pair of substrates by using a part. The position line can be electrically connected to the

[0313] Also, instead of the element using the twist ball, an electrophoretic element can be used. A transparent liquid is enclosed in a 1 mm diameter tube containing positively charged white particles and negatively charged black particles. Microcapsules with a size of about 0 μm to 200 μm are used. The microcapsules placed between the first and second electrode layers are subjected to an electric field. When the light is turned on, the white particles and black particles move in opposite directions, resulting in a white or black display. A display element that applies this principle is an electrophoretic display element, commonly known as electronic paper. Since electrophoretic display elements have a higher reflectivity than liquid crystal display elements, the auxiliary lines No light is required, the power consumption is low, and the display can be seen even in dimly lit places. In addition, even if power is not supplied to the display unit, the image once displayed is retained. Therefore, it is possible to transmit a signal from a radio wave source to a semiconductor device with a display function (simply a display device or a display). The displayed image is preserved even if the device (also called a semiconductor device having a display device) is moved away. It is possible to keep it.

[0314] Through the above steps, electronic paper having high reliability as a semiconductor device can be manufactured. .

[0315] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0316] (Embodiment 11) An example of a light-emitting display device is shown as a semiconductor device. is shown using a light-emitting element that uses electroluminescence. The light-emitting element that uses the light-emitting material is classified into two types according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter an inorganic EL element.

[0317] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into layers containing light-emitting organic compounds, causing a current to flow. The rears (electrons and holes) recombine to form an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0318] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0319] FIG. 12 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0320] The configuration of a pixel to which digital time gray scale driving can be applied and the operation of the pixel will be described. The figure shows an n-channel transistor that uses an oxide semiconductor layer as a channel formation region in one pixel. Here is an example of using two of them.

[0321] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, The switching transistor 64 has a light emitting element 6404 and a capacitor element 6403. 01 has a gate connected to a scanning line 6406 and a first electrode (one of the source and drain electrodes) The first electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is connected to a drive The driving transistor 6402 is connected to the gate of the driving transistor 6402. The gate is connected to a power supply line 6407 via a capacitor element 6403, and the first electrode is connected to a power supply line 640 7, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. The driving transistor 640 is electrically connected to a common potential line formed on the substrate. 2 is a driving transistor for the light emitting element 6404 .

[0322] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. Note that the low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. In order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or higher than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0323] The capacitor 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. It is also possible to set the gate capacitance of the driving transistor 6402 as follows: A capacitance may be formed between the gate electrode and the second electrode.

[0324] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is The driving transistor 6402 is in two states, either fully on or fully off. A video signal is inputted, that is, the driving transistor 6402 is operated in a linear region. In order to operate the driving transistor 6402 in a linear region, the voltage of the power supply line 6407 must be higher than that of the driving transistor 6402. A high voltage is applied to the gate of the driving transistor 6402. A voltage equal to or higher than (power supply line voltage + Vth of the driving transistor 6402) is applied.

[0325] In addition, when analog gray scale driving is performed instead of digital time gray scale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 12 can be used.

[0326] In the case of performing analog gradation driving, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or higher than the forward voltage of the light emitting element 6401 and the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and should be at least 100% forward voltage. In addition, the video transistor 6402 is designed to operate in the saturation region. By inputting an optical signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is The gate potential of the light emitting element 6402 is set higher than that of the gate of the transistor 6403. Analog gradation drive can be performed by passing a current corresponding to a video signal through 6404.

[0327] Note that the pixel configuration shown in FIG. 12 is not limited to this. For example, A switch, a resistive element, a capacitive element, a transistor, a logic circuit, or the like may be added.

[0328] Next, the configuration of the light emitting element will be described with reference to FIG. 13. Here, the driving TFT is The cross-sectional structure of a pixel will be described using the example of the type shown in Figure 13(A), (B), and (C). Driving TFTs 7001 and 7011, which are TFTs for driving light emitting elements used in semiconductor devices, The thin film transistor 7021 can be manufactured in a manner similar to that of the thin film transistor described in Embodiment 1. The thin film transistors shown in the second, fifth and sixth embodiments are highly reliable. The transistors can also be used as the driving TFTs 7001, 7011, and 7021.

[0329] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and side emission. There are light-emitting elements with a double-sided emission structure that emits light from the side of the pixel. The present invention can also be applied to optical elements.

[0330] A light emitting element having a top emission structure will be described with reference to FIG.

[0331] In FIG. 13A, a driving TFT 7001 is an n-type TFT, and light emitted from a light-emitting element 7002 is FIG. 13A shows a cross-sectional view of a pixel when the light emitting element 70 The cathode 7003 of the TFT 7002 is electrically connected to the driving TFT 7001. A light-emitting layer 7004 and an anode 7005 are laminated in this order on the cathode 7003. and a conductive film formed over the insulating film 7007, having a low work function and reflecting light. For example, Ca, Al, MgAg, AlLi, etc. are preferable. The light-emitting layer 7004 may be composed of a single layer or a plurality of layers. In the case where the cathode is made up of multiple layers, the cathode 7003 An electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are laminated on top of each other in this order. It is not necessary to provide all of these layers. The anode 7005 is a conductive material having a light-transmitting property. The insulating layer is formed using a conductive material, for example, indium oxide containing tungsten oxide, tungsten oxide, Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc A light-transmitting conductive film such as an oxide or an indium tin oxide film containing silicon oxide is used. is also good.

[0332] In addition, a partition wall is formed between the cathode 7003 and the cathode 7008 of the adjacent pixel, covering the ends of each. The partition wall 7009 is made of polyimide, acrylic resin, polyamide, epoxy resin, etc. The partition wall 70 is formed using an organic resin film such as a silicone resin film, an inorganic insulating film, or polysiloxane. 09 is made of a photosensitive resin material, and the side of the partition wall 7009 is formed with a continuous curvature. It is preferable to form the partition wall 7009 so as to have an inclined surface. When the material is used, the step of forming a resist mask can be omitted.

[0333] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 constitutes the light-emitting element 7002. In the case of the pixel shown in FIG. 13A, the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as indicated by the mark.

[0334] Next, a light emitting element having a bottom emission structure will be described with reference to FIG. When 011 is an n-type light emitting element and light emitted from the light emitting element 7012 is emitted to the cathode 7013 side, FIG. 13B shows a cross-sectional view of a pixel. A cathode 7013 of a light-emitting element 7012 is formed on a light-transmitting conductive film 7017. A light-emitting layer 7014 and an anode 7015 are laminated in this order on the cathode 7013. When the anode 15 has a light-transmitting property, a shielding layer for reflecting or blocking light is provided so as to cover the anode. The cathode 7013 may have a film 7016 formed thereon, as in the case of FIG. Various conductive materials with small thermal coefficients can be used. However, the thickness of the material should be The thickness is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). For example, a 20 nm film An aluminum film having a thickness of 700 nm can be used as the cathode 7013. 13(A), even if it is composed of a single layer, multiple layers are laminated. The anode 7015 does not need to transmit light, but as shown in FIG. As in the case of 13(A), the insulating film 13 can be formed using a conductive material having light-transmitting properties. The shielding film 7016 may be made of, for example, a metal that reflects light, but is not limited to a metal film. For example, a resin containing a black pigment may be used.

[0335] In addition, between the conductive film 7017 and the conductive film 7018 of the adjacent pixel, A partition 7019 is provided. The partition 7019 is made of polyimide, acrylic resin, polyamide, or ethylene. The partition wall is formed by using an organic resin film such as a epoxy resin film, an inorganic insulating film, or polysiloxane. The partition wall 7019 is made of a photosensitive resin material, and the side of the partition wall 7019 has a continuous curvature. It is preferable to form the partition wall 7019 so that the partition wall 7019 has an inclined surface. When a resin material is used, the step of forming a resist mask can be omitted.

[0336] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 13B, the light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0337] Next, a light emitting element having a dual emission structure will be described with reference to FIG. In this example, a conductive film 7027 having a light-transmitting property and electrically connected to the driving TFT 7021 is formed on the substrate 7022. A cathode 7023 of the light-emitting element 7022 is formed, and a light-emitting layer 7024 is formed on the cathode 7023. The anode 7025 is laminated in order. The cathode 7023 is, as in the case of FIG. Various conductive materials with small thermal coefficients can be used. However, the thickness of the material should be For example, the cathode 7023 is made of Al having a thickness of 20 nm. The light-emitting layer 7024 can be formed of a single layer, as in FIG. The anode 70 may be configured as a single layer or as a laminate of multiple layers. 25 is formed using a conductive material having a light transmitting property, similar to FIG. It is possible.

[0338] In addition, between the conductive film 7027 and the conductive film 7028 of the adjacent pixel, A partition 7029 is provided. The partition 7029 is made of polyimide, acrylic resin, polyamide, or ethylene. The partition wall is formed by using an organic resin film such as a epoxy resin film, an inorganic insulating film, or polysiloxane. 7029 is made of a photosensitive resin material, and the side of the partition 7029 has a continuous curvature. It is preferable to form the partition wall 7029 so that the partition wall 7029 has an inclined surface. When a resin material is used, the step of forming a resist mask can be omitted.

[0339] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 constitutes the light-emitting element 70. In the case of the pixel shown in FIG. 13C, the light emitted from the light emitting element 7022 is is emitted toward both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0340] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements can also be used as the light-emitting element. It is also possible to provide an L element.

[0341] In addition, a thin film transistor (a TFT for driving a light-emitting element) that controls the driving of the light-emitting element and a light-emitting element In the above example, the current control TFT is electrically connected between the driving TFT and the light emitting element. The configuration may be such that FT is connected.

[0342] The semiconductor device is not limited to the configuration shown in FIG. 13, and may be any of the configurations disclosed in this specification. Various modifications based on the technical concept are possible.

[0343] Next, the appearance and structure of a light-emitting display panel (also called a light-emitting panel) which corresponds to one embodiment of a semiconductor device will be described. The cross section will be described with reference to FIG. 11. FIG. 11 shows a thin film transistor formed on a first substrate. A flat surface of a panel in which a transistor and a light-emitting element are sealed between the second substrate and the substrate by a sealant. 11(B) corresponds to a cross-sectional view taken along line HI in FIG. 11(A).

[0344] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 4505 is formed so as to surround the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. The filling material 4507 is sealed with the sealing material 4507. Highly sealed protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the package in a material such as a film or a cover material.

[0345] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of thin film transistors. In FIG. 11B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45, a thin film transistor 4509 included in a line driver circuit 4503a is illustrated.

[0346] The thin film transistors 4509 and 4510 are the oxide semiconductors shown in the first, second, fifth and sixth embodiments. A highly reliable thin film transistor including a dielectric layer can be applied. The transistor 4509 is the thin film transistor 26 shown in the first, second, fifth and sixth embodiments. 0, 245, 270, and the thin film transistor 4510 for the pixel is a thin film transistor 4 20, 448, 220, 280, and 290 can be used. The thin film transistors 4509 and 4510 are n-channel thin film transistors.

[0347] The oxide semiconductor layer of the thin film transistor 4509 for the driver circuit is formed over the insulating layer 4544. A conductive layer 4540 is provided in a position overlapping with the channel forming region. By providing the MOSFET in a position overlapping the channel formation region of the semiconductor layer, It is possible to reduce the amount of change in the threshold voltage of the thin film transistor 4509. The potential of the gate electrode layer 4540 may be the same as that of the gate electrode layer of the thin film transistor 4509 or may be different. The conductive layer 4 may be formed of a conductive material and may function as a second gate electrode layer. The potential of 540 may be GND, 0V, or may be in a floating state.

[0348] The thin film transistor 4509 includes an insulating layer 4541a functioning as a channel protective layer and an oxide An insulating layer 4541b is formed to cover the peripheral portion (including the side surface) of the laminate of the compound semiconductor layers. Similarly, the thin film transistor 4510 has an insulating layer 4542a serving as a channel protective layer. An insulating layer 4542b is formed to cover the periphery (including the side surface) of the stack of oxide semiconductor layers. There are.

[0349] An insulating layer 4541 which is an oxide insulating layer covering the periphery (including the side surface) of the stack of oxide semiconductor layers b, 4542b are a gate electrode layer and a wiring layer (source wiring) formed above or around the gate electrode layer. This increases the distance between the insulation layer and the wiring layer (such as the wiring layer or the capacitance wiring layer) and reduces the parasitic capacitance. The layers 4541a, 4541b, 4542a, and 4542b are the oxide insulators shown in the first embodiment. The layers 426a and 426b may be formed using the same material and method. In order to reduce the surface unevenness, the insulating layer 4543 is covered with the insulating layer 4543, which functions as a planarizing insulating film. Here, insulating layers 4541a, 4541b, 4542a, and 4542b are implemented as Using the first embodiment, a silicon oxide film is formed by sputtering.

[0350] In addition, an insulating layer 4543 is formed on the insulating layers 4541a, 4541b, 4542a, and 4542b. The insulating layer 4543 is formed using a material similar to that of the protective insulating layer 403 described in Embodiment 1. Here, the insulating layer 4543 is formed by a nitride film formed by an RF sputtering method. A silicon film is formed.

[0351] In addition, an insulating layer 4544 is formed as a planarization insulating film. The planarization insulating layer 404 may be formed using a material and a method similar to those of the planarization insulating layer 404 described in Embodiment 1. Acrylic is used as the insulating layer 4544 .

[0352] In this embodiment, a plurality of thin film transistors in a pixel portion are surrounded by a nitride insulating film. The insulating layer 4543 and the gate insulating layer may be formed using a nitride insulating film as shown in FIG. In order to achieve this, an insulating layer 4543 is provided so as to surround at least the periphery of the pixel portion of the active matrix substrate. In this manufacturing process, the external In addition, when the semiconductor device is used as a display device, for example, Even after the design is completed, it can prevent moisture from entering from the outside for a long period of time, ensuring long-term reliability of the device. This can improve reliability.

[0353] In addition, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 is The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured as a first electrode layer 4517, an electroluminescent layer The light emitting element 4512 and the second electrode layer 4513 are stacked together, but the structure is not limited to the one shown in the figure. The configuration of the light emitting element 4511 can be changed appropriately according to the direction of the light extracted from the element 4511. It is possible.

[0354] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or polysiloxane. An opening is formed on the first electrode layer 4517 using a photosensitive material, and the sidewall of the opening is It is preferable to form the inclined surface so as to have a continuous curvature.

[0355] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it is done or not.

[0356] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511, the second electrode layer A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be a silicon nitride film, A silicon oxynitride film, DLC film, etc. can be formed.

[0357] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are It is supplied by b.

[0358] The connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed from the source of the thin film transistors 4509 and 4510. The source electrode layer and the drain electrode layer are formed from the same conductive film.

[0359] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. The electrodes are electrically connected to each other.

[0360] The second substrate 4506 located in the direction in which light is extracted from the light emitting element 4511 must be transparent. In this case, a glass plate, a plastic plate, a polyester film or A light-transmitting material such as an acrylic film is used.

[0361] In addition, filler 4507 can be inert gas such as nitrogen or argon, or ultraviolet-curing resin. Can be made of oil or thermosetting resin, PVC (polyvinyl chloride), acrylic Resin, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used as a filler. can be used.

[0362] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0363] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Also, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted, and the configuration is not limited to that of FIG.

[0364] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0365] This embodiment mode may be appropriately combined with the configurations described in the first to fourth and sixth to eighth embodiments. It is possible to implement.

[0366] (Embodiment 12) The semiconductor device disclosed in this specification can be applied as electronic paper. Par can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, train rides, etc. It can be used for in-car advertising, display on various cards such as credit cards, etc. An example of an electronic device is shown in Figure 20.

[0367] FIG. 20 shows an example of an electronic book 2700. For example, the electronic book 2700 has a housing 2 The device is made up of two housings, housing 2701 and housing 2703. 03 is integrated with an axis portion 2711, and performs opening and closing operations around the axis portion 2711. This configuration makes it possible to operate like a paper book. .

[0368] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display (display 2705 in FIG. 20) and An image can be displayed on the display unit 2707 in FIG.

[0369] FIG. 20 shows an example in which the housing 2701 is provided with an operation unit. 701, a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The configuration may include a touch panel, a touch screen, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables such as a cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary. This is also fine.

[0370] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0371] (Embodiment 13) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras digital photo frames; mobile phones (also called mobile phones or mobile phone devices); Examples include game machines, mobile information terminals, audio playback devices, and large game machines such as pachinko machines. do.

[0372] FIG. 21A shows an example of a television device. The television device 9600 includes: A display unit 9603 is incorporated in a housing 9601. The display unit 9603 displays images. In this embodiment, the housing 9601 is supported by a stand 9605. The figure shows a configuration in which

[0373] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the display 9603 shows In addition, the remote control unit 9610 can control the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0374] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0375] FIG. 21B shows an example of a digital photo frame. In the frame 9700, a display unit 9703 is incorporated in a housing 9701. 3 is capable of displaying various images, for example images taken with a digital camera. By displaying data, it can function just like a normal photo frame.

[0376] The Digital Photo Frame 9700 is equipped with an operation unit, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section, etc. These components may be installed on the same surface as the display unit, but they may be installed on the side or back. It is preferable to have a digital photo frame with a built-in memory card because it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The captured image data can be displayed on the display portion 9703 .

[0377] The digital photo frame 9700 may also be configured to transmit and receive information wirelessly. It is also possible to wirelessly import and display desired image data.

[0378] FIG. 22(A) shows a portable gaming machine, which is composed of two housings, a housing 9881 and a housing 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in FIG. 22(A) also includes a speaker unit 9884 and a recording medium insertion unit 988. 6, LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration 9889) equipped with a microphone, etc. Of course, the configuration of the portable gaming machine is not limited to the above, and may be at least as described in the present specification. The present invention is not limited to the above, and may be applied to any configuration having the semiconductor device disclosed in the above and other auxiliary equipment. The portable game machine shown in FIG. 22(A) can be used to play a game recorded on a recording medium. The function of reading out the program or data and displaying it on the display unit, and wireless communication with other portable gaming machines The portable gaming machine shown in FIG. 22(A) has the following functions: The functions are not limited to these, and various functions can be provided.

[0379] FIG. 22(B) shows an example of a slot machine, which is a large gaming machine. Slot Machine 9 The slot machine 900 includes a display unit 9903 built into a housing 9901. 900 also includes other operating means such as a start lever and stop switch, a coin slot, Of course, the configuration of the slot machine 9900 is not limited to the above. However, the present invention is not limited to the above, and may be configured to include at least the semiconductor device disclosed in the present specification. The configuration may include appropriate auxiliary equipment.

[0380] FIG. 23A is a perspective view showing an example of a portable computer.

[0381] The portable computer of FIG. 23(A) has an upper housing 9301 and a lower housing 9302 connected to each other. The hinge unit is closed to form an upper housing 9301 having a display unit 9303 and a keyboard. The lower housing 9302 having the base 9304 can be stacked on top of each other, making it easy to carry. This is convenient, and when the user wants to type on the keyboard, the hinge unit needs to be opened. The user can perform input operations by looking at the display portion 9303.

[0382] The lower housing 9302 also includes a keyboard 9304 and a pointing device for inputting data. If the display portion 9303 is a touch input panel, Input operations can be performed by touching the touch panel. The lower housing 9302 has a computing function unit such as a hard disk. It has an external connection port 9305 into which a communication cable conforming to the USB communication standard is inserted. There are.

[0383] The upper housing 9301 further includes a display unit 93 that can be slid and stored inside the upper housing 9301. 07, it is possible to realize a wide display screen. The orientation of the screen of the 9307 can be adjusted by the user. If it is a panel, input operations can be performed by touching a part of the retractable display unit.

[0384] The display unit 9303 or the foldable display unit 9307 may be a liquid crystal display panel, an organic light emitting element, or The display device uses an image display device such as a light-emitting display panel using inorganic light-emitting elements.

[0385] The portable computer shown in FIG. 23A is configured with a receiver and the like, and is also a television. It is possible to receive broadcasts and display images on the display unit or the display unit. The hinge unit connecting the display unit 9301 and the lower housing 9302 is closed. 7. Slide the screen to expose the entire screen, and adjust the screen angle to watch TV broadcasts. In this case, the hinge unit can be opened to display the display unit 9303. Furthermore, it only activates the circuits that display TV broadcasts, so it consumes minimal power. This is useful for portable computers with limited battery capacity. do.

[0386] FIG. 23(B) shows a portable electronic device that can be worn on the user's arm like a wristwatch. FIG. 13 is a perspective view showing an example of a story.

[0387] This mobile phone is a main body having at least a communication device having a telephone function and a battery. A band part 9204 for attaching the body to the arm, and an adjustment part for adjusting the fastening state of the band part to the arm It is composed of a joint part 9205, a display part 9201, a speaker 9207, and a microphone 9208. There are.

[0388] The main body also has an operation switch 9203, which serves as a power input switch and a display switching switch. In addition to the camera switch and the camera start switch, there are also other buttons, such as a button that starts an Internet program. Each function can be associated with a specific function, such as being started.

[0389] Input operations of this mobile phone are performed by touching the display portion 9201 with a finger or an input pen, or by operating the mobile phone. This is done by operating a switch 9203 or by inputting voice into a microphone 9208. 23(B) shows a display button 9202 displayed on a display unit 9201. Input can be made by touching the screen with a finger or other object.

[0390] The main body also includes an imaging device that converts the subject image formed through the photographic lens into an electronic image signal. The camera unit 9206 has a step. Note that the camera unit does not necessarily have to be provided.

[0391] The mobile phone shown in FIG. 23(B) is configured with a television broadcast receiver and the like. It can receive TV broadcasts and display the images on the display unit 9201, and can also store data in memory, etc. It is possible to record television broadcasts in memory by using a storage device. The mobile phone shown in B) may have a function capable of collecting location information such as GPS.

[0392] The display unit 9201 is a light-emitting display panel such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element. The mobile phone shown in FIG. 23(B) is small and lightweight. Therefore, the battery capacity is limited, and the display device used for the display portion 9201 is a low-power display device. It is preferable to use a force actuable panel.

[0393] Although FIG. 23B illustrates an electronic device that is worn on the arm, the electronic device is not limited to this. It is sufficient that the device has a shape that can be carried around.

[0394] (Embodiment 14) In this embodiment, as one form of a semiconductor device, the thin film transistor shown in the first, second, fifth and sixth embodiments is used. An example of a display device having a transistor will be described with reference to FIGS. 24 to 35. An example of a liquid crystal display device using a liquid crystal element as a display element will be described with reference to FIGS. 24 to 35. The TFTs 628 and 629 used in the liquid crystal display devices shown in FIGS. The thin film transistors shown in the first, second, fifth, and sixth embodiments can be applied. It is a thin-film transistor with excellent electrical characteristics and high reliability that can be fabricated in the same manner as in the process shown in 6. The TFT 628 includes a channel protection layer 608, and the TFT 629 includes a channel protection layer 611. The inverted staggered thin film transistor has a semiconductor layer film as a channel formation region.

[0395] First, we will explain the VA (Vertical Alignment) type liquid crystal display device. A VA type LCD is a type of LCD that controls the alignment of liquid crystal molecules in the LCD panel. In a VA type LCD device, when no voltage is applied, the liquid crystal molecules are aligned relative to the panel surface. In this embodiment, the pixels are arranged in a vertical direction. It is designed to divide the area (subpixels) into separate areas and tilt the molecules in different directions. This is called multi-domain or multi-domain design. In the following explanation, A liquid crystal display device in which the display design is taken into consideration will be described.

[0396] 25 and 26 show a pixel electrode and a counter electrode, respectively. FIG. 2 is a plan view of the substrate side on which electrodes are formed, showing a cross-sectional structure corresponding to a cutting line EF shown in the figure. FIG. 24 shows the structure. FIG. 26 shows a plan view of the substrate on which the counter electrode is formed. The following description will be given with reference to these figures.

[0397] FIG. 24 shows a TFT 628, a pixel electrode layer 624 connected thereto, and a storage capacitor 630. The substrate 600 on which the counter electrode layer 640 and the like are formed is laminated on the counter substrate 601. 4 shows the state in which liquid crystal has been injected.

[0398] The counter substrate 601 is provided with a colored film 636, a counter electrode layer 640, and protrusions 64 on the counter electrode layer 640. An alignment film 648 is formed on the pixel electrode layer 624, and a counter electrode An alignment film 646 is also formed on the layer 640 and the protrusions 644. A liquid crystal layer 650 is formed between the first and second electrodes 610 and 611.

[0399] On the substrate 600, a TFT 628, a pixel electrode layer 624 connected thereto, and a storage capacitor 6 The pixel electrode layer 624 includes a TFT 628, a wiring 616, and a storage capacitor 630. The insulating film 620 covering the insulating film 30 and the insulating film 622 covering the insulating film 620 are penetrated by contacts. The TFT 628 is connected to the wiring 618 through a hole 623. The storage capacitor 630 may be formed of a thin film transistor such as a TFT6 The first capacitance wiring 604 and the gate insulating film 606 are formed at the same time as the gate wiring 602 of 28. and a second capacitance wiring 617 formed at the same time as the wirings 616 and 618.

[0400] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a liquid crystal element. It has been made.

[0401] 25 shows a planar structure on a substrate 600. The pixel electrode layer 624 is made of the material shown in the first embodiment. The pixel electrode layer 624 is formed using a slit 625. The slit 625 is formed by This is to control the crystal orientation.

[0402] The TFT 629 and the pixel electrode 626 and storage capacitor 631 connected thereto shown in FIG. The TFT 628, the pixel electrode layer 624, and the storage capacitor 630 can be formed in the same manner. Both the TFT 628 and the TFT 629 are connected to the wiring 616. The pixel of the liquid crystal display is composed of a pixel electrode layer 624 and a pixel electrode 626. The pixel electrode layer 624 and the pixel electrode 626 form a subpixel.

[0403] 26 shows a planar structure of the opposing substrate side. An opposing electrode layer 640 is formed on a light-shielding film 632. The counter electrode layer 640 is preferably formed using the same material as the pixel electrode layer 624. On the counter electrode layer 640, protrusions 644 are formed to control the alignment of the liquid crystal. In FIG. 26, a pixel electrode layer 624 and a pixel electrode layer 626 formed on a substrate 600 are indicated by dashed lines. The counter electrode layer 640, the pixel electrode layer 624, and the pixel electrode layer 626 are arranged to overlap each other. This shows how the system is being used.

[0404] The equivalent circuit of this pixel structure is shown in Figure 27. TFT628 and TFT629 both have gate The line 602 is connected to the wiring 616. In this case, the capacitance wiring 604 and the capacitance wiring 605 are connected to each other. By making the positions different, the operations of the liquid crystal elements 651 and 652 can be made different. That is, the potentials of the capacitance wiring 604 and the capacitance wiring 605 are individually controlled. The orientation of the liquid crystal is precisely controlled to widen the viewing angle.

[0405] When a voltage is applied to the pixel electrode layer 624 having the slit 625, The slit 625 and the protrusion on the opposing substrate 601 side cause distortion of the electric field (diagonal electric field). By arranging the 644 in an alternating pattern, a diagonal electric field is effectively generated, and the liquid crystal By controlling the orientation, the direction in which the liquid crystal is oriented can be made to differ depending on the location. The viewing angle of the LCD panel is expanded by creating a multi-domain structure.

[0406] Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 28 to 31. do.

[0407] 28 and 29 show the pixel structure of a VA type liquid crystal display panel. FIG. 28 shows a cross-sectional structure corresponding to the cutting line YZ shown in the figure.

[0408] In this pixel structure, one pixel has multiple pixel electrodes, each of which is connected to a TFT. Each TFT is configured to be driven by a different gate signal. That is, in a pixel with a multi-domain design, the signals applied to each pixel electrode are independent. The control circuit has a configuration in which the

[0409] The pixel electrode layer 624 is formed by contact holes penetrating the insulating film 620 and the insulating film 622. In the filter 623, the wiring 618 is connected to the TFT 628. In the contact hole 627 penetrating the insulating film 620 and the insulating film 622, , and a wiring 619 is connected to the TFT 629. The gate wiring 603 of T629 is separated so that different gate signals can be applied. On the other hand, the wiring 616 functioning as a data line is connected to the TFT 628 and the TFT 629. The TFT628 and TFT629 are the same as those shown in the first, second, fifth and sixth embodiments. A thin film transistor can be appropriately used. A gate insulating film 606 is formed on the gate insulating film 606 and the capacitance wiring 690 .

[0410] The pixel electrode layer 624 and the pixel electrode layer 626 have different shapes and are separated by a slit 625. The pixel electrode layer 626 is arranged so as to surround the outside of the pixel electrode layer 624 that spreads in a V shape. A voltage is applied to the pixel electrode layer 624 and the pixel electrode layer 626 through the TFT 628. The alignment of the liquid crystal is controlled by changing the polarity of the TFT 629. The equivalent circuit is shown in FIG. 31. The TFT 628 is connected to the gate wiring 602, and the TFT 629 is The TFT 628 and the TFT 629 are both connected to the wiring 616. To give different gate signals to the gate wiring 602 and the gate wiring 603, Therefore, the operation of the liquid crystal element 651 and the liquid crystal element 652 can be made different. By controlling the operation of T628 and TFT629 individually, the liquid crystal element 651 and the liquid crystal element The orientation of the liquid crystals in 652 can be precisely controlled to widen the viewing angle.

[0411] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. A flattening film 637 is formed between the electrode layer 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. FIG. 30 shows the structure of the opposing substrate side. The opposing electrode layer 640 is shared between different pixels. The electrode is connected to the pixel electrode, but a slit 641 is formed therein. The polar layer 624 and the slits 625 on the pixel electrode layer 626 side are arranged so as to interdigitate with each other. This makes it possible to effectively generate an oblique electric field and control the alignment of the liquid crystal. In this case, the orientation direction of the liquid crystal can be varied depending on the location, thereby widening the viewing angle. In FIG. 30, a pixel electrode layer 624 and a pixel electrode layer 626 formed on a substrate 600 are indicated by dashed lines. The counter electrode layer 640, the pixel electrode layer 624, and the pixel electrode layer 626 are arranged to overlap each other. This shows how the system is being used.

[0412] An alignment film 648 is formed on the pixel electrode layer 624 and the pixel electrode layer 626. An alignment film 646 is also formed on the layer 640. The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are formed. The first liquid crystal element 651 is formed by overlapping the pixel electrode layer 626. The liquid crystal layer 650 and the counter electrode layer 640 are overlapped to form a second liquid crystal element 652. The pixel structure of the display panel described in FIG. 28 to FIG. 31 has a first liquid crystal element in one pixel. The liquid crystal display has a multi-domain structure in which a first liquid crystal element and a second liquid crystal element are provided.

[0413] Next, we will explain the in-plane switching type liquid crystal display device. In the in-plane switching type, This method applies an electric field in the horizontal direction to drive the liquid crystal and express gradation. If this is done, the viewing angle can be expanded to approximately 180 degrees. A liquid crystal display device to be used will be described.

[0414] FIG. 32 shows a structure in which an electrode layer 607, a TFT 628, and a pixel electrode layer 624 connected to the TFT 628 are formed. The substrate 600 and the opposing substrate 601 are overlapped and liquid crystal is injected. A colored film 636, a flattening film 637, etc. are formed on the counter substrate 601. No counter electrode is provided on the counter substrate 601 side. A liquid crystal layer 650 is formed on the liquid crystal layer 642 with an alignment film 646 and an alignment film 648 interposed therebetween.

[0415] On the substrate 600, an electrode layer 607, a capacitance wiring 604 connected to the electrode layer 607, and a T The capacitance wiring 604 is formed at the same time as the gate wiring 602 of the TFT 628. As the TFT 628, the thin film transistor shown in the first, second, fifth and sixth embodiments can be used. The electrode layer 607 may be a pixel electrode layer as described in Embodiment 1. The electrode layer 607 may be formed of a similar material. A gate insulating film 606 is formed on the electrode layer 607 and the capacitance wiring 604. can be.

[0416] The wiring 616 and the wiring 618 of the TFT 628 are formed on the gate insulating film 606. 6 is a data line that carries a video signal in a liquid crystal display panel and is a wiring that extends in one direction. At the same time, the source region or drain region of the TFT 628 is connected to the source and drain regions. The wiring 618 serves as the other electrode of the source and drain, and the pixel electrode layer This is the wiring that connects to 624.

[0417] An insulating film 620 is formed on the wiring 616 and the wiring 618. A pixel electrode connected to the wiring 618 is formed through a contact hole 623 formed in the insulating film 620. The pixel electrode layer 624 is formed in the same manner as the pixel electrode layer shown in the first embodiment. It is formed using a material.

[0418] In this manner, the TFT 628 and the pixel electrode layer 624 connected thereto are formed on the substrate 600. The storage capacitor is formed between the electrode layer 607 and the pixel electrode layer 624.

[0419] 33 is a plan view showing the configuration of a pixel electrode. The surface structure is shown in Figure 32. The pixel electrode layer 624 is provided with a slit 625. The liquid crystal alignment layer 625 is for controlling the alignment of the liquid crystal. In this case, the electric field is applied to the electrode layer 607 and The gate insulating layer 607 is located between the pixel electrode layer 624 and the pixel electrode layer 624. The thickness of the gate insulating film 606 is 50 to 200 nm. Since the thickness of the liquid crystal layer is about 10 μm, the thickness of the substrate 600 is substantially parallel to the substrate 600. An electric field is generated in the horizontal direction. This electric field controls the alignment of the liquid crystal. The liquid crystal molecules are rotated horizontally using an electric field in a nearly parallel direction. Since the display is horizontal even in this state, the effect of contrast on the viewing angle is minimal, and the viewing angle is wide. In addition, since the electrode layer 607 and the pixel electrode layer 624 are both light-transmitting electrodes, , the aperture ratio can be improved.

[0420] Next, another example of a liquid crystal display device of the lateral electric field type will be described.

[0421] Figures 34 and 35 show the pixel structure of an IPS type liquid crystal display device. Figure 35 is a plan view. The cross-sectional structure corresponding to the section line VW shown in the figure is shown in FIG. The following description will be given with reference to these two figures.

[0422] FIG. 34 shows a substrate 600 on which a TFT 628 and a pixel electrode layer 624 connected thereto are formed, The opposing substrate 601 is overlapped and liquid crystal is injected. A coloring film 636, a flattening film 637, etc. are formed on the opposing substrate 601 side. An alignment film 646 and an alignment film 647 are provided between the substrate 600 and the counter substrate 601. A liquid crystal layer 650 is formed via 48 .

[0423] A common potential line 609 and a TFT 628 are formed on the substrate 600. 9 can be formed simultaneously with the gate wiring 602 of the TFT 628. For this purpose, the thin film transistors described in any of the first, second, fifth and sixth embodiments can be applied.

[0424] The wiring 616 and the wiring 618 of the TFT 628 are formed on the gate insulating film 606. 6 is a data line that carries a video signal in a liquid crystal display panel and is a wiring that extends in one direction. At the same time, the source region or drain region of the TFT 628 is connected to the source and drain regions. The wiring 618 serves as the other electrode of the source and drain, and the pixel electrode layer This is the wiring that connects to 624.

[0425] An insulating film 620 is formed on the wiring 616 and the wiring 618. A pixel electrode connected to the wiring 618 is formed through a contact hole 623 formed in the insulating film 620. The pixel electrode layer 624 is formed in the same manner as the pixel electrode layer shown in the first embodiment. As shown in FIG. 35, the pixel electrode layer 624 is formed by using a material. The interdigital electrode is formed at the same time as the pixel electrode 09 so that a horizontal electric field is generated. The comb-tooth portion of the layer 624 alternately interdigitates with the comb-shaped electrode formed at the same time as the common potential line 609. It is formed as follows.

[0426] When an electric field is generated between the potential applied to the pixel electrode layer 624 and the potential of the common potential line 609, The orientation of the liquid crystal is controlled by this electric field. Rotate the molecules horizontally. In this case, the liquid crystal molecules are horizontal in any state, so the viewing angle This has little effect on contrast, etc., and results in a wider viewing angle.

[0427] In this manner, the TFT 628 and the pixel electrode layer 624 connected thereto are formed on the substrate 600. The storage capacitor is provided with a gate insulating film 606 between a common potential line 609 and a capacitor electrode 615. The capacitance electrode 615 and the pixel electrode layer 624 are formed through a contact hole 63. It is connected via 3.

[0428] Through the above steps, a liquid crystal display device can be manufactured as a display device. The liquid crystal display device has a high aperture ratio.

[0429] (Embodiment 15) In this embodiment, the size of the liquid crystal display panel exceeds 10 inches, and is 60 inches or even When using a 120-inch display, the wiring resistance of the light-transmitting wiring may become a problem. An example in which a part of the gate wiring is made into a metal wiring to reduce the wiring resistance will be shown.

[0430] In FIG. 36(A), the same reference numerals are used for the same parts as in FIG. 3(A), and detailed explanations of the same parts will be omitted. Note that this embodiment mode is applicable to the active matrix substrate shown in Embodiment Mode 1. It can be used.

[0431] 36(A) and (B) show an example in which the gate electrode layer of the thin film transistor of the driving circuit is made of metal wiring. In the driver circuit, the material of the gate electrode layer is not limited to a light-transmitting material. In order to form metal wiring, the number of photomasks is smaller than that in the first and second embodiments. increase.

[0432] In FIG. 36A, a thin film transistor 260 of the driving circuit is formed on a first metal wiring layer 242. A gate electrode layer is formed by laminating a second metal wiring layer 241 on the first metal wiring layer 241. 42 can be formed using the same material and process as the first metal wiring layer 236. The second metal wiring layer 241 is formed of the same material and in the same process as the second metal wiring layer 237. This can be done.

[0433] Similarly, in FIG. 36B, the thin film transistor 270 of the driving circuit is formed of the first metal wiring layer A gate electrode layer is formed by laminating a second metal wiring layer 243 on the first metal wiring layer 244. The wiring layer 244 can be formed using the same material and process as the first metal wiring layer 236. The second metal wiring layer 243 is formed of the same material and in the same process as the second metal wiring layer 237. It can be achieved.

[0434] In addition, when the first metal wiring layer 242 and the conductive layer 267 are electrically connected to each other, The second metal wiring layer 241 for preventing oxidation of the wiring layer 242 is preferably a metal nitride film. Similarly, when the first metal wiring layer 244 and the conductive layer 277 are electrically connected, the first The second metal wiring layer 243 for preventing oxidation of the metal wiring layer 244 is a metal nitride film. preferable.

[0435] First, a layer capable of withstanding a first heat treatment for dehydration or dehydrogenation is formed on the substrate 200. A heat-resistant conductive material film (thickness: 100 nm or more and 500 nm or less) is formed.

[0436] In this embodiment, a tungsten film with a thickness of 370 nm and a tantalum nitride film with a thickness of 50 nm are used. Here, the conductive film is a laminate of a tantalum nitride film and a tungsten film. It is not limited, and an element selected from Ta, W, Ti, Mo, Al, Cu, or the above-mentioned elements An alloy film having the above-mentioned elements as components, an alloy film having the above-mentioned elements as components, The heat-resistant conductive material film is not limited to a single layer containing the above-mentioned elements, and may be a bilayer. A stack of more than one layer may be used.

[0437] A metal wiring is formed by a first photolithography process, and a first metal wiring layer 236 and a second The first metal wiring layer 237, the first metal wiring layer 242 and the second metal wiring layer 241, A line layer 244 and a second metal wiring layer 243 are formed. Etching is done using ICP (Inductively Coupled Plasma) It is recommended to use the ICP etching method. Conditions (power applied to the coil-type electrode, power applied to the board-side electrode, By appropriately adjusting the electrode temperature, etc., the film can be etched into the desired tapered shape. By forming the first metal wiring layer 236 and the second metal wiring layer 237 in a tapered shape, Therefore, it is possible to reduce defects in the formation of a light-transmitting conductive film formed in contact therewith above.

[0438] Next, a light-transmitting conductive film is formed, and then a gate is formed by a second photolithography process. A gate wiring layer 238 and a gate electrode layer of the thin film transistor 220 are formed. The conductive film is formed using the conductive material having a visible light-transmitting property described in Embodiment 1.

[0439] Depending on the material of the conductive film having light transmitting properties, for example, the gate wiring layer 238 may be a first gold If there is an interface in contact with the metal wiring layer 236 or the second metal wiring layer 237, it may be difficult to perform subsequent heat treatment, etc. Therefore, an oxide film is formed, which may increase the contact resistance. Therefore, the second metal wiring layer 237 It is preferable to use a metal nitride film that prevents the first metal wiring layer 236 from being oxidized.

[0440] Next, a gate insulating layer, an oxide semiconductor layer, and the like are formed in the same steps as those in the first embodiment. In this process, an active matrix substrate is manufactured according to the first embodiment.

[0441] In FIG. 36(A) and (B), the gate wiring layer 238 overlapping a part of the second metal wiring layer 237 is As shown in FIG. 1, the gate wiring covers the entire first metal wiring layer 236 and the second metal wiring layer 237. That is, the first metal wiring layer 236 and the second metal wiring layer 237 may be a gate The wiring layer 238 can be called an auxiliary wiring for reducing the resistance.

[0442] In the terminal section, a first terminal electrode having the same potential as the gate wiring is provided on the protective insulating layer 203. The wiring from the terminal portion is also made of metal. Formed by wiring.

[0443] In addition, the gate wiring layer and the capacitance wiring layer in the non-display area are made to have low wiring resistance. Metal wiring, that is, the first metal wiring layer 236 and the second metal wiring layer 237 are used as auxiliary wiring. It can also be used.

[0444] In this embodiment, the wiring resistance is reduced by partially using metal wiring, and the size of the liquid crystal display panel is Even if the display size exceeds 10 inches and is increased to 60 inches or even 120 inches, It is possible to achieve high definition and a high aperture ratio.

Claims

[Claim 1] A first thin film transistor and a second thin film transistor are included, the first thin film transistor includes a stack of a first oxide semiconductor layer and a second oxide semiconductor layer overlapping a first gate electrode layer with a first gate insulating layer interposed therebetween; the second thin film transistor includes a third oxide semiconductor layer overlapping with a second gate electrode layer with a second gate insulating layer interposed therebetween; a stack of the first oxide semiconductor layer and the second oxide semiconductor layer is in contact with an oxide insulating layer covering a periphery and a side surface; the semiconductor device further comprising a source electrode layer and a drain electrode layer over the oxide insulating layer and electrically connected to the second oxide semiconductor layer.

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