Information processing system, information processing apparatus, server device, program, reconfigurable device, or method

Abstract

To provide an information processing system, an information processing apparatus, a server device, a reconfigurable device, a program, and a method that more appropriately utilize a reconfigurable device.SOLUTION: A system includes: an acquisition unit that acquires information indicating a first resource from a user; a specification unit that specifies a first reconfigurable device corresponding to the information indicating the first resource; and an instruction unit that instructs the first reconfigurable device to write a first partition shell corresponding to the information indicating the first resource. The acquisition unit further acquires information indicating a second resource that is different from the information indicating the first resource, and the instruction unit instructs the first reconfigurable device to write a second partition shell different from the first partition shell corresponding to the information indicating the second resource.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The technology disclosed in this application relates to an information processing system, an information processing device, a server device, a reconfigurable device, a program, or a method. [Background technology]

[0002] In recent years, programmable logic devices, the circuits of which can be modified, have begun to be introduced in various fields. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-135318 A [Patent Document 2] JP 2010-251925 A [Patent Document 3] Japanese Patent Publication No. H7-6080 Summary of the Invention [Problem to be solved by the invention]

[0004] However, there is a situation where technology using reconfigurable devices for distributed processing is not being utilized. Therefore, in order to solve the above problems, various embodiments of the present invention provide an information processing system, an information processing device, a server device, a program, a reconfigurable device, or a method. [Means for solving the problem]

[0005] One embodiment of the present application is an acquisition unit that acquires information indicating the first resource from a user; an identification unit that identifies a first reconfigurable device corresponding to information indicating the first resource; an instruction unit that instructs the first reconfigurable device to write a first partition shell corresponding to information indicating the first resource; A system comprising:

[0006] Another embodiment of the present application is The system, obtaining information indicative of a first resource from a user; identifying a first reconfigurable device corresponding to information indicating the first resource; instructing the first reconfigurable device to write a first partition shell corresponding to information indicating the first resource; How to do it.

[0007] Another embodiment of the present application is The system, means for acquiring information indicating a first resource from a user; means for identifying a first reconfigurable device corresponding to the information indicating the first resource; a means for instructing the first reconfigurable device to write a first partition shell corresponding to information indicating the first resource; A program to operate as. Effect of the Invention

[0008] According to an embodiment of the present invention, reconfigurable devices can be utilized more appropriately. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram of an example showing the relationship between a system according to an embodiment and a reconfigurable device. [Diagram 2] FIG. 2 is a block diagram of an example showing the relationship between a system according to an embodiment and a reconfigurable device. [Diagram 3]FIG. 3 is a block diagram illustrating the functions of a system according to one embodiment. [Figure 4] FIG. 4 is a diagram illustrating a process flow of an example of a system according to an embodiment. [Diagram 5] FIG. 5 is a diagram illustrating an example of a data format of a system according to an embodiment. [Figure 6] FIG. 6 is a diagram illustrating an example of a data format of a system according to an embodiment. [Figure 7] FIG. 7 is a diagram illustrating an example of a data format of a system according to an embodiment. [Figure 8] FIG. 8 is a diagram illustrating a process flow of an example of a system according to an embodiment. [Figure 9] FIG. 9 is a diagram illustrating an example of a data format of a system according to an embodiment. [Figure 10] FIG. 10 is a block diagram illustrating the functions of a system according to one embodiment. [Figure 11] FIG. 11 is a block diagram illustrating the functions of a system according to one embodiment. [Figure 12] FIG. 12 is a diagram illustrating a part of an example of processing of a system according to an embodiment. [Figure 13] FIG. 13 is a diagram illustrating a part of an example of processing of a system according to an embodiment. [Figure 14] FIG. 14 is a diagram illustrating a part of an example of processing of a system according to an embodiment. [Figure 15] FIG. 15 is a diagram illustrating a part of an example of processing of a system according to an embodiment. [Figure 16] FIG. 16 is a diagram illustrating a part of an example of processing of a system according to an embodiment. [Figure 17] FIG. 17 is a diagram illustrating a part of an example of processing of a system according to an embodiment. [Figure 18] FIG. 18 is a diagram illustrating a part of an example of processing of a system according to an embodiment. [Figure 19] FIG. 19 is a diagram illustrating a part of an example of processing of a system according to an embodiment. [Figure 20] FIG. 20 is a diagram illustrating a part of an example of processing of a system according to an embodiment. [Figure 21] FIG. 21 is a diagram illustrating a part of an example of processing of a system according to an embodiment. [Figure 22] FIG. 22 is a block diagram illustrating the functions of a system according to one embodiment. [Diagram 23] FIG. 23 is a diagram illustrating a process flow of an example of a system according to an embodiment. [Figure 24] FIG. 24 is a block diagram illustrating an example of a configuration of a system according to an embodiment.

[0010] 1. Overview An example of the technology disclosed in the present application relates to a rewritable circuit. However, an example of the technology may be used in an information processing device including a non-rewritable circuit. In the present application, the rewritable circuit is also called a programmable logic device, etc., and in the present application, these are all referred to as a reconfigurable device. On the other hand, the non-rewritable circuit is sometimes called an instruction decoding system, a von Neumann type device, etc., and in the present application, these are all referred to as a program variable device.

[0011] Examples of reconfigurable devices include PAL (Programmable Array Logic), PLA (Programmable Logic Array), GAL (Generic Array Logic), CPLD (Complex Programmable Logic Device), FPGA (Field Programmable Gate Array), and CGRA (Coarse-Grained Reconfigurable Array).

[0012] In the following of this application, the reconfigurable device will be mainly described using an FPGA, but it goes without saying that the present invention can be applied to other reconfigurable devices instead of the FPGA. In particular, the reconfigurable device may be capable of partial reconfiguration, that is, a function that allows multiple regions (e.g., PR regions) in one programmable logic device to be written independently of each other, and may be capable of processing each region as described below. Here, being able to write independently of each other may include a function that allows writing to another region in one programmable logic device that is different from the one region while processing is being performed in the one region in the one programmable logic device.

[0013] In this application, the term "information processing device" is used as a generic term for both reconfigurable devices and programmable devices.

[0014] In addition, the following first to fourth systems are independent inventions, but in the explanation of the following second to fourth systems, explanations of terms that are the same as those in the first system will be omitted unless there are circumstances specific to each system.

[0015] 2. Example of the first system The system of this example relates to a system that provides a user with hardware resources into which a hypervisor shell and a partition shell including a communication function are written before the user writes an application. Such a system has the advantage of being able to appropriately provide the user with hardware resources of a reconfigurable device.

[0016] The system of this example may be configured with one or more information processing devices. The one or more information processing devices may be configured with one or more FPGAs and / or one or more programmable devices.

[0017] Moreover, the system of this embodiment may be connected to one or more FPGAs, which has the advantage of being able to manage one or more FPGAs.

[0018] FIG. 1 shows an example in which the system of this example is connected to one or more FPGAs. The system (001) of this example is connected to FPGA1 (0021) to FPGA4 (0024). Such connection may be via Ethernet or via a bus such as PCI Express. The system of this example may be connected only to one or more FPGAs as a computation function for executing a user's application. In this case, a programmable device may be connected as a hardware resource for executing functions other than the computation function for executing a user's application.

[0019] The system of this example may be connected to one or more FPGAs and may also be connected to one or more programmable devices. In this case, the system of this example has the advantage that it can manage distributed processing including the programmable devices in addition to managing the FPGAs.

[0020] In the case where the system of the present example is connected to one or more FPGAs and / or one or more programmable devices, the connection may be directly or indirectly connected via a network. The one or more FPGAs may be installed in the same facility as the system of the present example, or in a different facility. The specific location of the one or more FPGAs may be any. For example, the one or more FPGAs may be installed inside a building (indoors) or outside a building (outdoors). IoT devices such as sensors may operate inside and / or outside a building, and these may be implemented by FPGAs. The network may be wired, wireless, or a mixture of these.

[0021] FIG. 2 shows a state in which the system of this example is connected to an FPGA and a programmable device via a network (000). In this figure, an example of a configuration including multiple FPGAs and programmable devices in an FPGA group (002). Here, CPU1 and CPU2 are written to indicate the programmable devices, and for convenience, these are also shown as part of the FPGA group. In addition, the FPGA group (003) includes multiple FPGAs and an information processing device including an FPGA writer function. Such an FPGA writer may be capable of both writing a bitstream to the FPGA group (003) and writing a bitstream to the FPGA group (002). The network in these FPGA groups (002) and (003) may be a bus, Ethernet, or the like.

[0022] The system of this example, the one or more FPGAs described above, and / or the one or more programmable devices described above may be an information processing device on the cloud.

[0023] 2.1. System Functions The system of this example may include a database unit that contains FPGA information, and a management unit that manages the information in the database unit. Figure 3 illustrates an example of such functionality.

[0024] 2.1.1. Management Department The management unit has a function of managing processing. Here, processing may include, for example, a function of providing information, a function of accepting information, a function of transmitting information, and / or a function of receiving information. Furthermore, the information to be provided, accepted, transmitted, and received may be the same or different.

[0025] For example, the management unit may have a function of providing information to a user. In this case, the system of this example has the advantage of providing information to the user and enabling the user to make a meaningful decision. The management unit may also have a function of accepting information input by the user. In this case, the system of this example has the advantage of being able to use the information accepted from the user. The management unit may also have a function of transmitting information to the FPGA. In this case, the system of this example has the advantage of being able to affect the FPGA by the information transmitted to the FPGA. The management unit may also have a function of receiving information from the FPGA. In this case, the system of this example has the advantage of being able to manage the status of the FPGA by the information received from the FPGA. These details will be described later.

[0026] 2.1.2.Database section The database unit has a function of storing information about the FPGA. In particular, the database may store one or more pieces of resource information, which will be described later. The database unit may also store other information. By providing the database unit in the system of this example, there is an advantage in that the FPGA information managed by the system of this example can be used.

[0027] 2.2.Processing flow An example of this system will be described in two stages: a preparation stage and an operation stage. The preparation stage may be a stage carried out when a new FPGA is connected to the system. Such cases include, for example, a case where an FPGA is added or a case where a conventional FPGA is changed. A case where a conventional FPGA is changed may include a case where a configuration within the conventional FPGA is changed. The operation stage may be a stage for a system for which the preparation stage has been completed.

[0028] 2.2.1. Preparation Phase The preparation stage will be explained with reference to FIG.

[0029] Step 1 First, the system of this embodiment and the FPGA may be connected to each other so as to enable signal communication. Such a connection may be wired or wireless so as to enable signal communication.

[0030] Such a connection may be made when adding a new FPGA, when changing the physical configuration of the FPGA due to repairs, etc., but is not limited to these.

[0031] Such connections may also include connecting FPGAs together via a network, and connecting an FPGA to an information processing device including another CPU via a network.

[0032] Step 2 The system of this embodiment may support a process of writing a hypervisor shell to a connected FPGA. A known technique may be used for writing to the FPGA.

[0033] The hypervisor shell may be written automatically by the system of this embodiment, or may be written manually.

[0034] The hypervisor shell may be written in any programming language. When the hypervisor shell is written, it may be converted into a bitstream and written to the FPGA using known techniques, such as via JTAG or USB.

[0035] The hypervisor shell to be written may be one that corresponds to the type and functions of the target FPGA.

[0036] The hypervisor shell does not need to have all the functions of the hypervisor shell described below as long as it can provide the FPGA with a communication function with the management unit by being written into the FPGA. By writing the hypervisor shell in this step, the system of this example becomes able to communicate with the FPGA in which the hypervisor shell is written.

[0037] Step 3 The system of this example may assist in registering information about the physically connected FPGA in a database. By registering information about the FPGA in advance in the database, the system of this example has the advantage that it can use the information about the FPGA via the information held in the database.

[0038] Such a database may or may not utilize a database management system as long as it is capable of storing the information described below. If there is a data model on which the database is based, the type may be of various types, such as a hierarchical type, a network type, a relational data model, an object data model, etc., and is not limited thereto. Furthermore, the hardware resources that realize such a database may be a dedicated device or a general-purpose device, or may be various information processing devices such as a cloud or a server.

[0039] When the system of the present embodiment uses a database, it is sufficient that the system can access the database, and the system of the present embodiment may or may not include a database. In the latter case, it is sufficient that the system of the present embodiment can be directly or indirectly connected to the database via a network or the like.

[0040] The database may store information that actually identifies an FPGA and information on the functions of the FPGA (sometimes referred to as "resource information" in the present application) in association with each other. The resource information may include, for example, the type of reconfigurable device, attributes related to the arithmetic unit, attributes related to the storage device, and / or attributes related to the communication device. The attributes related to the arithmetic unit may include, for example, the type of arithmetic unit, the number of arithmetic units such as the number of cells, the capabilities of the arithmetic unit such as the clock frequency, and / or the power used by the arithmetic unit. The arithmetic unit may include, for example, logic elements (LE), logic cells (LC), and / or LUTs (look-up tables). The attributes related to the storage unit may include, for example, the type of storage unit, the capacity of the storage unit, the read / write speed of the storage unit, and / or the power used by the storage unit. The storage unit may be, for example, an on-chip storage unit in the reconfigurable device, or may be another storage unit installed outside the reconfigurable device. The attributes of the communication device may include attributes of an internal communication device and / or attributes of an external communication device. The attributes of the internal communication device may be information of communication within the FPGA. The attributes of the external communication device may include a network bandwidth and / or a bandwidth speed for communication with the outside.

[0041] Moreover, one FPGA may include one or more PR regions. A PR region is a section whose circuit configuration can be changed independently. For each PR region, the FPGA may be able to execute one or more independent operations using partial reconfiguration, or may be able to execute one or more independent operations without using partial reconfiguration. Since they are independent, for example, when one FPGA includes PR region A and PR region B, PR region A and PR region B may operate independently in terms of rewriting the circuit and executing the circuit. Therefore, PR region B may be able to be rewritten while PR region A is executing.

[0042] In this application, "one" resource information may be one unit that can be used as a hardware resource by a user. Therefore, if an FPGA is not managed in units of PR regions, one piece of resource information may be one FPGA, but if an FPGA is managed in units of PR regions and is a hardware resource that can be used for each PR region, one piece of resource information may be one PR region in one FPGA.

[0043] The above-mentioned database may store the above-mentioned resource information in association with each of one or more PR regions included in one FPGA.

[0044] Note that there may be multiple methods for setting PR regions for one FPGA. For example, one FPGA may be divided into two PR regions, PR regions A and B, or into four PR regions, PR regions A to D. When the division methods differ in this way, the resource information for each PR region also differs, so resource information may be associated with a specific PR region in a certain division method and stored.

[0045] 5 shows an example of logically organizing information held in a database in which FPGA resource information is registered. FPGAID indicates an ID assigned to an FPGA actually connected to the system of this example. Since resource information may have the above-mentioned classification, the resource information may be stored in association with the ID of each FPGA.

[0046] 6 is another example of logically arranging information held by a database in which FPGA resource information is registered. This figure shows an example in which multiple PR regions are set for one FPGA. For example, two PR regions are set for an FPGA with an FPGA ID of 001, and three PR regions are set for an FPGA with an FPGA ID of 002. Resource information is set for each PR region. This is because each PR region may have the same resource or may have different resources. In particular, the latter case has the advantage that resource information corresponding to each PR region can be set.

[0047] 7 is another example of logically arranging information held by a database in which FPGA resource information is registered. This figure shows a case where there are multiple PR region division methods for one FPGA. For example, for FPGA ID 001, there are PR region division method 1 and division method 2, where division method 1 is a case where the PR region is divided into two, and division method 2 is set as a method where the PR region is divided into four. As described above, each PR region may have the same resource or may have different resources, so that resource information for each PR region may be stored in association with information identifying each PR region.

[0048] 5 to 7, the database may store information for identifying the type of FPGA in association with information for identifying each actual FPGA. The type of FPGA is required when a user programs in a high-level synthesis language such as VHDL, Verilog, or C, which is a hardware description language (HDL), or when generating a bitstream.

[0049] The database may also store information indicating whether each PR region is in use or not in association with the corresponding PR region, which has the advantage that the information indicating whether the corresponding PR region is in use or not can be used to manage whether the corresponding PR region is being used by a user.

[0050] In addition, the database may store information indicating the PR region being used and information indicating the user using the PR region in association with each other when each PR region is being used. In this case, there is an advantage that the user can be managed when the PR region is being used.

[0051] The database may store information related to the user associated with information indicating the user. The information related to the user may include information about the user that identifies the user in the real world, such as the user's address and email address, the user's ID, a password corresponding to the ID, and / or information related to the service used by the user. The information related to the service may include information about the course of the service for which the user has paid and / or information about options to which the user can subscribe.

[0052] The database may be associated with each FPGA and store information related to licenses for each FPGA. For example, the database may store information indicating the presence or absence of a license required for each FPGA. The database may be associated with each FPGA and store information indicating the type of license required for each FPGA. By storing such license information, it is possible to verify the presence or absence of a license required when using each FPGA and the type of license. The license may be a license for each type of FPGA, a computing function, a storage function, and / or a communication function. This is because the license may differ for each type of FPGA, a computing function, a storage function, and / or a communication function. In particular, the license may be capable of being stored for various licenses such as a low-cost version, a high-cost version, and a license for special purposes. The license may be a license for one FPGA or a package license for multiple FPGAs depending on its nature.

[0053] The database may also include information on licenses held by users in association with the information indicating the users. For example, the database may include information specifying the presence or absence and / or type of licenses held by the users. In this case, there is an advantage in that information indicating what type of FPGA a user has a license to use can be generated or verified.

[0054] The database may also store physical information about the FPGA in association with information indicating the FPGA. The physical information about the FPGA may include, for example, geographical information about where the FPGA is installed. The physical information about the FPGA may also include, for example, the latitude and longitude where the FPGA is installed, the name of the facility where the FPGA is installed, the name of the facility manager who manages the FPGA, and / or management level information of the facility where the FPGA is managed. Such information may be useful as reference information for considering security and response capabilities to incidents regarding the location where the FPGA is installed and its management.

[0055] The database may be composed of a single database for all connectable FPGAs, or may be composed of multiple databases. The latter may be managed separately, for example, into a database for FPGAs in which a partition shell has already been written (described later) and a database for FPGAs in which a partition shell has not yet been written. In the latter case, when the amount of written FPGAs is small, there is an advantage that quick access is possible.

[0056] Such resource information about the FPGA may be manually registered in the database by a person, or may be recorded and registered in the database as information corresponding to the FPGA.

[0057] 2.2.2. Operational Phase The operation stage will be explained with reference to Figure 8. Step 1 The system of this example presents a flavor to the user. A flavor may be a template of virtual hardware. Although flavor is a term used in OpenStack, which is a middleware for virtualization, it may be a similar function in other virtualization middleware. The flavor may be displayed on a display device provided by the system of this example. A flavor may include one or more pieces of resource information for one or more FPGAs. One piece of resource information may include information associated with a device name, a PR shell, a PR region, and / or device information. The PR shell is a shell that manages a PR region, and may refer to the same thing as the partition shell in the present application. By displaying the flavor, there is an advantage that the user can use the resource information to select resource information suitable for a circuit to be written. In particular, as described above, the resource information includes information such as the type of reconfigurable device, attributes related to a computing device, attributes related to a storage device, and / or attributes related to a communication device, and therefore there is an advantage that the resource information suitable for a circuit to be written can be selected.

[0058] FIG. 9 is an example of a flavor. For a device named FPGA1, the PR shell is 1 (displayed as PRS1) and the PR region is displayed as PR1. For a device named FPGA2, a shell capable of managing two PR regions corresponds as a PR shell (displayed as PRS2), and the two PR regions are displayed as PR1 and PR2. A flavor may include information indicating a plurality of PR region setting methods for one physical device. For example, FPGA4 may be divided into two PR regions or into four PR regions. In the former case, the names PR1 and PR2 are given to the two PR regions, and PRS2 corresponds as the shell that manages them. In the latter case, the names PR1 to PR4 are given to the four PR regions, and PRS4 corresponds as the shell that manages them. Here, the method of dividing FPGA4 into two PR regions and four PR regions has been described, but it is not limited thereto. In the case where each FPGA can be divided into any number of PR regions that it can handle, the system of this example may be capable of managing any number of PR regions that correspond to the number. In this case, the system of this example may be capable of managing a combination of the number of PR regions that can be divided and may be included in the flavor. In this way, by presenting multiple division methods for the same device, there is an advantage that the user can select one division from multiple division methods allowed for the physical device. Note that the database may store one or multiple division methods associated with one FPGA device so that such a display can be presented. Note that in this figure, the display includes a PR shell, but such a PR shell may not be present.

[0059] Also, the flavor may include a type of FPGA associated with information indicating one FPGA as an element of the resource information as described above. In this case, there is an advantage that a user can select desired resource information including the type of FPGA. Also, the flavor may include a PR region as an element of the resource information as described above. In this case, there is an advantage that a user can select desired resource information including the resource information. For example, a bitstream of an application written in an FPGA may be generated according to the type of FPGA and / or the PR region. For example, when a program written in a hardware description language or a high-level synthesis language for rewriting an FPGA is compiled to generate a bitstream, there is an advantage that information on the type of FPGA and / or the PR region can be used. This has the advantage of avoiding the problem that a program for rewriting an FPGA may require the FPGA type and / or PR region at the time of compilation, and the compilation may take a significant amount of time, up to several hours, and if the FPGA type and / or PR region associated with the compiled program for the FPGA prepared by the user differs from the FPGA type and / or PR region associated with the hardware resources related to the resource information provided by the system of this example, a new compilation may be required.

[0060] Furthermore, the resource information presented by a flavor may or may not have a one-to-one relationship with resource information in the real world. The former indicates that the resource information presented by the flavor actually exists, and means that, for example, if there are two hardware resources with the same resource information α in reality, two flavors can also present the same information. In this case, there is an advantage in that it is possible to display whether the hardware resource corresponding to the resource information is substantially only one or multiple. On the other hand, the latter means that the resource information presented by a flavor and resource information in the real world may have a one-to-many relationship. For example, this means that if there are two hardware resources with the same resource information α in reality, the flavor will present one such resource information α. ​​In this case, since it is the same resource information, there is an advantage in that the display area can be used effectively.

[0061] Furthermore, a flavor may display both of the above. For example, the resource information presented by the flavor may display one of the one-many relationships with the real-world resource information, while separately presenting a different element as the many. The different element as the many may be, for example, the number of hardware resources related to the real resource information, the installation location where the hardware resource related to the real resource information is installed, or the distance from the system to the location where the hardware resource related to the real resource information is installed. Here, the distance may be a physical distance, as described below, or a distance related to the communication of information.

[0062] The flavor may include and present all resource information that the database has, regardless of whether the device is available to the user or not. In this case, there is an advantage that the user can understand what hardware resources the database has. For example, there is an advantage that the user can understand whether the number of hardware resources including a certain resource information is more than a predetermined number or less than a predetermined number.

[0063] Alternatively, the flavor may include and present one or more pieces of resource information for which there are writable users, regardless of the relationship with a specific user. That is, the flavor may present resource information excluding resource information currently in use. In this case, since resource information already in use is not displayed, there is an advantage that it is easier to select resource information. In this case, additionally, resource information currently in use by the user selecting the resource information may be displayed. In this case, there is an advantage that the user selecting the resource information can select new resource information while referring to the resource information currently in use.

[0064] Alternatively, instead of such a configuration, the flavor may include and present one or more pieces of resource information available to a specific user who selects the flavor. For example, available resource information may be predetermined for a user based on the presence or absence and type of license the user has, or the membership course and terms of the system of this example, and only one or more pieces of resource information available to the user may be presented. Even in this case, the resource information currently being used by the user who selects the resource information may be displayed. In this case, there is an advantage that the user who selects the resource information can select new resource information while referring to the resource information currently being used.

[0065] Alternatively, the flavor may include and present one or more pieces of resource information available to a specific user who selects the flavor, and one or more pieces of resource information available to the specific user when the specific user satisfies specific conditions. Here, the specific conditions may include, for example, obtaining a new license, changing a membership course of the system of this example, and / or obtaining an option for the membership of the system of this example. These specific conditions may also be presented in association with the resource information available when each condition is satisfied. In this case, there is an advantage that the user can understand what conditions must be satisfied in order to select the corresponding resource information.

[0066] The flavor may also include and present physical information about the FPGA, which is advantageous in that the user can select a flavor while taking into account the physical information about the FPGA.

[0067] The physical information about the FPGA may include, for example, geographical information about where the FPGA is installed. The physical information about the FPGA may also include, for example, the latitude and longitude where the FPGA is installed, the name of the facility where the FPGA is installed, the name of the facility manager who manages the FPGA, and / or management level information of the facility where the FPGA is managed. When such information is displayed in association with physical information corresponding to resource information, it may be advantageous to use the location where the FPGA is installed and its management as reference information for considering security and response capabilities to incidents.

[0068] Moreover, the physical information about the FPGA may include information indicating the distance between the FPGAs. The distance between the FPGAs may be a physical distance or a distance related to the communication of information. The former may be a Euclidean distance, and the measurement method may be a straight-line distance between the FPGAs or a distance along a communication network between the FPGAs. The latter distance related to the communication of information may be a distance using the number of hops or the amount of network bandwidth during communication between the FPGAs. In this case, there is an advantage that the distance can be specified based on the communication situation. Furthermore, the above-mentioned distance between the FPGAs may be the distance between the two FPGAs if there are two FPGAs, and may be the sum of the distances between two FPGAs between the three or more FPGAs for three or more FPGAs, or may be the maximum distance when transmitting information between the three or more FPGAs. The above-mentioned distance between the FPGAs may be such that information indicating the distance between the selected multiple FPGAs is calculated and displayed for the selected multiple resource information. In this case, the selection may be provisional.

[0069] The distance between the devices may be displayed using a two-dimensional or three-dimensional graph. In particular, such a graph may be displayed so that each node of the graph is positioned at a position corresponding to the calculated distance between the devices. In this case, there is an advantage that the user can understand more intuitively.

[0070] Furthermore, the flavor may correspond to the type and / or number of PR regions that a partition shell prepared in advance for a certain FPGA can provide, in terms of the PR region that the user can provide for that FPGA. For example, if an administrator prepares PR region 2 and PR region 4 for a certain FPGA in advance, the flavor may include resource information for PR region 2 and / or resource information for PR region 4.

[0071] Furthermore, as described later, when the partition shell has a function of being provided hierarchically, the flavor may include a plurality of patterns that can be provided when the partition shell is written for a PR region that has not been written, even for an FPGA in which the partition shell has already been written. For example, in a case where one PR region (first PR region) has already been written in an FPGA in which a partition shell (first partition shell) for providing two PR regions has been written, if the partition shell is not provided hierarchically, the flavor can provide only the remaining one PR region (second PR region) (even if a partition shell different from the first partition shell that can provide the number and type of multiple PR regions can be provided for the FPGA, in the case where the first PR region has already been written and the first PR region and the first partition shell are not deleted). However, when a partition shell (second partition shell) is written in the second PR region, one or more pieces of resource information may be provided within the scope that the second partition shell can provide.

[0072] In the above description, the flavors are expressed in a table format, but they may be displayed to the user in such a manner, or they may be displayed to the user in various manners without being limited to such a manner.

[0073] Furthermore, in this step, the information presented to the user as flavors has been described; however, in addition to this, all or part of the information stored in the database described in the preparatory stage above may be presented to the user as flavors.

[0074] Step 2 Next, the user selects one or more pieces of resource information from the flavors presented by the system of this example, and the system of this example obtains information identifying the selected one or more pieces of resource information corresponding to the resource information selected by the user.

[0075] In this step, if the flavor of the system of this example presents resource information that has a one-to-one correspondence with resource information in physical hardware resources, information that identifies a hardware resource that has a one-to-one correspondence with the resource information selected by the user may be obtained in response to the resource information selected by the user.

[0076] On the other hand, in the case where the relationship between the resource information in the flavor presented in the above-mentioned flavor and the hardware resources related to the actual resource information is a one-to-many relationship, the system of this example may perform a hardware resource identification process to identify one of such many hardware resources.

[0077] The hardware resource identification process may be performed in various ways. For example, the hardware resource identification process may use information about the user and / or information about the hardware resources utilized by the user.

[0078] In addition, the information relating to the user may be information relating to the user's membership and / or information relating to the user's membership period, etc.

[0079] As an example of using information related to the user's membership period, for example, the system of this example may specify a hardware resource using the length of the user's membership period. For example, the system of this example may perform a process of allocating one of the hardware resources for long-term use when the remaining period of the user's membership period is equal to or longer than a predetermined period. In this case, there is an advantage that the administrator of the system of this example can efficiently perform maintenance of the hardware resources. Also, for example, the system of this example may specify a hardware resource using the remaining period of the user's membership period and the hardware replacement schedule. For example, when the remaining period of the user's membership period is equal to or longer than a predetermined period, the system of this example may not allocate a hardware resource that is within a predetermined period until the replacement time of the hardware resource. Also, when the remaining period of the user's membership period is a first predetermined period, the system of this example may determine the hardware resource based on the hardware resource that is equal to or longer than the first predetermined period until the next replacement time of the hardware resource. In such a case, there is an advantage that when the user's membership period is not extended, there is an advantage that the maintenance of the hardware resource can be efficiently performed. The information regarding the membership period may include the remaining period for which the hardware resources can be used, and / or the total or continuing period from when the user joined the system of this example.

[0080] Furthermore, the information related to the user's membership may include information related to the member's course or status. For example, the system of this example may perform a process of allocating one of the specified hardware resources when the user's membership course is a specified one and / or the member's status is a specified one. Such a specified hardware resource may be a hardware resource with high stability and robustness compared to other hardware resources. In this case, when the user is a specific member or has a specified course, there is an advantage in that a higher quality hardware resource can be used. Note that the information related to the member's course or status may be selected by the user when using the system of this example. For example, it may be obtained by a contract for the purpose of using a certain amount of resource information.

[0081] Furthermore, the information on the hardware resources used by the user may include one or more hardware resources that the user is using at the time of the above-mentioned selection. For example, the system of this example may include, among the actual hardware resources that match the resource information selected by the user, 1) hardware resources in the same FPGA as the FPGA containing the one or more hardware resources currently used by the user, 2) hardware resources in the same local area network or bus as the one or more hardware resources currently used by the user, and / or 3) hardware resources that are close to the one or more hardware resources currently used by the user.

[0082] In the case of 1) above, since the resources are located within the same FPGA, there is an advantage that the hardware resources within the same FPGA can be used by the user for the same or related applications, thereby helping to provide hardware resources that achieve more efficient communication.

[0083] In the case of 2) above, the former same local area network or bus also has the advantage of being able to support the provision of hardware resources that realize more efficient communication because they are in the same network or bus. Note that the identity of the local area network or bus may be of any hierarchical level as long as it can reduce the processing required for communication across the network.

[0084] The above 2) may be a virtual local network. In this case, the physical distance is not necessarily shorter than a certain distance, and the distance involved in the communication of information is not necessarily shorter than a certain distance, but the network has the advantage of being highly secure.

[0085] In the above case of 3), the distance may be the physical distance or the distance related to the communication of information. By selecting the hardware resource that is closest to one or more hardware resources currently being used by the user among the actual hardware resources that match the resource information selected by the user, there is an advantage that it is possible to support the provision of a hardware resource that realizes more efficient communication than the other resources.

[0086] Step 3 Next, the system of this example checks whether one or more hardware resources corresponding to one or more pieces of resource information selected by the user are available. That is, the system of this example attempts to write a partition shell corresponding to the resource information to an FPGA device, which is a hardware resource corresponding to the resource information. This writing may be performed by writing a bit stream, and the information may be transmitted using a TAG or a USB, and there is no limitation to the manner. In addition, the writing technique for the FPGA itself may be a known technique.

[0087] In addition, if the system of this example fails to write the partition shell, the system of this example may display a message indicating that the resource information selected by the user cannot be selected due to the failure to write the partition shell, and the system of this example may display a message prompting the user to select new resource information.

[0088] The partition shell may be the same as or different from the partition shell described below. The partition shell only needs to have a function to support a user in using the hardware resources in the FPGA in which the partition shell is written, and does not need to have all the functions of the partition shell described below.

[0089] Step 4 In the system of this example, when the partition shell is successfully written, information about the successfully written resource information is registered in the database.

[0090] Furthermore, the system of this example may feed back information about the resource information that has been successfully written to the user. There may be various modes of feeding back to the user. For example, the information about the resource information that has been successfully written may be displayed on a display device, emailed to the user, or stored in a predetermined location of the user that is accessible to the user. The information about such resource information may include information that identifies the hardware resource to which the partition shell has actually been written, and the information that identifies such hardware resource may include information that identifies a specific reconfigurable device. The information about such resource information may include the type of FPGA, attributes related to the arithmetic device, attributes related to the storage device, attributes related to the communication device, the PR region, and / or information that identifies the location on the network. For example, the information that identifies the location on the network may be an IP address for an FPGA, and the PR region in the FPGA may be an IP address or a port number.

[0091] The user may be able to access the written PR regions using this information, for example, by writing a program that is an application that the user intends to use in the FPGA and that has been compiled into a bitstream into the corresponding FPGA using such information.

[0092] The system of the present example may use the above information to assist in writing such a user-supplied bitstream into a corresponding FPGA via USB (JTAG), Ethernet, or PCIe.

[0093] In addition, in a different embodiment from the above, the system of this example first selects resource information once by the user, and when an attempt is made to write the PR shell and the selection is not successful,

[0094] In addition, the system of this example may perform a process of managing user membership registration in a stage before step 1 of the operation stage. For example, the system of this example may have a function of managing user registration and modification of user membership information.

[0095] The user registration may be a process in which the system of this example acquires information related to the user described above. For example, the system of this example may present to the user course and / or service options selectable by the user, acquire the course and / or service option selected by the user from the presented course and / or service options, and store the acquired course and / or service option in association with information identifying the user.

[0096] In the process of acquiring information related to the user, the system of this example may acquire information on the orientation of the reconfigurable device used by the user and store the information in association with information identifying the user. The orientation information on the reconfigurable device may include, for example, information on the type of reconfigurable device that the user plans to use, attributes related to the computing device, attributes related to the storage device, and / or attributes related to the communication device. This is because, if a user has a specific type of reconfigurable device that he or she normally uses, it is considered that the user is familiar with that type of reconfigurable device, and therefore the reconfigurable device used in the system of this example is likely to be the same type of reconfigurable device, and therefore convenience may be improved by using such information. Similarly, if the attributes related to the computing device, the attributes related to the storage device, and / or the attributes related to the communication device are in line with the user's orientation, convenience for the user may be improved.

[0097] In addition, the user may directly input the above steps to the system of this example. For example, when the system of this example includes a user terminal used by the user, the above steps may be performed in the system of this example through interaction with the user, and the system of this example may directly display the steps to the user and directly obtain the user's input.

[0098] On the other hand, if the system of this example does not have a display to a user or an input mechanism from a user, the system of this example may be directly or indirectly connected to a user terminal used by a user not included in the system of this example, and the above steps may be carried out by interaction between the system of this example and one or more user terminals. For example, in the above step 1, information including a flavor may be transmitted from the system of this example to a user terminal, and the information including the flavor may be displayed on the user terminal. In the above step 2, resource information selected on the user terminal may be transmitted from the user terminal to the system of this example, and the resource information may be received by the system of this example. In the above step 3, the system of this example may check whether or not a hardware resource corresponding to the resource information is available. In the above step 4, the system of this example may register in a database.

[0099] Regardless of whether the system of this example includes a terminal used by a user or not, the reconfigurable device to which the partition shell is written in step 3 may be a part of the system of this example or may be external to the system of this example. Also, the database registered in step 4 may be a part of the system of this example or may be external to the system of this example.

[0100] 3. Second System The second system may be related to a reconfigurable device. For example, the second system may be a reconfigurable device itself in which the functions described below are implemented as functions to be written into an FPGA, a bitstream that realizes the functions described below when written into a reconfigurable device, or a program written in an HDL description language that is compiled and converted into such a bitstream. As described above, the following description is mainly given using an FPGA, but the second system can also be implemented in a reconfigurable device instead of an FPGA.

[0101] 3.1. System Functions The functions written into the FPGA may include functions processed by the hypervisor shell (hypervisor shell functions) and / or functions processed by the partition shell (partition shell functions). That is, after such functions are written, the FPGA may include a hypervisor shell section including the hypervisor shell functions and / or a partition shell section including the partition shell functions, which will be described later. Figure 10 illustrates such functions and examples of the functions that these functions include.

[0102] One hypervisor shell may be associated with one FPGA. The one hypervisor shell may be written into the one FPGA. Also, one partition shell may be associated with one FPGA. Therefore, for example, even if one FPGA has multiple PR regions, there may be one partition shell, and the partition shell may be written into the one FPGA.

[0103] The hypervisor shell may be determined according to information such as the type of FPGA to be written, attributes related to the arithmetic unit, attributes related to the storage device, and / or attributes related to the communication device. On the other hand, the partition shell may be determined according to the type of FPGA to be written, attributes related to the arithmetic unit, attributes related to the storage device, attributes related to the communication device, the number of PR regions, attributes related to the arithmetic unit in the PR region, attributes related to the storage device in the PR region, and / or attributes related to the communication device in the PR region.

[0104] Therefore, the database of the system of this example may store a hypervisor shell associated with information such as the type of FPGA, attributes related to the computing device, attributes related to the storage device, and / or attributes related to the communication device. In this case, as described below, the system of this example has the advantage of being able to acquire the type and / or function of the FPGA, and identify and use a corresponding hypervisor shell according to the type and / or function of the FPGA. Furthermore, the database of the system of this example may store a partition shell associated with information such as the type of FPGA, attributes related to the computing device, attributes related to the storage device, attributes related to the communication device, and / or the number of PR regions. In this case, as described below, the system of this example has the advantage of being able to acquire the type, function, and / or number of PR regions of the FPGA, and identify and use a corresponding partition shell according to the type, function, and / or number of PR regions of the FPGA.

[0105] In the following, the hypervisor shell and the partition shell may have different functions. However, the hypervisor shell and the partition shell may include the same functions. By dividing the functions written to the FPGA into two, there is an advantage that it is possible to distinguish between a function that changes in response to dynamic changes in the PR region (partition shell function) and a function that does not change in response to dynamic changes in the PR region (hypervisor shell function).

[0106] The timing at which the hypervisor shell and the partition shell are written into the FPGA may be the same within a predetermined range, or may be different. The former may include a case where the partition shell is written consecutively, for example, immediately after the hypervisor shell is written. On the other hand, different times may mean that the hypervisor shell is written when the FPGA is registered, and the partition shell is written at a stage when the user writes application data (or immediately before the user writes application data). Also, the partition shell may be written once, then deleted, and then written again.

[0107] 3.1.1. Hypervisor Shell The hypervisor shell unit may include functions of communication with the management unit, communication with an external device, provision of a communication function to the partition shell, a write-related function, and / or initialization. When the hypervisor shell has some or all of these functions, there is an advantage in that the convenience of the corresponding functions of the reconfigurable device that is enabled to execute a program by being written is improved.

[0108] The communication with the management unit may include a function of responding to a request from the management unit. For example, when there is a request from the management unit to inquire about the status of a specific PR region, a response may be made regarding the status of the specific PR region. The status of the PR region may include, for example, information such as not written, written, in use, not in use, etc. In this way, when the FPGA has a function of a hypervisor shell and is capable of communicating with the management unit, there is an advantage that the management unit can obtain information about the status of the FPGA from an FPGA that is different from a normal CPU.

[0109] The communication with the external device may include a function of sending information to the external device and / or receiving information from the external device. The external device may be, for example, a storage medium. In this case, the hypervisor shell unit may provide an interface to the external device. Furthermore, the external device may provide an interface for communication with an external storage device by a partition shell described later.

[0110] Providing a communication function to the partition shell may include support for a PR region in an FPGA to communicate. A PR region in an FPGA may transmit information when communicating with another PR region in the same FPGA as its own PR region and / or when communicating with another device in an FPGA different from its own PR region. In this case, the communication function of the partition shell may set and / or change the destination of such information as necessary. In order to provide a communication function to the partition shell, the hypervisor shell may include a table regarding communication destination relationships (sometimes referred to as a "communication destination table" in this application). Such a communication destination table may include relationships between destinations in an application used by a user (sometimes referred to as a "user destination" in this application) and the PR region, which is a processing entity in the FPGA, and / or a computing entity outside the FPGA (sometimes referred to as a "node destination" in this application). When the hypervisor shell has such a relationship between a user destination and a node destination, the user destination used by the user within the application is set to the node destination provided by the system related to this application document and information is transmitted, which has the advantage that the user can build an application without worrying about the fact that the FPGA's computational entity is different.

[0111] The hypervisor shell unit may also have a write-related function. The write-related function may include a write function for the partition shell. The hypervisor shell may have a function for writing the partition shell acquired from the management unit into the FPGA to which the hypervisor shell belongs, or a function for supporting the writing. The function for supporting the writing may be obtained by using code having a write function acquired from the management unit. When the hypervisor shell has a write-related function, there is an advantage in that the administrator or user does not need to manually write the partition shell, thereby reducing the burden.

[0112] Moreover, the write-related function of the hypervisor shell unit may have a function related to the authority of the user. The function related to the authority of the user may include a function of confirming the authority of the PR region to which the user writes. For example, the PR region to which the user writes may contain information indicating the user's program, and thus the compiled bitstream, or the write destination of such bitstream, to be written to a PR region to which the user does not have authority. In this case, if the write-related unit writes as is, the information will be written to a PR region to which the user does not have authority, and problems such as, for example, destroying an application running in a PR region of another user may occur. Therefore, the hypervisor shell unit to which the bitstream is to be written may have a function of confirming whether the user has write authority for the PR region to which the bitstream is to be written before performing a process of writing the received bitstream. This function has the advantage of preventing the bitstream constituting an application related to the user from being written to a PR region to which the user does not have write authority, either intentionally or by negligence.

[0113] When the write-related function of the hypervisor shell part includes a function related to user authority, for example, the following process may be performed.

[0114] First, the hypervisor shell unit receives information including a first bitstream that realizes a first application related to a first user when written via a network (step 1).

[0115] Next, in response to receiving information including the first bitstream, the hypervisor shell unit obtains, from the information including the first bitstream, information identifying a first PR region to which the first bitstream is to be written, and information identifying the first application (step 2).

[0116] Next, the hypervisor shell unit transmits information including information for identifying the first application and information for identifying the first PR region to be written to the management unit (step 3).

[0117] In response to receiving information including information identifying the first application and information identifying the first PR region, the management unit uses the information identifying the first application and the information identifying the first PR region to determine whether the first application has authority to be written to the first PR region (step 4).

[0118] If the management unit determines that the authority exists, it transmits permission to execute writing to the hypervisor shell unit, and if the management unit determines that the authority exists, it does not transmit permission to execute writing to the hypervisor shell unit (step 5).In the latter case, it may transmit non-permission to execute writing.

[0119] In the above, instead of the information identifying the first application, information identifying a user who instructed to write the first application may be used. For example, in the above step 4, the information identifying the first application may be used to identify a first user who instructs to write the first application and / or executes the first application, and information on hardware resources assigned to the first user may be used to determine whether the first user has write authority to the first PR region. The above is an example, and if information identifying the first user is included in the information including the first bitstream acquired by the hypervisor shell unit, the information may be used to transmit the information to the management unit to determine whether the first user has write authority to the first PR region.

[0120] Also, in the above description, the hypervisor shell unit has been described as writing a bit stream, but instead of such a configuration, in response to acquiring information including the bit stream, the hypervisor shell unit may transmit the information including the bit stream to a configuration memory in the FPGA to which the hypervisor shell unit belongs, and the configuration memory may acquire information identifying the PR region to be written from the information including the bit stream, and the configuration memory may write the information including the bit stream to the PR region corresponding to the information identifying the PR region.

[0121] Moreover, the initialization function of the hypervisor shell unit may include an initialization function of the storage function and / or the communication function related to the FPGA to which the hypervisor shell unit belongs. The initialization function may include a function of returning to an unused state. The initialization has the advantage of preventing malfunction. The initialization of the storage function may include, for example, returning information in the storage function to an initial state. In this case, there is an advantage of avoiding a state in which meaningless information is stored. Furthermore, the initialization of the communication function may include, for example, processing such as deleting a FIFO queue in the communication function, or resetting information in an intermediate stage of a bus handshake sequence to return to an initial state. In this case, there is an advantage of removing an intermediate stage of communication.

[0122] In particular, by having the hypervisor shell unit perform the initialization, the distributed processing of the system in this example has the advantage of reducing application malfunctions even if the initialization function is not included in the execution mechanism of the user's application.

[0123] The initialization may be performed at various times. For example, in response to the execution of the above-mentioned partition shell writing, the storage function and / or communication function used by the partition shell may be initialized. Writing a partition shell has an advantage that the initialization can be performed before the use of an application, since the user plans to write an application thereafter. However, the initialization may require time, and in this case, the writing of the user's application may be delayed. In addition, in response to the execution of the writing of a user's application, the storage function and / or communication function used by the application may be initialized. Writing an application has an advantage that the initialization can be performed before the use of the application, since the user plans to use the application thereafter. However, the initialization may require time, and in this case, the use of the user's application may be delayed.

[0124] In addition, in response to a change in a user's status, the storage function and / or communication function of the PR region related to the user may be initialized. For example, in response to the end of a course or option of the user's membership, the storage function and / or communication function of the PR region related to the user may be initialized.

[0125] In this case, the management unit may monitor the expiration of each user's membership course or option and / or the PR region used by the user, and in response to the arrival of these expiration times, the management unit may use information identifying the PR region used by the user to communicate with the hypervisor shell unit of the FPGA to which the PR region belongs to initialize the storage function and / or communication function related to the PR region. In response to such communication from the management unit, the hypervisor shell unit may initialize the storage function and / or communication function related to the corresponding PR region.

[0126] In this way, when initialization is performed in response to a change in the user's status, particularly in response to the time when the user terminates use of the PR region, if there is time between the time of termination and the time of next use, there is an advantage that even if initialization requires time, there is little risk of delaying the next use.

[0127] 3.1.2. Partition shell The partition shell unit has a function to support the functions in the PR region. For example, the partition shell unit may manage a clock frequency function, a memory function, and / or a communication function used by the functions in the PR region. If the partition shell has some or all of these functions, there is an advantage in that the convenience of the corresponding functions in the PR region supported by the partition shell is improved.

[0128] The partition shell unit may manage a clock frequency function used by the functions in the PR region. For example, the partition shell unit may be responsible for supplying a clock frequency signal to the PR region.

[0129] The partition shell unit may have a function of generating one or more clock frequency signals to be supplied to the PR region. The partition shell unit may have a function of generating a plurality of different clock frequency signals. The clock frequency generated by the partition shell unit may be available to the circuit in the PR region. There is an advantage that the user can use the clock frequency signal in the circuit in the PR region without preparing it by himself. In addition, when the partition shell unit generates a plurality of different clock frequency signals, there is an advantage that a clock frequency signal suitable for the circuit written in the PR region can be selected, and the range of clock frequency signals available to the circuit is expanded. For example, there is an advantage that a clock frequency signal according to the circuit configuration can be selected, such as a higher clock frequency signal being set when the circuit in which the reconfigurable device is written is simple, and a lower clock frequency signal being set when the circuit is complex.

[0130] The partition shell unit may also supply one or more clock frequency signals to one PR region. For example, the partition shell unit may supply different clock frequency signals to the same or different circuits written in one PR region. Even if a user wants to use different clock frequencies for the same or different circuits in one PR region depending on the complexity or role of the circuit, the above case has the advantage of being able to use a clock frequency signal corresponding to each circuit.

[0131] The clock frequency signal used by the circuit may be determined in advance by a user who determines the circuit to be written. In order for the user to determine the clock frequency used by the circuit, the system of this example may support an environment in which the user can specify a clock frequency available to the circuit in an environment in which the user programs the circuit using a hardware description language or a high-level synthesis language. In addition, when it is desired to supply different clock frequency signals to the same or different circuits in one PR region, the system of this example may support an environment in which the user can specify a clock frequency available to each of the same or different circuits in an environment in which the user programs the circuit using a hardware description language or a high-level synthesis language. Supporting an environment in which a clock frequency signal can be specified may include, for example, a process of displaying one or more clock frequency signals available to the circuit for one or more identical or different circuits, a process of storing the clock frequency signal selected by the user in association with the target circuit, and / or a process of writing the connection relationship between the associated circuit and the clock frequency signal when writing in the PR region.

[0132] The partition shell unit may have a function of managing the correspondence between the storage function used by the arithmetic function in the PR region and the storage function used by the FPGA to which the PR region belongs. By managing such correspondence, there is an advantage that the risk of interfering with the storage-related processing of other PR regions is reduced. For example, when the memory used by the arithmetic function in the PR region has an address of 000 to 999, and such an address corresponds to 20000 to 20999 of the storage functions used by the FPGA to which the PR region belongs, the partition shell may have a table showing such correspondence, and the partition shell may use such a table to support the use of the memory corresponding to the storage function used by the FPGA to which the PR region belongs, in correspondence with the specific address of the memory used by the arithmetic function in the PR region. Here, the storage function used by the FPGA may be a storage device installed in the FPGA, or may be an external storage device accessible by the FPGA.

[0133] The partition shell unit may also have a function for managing the correspondence between information for identifying a communication channel used by a communication function in a PR region and information for identifying a communication channel with the outside of the FPGA to which the PR region belongs. By managing such correspondence, there is an advantage in that the risk of interfering with communication-related processing of other PR regions is reduced. For example, for communication based on a communication channel used by a certain PR region, information indicating that the communication is based on the PR region may be added, and the communication information may be passed to the hypervisor shell.

[0134] The partition shell portion may be provided hierarchically within the PR region.

[0135] The advantage of providing partition shell units hierarchically (for example, providing another partition shell unit within a PR region managed by a partition shell unit) becomes clear in the following example. Assume that an FPGA has two PR regions (two 1 / 2 PR regions), and one PR region (the first 1 / 2 PR region) has already been written and is in use. In this case, the remaining 1 / 2 PR region (the second 1 / 2 PR region) can be provided to the user, but consider a case in which the user only needs to use 1 / 4 of the PR region. In this case, the partition shell unit (first partition shell unit) in which two PR regions have already been set has already been written, and the first 1 / 2 PR region is in use. Therefore, by writing a new partition shell part (second partition shell part) capable of managing two 1 / 4PR regions (the first 1 / 4PR region and the second 1 / 4PR region) into the second 1 / 2PR region that has not yet been used, and allowing the user to use the first 1 / 4PR region, there is an advantage in that efficient utilization is possible.

[0136] The partition shell unit may eventually communicate with a lower-layer partition shell unit provided hierarchically as described above. In this case, the partition shell unit may support a circuit in a PR region managed by the lower-layer partition shell via a communication function and / or a storage function managed by the lower-layer partition shell.

[0137] 4. The third system The third system example is an example of a system that supports distributed processing using an FPGA. For example, as shown in FIG. 11, the system of this example may include a JOB manager function, a resource manager function, and a TASK manager function. The JOB manager and resource manager functions may be implemented on a programmable device. The TASK manager function may be implemented as a function on a reconfigurable device. As described above, the following description will be mainly given using an FPGA, but the same implementation is possible in a reconfigurable device instead of an FPGA. In addition, in the third system, a hypervisor shell and / or a partition shell may or may not be written in the FPGA. Even if the hypervisor shell and / or the partition shell are not written as in the latter case, distributed processing may be executed by writing a bit stream as follows.

[0138] Function 4.1.1.JOB Manager The job manager has a function for managing jobs.

[0139] A JOB may be a single unit predefined by a programmer, or it may be a unit predefined by a programmer that is further subdivided using a separate JOB management technology for distributed processing, or a collection of multiple units predefined by a programmer.

[0140] When a JOB is executed on an FPGA, it may be a program written by a programmer and converted into a bit stream, whereas when a JOB is executed on a programmable device, it may be in a form executable on hardware, such as a program compiled by a programmer or converted into machine code.

[0141] A job may be managed using information that can identify the job, such as a job ID that can uniquely identify the job. Therefore, the job manager may have a database that stores information that identifies a job and a job that is actually executed in association with each other.

[0142] The JOB manager may perform data flow analysis on the JOBs and determine the order in which the JOBs are processed according to the data flow. This order may be determined by performing data flow analysis using information on the input data and output data of each JOB.

[0143] The JOB manager may also manage TASKs, which are processes with a granularity smaller than JOBs. For example, management by the JOB manager may include a process of decomposing one JOB into one or more TASKs, a process of acquiring information about the processing status of the TASKs executed in the hardware resources, and a process of issuing instructions for execution of the decomposed TASK or TASKs in the hardware resources to which the decomposed TASK or TASKs are assigned. The information about the processing status of the TASK may include, for example, initialization for the TASK, starting execution of the TASK, management of a timer for executing the TASK, processing for handling abnormalities in the TASK, and terminating the TASK. The terminating process may include, for example, a function of receiving a TASK termination report from the TASK. The instructions for execution may include instructions corresponding to the above-mentioned processing status.

[0144] Resource Manager The resource manager has a function of managing hardware resources for one or more tasks that constitute a job. The resource manager may include a database related to the above-mentioned resource information associated with the hardware resources, and may manage the hardware resources.

[0145] The resource manager may store information (e.g., ID, etc.) that identifies one or more TASKs that constitute one JOB in association with the hardware resource in which the TASK is written in a database. Such an ID may be assigned to each bit stream. In addition, such an ID may be assigned to something like a function, for example, in a simple explanation using a program language. Therefore, various input information (arguments) may be given when a function is executed, and a function whose output result may change depending on such arguments may be associated with one ID. The input information resource manager may use such a database to determine whether information that identifies a TASK has been written in a hardware resource, and if it has been written, may use the written circuit, and if it has not been written, may execute it after newly writing it. Such association has the advantage of reducing unnecessary writing. Note that one TASK may be assigned to one FPGA described above, or one TASK may be assigned to one PR region in one FPGA.

[0146] The management function of the resource manager may include a function for providing hardware resources to a task.

[0147] For example, when a request for hardware resources corresponding to a task is received from a job manager, the resource manager may select the hardware resources corresponding to the task and transmit them to the job manager.

[0148] Here, the resource manager may obtain information related to the TASK from the JOB manager when selecting the hardware resource. The information related to the TASK may include the above-mentioned resource information, and may include, for example, information such as the type of reconfigurable device, the attributes related to the arithmetic device, the attributes related to the storage device, and / or the attributes related to the communication device for executing the TASK. The resource manager may select a hardware resource corresponding to the information related to the TASK, i.e., one having a hardware resource capable of executing the TASK, from within a database of resource information. Here, the selection may be a hardware resource capable of executing the TASK, so the type and type of the type of the reconfigurable device, the attributes related to the arithmetic device, the attributes related to the storage device, and / or the attributes related to the communication device must match, but the functional information such as the attributes related to the arithmetic device, the attributes related to the storage device, and / or the attributes related to the communication device may include the functions of the information related to the TASK. The resource manager may transmit information identifying the actual hardware resource corresponding to the selected resource information to the JOB manager. For example, the resource manager may transmit information such as the physical ID of the reconfigurable device to be written, the location on the network such as an IP address identifying such a device, and / or the location on the FPGA or network such as an IP address or port number identifying the PR region to be written to the JOB manager. In addition, the fact that such a TASK has been assigned may be stored in the database in association with the information identifying the assigned hardware resource.

[0149] Here, the resource manager may sequentially process the following three steps when selecting a device having hardware resources capable of executing the TASK. When the following steps are executed, there is an advantage that it may be possible to further reduce the time.

[0150] (Step 1) If the task to which the hardware resource is to be allocated has already been written in the hardware resource, the hardware resource of the operator is allocated. If the operator has already been written, there is an advantage that the time required to newly write the operator can be shortened. The presence or absence of the written operator is determined by using an ID associated with the task, as described above. In addition, the user may determine whether to use the written operator or to newly write the operator via the ID. In addition, as another aspect, when a certain task is being executed using other input information, a configuration may be made in which the hardware resource is allocated, or a configuration may be made in which a selection is made to allocate other hardware resources. In the latter case, the process may proceed to step 2 below. Such a selection may be determined based on a prediction process that predicts a comparison between the time required to newly write a bit stream corresponding to the task and the expected completion time of other tasks being executed. In addition, the latter process may be performed only when information such as a priority task is attached to the task. In the case of a task that should be processed with priority, even if the task has already been written, the purpose is to prevent delays due to the execution of other tasks.

[0151] (Step 2) If the TASK to which the hardware resource is to be allocated has not been written in the hardware resource, and if a PR region in which the TASK can be written can be selected in the database, the bitstream for the TASK is written to the PR region. Compared to the next three steps, this has the advantage of being able to reduce the time required for writing the partition shell and the compilation, which may take several hours, using information on the newly selected PR region. Here, the PR region selection criteria may use the above-mentioned hardware resource specification process.

[0152] (Step 3) When the TASK to which the hardware resource is to be allocated has not been written in the hardware resource and a PR region in which the TASK can be written cannot be selected in the database, the partition shell is written to an FPGA in which a PR region in which the TASK can be written can be secured. After the partition shell is written, the TASK is written to a PR region based on the partition shell. In this case, instead of writing a new partition shell, the TASK may be written without using a PR region in an FPGA in which a hypervisor shell has been written but no partition shell has been written. Even if a PR region in which the TASK can be written can be selected, 1) the partition shell may be written to another FPGA in which a PR region in which the TASK can be written can be secured separately, and the TASK may be written to a PR region based on the partition shell, or 2) the TASK may be written without using a PR region in an FPGA in which a hypervisor shell has been written but no partition shell has been written. In addition, in the case where a TASK to which a hardware resource is to be allocated has not been written in the hardware resource and a PR region in which the TASK can be written cannot be selected in the database, instead of the above, a bit stream corresponding to the TASK may be written to the FPGA using a USB cable or JTAG without writing a partition shell and / or a hypervisor shell. In this case, the USB cable may be connected in advance, and the bit stream corresponding to the TASK may be automatically written by a program via JTAG, or a person may connect the USB cable and write the bit stream corresponding to the TASK using JTAG.

[0153] TASK Manager The TASK manager has a function of managing the TASK. The TASK manager uses instructions from the JOB manager to manage the TASK executed in the same FPGA as the FPGA in which the TASK manager is written. Alternatively, the TASK manager may transmit the processing status of the TASK to the JOB manager.

[0154] The TASK manager may have a table showing the relationship between information indicating a JOB executed in the FPGA in which the TASK manager is written and the current execution status of the JOB. Such execution status may include statuses such as being executed, not being executed, and / or being suspended.

[0155] The instructions from the JOB manager may include instructions to initialize, start, abort, or cancel, which are associated with information identifying the JOB.

[0156] The initialization includes the initialization of storage information and / or communication information used by the JOB. Such an initialization instruction may be processed when an operator is newly written in the FPGA and / or when a new JOB is executed. When an operator is newly written, the storage information and / or communication information may be initialized as one step of the writing process, but there is an advantage that the initialization can be more guaranteed if the initialization is performed again as one step of the distributed processing. Also, in the case of a new JOB within the same operator, there is an advantage that the influence of the processing of the previously executed JOB is eliminated.

[0157] The start may be an instruction to start a task. The start instruction may be associated with parameters (input information for executing the task) used by an operator and acquired by the task manager from the job manager. The task manager may send the start instruction for the task, together with the input information for executing the task, to the PR region that executes the task related to the start instruction, to cause the start of the task to be executed.

[0158] The interruption may be to temporarily stop the execution of the TASK. When a command to start is received again, the execution of the TASK may be resumed.

[0159] Furthermore, the TASK manager may transmit abnormal processing of a TASK or a completion report of a TASK to the JOB manager as the processing status of the TASK.

[0160] 4.2.Processing flow 4.2.1. First Example of Processing Flow Next, an example of the process flow of the system of this embodiment will be described, but it goes without saying that the present invention is not limited to this example and various examples can be realized.

[0161] First, as a preparatory process, information about the actual FPGA is stored in a database related to the resource manager. For example, information such as the type of the FPGA, attributes related to the arithmetic unit, attributes related to the storage unit, and / or attributes related to the communication unit is stored in association with information identifying the connected physical FPGA. With this configuration, as described above, the resource manager can identify hardware resources capable of executing the inquired JOB. Such information may be manually or automatically registered in the database.

[0162] The JOB manager may also have a table of information relating to each JOB.

[0163] Step 1 The JOB manager performs data flow analysis of the JOB and determines the JOB to be executed. Here, the JOB manager may perform the data flow analysis using information related to each JOB. The information related to the JOB may be information necessary for the data flow analysis, such as input data of the JOB and output data of the JOB. The data flow analysis itself may use a known technique. Furthermore, the JOB may be compiled so as to be executable on the FPGA, and may be in the form of a bit stream.

[0164] Step 2 The JOB manager inquires of the resource manager about hardware resources capable of executing the JOB to be executed. Here, the JOB manager may hold resource information required for each JOB in advance. Such resource information may be registered in advance by a programmer as resource information required when executing each JOB. Note that, when a JOB is compiled as described above and is in the form of a bitstream, information such as information on the assumed FPGA and / or information on the PR region may be included in the resource information and used for selecting hardware resources.

[0165] Step 3 The resource manager determines the hardware resources for the job to be executed and transmits the hardware resources to the job manager. In this case, the above three steps may be processed.

[0166] Step 4 The JOB manager communicates a bitstream related to the JOB and / or input information for executing the JOB to the hardware resource corresponding to each JOB. In this case, the partition shell and / or the operator related to the JOB may be written in the corresponding hardware resource in the form of a bitstream or the like. In this case, the FPGA writer and / or the partition shell may be used to write.

[0167] Step 5 A task manager in the hardware resource corresponding to each job manages the tasks included in the job and executes the tasks.

[0168] 4.2.2. Second Example of Processing Flow Next, as one aspect of the above-mentioned process flow, a flow focusing on the JOB manager and TASK manager will be described. In the following flow, the JOB manager also performs the role of the above-mentioned resource manager. Also, although this is an example of using an FPGA writer, this function may be implemented anywhere other than within the reconfigurable device.

[0169] First, as shown in FIG. 12, the JOB manager 01 sends to the FPGA writer 02 bitstream information to be used in the FPGAs 03A and 03B.

[0170] Next, as shown in FIG. 13, the FPGA writer 02 sends the bit stream to the FPGAs 03A and 03B and writes them.

[0171] Then, as shown in FIG. 14, the JOB manager 01 transmits a task start command to each TASK manager in the FPGAs 03A and 03B where the task is to be executed, and each TASK manager starts execution in a processing circuit in the same FPGA.

[0172] In the above example, the bit stream is transmitted from the JOB manager, but when the JOB to be executed and the hardware resources where the JOB is to be executed are determined within the JOB manager, the bit stream corresponding to the JOB may be stored and used in a storage, database, or storage system related to the information processing device on which the FPGA writer is executing.

[0173] 4.2.3. Third Example of Processing Flow Next, as an example of distributed processing, an example of summing up 1 to 1000 will be described.

[0174] 15, the system of this example may include a server 01 having a JOB manager implemented in a programmable device, a server 02 including a programmable device implementing an FPGA writer and an FPGA connected to the programmable device via PCIe, and a server 03 including an FPGA, all connected via a network. This configuration is one example, and the number of FPGAs in the server is not limited to two and may be one or more, the number of servers including FPGAs connected to the FPGA writer is also not limited to two and may be one or more, and various network configurations are possible.

[0175] Next, FIG. 16 shows a state in which the bit stream to be written to the FPGA is sent from the JOB manager to the FPGA writer in the server 02. Here, the bit streams used for each FPGA may be the same or different. For example, in this example, as described later, it is assumed that the total of 1 to 1000 is calculated separately as 1 to 250, 251 to 500, 501 to 750, and 751 to 1000, but the bit stream for the FPGA that calculates each of these divided partial calculations and returns the results may be different from the bit stream for the FPGA that calculates the total of these divided partial calculations in addition to each of these divided partial calculations. Also, in the former case, if the type of FPGA to be written or the function in the FPGA is different, the bit stream may be different according to them.

[0176] 17 shows how the FPGA writer writes a bitstream to each FPGA. The bitstream may be written to each FPGA via an interconnect such as PCIe, USB, JTAG, Ethernet, or Infiniband. The FPGA to which the bitstream is written may be in the same server as the FPGA writer, or may be in a different server from the FPGA writer.

[0177] Next, Fig. 18 shows a state where a task start command is transmitted from the JOB manager to the task manager in each FPGA. In this step, input information used for the task may also be transmitted. For example, in this example, input information such as 1 to 250, 251 to 500, 501 to 750, 751 to 1000, etc. may be transmitted.

[0178] 19, the processing circuit in each FPGA to which the bitstream is written executes the task in response to an instruction from the TASK manager. For example, in this example, each part of 1 to 250, 251 to 500, 501 to 750, and 751 to 1000 may be calculated.

[0179] Next, Fig. 20 shows a state in which the results calculated in each FPGA are transmitted to the processing circuit of the task in one FPGA, and the sum of these is calculated. For example, each result calculated by FPGA04A to 04C may be transmitted to FPGA04D. In this case, the position of FPGA04D on the network may be determined in advance based on data flow analysis by the JOB manager. Such a position on the network may be included in the bit stream and written to each FPGA, or may be transmitted to each FPGA as input information to the task indicating the transmission destination of the processing result together with the start command of each task.

[0180] Finally, FIG. 21 shows the state in which each task manager in the FPGA notifies the JOB manager that the execution of each task has been completed.

[0181] 4.3.Other Examples The system according to one aspect of the present invention comprises: A distributed processing management system including a JOB manager and a resource manager, The job manager acquires a plurality of jobs, including one or more jobs to be executed on an FPGA; The resource manager selects a resource corresponding to the JOB, The JOB manager allocates the JOB to the resource, When the JOB is a bitstream JOB that is executed by writing a bitstream on the FPGA, the resource manager selects a corresponding bitstream corresponding to a PR region to which the bitstream JOB is assigned from among a plurality of bitstreams related to the bitstream JOB. It may be a distributed processing system. In addition, when the JOB is a bitstream JOB that is executed by writing a bitstream on the FPGA, The resource manager: When the bitstream capable of executing the JOB is written in the FPGA, information corresponding to the written position is transmitted to a JOB manager; If the bitstream capable of executing the JOB is not written in the FPGA but there is a writable PR region, transmit information including information indicating the writable PR region to a JOB manager; If the bitstream capable of executing the JOB is not written in the FPGA and there is no writable PR region, transmit information including information indicating the writable region to a JOB manager. It may be a distributed processing system.

[0182] 5. The Fourth System The fourth system is a technology related to a development tool for developing a bitstream to be written by a user in the above-mentioned first system. When a user writes a program to be executed on an FPGA after developing the program on the FPGA, the program written in a hardware description language or a high-level synthesis language (sometimes referred to as an "HDL program or HLS program" in the present application) needs to be compiled into a bitstream so that it can be written on the FPGA. This bitstream needs to correspond to resource information such as the type of FPGA and the PR region, and a bitstream that does not correspond to resource information such as the type of FPGA and the PR region cannot be written to an FPGA with the incompatible resource information. In this case, it is necessary to compile the HDL program or HLS program into a bitstream for the FPGA to be written, and depending on the HDL program or HLS program, the compilation time may take several hours or more. Therefore, in the first system, if a user secures hardware corresponding to specific resource information and a bitstream corresponding to the secured hardware is not generated, it takes time to generate the bitstream, and during that time, the secured hardware is unused. This is an inefficient use of hardware resources, and if the user is charged by the time, costs will be incurred even if the hardware is not used. The fourth system addresses this issue and makes it possible to improve the efficiency of hardware resource usage. As mentioned above, the following explanation mainly uses FPGAs, but it can also be implemented in a reconfigurable device instead of FPGAs.

[0183] The fourth system may be associated with the first system described above, or may be a system in an environment where the first system is not implemented.

[0184] 5.1. Configuration Example The fourth system may be directly or indirectly connected to a hardware information providing device (described later) and a compiling device (described later) via a network or the like.

[0185] The fourth system may be a system used by a user. The fourth system may be a terminal device used by the user, an information processing device accessed by a terminal used by the user, or a program executed on these devices.

[0186] 5.2. Example of Function As shown in FIG. 22, a system as an example of the fourth system may include a user interface unit, a hardware information providing device communication unit, and / or a compiler communication unit.

[0187] 5.2.1. User interface section The user interface unit may obtain information from a user, for example, an instruction to update information related to a flavor from the user.

[0188] The user interface unit may also provide information to the user.

[0189] The information about the flavor may be updated not only in response to an instruction from a user but also in response to a predetermined condition, which may include, for example, every predetermined period.

[0190] 5.2.2. Hardware Information Providing Device Communication Unit The hardware information providing device communication unit may have a function capable of communicating with a system capable of providing hardware information that is different from the fourth system. The device capable of providing hardware information (sometimes referred to as the "hardware information providing device" in this application) may be the above-mentioned first system, or may not be the above-mentioned first system. The hardware information providing device may have a function capable of providing information that identifies an FPGA or a PR region within an FPGA to which an HDL program or an HLS program is written.

[0191] The hardware information providing device communication unit may request, in response to a predetermined condition, information (sometimes referred to as "hardware specific information" in the present application) from the hardware information providing device that identifies an FPGA or a PR region within the FPGA into which an HDL program or an HLS program is to be written. Here, the hardware specific information may be resource information that is specified to the extent that a bitstream compiled from an HDL program or an HLS program can be written. For example, the hardware information may be resource information that allows the same bitstream to be written even in different hardware, such as resource information that includes information that identifies a PR region. This is because resource information that does not include a PR region does not allow the same bitstream to be written if the PR region is different. The predetermined condition may include a case where information for updating the flavor is obtained from a user. The predetermined condition may also include a case where a predetermined time condition is satisfied. The predetermined time condition may be at a predetermined regular time. The predetermined time condition may also be a predetermined date and time.

[0192] The hardware information providing device communication unit may have a function of acquiring hardware identifying information from the hardware information providing device. The hardware information providing device communication unit may acquire the hardware identifying information in response to the above-mentioned request, or may acquire the hardware identifying information without making the above-mentioned request. In the latter case, for example, the hardware information providing device may transmit the hardware identifying information to the fourth system based on a predetermined condition, and the hardware information providing device communication unit may acquire the hardware identifying information in response to such transmission.

[0193] The hardware identification information acquired by the hardware information providing device communication unit may be hardware identification information for all hardware that can be provided by the hardware information providing device, or may be hardware identification information for a part of the hardware that can be provided by the hardware information providing device. The part may be selected based on information of hardware available to the user in the hardware provided by the hardware information providing device. For example, if the user who uses the HDL program or HLS program to be compiled is a specific member, the part of the hardware identification information may be selected from hardware available to the member. The selection may be based on a specific criterion. The specific criterion may be, for example, selection from hardware that the administrator of the first system wants the user to use among the hardware available to the user.

[0194] 5.2.3. Compiler Communication Section The compiler communication unit has a function of communicating with a compiler outside the fourth system. The compiler communication unit may have a function of sending a compilation instruction to the compiler. The compiler communication unit may send information used for compilation in association with the compilation instruction to the compiler. Such information may include, for example, an HDL or HLS program to be compiled and / or hardware specific information to which the compiled bitstream will be written.

[0195] The compiler communication unit may obtain the compilation result from the compiler after the compilation is completed. The compilation result may include a design intermediate file. The design intermediate file may include information on placement and wiring with a portion other than the target PR region. For example, when the hardware specific information includes a PR region 1 of a first FPGA, the corresponding design intermediate file may include wiring information with a portion in the first FPGA other than the PR region 1 of the first FPGA. Note that, when the hardware specific information includes a plurality of PR regions, the corresponding design intermediate file may include wiring information with a portion in the FPGA other than each PR region (including each PR region) corresponding to each of the plurality of PR regions. Also, the compilation result may include information in the format of a bitstream. The compiler result may include information in the format of a plurality of partial bitstreams.

[0196] 5.3. Example of processing flow Next, an example of the processing flow of the system of this embodiment will be described with reference to FIG. 23. However, the processing of the functions of the system of this embodiment is not limited to this flow, and various other processing may be possible.

[0197] First, the fourth system, which is the system of this example, receives an instruction to update the hardware-specific information from the user (step 1).

[0198] Next, the system of this example instructs the hardware information providing device to update the hardware specific information (step 2).

[0199] Next, the system of this example obtains hardware specific information from the hardware information providing device and updates it (step 3). For example, the system of this example obtains hardware specific information from the hardware information providing device. Note that step 3 may be performed without steps 1 and / or 2, in which case steps 1 and 2 may or may not be present.

[0200] Next, the system of this example transmits information from the user relating to the HDL program etc. to be compiled (including the HDL program or HLS program, and / or information identifying the HDL program or HLS program; the same applies below) and the hardware specific information to the compiling device (step 4). Here, the hardware specific information may be all of the hardware specific information possessed by the system of this example, or only a portion of it. The advantage is that the more hardware specific information to be compiled, the more targets that can be written. On the other hand, if only a portion of the information is used, the advantage is that although there are fewer targets that can be written, the total compilation time is shorter.

[0201] The compiling device performs compilation using information related to the HDL program etc. to be compiled and the hardware-specific information (step 5). In this case, the compiling device may compile for all hardware-specific information, or may compile using a predetermined range of hardware-specific information. The more hardware-specific information to be compiled, the more writable targets there are, which is an advantage. On the other hand, if it is limited to a predetermined range, the number of writable targets is reduced, but the total compilation time is shortened.

[0202] The compiling device transmits the compilation result to the system of this embodiment, and the system of this embodiment receives the compilation result from the compiling device (step 6).

[0203] After this, the processing may be performed as described in the first system. For example, when the system of this example is connected to the first system, the system of this example may select one or more pieces of resource information in the flavor and request the first system to reserve the corresponding hardware resource. When the first system has successfully reserved the corresponding hardware resource, the first system may register the reserved hardware resource in a database and transmit the information of the reserved hardware resource to the system of this example. The information of the reserved hardware resource may include, for example, information to identify an available PR region in which a partition shell is written. The information to identify the available PR region may include a network address related to the PR region, such as an IP address or a MAC address, an ID of the PR region, and / or information to identify an FPGA including the PR region.

[0204] An example of the fourth system is A user interface unit for providing information to a user and / or acquiring information from a user; a hardware-specific information providing device communication unit having a function capable of communicating with the first system or the hardware-specific information providing device; A compiler communication unit having a function of communicating with a compiler capable of converting an HDL program or an HLS program into a bit stream that can be written to an FPGA; may be provided.

[0205] 6. Various embodiments The system according to the first aspect includes: an acquisition unit that acquires information indicating the first resource from a user; an identification unit that identifies a first reconfigurable device corresponding to information indicating the first resource; an instruction unit that instructs the first reconfigurable device to write a first partition shell corresponding to information indicating the first resource; "A system equipped with the above."

[0206] The system according to the second aspect is the same as the system according to the first aspect. The acquisition unit acquires information indicating a second resource that is not identical to the information indicating the first resource; The instruction unit instructs the first reconfigurable device to write a second partition shell that corresponds to information indicating the second resource and is different from the first partition shell.

[0207] The system according to the third aspect is the same as the system according to the first aspect or the second aspect. A presentation unit that presents one or more pieces of resource information to the user, The information indicative of the first resource is "part of the presented resource information of the one or more reconfigurable devices."

[0208] The system according to the fourth aspect is the system according to any one of the first to third aspects. The presentation unit presents a plurality of setting methods for setting a PR region for the first reconfigurable device.

[0209] The system according to the fifth aspect is one in any one of the first to fourth aspects, wherein "the one or more resource information includes information relating to a computing function, information relating to a memory function, and / or information relating to a communication function."

[0210] The system according to the sixth aspect is the system according to any one of the first to fifth aspects. The acquisition unit acquires information indicating a third resource that is not identical to the information indicating the first resource and the information indicating the second resource, The identification unit identifies a third reconfigurable device that corresponds to information indicating the third resource and is different from the first reconfigurable device; The instruction unit instructs the third reconfigurable device to write a third partition shell corresponding to information indicating the third resource.

[0211] The system according to the seventh aspect is any one of the first to sixth aspects. The system at least includes a database that stores information indicating the first resource and information indicating the first reconfigurable device corresponding to the information indicating the first resource in association with each other.

[0212] The system according to the eighth aspect is the system according to any one of the first to seventh aspects. A hypervisor shell having functions that the first partition shell does not have is already written into the first reconfigurable device.

[0213] The system according to the 9th aspect is any one of the above 1 to 8 aspects, the system includes an inquiry unit that inquires about a status of a first PR region corresponding to the hypervisor shell; The hypervisor shell is capable of responding to an inquiry from the inquiry unit regarding the status of the first PR region.

[0214] The system according to the tenth aspect is the system according to any one of the first to ninth aspects, The hypervisor shell has a function for verifying the authority of the PR region to which the user writes.

[0215] The system according to the 11th aspect is any one of the first to tenth aspects above, in which "the hypervisor shell has an authority verification function for a PR region to which the user writes, which may include an initialization function for a memory function and / or a communication function related to the first reconfigurable device."

[0216] The method according to the twelfth aspect of the present invention comprises: The system, obtaining information indicative of a first resource from a user; identifying a first reconfigurable device corresponding to information indicating the first resource; instructing the first reconfigurable device to write a first partition shell corresponding to information indicating the first resource; "How to do it."

[0217] The method according to the 13th aspect is the same as the 12th aspect above, in which "the system stores information identifying a first reconfigurable device corresponding to information indicating the first resource."

[0218] The computer program according to the fourteenth aspect includes: The system, means for acquiring information indicating a first resource from a user; means for identifying a first reconfigurable device corresponding to the information indicating the first resource; a means for instructing the first reconfigurable device to write a first partition shell corresponding to information indicating the first resource; It is a program for operating as a

[0219] The computer program according to a 15th aspect is the same as the 14th aspect above, in which "the system stores information identifying a first reconfigurable device corresponding to information indicating the first resource."

[0220] 7. Example of programmable device configuration 24 , the programmable device 10 may include a calculation unit 12, a storage unit 13, a communication IF 16, and a bus 11 connecting these. The programmable device 10 may further include an input unit 14, a display unit 15, and a bus 11 connecting these. The programmable device 10 may be connected directly or indirectly to another information processing device via a network 19.

[0221] The programmable device 10 may be an information processing device such as a server or a cloud. It may be a dedicated device or a general-purpose device. The programmable device 10 itself may be a reconfigurable device in which a circuit is written. In this case, there is an advantage that the programs of the various embodiments described above can be executed more quickly.

[0222] Although the above description is of the configuration implemented by the system of the present example, these may be configurations implemented by one or more information processing devices in the system. The system according to the present application document may be presented in various ways. For example, presentation may include display. For example, the system of the present example may be displayed by a display device included in the system of the present example, or may be displayed on a display device in another information processing device to which the system of the present example is directly or indirectly connected.

[0223] It goes without saying that the invention examples described in the embodiments of this application document are not limited to those described in this application document, but can be applied to various examples within the scope of the technical concept thereof.

[0224] In addition, the processes and procedures described in the present application may be realized not only by those explicitly described in the embodiments, but also by software, hardware, or a combination of these. In addition, the processes and procedures described in the present application may be implemented as computer programs and executed by various computers. In addition, these computer programs may be stored in a storage medium. In addition, these programs may be stored in a non-transient or temporary storage medium.

Claims

1. an acquisition unit that acquires information indicating a first resource from a user; an identification unit that identifies a first reconfigurable device corresponding to information indicating the first resource; an instruction unit that instructs the first reconfigurable device to write a first partition shell corresponding to information indicating the first resource; A system comprising:

2. The acquisition unit acquires information indicating a second resource that is not identical to the information indicating the first resource, the instruction unit instructs the first reconfigurable device to write a second partition shell that corresponds to information indicating the second resource and is different from the first partition shell. The system of claim 1 .

3. A presentation unit that presents one or more pieces of resource information to the user, the information indicative of the first resource is a portion of the presented resource information of the one or more reconfigurable devices; The system of claim 2.

4. The presenter presents a plurality of setting methods for setting a PR region for the first reconfigurable device. The system of claim 3.

5. The one or more pieces of resource information include information related to a computing function, information related to a storage function, and / or information related to a communication function; The system of claim 3.

6. The acquisition unit acquires information indicating a third resource that is not identical to the information indicating the first resource and the information indicating the second resource, The identification unit identifies a third reconfigurable device corresponding to information indicating the third resource and different from the first reconfigurable device; the instruction unit instructs the third reconfigurable device to write a third partition shell corresponding to information indicating the third resource; A system according to any one of claims 2 to 5.

7. The system includes at least a database that stores information indicating the first resource and information indicating the first reconfigurable device corresponding to the information indicating the first resource in association with each other. A system according to any one of claims 1 to 6.

8. A hypervisor shell having a function that the first partition shell does not have is written in advance to the first reconfigurable device. A system according to any preceding claim.

9. the system includes an inquiry unit that inquires about a status of a first PR region corresponding to the hypervisor shell; The hypervisor shell is capable of responding to an inquiry about the status of the first PR region from the inquiry unit. The system of claim 8.

10. The hypervisor shell has a function of verifying the authority of the PR region to which the user writes.

10. A system according to claim 8 or 9.

11. The hypervisor shell has a function of verifying authority for a PR region to which a user writes, which may include an initialization function for a memory function and / or a communication function related to the first reconfigurable device; A system according to any one of claims 8 to 10.

12. The system, obtaining information indicating a first resource from a user; identifying a first reconfigurable device corresponding to information indicating the first resource; instructing the first reconfigurable device to write a first partition shell corresponding to information indicating the first resource; How to do it.

13. The system stores information identifying a first reconfigurable device corresponding to the information indicating the first resource. method.

14. The system, means for acquiring information indicating a first resource from a user; means for identifying a first reconfigurable device corresponding to the information indicating the first resource; a means for instructing the first reconfigurable device to write a first partition shell corresponding to information indicating the first resource; A program to operate as.

15. The system stores information identifying a first reconfigurable device corresponding to the information indicating the first resource. program.

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