On-board electronic control device

Abstract

To provide an on-board electronic control device that can reduce storage capacity of a nonvolatile memory without impairing data to be stored when storing vehicle data that indicates a vehicle state at the time of vehicle malfunction.SOLUTION: When an on-board electronic control device detects a malfunction and stores vehicle data indicating a vehicle state in a nonvolatile memory in a time series order, the on-board electronic control device stores a flag indicating a difference and corresponding data to the nonvolatile memory for the data that varies over time, whereas stores a flag indicating a difference to the nonvolatile memory and does not store the corresponding data itself to the nonvolatile memory.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present disclosure relates to an on-board electronic control device mounted in a vehicle, and more particularly to an on-board electronic control device including a storage device that stores fault information in the vehicle. [Background technology]

[0002] A vehicle is equipped with multiple on-board electronic control units (ECUs: Electronic Control Units) to control functional components such as the engine and transmission.

[0003] The ECU has a self-diagnosis function that detects malfunctions based on data sent from sensors to determine whether any abnormalities are occurring in the vehicle.

[0004] Sensor detection values ​​and data calculated for ECU control (fault analysis data) stored in the ECU's volatile memory are overwritten and stored in chronological order at regular intervals (e.g., 500 msec) in a ring buffer located in a separate area of ​​the volatile memory.

[0005] When a fault is detected by the self-diagnosis function, the data stored in the ring buffer at the time of fault detection and before the fault occurred are stored as freeze frame data in a non-volatile memory (EEPROM) that can maintain (save) data even if the power supply to the ECU is cut off. The stored freeze frame data can be read by a scan tool in a repair shop or the like to know the sensor detection values ​​at the time of fault detection in chronological order, which is useful for identifying the cause of the fault. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2004-232498 A Summary of the Invention [Problem to be solved by the invention]

[0007] However, the technology described in Patent Document 1 stores failure analysis data at the time of failure detection in chronological order in non-volatile memory, so if the number of types of data to be stored is increased or the storage time is extended in order to identify the cause of the failure in detail, the amount of data will become enormous, which is expected to put pressure on the storage area of ​​the non-volatile memory. In other words, the amount of storage capacity used to store data out of the storage capacity of the storage area of ​​the non-volatile memory will increase, and the remaining unused storage capacity where data is not stored will decrease.

[0008] The present disclosure has been made in consideration of the above-mentioned problems, and aims to reduce the amount of storage capacity of a non-volatile memory that is used for storing data, without damaging the data to be stored. [Means for solving the problem]

[0009] In the on-board electronic control device according to the present disclosure, the failure analysis data, which is stored in a ring buffer in chronological order in a volatile memory, includes vehicle speed information, transmission range information, gear ratio, and various sensor detection values, but when the vehicle is stopped or traveling at a constant speed, there are many cases where the values ​​hardly change. Therefore, when an abnormality is detected (when a failure is detected) in the self-diagnosis function, it is possible to determine whether or not adjacent data in the chronological order have changed over time, and for data that has not changed, only a flag is set and the data itself is not stored, thereby reducing the amount of storage capacity used in the non-volatile memory.

[0010] That is, the in-vehicle electronic control device according to the present disclosure is A data table in which a plurality of frames each storing a plurality of data constituting vehicle data (fault analysis data) indicating a vehicle state are stored in chronological order; a data storage control unit that stores, when a fault is detected, the plurality of data of new frames in chronological order stored in the data table immediately before the fault is detected in a non-volatile memory; the data storage control unit, in storing in the non-volatile memory a previous frame that is stored chronologically before the new frame, compares adjacent data in the new frame and adjacent data in the previous frame, For data that changes over time, a flag indicating a difference and the corresponding data are recorded in the non-volatile memory; For data that does not change over time, only a flag indicating a difference is recorded in the non-volatile memory, and the corresponding data itself is not stored in the non-volatile memory. Effect of the Invention

[0011] According to the in-vehicle electronic control device of the present disclosure, it is possible to reduce the amount of storage capacity of the non-volatile memory used without damaging the data to be stored. Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments. [Brief description of the drawings]

[0012] [Figure 1] 1 is a configuration diagram showing a configuration of a control means of an on-vehicle electronic control device to which the present disclosure is applied; [Diagram 2] 1 is a configuration diagram showing a software configuration of an in-vehicle electronic control device to which the present disclosure is applied; [Diagram 3] FIG. 2 is a configuration diagram of a data registration table used in the present disclosure. [Figure 4] FIG. 2 is a configuration diagram of a failure analysis ring buffer used in the present disclosure. [Diagram 5] FIG. 11 is an explanatory diagram of a case where initial freeze frame data is generated from the failure analysis ring buffer. [Figure 6] FIG. 11 is an explanatory diagram of a case where freeze frame data is generated from the failure analysis ring buffer from the first time onward; [Figure 7A]10 is a flowchart illustrating details of a process for generating freeze frame data. [Figure 7B] 7B is a flowchart illustrating details of a process for generating freeze frame data, and is a flowchart illustrating details of area 7B of FIG. 7A. [Figure 7C] 7B is a flowchart illustrating the details of the process of generating freeze frame data, which is a continuation of parts 1 and 2 of FIG. 7A. [Figure 8] 11 is an explanatory diagram of a process of reading initial freeze frame data from an EEPROM; FIG. [Figure 9] 11 is an explanatory diagram of a process of reading freeze frame data from the EEPROM after the first time. FIG. [Figure 10A] 10 is a flowchart illustrating details of a process for reading freeze frame data from an EEPROM. [Figure 10B] 10B is a flowchart illustrating details of a process for reading freeze frame data from an EEPROM, and is a flowchart illustrating details of an area 10B in FIG. 10A. [Figure 10C] 10 is a flowchart illustrating the details of a process for reading freeze frame data from an EEPROM, and is a flowchart continuing from parts 1, 2, and 3 of FIGS. 10A and 10B. [Figure 10D] 10B is a flowchart illustrating details of a process for reading freeze frame data from an EEPROM, and is a flowchart illustrating details of an area 10D in FIG. 10C. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. The accompanying drawings show specific embodiments according to the principles of the present disclosure, but the drawings are for understanding the present disclosure and are not to be used to interpret the present disclosure in a limiting manner. EXAMPLES

[0014] 1 is a block diagram showing a configuration of an on-vehicle electronic control device according to an embodiment of the present disclosure. An on-vehicle electronic control device (ECU: Electronic Control Unit) 10 includes a microcomputer 11. The microcomputer 11 includes an input / output interface (I / F) 17, an external communication interface (I / F) 20, a volatile memory (RAM: Random Access Memory) 13, a first non-volatile memory (ROM: Read Only Memory) 14, a second non-volatile memory (EEPROM: Electrically Erasable and Programmable Read Only Memory) 15, and a central processing unit (CPU) 12, and these elements (12 to 15, 17, 20) are connected to each other via a bus 16.

[0015] The input / output I / F 17 is connected to a group of sensors 18 and a group of actuators 19. The external communication I / F 20 is connected to an external communication bus 22, and transmits and receives signals via the external communication bus 22 to and from one or more external devices 21 connected to the external communication bus 22. The RAM 13 is a volatile memory that temporarily stores information. The ROM 14 is a non-volatile memory that stores control programs and various control setting data. The EEPROM 15 is a non-volatile memory that stores data that should be continuously stored even when the power supply to the on-board electronic control device is stopped (for example, learning values ​​and self-diagnosis results used for automobile control).

[0016] When the ECU 10 is a device for controlling a vehicle transmission, for example, the sensor group 18 may include an oil temperature sensor, an oil pressure sensor, a vehicle speed sensor, and a range switch. Values ​​detected by the sensor group 18 are input to the CPU 12 via the input / output I / F 17 and temporarily stored in the RAM 13 as sensor detection values.

[0017] The external device 21 is, for example, an on-board electronic control device other than the ECU 10, a scan tool used in a maintenance shop, or a device that rewrites the control program and various control setting data stored in the ROM 14 (hereinafter, referred to as a reprogramming device). The external device 21 transmits and receives information used for automobile control (e.g., engine speed) and information used for rewriting the ROM 14 via the external communication I / F 20 and the external communication bus 22. The information transmitted from the external device 21 to the ECU 10 is temporarily stored in the RAM 13 as an external input value.

[0018] The CPU 12 is a calculation device that executes each control according to a control program stored in a ROM 14 while referring to the sensor detection values ​​and external input values ​​temporarily stored in a RAM 13. The CPU 12 controls an actuator 19 through an input / output I / F 17 and outputs information to an external device 21 through an external communication I / F 20 according to the calculation results temporarily stored in the RAM 13.

[0019] The CPU 12 also controls the actuator 19 and outputs information to the external device 21, and also executes a self-diagnosis process for diagnosing whether or not a malfunction has occurred in the automobile.

[0020] Among the sensor detection values ​​and calculation results temporarily stored in the RAM 13, information that can be used to identify the cause of a failure is overwritten and stored as failure analysis data for multiple frames in chronological order at regular intervals in a failure analysis ring buffer (described later) in the RAM 13. The failure analysis data can be rephrased as vehicle data indicating the vehicle state.

[0021] That is, the RAM 13 is provided with a failure analysis ring buffer, and the failure analysis ring buffer is configured to store failure analysis data. The failure analysis ring buffer has a plurality of frame storage areas in which a plurality of frames are stored. The failure analysis data is configured to be stored in the plurality of frame storage areas in a frame unit, at a fixed period, in chronological order. After the frame unit failure analysis data is stored in all of the plurality of frame storage areas, when the first new frame unit failure analysis data is further stored in the failure analysis ring buffer, the first new frame unit failure analysis data is stored in the frame storage area in which the frame unit failure analysis data is stored first. Furthermore, when the second new frame unit failure analysis data is stored in the failure analysis ring buffer, the second new frame unit failure analysis data is stored in the frame storage area in which the frame unit failure analysis data is stored second. In this way, the plurality of frame storage areas configured in a ring shape are configured to store failure analysis data of a plurality of frames.

[0022] When a fault is detected during the self-diagnosis process (when a fault is detected), multiple frames of fault analysis data temporarily stored in the fault analysis ring buffer are stored as freeze frame data in the EEPROM 15, which is a non-volatile memory that can retain data even if the power supply to the ECU 10 is cut off.

[0023] The storage process of the failure analysis ring buffer continues even after the freeze frame data storage process in the EEPROM 15. If a new failure is detected, the new failure is stored in an area separate from the previously stored freeze frame data, making it possible to deal with multiple failures.

[0024] In response to a freeze frame data read request transmitted from a scan tool used in a repair shop or the like connected as an external device 21, the freeze frame data stored in the EEPROM 15 is temporarily stored in a read data storage buffer of the RAM 13 (described later) and transmitted to the scan tool of the external device 21.

[0025] Next, an embodiment of the control device according to the present disclosure used in such an on-vehicle electronic control device will be described in detail. The failure analysis data, which is stored in a ring buffer provided in a volatile memory in chronological order as a data table, includes vehicle speed information, transmission range information, gear ratio, and various sensor detection values. When the vehicle is stopped or traveling at a constant speed, there are many cases in which the vehicle speed information, transmission range information, gear ratio, and various sensor detection values ​​hardly change. Therefore, in the on-vehicle electronic control device of the present disclosure, when an abnormality is detected (when a failure is detected) in the self-diagnosis function, it is determined whether or not there is no change in the failure analysis data adjacent in the chronological order, and for the failure analysis data that does not change, only a flag of difference information is stored in the EEPROM 15, and the failure analysis data itself that does not change is not stored in the EEPROM 15. This makes it possible to reduce the amount of storage capacity used in the non-volatile memory.

[0026] FIG. 2 is a block diagram showing a software configuration according to an embodiment of the present disclosure.

[0027] The CPU 12 executes arithmetic processing according to a failure analysis data accumulation process 203, a freeze frame data generation process 204, and a freeze frame data reading process 205 stored in a control program storage area 202 of the ROM 14. The freeze frame data generation process 204 and the freeze frame data reading process 205 can be collectively referred to as a data storage control unit 210.

[0028] The failure analysis data accumulation process 203 is a process for sequentially storing failure analysis data registered in a freeze frame data registration table 201 (hereinafter, referred to as a data registration table) stored in the data storage area 200 in a failure analysis ring buffer 206 of the RAM 13 at regular intervals. The data registration table 201 and the failure analysis ring buffer 206 can be rephrased as a data table of failure analysis data.

[0029] The freeze frame data generation process 204 is a process in which, when a fault is detected by the self-diagnosis function, the fault analysis data registration presence / absence information in the data registration table 201 and the fault analysis data stored in the fault analysis ring buffer 206 of the RAM 13 are processed into a format suitable for storage in the freeze frame data 209 of the EEPROM 15, and the data is temporarily stored in a temporary buffer 207 of the RAM 13, and the data of the temporary buffer 207 is stored as the freeze frame data 209 of the EEPROM 15.

[0030] The freeze frame data read process 205 is a process in which, when a freeze frame data read request is received from a scan tool used in a repair shop or the like, the freeze frame data 209 stored in the EEPROM 15 is processed into a freeze frame data read format for each frame, the data is temporarily stored in a temporary buffer 207 in the RAM 13, and then the data is sequentially stored in a read data storage buffer 208.

[0031] Next, a configuration example of a data registration table will be described with reference to Fig. 3. Fig. 3 is a configuration diagram of a data registration table used in the present disclosure. Fig. 3 shows an example of the configuration of a data registration table 201 of freeze frame data stored in ROM 14.

[0032] The data registration table 201 is composed of a header H[] consisting of a 1-byte array that stores registration presence / absence information indicating whether data is registered for each bit from bit 7 to bit 0, and a failure analysis data address that stores a reference address of failure analysis data such as a sensor detection value or a calculation result that can be used to identify a failure cause temporarily stored in the RAM 13. In Fig. 3, a header H[0] and a header H[1] are illustrated as examples of the header H[].

[0033] The registration presence / absence information is set to "1b" when failure analysis data is "present" and "0b" when it is "absent" (Figure 3 shows it as "present (1)" and "absent (0)"). With this registration presence / absence information, if it becomes necessary to add or change failure analysis data in a future software update, it will be possible to accommodate this without making major software changes. Here, the "b" in "1b" or "0b" indicates that the data is in binary (two-value) format.

[0034] The number of addresses that can be registered in the failure analysis data address corresponds to each bit of the header H[], so it is the array size of the header H[] × 8 (bits) (in FIG. 3, the registerable failure analysis data addresses are configured to be able to register 16 addresses, which is the array size of the header H[] 2 × 8 (bits)). Note that since the data indicated by the address registered in the failure analysis data address is referenced in 1 byte units by the data accumulation processing 203 and the data storage control unit 210, if the original failure analysis data exceeds 1 byte, the failure analysis data is divided into 1 byte units, and the divided addresses are registered for each byte. Also, if there is no failure analysis data (if the registration presence / absence information is "absent"), a NULL pointer indicating an invalid value is registered in the registered analysis data address.

[0035] In FIG. 3, as shown by way of example, in order to register data 1 to 3, which are failure analysis data with a data size of 4 bytes, from the upper bits of H[0], "1b" (registered: yes (1)) is set to bits 7 to 0 of H[0] and bits 7 to 4 of H[1], and "0b" (not registered: no (0)) is set to the remaining H[1]. In order to register data 1 in a failure analysis data address, the original 4-byte failure analysis data is divided into four pieces in 1-byte units, and the data is registered in ascending order of addresses of data 1 from the upper bits of H[0]. Data 2 and data 3 are also divided into four pieces in 1-byte units and registered in the same way as data 1, but a description thereof will be omitted. In addition, since there is no data to be registered in bits 3 to 0 of H[1], a NULL pointer is registered. A NULL pointer can be regarded as empty data with no registered data.

[0036] 3, the number of headers is two, H[0] and H[1]. The number of headers may be one, two, three, or four or more depending on the size of the data to be stored.

[0037] Next, a configuration example of the failure analysis ring buffer will be described with reference to Fig. 4. Fig. 4 is a configuration diagram of the failure analysis ring buffer used in the present disclosure.

[0038] 4 is a diagram showing a data structure of the failure analysis ring buffer 206 (hereinafter, referred to as the ring buffer) temporarily stored in the RAM 13, and a state in which three sets of failure analysis data (three frames) are stored in the ring buffer 206. The vertical axis of FIG. 4 shows the number of frames of the ring buffer 206 stored at a fixed cycle, and the horizontal axis shows the names of the buffers (D1 to D16) for storing data indicated by the failure analysis data addresses registered in the data registration table 201, and the data stored in the buffers. The buffers (D1 to D16) are configured from the left to right as a 1-byte array that stores data indicated by the failure analysis data addresses registered in the data registration table 201 from the most significant bit of H[0] to the least significant bit of H[1] in 1-byte units. Therefore, the buffer size per frame is the same as the number of failure analysis data tables that can be registered in the data registration table 201 (the number of bits of the header H[]).

[0039] That is, the data registration table 201 in Fig. 3 also shows the configuration of failure analysis data per frame. Therefore, in Fig. 4, in each of frames 1 to 3, the failure analysis data of data 1 to 3 registered in the failure analysis data addresses of the data registration table 201 are stored in buffers D1 to D12, and (NULL) is stored in buffers D13 to D16 as "no registered data (NULL)". As shown in Fig. 4, the stored data is shown in hexadecimal in the buffers (D1 to D16).

[0040] The ring buffer 206 is stored in the EEPROM 15 while being processed into the data format of the freeze frame data 209 by a freeze frame data generation process 204, the details of which will be described later. At this time, since the data size is reduced, the overall size of the ring buffer 206 (number of frames x number of buffers) can be set to be larger than the area for storing the freeze frame data 209. However, if the failure analysis data changes every time in a chronological order, the reduction rate of the data size decreases, so it is necessary to set the data so that the truly necessary data for identifying the cause of the failure and the storage time can all be stored in the freeze frame data 209.

[0041] Hereinafter, the frames of the ring buffer 206 will be referred to as frame 1, frame 2, . . . frame n from the top, and the buffers will be referred to as D1, D2, .

[0042] The ring buffer 206 stores failure analysis data while switching frames every time the failure analysis data accumulation process 203 is executed at regular intervals (every 500 msec in this embodiment). The frames are switched cyclically, such as frame 1, frame 2, frame n, frame 1, etc., every time the failure analysis data accumulation process 203 is executed.

[0043] When the failure analysis data is stored in the buffer, if the registration information in the data registration table 201 is "Yes", the data stored in the failure analysis data address is stored, and if the registration information is "No", "0x00" is stored. Here, "0x" indicates that the data is in hexadecimal.

[0044] In this embodiment, bits 7-0 of header H[0] and bits 7-4 of header H[1] in data registration table 201 are registered "Yes", so information on Data 1 divided in 1 byte units is stored in D1-D4, information on Data 2 is stored in D5-D8, and information on Data 3 is stored in D9-D12. Since the registered information on bits 3-0 of header H[1] is "No", "0x00" is stored in D13-D16.

[0045] Next, the operation of the freeze frame data generation process 204 when a failure occurs at the timing when the failure analysis data is stored in frame 3 of the ring buffer 206 will be described with reference to Fig. 5 and Fig. 6. Fig. 5 is an explanatory diagram of the case where the first freeze frame data is generated from the failure analysis ring buffer. Fig. 6 is an explanatory diagram of the case where the first and subsequent freeze frame data are generated from the failure analysis ring buffer.

[0046] The freeze frame data generation process 204 starts its operation when a failure is detected in the self-diagnosis process, and stores the registration presence / absence information of the data registration table 201 in the header of the temporary buffer 207, as shown in Fig. 5. At the same time, the freeze frame data generation process 204 stores the information D1 to D12 corresponding to the part of the registration presence / absence information in the data registration table 201 that is "present" among the data stored in frame 3 of the ring buffer 206 (failure analysis data immediately before the failure detection, a new frame that is new in time series) in the data of the temporary buffer 207. The freeze frame data generation process 204 further stores the headers H[0] and H[1] and the data D1 to D12 stored in the temporary buffer 207 in the storage area of ​​the freeze frame data 209 on the EEPROM 15. Therefore, among the failure analysis data stored in frame 3, the failure analysis data D13 to D16 that do not have the registration information are not stored in the freeze frame data 209. Therefore, since the storage capacity for the failure analysis data D13 to D16 having no registered information is not required, the amount of usage (used area) of the storage area of ​​the EEPROM 15 can be reduced.

[0047] After the process shown in Fig. 5, the freeze frame data generation process 204 compares the failure analysis data stored in frame 3 in the ring buffer 206 with the failure analysis data of frame 2 (the previous frame stored chronologically before frame 3) stored one cycle ago (500 msec ago) in sequence for every 1 byte, and stores the comparison result (difference presence / absence information) in the header of the temporary buffer 207. The difference presence / absence information (flag) stored in the header of the temporary buffer 207 is processed to store "1b" if there is a difference, and "0b" if there is no difference. The freeze frame data generation process 204 then stores the failure analysis data determined to have a difference in the comparison process in the data of the temporary buffer 207 from the left without any gaps, and stores the data of 1 byte units from the headers H[0] and H[1] and D1 to D5 stored in the temporary buffer 207 in the EEPROM 15, filling the area next to the area where the information of frame 3 of the freeze frame data 209 is stored, without any blanks.

[0048] In other words, when processing frame 2, the temporary buffer 207 stores a flag indicating that there is a difference of “1b” (bit 4 of H[0], bits 7-4 of H[1]) and the corresponding data (“0x01” in D4 of data 1 of frame 2, and “0x11”, “0x11”, “0x11”, “0x11”) in D09-D12 of data 3 of frame 2) if there is no difference, and stores only “0b” in EEPROM 15 as a flag (bits 7-5, bits 3-0 of H[0], bits 3-0 of H[1]), and the data corresponding to no difference itself is not stored in EEPROM 15.

[0049] Thereafter, the contents of the temporary buffer 207 are stored in the EEPROM 15 as shown in Fig. 6. Therefore, in the EEPROM 15, the failure analysis data of frame 3 (including the header), the difference information (flag) between frames 3 and 2, and the data with the difference (including the header) are stored in a packed manner so that there is no blank space in the storage area. Therefore, the failure analysis data stored in frame 2 stores only the difference information between frames 3 and 2 and the data with the difference, so that the used area in the storage area of ​​the EEPROM 15 can be reduced. The process shown in Fig. 6 is repeatedly executed until a frame in which failure analysis data is not registered in the frame of the ring buffer 206 or until the ring buffer 206 is about to make a full rotation. As a result, all the failure analysis data temporarily stored in the ring buffer 206 can be stored as the freeze frame data 209.

[0050] In other words, it can be summarized as follows:

[0051] 1) When a failure is detected, the freeze frame data generation process 204 of the data storage control unit 210 stores a plurality of data of a new frame (corresponding to frame 3) in chronological order that was stored in the ring buffer area (206) as a data table immediately before the failure detection in the non-volatile memory EEPROM 15. Then, when storing in the EEPROM 15 the previous frame (corresponding to frame 2) that was stored chronologically earlier than the new frame (frame 3), the data storage control unit 210 compares adjacent data in chronological order between the plurality of data of the new frame (frame 3) and the plurality of data of the previous frame (frame 2) (for example, data 1 of frame 3 and data 1 of frame 2, or D1 of frame 3 and D1 of frame 2, etc.).

[0052] In this comparison, the following configuration is used.

[0053] For data that has changed over time, a flag indicating a difference ("1b") and the corresponding data are recorded in the EEPROM 15.

[0054] For data that does not change over time, only a flag indicating a difference ("0b") is recorded in the EEPROM 15, and the corresponding data itself is not stored in the EEPROM 15.

[0055] 2) When each of the multiple data is multiple bytes long, the data storage control unit 210, in comparing the multiple data of the new frame (frame 3) with the multiple data of the previous frame (frame 2), compares chronologically adjacent byte data of the multiple byte data of the new frame (frame 3) with the multiple byte data of the previous frame (frame 2) (for example, D1 of frame 3 and D1 of frame 2).

[0056] In this comparison, the following configuration is used.

[0057] For byte data that has changed over time, a flag indicating a difference ("1b") and the corresponding byte data are recorded in the EEPROM 15.

[0058] For byte data that does not change over time, only a flag (“0b”) indicating the difference is recorded in the EEPROM 15 , and the corresponding byte data itself is not stored in the EEPROM 15 .

[0059] 3) The freeze frame data generation process 204 of the data storage control unit 210 is configured to store in the EEPROM 15 data that has changed during the time change going back from the time of failure detection (during the time change from the detection time of the vehicle data of frame 3 to the detection time of the vehicle data of frame 1), and to store only a flag in the EEPROM 15 for data that has not changed.

[0060] 4) The data storage control unit 210 processes a plurality of frames related to vehicle data registered in the ring buffer area (206) serving as a data table in chronological order, starting with the newest vehicle data frame (corresponding to frame 3) and proceeding to the oldest vehicle data frames (frames 2 and 1), and stores the processed frames in the EEPROM 15. In other words, the data storage control unit 210 processes the storage process of frame 3, the comparison process and storage process of frames 3 and 2, and the comparison process and storage process of frames 2 and 1, in that order.

[0061] 5) The data storage control unit 210 is also configured to store the vehicle data in the EEPROM 15 in the order (here, frame 3 -> frame 2 -> frame 1) registered in the ring buffer area (206) serving as a data table, filling the storage area so that there are no blank spaces.

[0062] Specific control operations of the freeze frame data generation process 204 are shown in the flowcharts of Figures 7A, 7B, and 7C. Figure 7A is a flowchart for explaining details of the process for generating freeze frame data 209. Figure 7B is a flowchart for explaining details of the process for generating freeze frame data 209, and is a flowchart for explaining details of area 7B of Figure 7A. Figure 7C is a flowchart for explaining details of the process for generating freeze frame data 209, and is a flowchart continuing from parts 1 and 2 of Figure 7A. Below, the control step functions of Figures 7A, 7B, and 7C will be explained.

[0063] <<Step S701>> If a failure occurs before failure analysis data is stored in the ring buffer 206, there is no data to be written to the EEPROM (NO: N (not present)), so the process proceeds to step S702, no processing is performed, and the freeze frame data generation process 204 is terminated. If data is stored in the ring buffer (YES: Y (present)), the process proceeds to step S703.

[0064] <<Step S703>> In order to analyze the failure analysis data stored in the ring buffer 206 for each frame, the processes from step S703 to step S722 are looped for the number of frames for which failure analysis data is temporarily stored in the ring buffer 206 (loops are repeated until the number of loops (n) is less than the number of stored ring buffer frames).

[0065] <<Step S704>> The temporary buffer data position (td) indicating the registered data position in the temporary buffer 207, the header H[] of the temporary buffer 207, and the frame data position (fd) indicating the data reference position on the frame of the ring buffer 206 are initialized to "0".

[0066] In addition, since the temporary buffer data position (td) and the frame data position (fd) indicate the data position of the buffer relative to zero, the position of the buffer name D1 is td=0, and the position of the buffer name D16 is td=15.

[0067] <<Steps S705 and S706>> In order to analyze all data registered in the frame of the ring buffer 206, the process from step S705 to step S715 is looped for the size of the header (looping until loop count (i) < header size). The loop count (i) also indicates the number of elements in the header H[] of the temporary buffer.

[0068] In addition, in order to analyze all the registration presence / absence information registered in the header during the loop processing of step S705, the processing from step S706 to step S714 is looped for the number of flags (looped until the loop count (j)<8). The loop count (j) also indicates the bit position of the header H[] in the temporary buffer.

[0069] <<Step S707>> 5 and 6, the freeze frame data generation process 204 has different processing methods for generating freeze frame data 209 from a frame immediately before a failure occurs (first time) and generating freeze frame data 209 from a frame before that, so the process branches depending on whether it is the first write or not. If it is the first write (YES: Y (first write)), the process proceeds to step S708, and if it is not the first write (NO: N (not the first write)), the process proceeds to step S723 shown in FIG. 7B.

[0070] <<Step S708>> If the registration information in the data registration table 201 indicates no registration ("0b") (NO: N (no registration)), the process proceeds to step S709 shown in Fig. 7B, and proceeds to step S713 without performing any processing. If the registration information indicates registration ("1b") (YES: Y (registered)), the process proceeds to step S710.

[0071] <<Step 710>> Since the failure analysis data is registered in the data registration table 201, a flag indicating the presence of failure analysis data is set in the corresponding bit of the header of the temporary buffer 207 (H[i]|=(0x80>>j)).

[0072] <<Step 711>> The data of the frame being analyzed is copied to the data portion of the temporary buffer 207 (data of the temporary buffer [td]=data of the frame being analyzed [fd]).

[0073] <<Step S712>> In preparation for the copy process of the next data, the temporary buffer data position (td) is incremented, and the process proceeds to step S713. If it is determined in step S708 that there is no registered data in the data registration table 201, the temporary buffer data position (td) is not incremented. This avoids storing unnecessary data with no registered data in the temporary buffer 207.

[0074] <<Step S713>> Increment the ring buffer data position (fd).

[0075] <<Step S714>> The loop count (j) is incremented, and the process returns to the loop process of step 706.

[0076] <<Step S715>> After the loop process of step S706 is completed, the loop count (i) is incremented and the process returns to the loop process of step S705. When the loop process of step S705 is completed, the process of storing the header and data in the temporary buffer 207 is completed. Then, the process proceeds to step S716 shown in FIG. 7C.

[0077] <<Step S723>> If it is determined in step S707 that this is not the first write (NO:N (not the first write)), then only information with differences in the data in the temporary buffer 207 is stored, so that the data [fd] of the frame used in the previous analysis is compared in BYTE units with the data [fd] of the frame being analyzed.

[0078] If it is determined in the comparison process that there is a difference (YES: Y (difference exists)), the same processes as those in steps S710, S711, and S712 described above are executed, and then the process proceeds to step S713. If it is determined that there is no difference (NO: N (no difference)), the process proceeds to step S709 without executing any process, and proceeds to S713 shown in FIG. 7A. At this time, as in the case of the initial write, if there is no difference, there is no need to store the failure analysis data, and therefore the process of incrementing the temporary buffer data position (td) is not executed.

[0079] <<Step S716>> As in step S707, the process to be executed differs depending on whether it is the first time or not, so the process is branched. If it is the first time writing (YES: Y (first time writing)), proceed to step S717, and if it is not the first time writing (NO: N (not the first time writing)), proceed to step S724.

[0080] <<Step S717>> In order to check whether the generated temporary buffer 207 can be written into the freeze frame data 209 area arranged in the EEPROM 15, an integrated write data size (ds) is calculated, and the process proceeds to step S718.

[0081] In the case of the initial write, the cumulative write data size (ds) is calculated by adding the size of the temporary buffer header (same value as i) plus the size of the data storing the failure analysis data (same value as td) (ds=i+td).

[0082] <<Step S724>> If it is determined in step S716 that this is not the first write (NO), the integrated write data size (ds) is calculated in the same manner as in step S717, and the process proceeds to step S718.

[0083] In this case, the accumulated write data is calculated by adding the previous accumulated write data size (ds) to the temporary buffer header size (i) and the size of the data storing the failure analysis data (td) (ds=i+td).

[0084] <<Step S718>> It is determined whether the accumulated write data size (ds) does not exceed the size of the freeze frame data 209 area arranged in the EEPROM 15. If it is determined that it does exceed (NO: N (exceeds)), the information stored in the temporary buffer 207 cannot be written to the EEPROM, so the process proceeds to step S725 and ends without performing any processing. If it is determined that the accumulated write data size (ds) does not exceed the size of the freeze frame data 209 (YES: Y (does not exceed)), the information stored in the temporary buffer 207 can be written to the EEPROM 15, so the process proceeds to step S719.

[0085] <<Step S719>> As in step S707, the process to be executed differs depending on whether it is the first time or not, so the process branches depending on whether it is the first time writing or not. If it is the first time writing (YES: Y (first time writing)), proceed to step S720, and if it is not the first time writing (NO: N (not the first time writing)), proceed to step S726 and proceed to S721 without performing any process.

[0086] <<Step S720>> When storing data in the EEPROM 15, it is necessary to erase the data storage area of ​​the EEPROM 15 and make it blank (undefined state). Therefore, in the case of the first write, the freeze frame data 209 area is erased. After the erase is completed, the process proceeds to step S721.

[0087] <<Step S721>> The data in which the header of the temporary buffer 207 and the failure analysis data are stored is stored in the freeze frame data 209 area of ​​the EEPROM 15. Note that the data is stored from the top of the freeze frame data 209 area at the first write, but from the second write onwards, the data is written following the end of the previous data so as not to overlap with the previous data. After the write is completed, the process proceeds to step S722.

[0088] <<Step S722>> Since the analysis of the frame and the storage process in the EEPROM 15 are completed, n, which is the number of frames to be referenced in the ring buffer, is incremented, and the process returns to the loop process of step S703.

[0089] When the loop process of step S703 ends, the analysis process and the write process to the EEPROM 15 for all frames are completed, and therefore the process ends.

[0090] Next, the freeze frame data read process 205 will be described with reference to Fig. 8. Fig. 8 is an explanatory diagram of the process of reading the first freeze frame data 209 from the EEPROM. Fig. 9 is an explanatory diagram of the process of reading the first and subsequent freeze frame data 209 from the EEPROM.

[0091] The freeze frame data read process 205 starts operation when a freeze frame data read request is received from the scan tool connected to the external device 21, and stores the header information stored at the beginning of the freeze frame data 209 in the EEPROM 15 in the header of the read data storage buffer 208 and the header of the temporary buffer 207, as shown in Fig. 8. Since the registration presence information in the header H[0] bit7-bit0 and H[1] bit7-bit4 of the temporary buffer 207 is "1b" indicating "present", it is determined that there is failure analysis data, and the failure analysis data is stored in the data section D1-D12 of frame 1 of the read data storage buffer 208 from the freeze frame data 209. Since the header registration presence information in the header H[1] bit3-bit0 of the temporary buffer 207 is "0b" indicating "not present", "0x00" is stored in the data section D13-D16 of frame 1. The size of the failure analysis data read from the freeze frame data 209 is the number of data whose registration presence information is "present".

[0092] After the process of Fig. 8, the second header information stored in the freeze frame data 209 of the EEPROM 15 is stored in the header of the temporary buffer 207 as shown in Fig. 9. Since the information indicating the presence or absence of a difference in the header H[0] bit7-bit5, H[0] bit3-bit0, and H[1] bit3-bit0 of the temporary buffer 207 is "0b" indicating "no difference", the information stored in the immediately preceding frame of the read data storage buffer 208 is inherited. Since the header H[0] bit4 and H[1] bit7-bit4 of the temporary buffer 207 is "1b" indicating "presence of a difference", the failure analysis data is read from the freeze frame data 209 and stored in the buffer positions D4 and D9-D12 corresponding to the header of the temporary buffer 207.

[0093] The process shown in FIG. 9 is repeatedly executed until the freeze frame data 209 becomes blank (undefined state) or until the information is read out to the end of the freeze frame 209 area.

[0094] The freeze frame data read process 205 differs from the freeze frame data generation process 204 in that it does not use information in the data registration table 201 in the ROM 14. Therefore, even if the registration presence / absence information set in the header of the data registration table 201 is rewritten to different data by a reprogramming device connected to the external device 21 after the freeze frame data 209 is stored in the EEPROM 15, when a read request is received from the scan tool, it is possible to transmit the read result of the freeze frame data 209 stored before the data rewriting to the scan tool.

[0095] Specific control operations of the freeze frame data read process 205 are shown in the flowcharts of Figures 10A, 10B, 10C, and 10D. Figure 10A is a flowchart for explaining the details of the process of reading freeze frame data 209 from EEPROM. Figure 10B is a flowchart for explaining the details of the process of reading freeze frame data 209 from EEPROM, and is a flowchart for explaining the details of area 10B in Figure 10A. Figure 10C is a flowchart for explaining the details of the process of reading freeze frame data 209 from EEPROM, and is a flowchart continuing from parts 1, 2, and 3 in Figures 10A and 10B. Figure 10D is a flowchart for explaining the details of the process of reading freeze frame data 209 from EEPROM, and is a flowchart for explaining the details of area 10D in Figure 10C. Each control step function in Figures 10A, 10B, 10C, and 10D will be explained below.

[0096] <<Step S1001>> A blank check process, which is a function of the microcomputer 11, for checking whether or not data has been written in the EEPROM area is executed from the end of the freeze frame data 209 storage area of ​​the EEPROM 15 to determine whether or not freeze frame data 209 has been written. If so, the end address of the written data (hereinafter referred to as the freeze frame data end address) is obtained, and the process proceeds to step S1002.

[0097] <<Step S1002>> A header pointer (hp) that stores an address for referencing the header information of the freeze frame data 209 is initialized to the start address of the freeze frame data 209 area, and the process proceeds to step S1003.

[0098] <<Step S1003>> It is determined whether or not the header information of the freeze frame data 209 can be read from the EEPROM 15. Since the size of the header information is the same as the header size of the data registration table 201, it is determined whether the header pointer (hp) + header size (2) exceeds the freeze frame data end address. If the header pointer (hp) + header size (2) does not exceed the freeze frame data end address, it is determined that the header information can be read (YES: Y (can be read)) and the process proceeds to step S1004. If it exceeds the freeze frame data end address, it is determined that the header information cannot be read (NO: N (cannot be read)) and the process proceeds to step S1008 shown in FIG. 10B.

[0099] <<Step S1004>> 8 and 9, the freeze frame data read process 205 differs between the first read and subsequent reads, so the process branches depending on whether it is the first read or not. If it is the first read (YES: Y (first read)), the process proceeds to step S1005, and if it is not the first read (NO: N (not the first read)), the process proceeds to step S1007.

[0100] <<Step S1005>> The data stored in the header pointer (hp) in the headers H[0] to H[1] of the read data storage buffer 208 is read out by the size of the header, and the process proceeds to step S1006.

[0101] <<Step S1006>> The data in the headers H[0] to H[1] of the read data storage buffer 208 is copied to the header portion of the temporary buffer 207, and the process proceeds to step S1011.

[0102] <<Step S1007>> Since only the initial header information needs to be stored in the header of the read data storage buffer 208, if it is not the first read in step S1004 (NO:N (not the first read)), the data stored in the header pointer (hp) in the temporary buffer 207 header H[0] to H[1] is read out by the size of the header, and then proceed to step S1011.

[0103] <<Step S1008>> As in step S1004, the process to be executed differs depending on whether it is the first time or not, so the process branches depending on whether it is the first read or not. If it is the first read (YES: Y (first read)), proceed to step S1009, and if it is not the first read (NO: N (not the first read)), proceed to step S1010.

[0104] <<Step S1009>> If the header information cannot be read and this is the first time the data is read, it can be determined that the freeze frame data 209 is not stored, so the read status is set to "no data" and the process ends as shown in FIG. 10C.

[0105] <<Step S1010>> If the header information cannot be read and this is not the first time the information has been read, it can be determined that all of the information written in the freeze frame data 209 has been read, so the read status is set to "data reading completed" and the process ends, as shown in FIG. 10C.

[0106] <<Step S1011>> Calculate the data size (ds) stored in the freeze frame data 209. The data size (ds) is equal to the number of flags in the header of the temporary buffer 207 that are "1b" (ds=number of flags in the temporary buffer header).

[0107] <<Step S1012>> It is determined whether or not the freeze frame data 209 can be read from the EEPROM 15. This is determined by whether the header pointer (hp) + data size (ds) exceeds the freeze frame data end address. If the header pointer (hp) + data size (ds) does not exceed the freeze frame data end address, it is determined that all the data can be read (YES: Y (all can be read)) and the process proceeds to step S1014. If it exceeds the freeze frame data end address, it is determined that the data cannot be read (NO: N (cannot be read)) and the process proceeds to step S1013 shown in FIG. 10B.

[0108] <<Step S1013>> Since it is determined in step S1012 that the data cannot be read (NO:N (cannot be read)), "data abnormal" is set to the read status, and the process ends as shown in FIG. 10C. This step occurs when the process is interrupted during the writing of the freeze frame data 209 in the freeze frame data generation process 204 due to an unstable power supply to the ECU 10. Even if such a state occurs for the data stored in the EEPROM 15, the failure analysis data can be stored in the read data storage buffer 208 until the data cannot be read, so it is possible to transmit the failure analysis data stored in the read data storage buffer to the scan tool.

[0109] <<Step S1014>> As in step S1004, the process to be executed differs depending on whether it is the first time or not, so the process branches depending on whether it is the first read or not. If it is the first read (YES: Y (first read)), proceed to step S1015, and if it is not the first read (NO: N (not the first read)), proceed to step S1016.

[0110] <<Step S1015>> The read frame number (fn), which indicates the data frame position in the read data storage buffer 208, is initialized to 0, and the process proceeds to step S1017.

[0111] <<Step S1016>> Since it is necessary to switch the data frame in the read data storage buffer 208, the number of read frames (fn) is incremented, and the process proceeds to step S1017.

[0112] <<Step S1017>> To read out data stored in EEPROM 15, the data pointer (dp) that stores an address for referencing data information is calculated by adding the header pointer (hp) to the header size (2) of data registration table 201. Also, "0x00" is stored in the read data buffer position (rd) that indicates the buffer position of the read data storage buffer 208, where the data is to be stored, and the process proceeds to step S1018 shown in FIG. 10C.

[0113] <<Steps S1018 and S1019>> To read all of the data for one round of freeze frame data 209, first, the process from step S1018 to step S1031 is looped the number of times equal to the size of the header (looped until loop count (i)<header size (2)). The loop count (i) also indicates the number of elements in the header H[] of the temporary buffer 207.

[0114] In order to analyze all the registration presence / absence information registered in the header during the loop processing of step S1019 (difference information after the first time), the processing from step S1019 to S1029 is looped for the number of flags (looped until loop count (j)<8). The loop count (j) also indicates the bit positions of the header H[] of the read data storage buffer 208 and the header H[] of the temporary buffer 207.

[0115] <<Step S1020>> It is determined whether or not a flag is set in the corresponding bit of the initial header (hereinafter referred to as the initial header) stored in the header of the read data storage buffer 208 (the determination formula is the header H[i]&(0x80>>j)!=0 of the read data storage buffer). If the flag is set in the initial header (YES: Y (flag present)), proceed to step S1021. If the flag is not set (NO: N (flag absent)), proceed to step S1025 shown in FIG. 10D.

[0116] <<Step S1021>> It is determined whether or not a flag is set in the corresponding bit of the header of the temporary buffer 207 (hereinafter referred to as the temporary header) (the determination formula is temporary header H[i] & (0x80>>j)!=0). If a flag is set in the temporary header H[i] (YES: Y (flag present)), proceed to step S1022. If the flag is not set (NO: N (flag absent)), proceed to step S1024.

[0117] <<Step S1022>> If the flag is set in the initial header and the temporary header, it can be determined that the failure analysis data has been registered at the first read, and that there is a difference from the previous data at the subsequent reads.

[0118] Therefore, the data stored in the data pointer (dp) is read into the data [rd] of the current frame [fn] in the read data storage buffer 208, and the process proceeds to step S1023.

[0119] <<Step S1023>> To read the next data, the data pointer (dp) is incremented and the process proceeds to step S1028.

[0120] <<Step S1024>> If the flag is set in the initial header and the flag is not set in the temporary header, it can be determined that there is no difference from the previous data, so the value of the data [rd] of the previous frame [fn-1] is stored in the data [rd] of the current frame [fn] in the read data storage buffer 208, and the process proceeds to step S1028. Note that in the case of the initial read, the values ​​of the initial header and the temporary header always match, so this process is not executed.

[0121] <<Step S1025>> The same determination as in step S1021 is performed. If the flag is set in the temporary header H[i] (YES: Y (flag present)), proceed to step S1026. If the flag is not set (NO: N (flag absent)), proceed to step S1027.

[0122] <<Step S1026>> If a flag is set in the temporary header even though no flag is set in the initial header, it means that data not registered in the data registration table 201 has been stored as failure analysis data, and therefore an abnormal state has occurred, such as RAM 13 being destroyed due to some physical factor or EEPROM 15 having broken down and unable to perform normal storage processing, and so "read abnormality" is set in the read status, and processing ends as shown in FIG. 10C.

[0123] <<Step S1027>> If the flag is not set in the initial header and also in the temporary header, there is no failure analysis data registered, so “0x00” is stored in the data [rd] of the current frame [fn] in the read data storage buffer 208, and the process proceeds to step S1028 shown in FIG. 10C.

[0124] <<Step S1028>> The read data buffer position (rd) is incremented, and the process proceeds to step S1029.

[0125] <<Step S1029>> The loop count (j) is incremented, and the process returns to the loop process of step S1019. When the loop process of step S1019 ends, the process proceeds to step S1030.

[0126] <<Step S1030>> The header pointer (hp) is incremented to read the next header information.

[0127] <<Step S1031>> The loop count (i) is incremented, and the process returns to the loop process of step S1018. When the loop process of step S1018 ends, reading of one frame's worth of data is completed, and the process proceeds to step S1032.

[0128] <<Step S1032>> In order to read the next frame of the freeze frame data 209, the address of the data pointer (dp) is stored in the header pointer (hp), and the process returns to step 1003, where the process is repeated until the header of the freeze frame data 209 cannot be read and the process ends.

[0129] While the present disclosure has been specifically described above based on the embodiments, it goes without saying that the present disclosure is not limited to the above embodiments and can be modified in various ways. [Explanation of symbols]

[0130] 10: ECU, 11: microcomputer, 12: CPU, 13: RAM, 14: ROM, 15: EEPROM, 16: bus, 17: input / output I / F, 18: sensor group, 19: actuator group, 20: external communication I / F, 21: external device, 22: external communication bus, 200: data storage area, 201: data registration table, 202: control program storage area, 203: failure analysis data accumulation process, 204: freeze frame data generation process, 205: freeze frame data reading process, 206: failure analysis ring buffer, 207: temporary buffer, 208: read data storage buffer, 209: freeze frame data, 210: data storage control unit.

Claims

1. a data table in which a plurality of frames each storing a plurality of data constituting vehicle data indicating a vehicle state are stored in a time series; a data storage control unit that stores, when a fault is detected, the plurality of data of new frames in chronological order stored in the data table immediately before the fault is detected in a non-volatile memory; the data storage control unit, in storing in the non-volatile memory a previous frame that is stored chronologically before the new frame, compares adjacent data in the new frame and adjacent data in the previous frame, For data that has changed over time, a flag indicating a difference and the corresponding data are recorded in the non-volatile memory; For data that does not change over time, only a flag indicating a difference is recorded in the non-volatile memory, and the corresponding data itself is not stored in the non-volatile memory. An in-vehicle electronic control device comprising:

2. 2. The vehicle-mounted electronic control device according to claim 1, the data storage control unit has a function of registering a plurality of byte data divided into 1 byte units when each of the plurality of data is composed of a multi-byte length; the data storage control unit, in comparing the plurality of data of the new frame with the plurality of data of the previous frame, compares chronologically adjacent byte data of the plurality of byte data of the new frame with the plurality of byte data of the previous frame; For byte data that changes over time, the flag indicating the difference and the corresponding byte data are recorded in the non-volatile memory; An in-vehicle electronic control device characterized in that, for byte data that does not change over time, only the flag indicating the difference is recorded in the non-volatile memory, and the corresponding byte data itself is not stored in the non-volatile memory.

3. 2. The vehicle-mounted electronic control device according to claim 1, The data storage control unit stores in the non-volatile memory data that has changed over time going back to the time of the fault detection, and stores only a flag for data that has not changed in the non-volatile memory.

4. 2. The vehicle-mounted electronic control device according to claim 1, The data storage control unit processes the multiple frames stored in the data table in chronological order, from newest vehicle data frames to oldest vehicle data frames, and stores them in the non-volatile memory.

5. 2. The vehicle-mounted electronic control device according to claim 1, The in-vehicle electronic control device is characterized in that the data storage control unit stores the multiple frames stored in the data table in the non-volatile memory in a packed manner so that there are no blank spaces in the memory area.

6. 2. The vehicle-mounted electronic control device according to claim 1, The in-vehicle electronic control device is characterized in that the data table includes null data that has no registered data.

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