Signal transmission device, electronic device, vehicle

Abstract

To eliminate an insulating element without switching a mode.SOLUTION: A signal transmission device 400 includes a transmission circuit 412 for performing pulse-driving on one of signals INH and INL when the logical level of the signal IN is switched, a reception circuit 423 for switching the logical level of a signal OUT in response to the signals INH and INL, and an isolation circuit 430 for transmitting each of the signals INH and INL while isolating the transmission circuit 412 and the reception circuit 423 from each other. The transmission circuit 412 performs pulse-driving on one of the signals INH and INL in accordance with a predetermined communication protocol when serial communication is performed after the pulse-driving is performed on one of the signals INH and INL in the case where the logical level of the signal IN is switched. After the logical level of the signal OUT is switched according to one of the signals INH and INL, the reception circuit 423 detects whether the one of the signals INH and INL complies with the communication protocol to determine whether the serial communication should be established / canceled.SELECTED DRAWING: Figure 14

Description

[Technical field]

[0001] The present disclosure relates to a signal transmission device, an electronic device, and a vehicle. [Background technology]

[0002] Conventionally, signal transmission devices that transmit signals between a primary circuit system and a secondary circuit system while electrically insulating the primary circuit system and the secondary circuit system have been used in various applications (such as power supplies or motor drive devices).

[0003] As an example of the related art, Patent Document 1 by the applicant of the present application can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2022 / 070944

[0005] [overview] However, in the conventional signal transmission device, there is room for reducing the number of insulating elements.

[0006] For example, a signal transmission device according to the present disclosure includes a transmission circuit configured to pulse-drive one of a second pulse signal and a third pulse signal when a logical level of a first pulse signal is switched, a reception circuit configured to switch a logical level of a fourth pulse signal in response to the second pulse signal and the third pulse signal, and an isolation circuit configured to transmit the second pulse signal and the third pulse signal while isolating between the transmission circuit and the reception circuit, wherein the transmission circuit pulse-drives one of the second pulse signal and the third pulse signal when a logical level of the first pulse signal is switched, and then pulse-drives the one of the second pulse signal and the third pulse signal in accordance with a predetermined communication protocol when performing serial communication, and the reception circuit switches the logical level of the fourth pulse signal in response to the one of the second pulse signal and the third pulse signal, and then detects whether the one of the second pulse signal and the third pulse signal complies with the communication protocol and determines whether to establish or abandon the serial communication. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing a basic configuration of a signal transmission device. [Diagram 2] FIG. 2 is a diagram showing the basic structure of a transformer chip. [Diagram 3] FIG. 3 is a perspective view of a semiconductor device used as a two-channel type transformer chip. [Figure 4] FIG. 4 is a plan view of the semiconductor device shown in FIG. [Diagram 5] FIG. 5 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device of FIG. [Figure 6] FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 8] FIG. 8 is an enlarged view (isolation structure) of the region XIII shown in FIG. [Figure 9] FIG. 9 is a diagram illustrating an example of the layout of a transformer chip. [Figure 10] FIG. 10 is a diagram showing a detailed configuration of the signal transmission device. [Figure 11] FIG. 11 is a diagram showing an example of a configuration of an electronic device equipped with a signal transmission device. [Figure 12] FIG. 12 is a diagram showing operation mode switching control. [Figure 13] FIG. 13 is a diagram showing an erroneous transition of the operation mode. [Figure 14] FIG. 14 is a diagram showing a first embodiment of a signal transmission device. [Figure 15] FIG. 15 is a diagram illustrating a signal transmission operation in the first embodiment. [Figure 16] FIG. 16 is a diagram showing a second embodiment of a signal transmission device. [Figure 17] FIG. 17 is a diagram showing a signal transmission operation (establishment of communication) in the second embodiment. [Figure 18] FIG. 18 illustrates a first example of communication failure. [Figure 19] FIG. 19 illustrates a second example of communication failure. [Figure 20] FIG. 20 illustrates a third example of communication failure. [Figure 21] FIG. 21 is a diagram showing the external appearance of the vehicle.

[0008] [Detailed Description] <Signal transmission device (basic configuration)> 1 is a diagram showing the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s while isolating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system) and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is configured by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0009] The controller chip 210 is a semiconductor chip that operates by receiving a supply of a power supply voltage VCC1 (for example, a maximum of 7 V with respect to GND1). In the controller chip 210, for example, a pulse transmission circuit 211 and buffers 212 and 213 are integrated.

[0010] The pulse transmitting circuit 211 is a pulse generator that generates the transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 211 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputs a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. That is, the pulse transmitting circuit 211 pulse-drives either one of the transmission pulse signals S11 and S21 in response to the logical level of the input pulse signal IN.

[0011] The buffer 212 receives the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0012] The buffer 213 receives the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0013] The driver chip 220 is a semiconductor chip that operates by receiving a power supply voltage VCC2 (for example, a maximum of 30 V with respect to GND2). The driver chip 220 has buffers 221 and 222, a pulse receiving circuit 223, and a driver 224 integrated therein.

[0014] The buffer 221 shapes the waveform of the reception pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231) and outputs the result to the pulse reception circuit 223.

[0015] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs the result to the pulse receiving circuit 223.

[0016] The pulse receiving circuit 223 generates an output pulse signal OUT by driving the driver 224 in response to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so as to raise the output pulse signal OUT to a high level in response to the pulse drive of the received pulse signal S12, and to lower the output pulse signal OUT to a low level in response to the pulse drive of the received pulse signal S22. That is, the pulse receiving circuit 223 switches the logical level of the output pulse signal OUT in response to the logical level of the input pulse signal IN. Note that, for example, an RS flip-flop can be suitably used as the pulse receiving circuit 223.

[0017] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223 .

[0018] The transformer chip 230 uses transformers 231 and 232 to provide DC insulation between the controller chip 210 and the driver chip 220, and outputs the transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 to the pulse reception circuit 223 as reception pulse signals S12 and S22, respectively. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0019] More specifically, the transformer 231 outputs a receiving pulse signal S12 from the secondary coil 231s in response to a transmitting pulse signal S11 input to the primary coil 231p, while the transformer 232 outputs a receiving pulse signal S22 from the secondary coil 232s in response to a transmitting pulse signal S21 input to the primary coil 232p.

[0020] As described above, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to a rise signal and a fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0021] Incidentally, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, in addition to the controller chip 210 and the driver chip 220, and these three chips are sealed in a single package.

[0022] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), making it possible to reduce manufacturing costs.

[0023] The signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device for on-board equipment mounted in a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (BEVs [battery electric vehicles], HEVs [hybrid electric vehicles], PHEVs / PHVs (plug-in hybrid electric vehicle / plug-in hybrid vehicle), or xEVs such as FCEVs / FCVs (fuel cell electric vehicle / fuel cell vehicle)).

[0024] <Trans chip (basic structure)> Next, the basic structure of the transformer chip 230 will be described. Fig. 2 is a diagram showing the basic structure of the transformer chip 230. In the transformer chip 230 of this figure, the transformer 231 includes a primary coil 231p and a secondary coil 231s that face each other in the vertical direction. The transformer 232 includes a primary coil 232p and a secondary coil 232s that face each other in the vertical direction.

[0025] Both the primary coils 231p and 232p are formed in a first wiring layer (lower layer) 230a of the transformer chip 230. Both the secondary coils 231s and 232s are formed in a second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. The secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0026] The primary coil 231p is laid in a spiral shape starting from a first end connected to the internal terminal X21 so as to surround the periphery of the internal terminal X21 in a clockwise direction, and a second end corresponding to the end point is connected to the internal terminal X22. On the other hand, the primary coil 232p is laid in a spiral shape starting from a first end connected to the internal terminal X23 so as to surround the periphery of the internal terminal X23 in a counterclockwise direction, and a second end corresponding to the end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are linearly arranged in the order shown in the figure.

[0027] The internal terminal X21 is connected to the external terminal T21 of the second layer 230b via a conductive wiring Y21 and a via Z21. The internal terminal X22 is connected to the external terminal T22 of the second layer 230b via a conductive wiring Y22 and a via Z22. The internal terminal X23 is connected to the external terminal T23 of the second layer 230b via a conductive wiring Y23 and a via Z23. The external terminals T21 to T23 are arranged in a straight line and are used for wire bonding with the controller chip 210.

[0028] The secondary coil 231s is laid in a spiral shape so as to surround the external terminal T24 in a counterclockwise direction, starting from a first end connected to the external terminal T24, and a second end corresponding to the end point is connected to the external terminal T25. On the other hand, the secondary coil 232s is laid in a spiral shape so as to surround the external terminal T26 in a clockwise direction, starting from a first end connected to the external terminal T26, and a second end corresponding to the end point is connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the illustrated order, and are used for wire bonding with the driver chip 220.

[0029] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, and are DC-insulated from the primary coils 231p and 232p. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0030] <Trans chip (2 channel type)> FIG. 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device 5 shown in FIG. 3. FIG. 5 is a plan view showing a layer in which a low potential coil 22 (corresponding to a primary coil of a transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 6 is a plan view showing a layer in which a high potential coil 23 (corresponding to a secondary coil of a transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view of region XIII shown in FIG. 7, showing an isolation structure 130.

[0031] 3 to 7, the semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide band gap semiconductor, and a compound semiconductor.

[0032] The wide band gap semiconductor is made of a semiconductor whose band gap exceeds that of silicon (about 1.12 eV). The band gap of the wide band gap semiconductor is preferably 2.0 eV or more. The wide band gap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride) and GaAs (gallium arsenide).

[0033] In this embodiment, the semiconductor chip 41 includes a semiconductor substrate made of silicon. The semiconductor chip 41 may be an epitaxial substrate having a layered structure including a semiconductor substrate made of silicon and an epitaxial layer made of silicon. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0034] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0035] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0036] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface in a plan view. The insulating main surface 52 extends parallel to the first main surface .

[0037] The insulating side walls 53A-53D include a first insulating side wall 53A, a second insulating side wall 53B, a third insulating side wall 53C, and a fourth insulating side wall 53D. The insulating side walls 53A-53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip side walls 44A-44D. Specifically, the insulating side walls 53A-53D are formed flush with the chip side walls 44A-44D. The insulating side walls 53A-53D form ground surfaces flush with the chip side walls 44A-44D.

[0038] The insulating layer 51 has a multi-layer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and a plurality of (11 layers in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the thickness of the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0039] Each of the interlayer insulating layers 57 has a laminated structure including a first insulating layer 58 on the lowermost insulating layer 55 side and a second insulating layer 59 on the uppermost insulating layer 56 side. The first insulating layer 58 may include silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, about 0.3 μm).

[0040] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, about 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0041] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of layers of the interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be realized. In addition, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0042] The semiconductor device 5 includes a first functional device 45 formed on an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (corresponding to the aforementioned transformer). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed in the inner part of the insulating layer 51 at intervals from the insulating side walls 53A to 53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0043] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side to the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. In the following, the structure of the first transformer 21A will be described as an example. The structures of the second transformer 21B, the third transformer 21C, and the fourth transformer 21D are omitted because the description of the structure of the first transformer 21A applies mutatis mutandis.

[0044] 5 to 7, the first transformer 21A includes a low potential coil 22 and a high potential coil 23. The low potential coil 22 is formed in an insulating layer 51. The high potential coil 23 is formed in the insulating layer 51 so as to face the low potential coil 22 in the normal direction Z. In this embodiment, the low potential coil 22 and the high potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., a plurality of interlayer insulating layers 57).

[0045] The low potential coil 22 is formed on the lowermost insulating layer 55 (semiconductor chip 41) side within the insulating layer 51, and the high potential coil 23 is formed on the uppermost insulating layer 56 (insulating main surface 52) side of the low potential coil 22 within the insulating layer 51. In other words, the high potential coil 23 faces the semiconductor chip 41 with the low potential coil 22 in between. The low potential coil 22 and the high potential coil 23 may be disposed in any position. Furthermore, it is sufficient that the high potential coil 23 faces the low potential coil 22 with one or more interlayer insulating layers 57 in between.

[0046] The distance between the low potential coil 22 and the high potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is appropriately adjusted according to the dielectric strength and electric field strength between the low potential coil 22 and the high potential coil 23. In this embodiment, the low potential coil 22 is formed in the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high potential coil 23 is formed in the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0047] The low potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape extending in an elliptical shape (oval shape) in a plan view. A portion forming the innermost periphery of the first spiral portion 26 defines a first inner region 66 having an elliptical shape in a plan view.

[0048] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0049] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the form shown in Fig. 5 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a rectangular shape, or in a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a rectangular shape, or in a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0050] The low potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low potential coil 22 may have a laminated structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0051] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape extending in an elliptical shape (oval shape) in a plan view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 having an elliptical shape in a plan view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0052] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. It is preferable that the number of turns of the second helical portion 29 exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26, or may be equal to the number of turns of the first helical portion 26.

[0053] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0054] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0055] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 6 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a rectangular shape, or in a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a rectangular shape, or in a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0056] The high potential coil 23 is preferably formed of the same conductive material as the low potential coil 22. That is, like the low potential coil 22, the high potential coil 23 preferably includes a barrier layer and a body layer.

[0057] 4, the semiconductor device 5 includes a plurality of (12 in this figure) low potential terminals 11 and a plurality of (12 in this figure) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0058] The low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the low potential terminals 11 are formed in a region on the insulating sidewall 53B side at intervals in the second direction Y from the transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0059] The low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E and a sixth low potential terminal 11F. In this embodiment, two of each of the low potential terminals 11A to 11F are formed. The number of the low potential terminals 11A to 11F is arbitrary.

[0060] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in a plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in a plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in a plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in a plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in a plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in a plan view.

[0061] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0062] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0063] The multiple high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the multiple low potential terminals 11. Specifically, the multiple high potential terminals 12 are formed in a region on the insulating sidewall 53A side at intervals from the multiple low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0064] The multiple high potential terminals 12 are formed in areas close to the corresponding transformers 21A to 21D in a plan view. The closeness of the high potential terminals 12 to the transformers 21A to 21D means that the distance between the high potential terminals 12 and the transformers 21 in a plan view is less than the distance between the low potential terminals 11 and the high potential terminals 12.

[0065] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A-21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A-21D in the first direction X in a plan view.

[0066] The multiple high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the multiple high potential terminals 12A to 12F are formed. The number of the multiple high potential terminals 12A to 12F is arbitrary.

[0067] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in a region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in a region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0068] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0069] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0070] 5 to 7, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of first low potential wirings 31, a plurality of second low potential wirings 32, a plurality of first high potential wirings 33, and a plurality of second high potential wirings 34 are formed.

[0071] The first low potential wiring 31 and the second low potential wiring 32 fix the low potential coil 22 of the first transformer 21A and the low potential coil 22 of the second transformer 21B to the same potential. The first low potential wiring 31 and the second low potential wiring 32 also fix the low potential coil 22 of the third transformer 21C and the low potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low potential wiring 31 and the second low potential wiring 32 fix all the low potential coils 22 of the transformers 21A to 21D to the same potential.

[0072] The first high potential wiring 33 and the second high potential wiring 34 fix the high potential coil 23 of the first transformer 21A and the high potential coil 23 of the second transformer 21B to the same potential. The first high potential wiring 33 and the second high potential wiring 34 also fix the high potential coil 23 of the third transformer 21C and the high potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high potential wiring 33 and the second high potential wiring 34 fix all the high potential coils 23 of the transformers 21A to 21D to the same potential.

[0073] The multiple first low potential wirings 31 are electrically connected to the corresponding low potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low potential coils 22), respectively. The multiple first low potential wirings 31 have the same structure. In the following, the structure of the first low potential wiring 31 connected to the first low potential terminal 11A and the first transformer 21A will be described as an example. The structure of the other first low potential wirings 31 will be omitted, as the description of the structure of the first low potential wiring 31 connected to the first transformer 21A applies mutatis mutandis.

[0074] The first low potential wiring 31 includes a through wiring 71, a low potential connection wiring 72, a pull-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0075] The through wiring 71, the low potential connection wiring 72, the lead-out wiring 73, the first connection plug electrode 74, the second connection plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low potential coil 22, etc. In other words, the through wiring 71, the low potential connection wiring 72, the lead-out wiring 73, the first connection plug electrode 74, the second connection plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably each include a barrier layer and a main body layer, similar to the low potential coil 22, etc.

[0076] The through wiring 71 penetrates the interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape extending along the normal direction Z. In this embodiment, the through wiring 71 is formed in a region between the lowermost insulating layer 55 and the uppermost insulating layer 56 in the insulating layer 51. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low potential coil 22.

[0077] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrode 80 are each formed of the same conductive material as the low potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrode 80 each include a barrier layer and a main body layer, similar to the low potential coil 22, etc.

[0078] The first electrode layer 78 forms an upper end of the through wiring 71. The second electrode layer 79 forms a lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0079] The multiple wiring plug electrodes 80 are embedded in the multiple interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The multiple wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 toward the uppermost insulating layer 56 so as to be electrically connected to each other, and electrically connect the first electrode layer 78 and the second electrode layer 79. The multiple wiring plug electrodes 80 each have a planar area less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0080] The number of layers of the multiple wiring plug electrodes 80 coincides with the number of layers of the multiple interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 penetrating the multiple interlayer insulating layers 57 may be formed.

[0081] The low potential connecting wire 72 is formed in the first inner region 66 of the first transformer 21A (low potential coil 22) in the same interlayer insulating layer 57 as the low potential coil 22. The low potential connecting wire 72 is formed in an island shape and faces the high potential terminal 12 (first high potential terminal 12A) in the normal direction Z. It is preferable that the low potential connecting wire 72 has a planar area larger than the planar area of ​​the wiring plug electrode 80. The low potential connecting wire 72 is electrically connected to the first inner end 24 of the low potential coil 22.

[0082] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the lowermost insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in a region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in a region between the semiconductor chip 41 and the low potential connection wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0083] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0084] The multiple pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The multiple substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the drawing wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the drawing wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the drawing wiring 73, respectively.

[0085] 6 and 7, the first high potential wirings 33 are electrically connected to the corresponding high potential terminals 12A-12D and the second inner ends 27 of the corresponding transformers 21A-21D (high potential coils 23). The first high potential wirings 33 each have a similar structure. In the following, the structure of the first high potential wiring 33 connected to the first high potential terminal 12A and the first transformer 21A will be described as an example. The structure of the other first high potential wirings 33 will be omitted, since the description of the structure of the first high potential wiring 33 connected to the first transformer 21A applies mutatis mutandis.

[0086] The first high potential wiring 33 includes a high potential connection wiring 81 and one or more (in this embodiment, multiple) pad plug electrodes 82. The high potential connection wiring 81 and the pad plug electrode 82 are preferably formed of the same conductive material as the low potential coil 22, etc. In other words, the high potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low potential coil 22, etc.

[0087] The high potential connection wiring 81 is formed in the second inner region 67 of the high potential coil 23 in the same interlayer insulating layer 57 as the high potential coil 23. The high potential connection wiring 81 is formed in an island shape and faces the high potential terminal 12 (first high potential terminal 12A) in the normal direction Z. The high potential connection wiring 81 is electrically connected to the second inner end 27 of the high potential coil 23. The high potential connection wiring 81 is formed at a distance from the low potential connection wiring 72 in a plan view and does not face the low potential connection wiring 72 in the normal direction Z. This increases the insulation distance between the low potential connection wiring 72 and the high potential connection wiring 81, and increases the dielectric strength voltage of the insulating layer 51.

[0088] The multiple pad plug electrodes 82 are formed in a region between the high potential terminal 12 (first high potential terminal 12A) and the high potential connecting wiring 81 in the uppermost insulating layer 56, and are electrically connected to the high potential terminal 12 and the high potential connecting wiring 81. Each of the multiple pad plug electrodes 82 has a plane area smaller than the plane area of ​​the high potential connecting wiring 81 in a plan view.

[0089] Referring to FIG. 7, it is preferable that the distance D1 between the low-potential terminal 11 and the high-potential terminal 12 exceeds the distance D2 between the low-potential coil 22 and the high-potential coil 23 (D2 < D1). The distance D1 preferably exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the breakdown voltage to be achieved.

[0090] Referring to FIGS. 6 and 7, the semiconductor device 5 includes dummy patterns 85 embedded in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view.

[0091] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high-potential coil 23 and the low-potential coil 22 and is independent of the transformers 21A to 21D. That is, the dummy pattern 85 does not function as the transformers 21A to 21D. The dummy pattern 85 is formed as a shield conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D and suppresses the electric field concentration on the high-potential coil 23. In this form, the dummy pattern 85 is routed with a line density equal to the line density of the high-potential coil 23 per unit area. That the line density of the dummy pattern 85 is equal to the line density of the high-potential coil 23 means that the line density of the dummy pattern 85 falls within the range of ±20% of the line density of the high-potential coil 23.

[0092] The depth position of the dummy pattern 85 inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high potential coil 23 than the low potential coil 22 in the normal direction Z. Note that the dummy pattern 85 being closer to the high potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low potential coil 22.

[0093] In this case, electric field concentration on the high potential coil 23 can be appropriately suppressed. The smaller the distance between the dummy pattern 85 and the high potential coil 23 in the normal direction Z, the more the electric field concentration on the high potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high potential coil 23. In this case, electric field concentration on the high potential coil 23 can be further appropriately suppressed. The dummy pattern 85 includes a plurality of dummy patterns having different electrical states. The dummy pattern 85 may include a high potential dummy pattern.

[0094] The depth position of the high-potential dummy pattern 86 inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0095] Dummy pattern 85 includes a floating dummy pattern formed in an electrically floating state within insulating layer 51 so as to be located around transformers 21A to 21D.

[0096] In this embodiment, the floating dummy pattern is laid out in a dense line shape so as to partially cover and partially expose the area around the high potential coil 23 in a plan view. The floating dummy pattern may be formed to have ends or to have no ends.

[0097] The depth position of the floating dummy pattern within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed.

[0098] The number of floating lines is arbitrary and is adjusted according to the electric field to be relaxed. The floating dummy pattern may be composed of a plurality of floating lines.

[0099] 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed by utilizing a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered by an insulating layer 51 (lowermost insulating layer 55). In FIG. 7, the second functional device 60 is shown in a simplified manner by a dashed line drawn on the surface layer portion of the first main surface 42.

[0100] The second functional device 60 is electrically connected to the low potential terminal 11 via a low potential wiring, and is electrically connected to the high potential terminal 12 via a high potential wiring. The low potential wiring has a similar structure to the first low potential wiring 31 (second low potential wiring 32) except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high potential wiring has a similar structure to the first high potential wiring 33 (second high potential wiring 34) except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A specific description of the low potential wiring and high potential wiring related to the second functional device 60 will be omitted.

[0101] The second functional device 60 may include at least one of a passive device, a semiconductor rectifier device, and a semiconductor switching device. The second functional device 60 may include a circuit network in which any two or more of the passive devices, the semiconductor rectifier device, and the semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0102] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifier device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0103] 5 to 7, the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape spaced apart from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0104] The device region 62 is a region including the first functional device 45 (multiple transformers 21), the second functional device 60, the multiple low potential terminals 11, the multiple high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. The outer region 63 is a region outside the device region 62.

[0105] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (the multiple transformers 21), the second functional device 60, the multiple low potential terminals 11, the multiple high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path connected to the device region 62.

[0106] The seal conductor 61 is formed in a band shape along the insulating side walls 53 to 53D in a plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in a plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in a plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 surrounding the device region 62 in a plan view.

[0107] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending between the upper end and the lower end in a wall shape. In this embodiment, the upper end of the seal conductor 61 is formed on the semiconductor chip 41 side with a gap therebetween from the insulating principal surface 52, and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed on the upper end side with a gap therebetween from the semiconductor chip 41.

[0108] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the multiple low potential terminals 11 and the multiple high potential terminals 12. Furthermore, the seal conductor 61 faces the first functional device 45 (multiple transformers 21), the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85 in the insulating layer 51 in a direction parallel to the insulating principal surface 52. The seal conductor 61 may face a part of the second functional device 60 in the insulating layer 51 in a direction parallel to the insulating principal surface 52.

[0109] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or a plurality (a plurality in this embodiment) of seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end portion of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end portion of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed of the same conductive material as the low potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low potential coil 22, etc.

[0110] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in a plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 toward the uppermost insulating layer 56 so as to be connected to each other. The number of stacked seal plug conductors 64 matches the number of stacked interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0111] As long as one annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end shape. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless shape (annular shape).

[0112] The multiple seal via conductors 65 are formed in the lowermost insulating layer 55 in the region between the semiconductor chip 41 and the seal plug conductor 64. The multiple seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The multiple seal via conductors 65 have a planar area less than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or greater than the planar area of ​​the seal plug conductor 64.

[0113] The width of the sealing conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the sealing conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the sealing conductor 61 is defined by the width in a direction perpendicular to the direction in which the sealing conductor 61 extends.

[0114] 7 and 8, the semiconductor device 5 further includes an isolation structure 130 that is interposed between the semiconductor chip 41 and the seal conductor 61 and electrically isolates the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0115] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0116] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41, and extends in a band shape along the seal conductor 61 in a plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in a plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion in which the lower end portion (seal via conductor 65) of the seal conductor 61 is embedded toward the semiconductor chip 41 side. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0117] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body portion 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in a plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0118] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed in the first main surface 42 with a gap therebetween from the chip sidewalls 44A to 44D.

[0119] The main body portion 130C has a flat surface extending approximately parallel to the first main surface 42 of the semiconductor chip 41. The main body portion 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body portion 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 may take various forms in addition to the field insulating film 131.

[0120] 7, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0121] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may include silicon oxide. The first inorganic insulating layer 141 preferably includes USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may include silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength voltage on the high potential coil 23 can be increased.

[0122] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of the USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable to form the first inorganic insulating layer 141 thicker than the second inorganic insulating layer 142.

[0123] The first inorganic insulating layer 141 may contain at least one of BPSG (boron doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. In this case, however, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0124] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have an overlapping portion that rides up onto the peripheral portion of the low potential terminal 11. The inorganic insulating layer 140 may have an overlapping portion that rides up onto the peripheral portion of the high potential terminal 12.

[0125] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0126] The thickness of the organic insulating layer 145 is preferably greater than the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low potential coil 22 and the high potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably equal to or greater than 2 μm and equal to or less than 10 μm. Furthermore, the thickness of the organic insulating layer 145 is preferably equal to or greater than 5 μm and equal to or less than 50 μm. According to these structures, the thickness of the inorganic insulating layer 140 and the organic insulating layer 145 can be suppressed, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high potential coil 23.

[0127] The organic insulating layer 145 includes a first portion 146 covering the region on the low potential side and a second portion 147 covering the region on the high potential side. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low potential terminal openings 148 that expose a plurality of low potential terminals 11 (low potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have an overlap portion that rises onto the periphery (overlap portion) of the low potential pad opening 143.

[0128] The second portion 147 is formed at a distance from the first portion 146, and exposes the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high potential terminal openings 149 that expose the plurality of high potential terminals 12 (high potential pad openings 144). The second portion 147 may have an overlap portion that rises onto the periphery (overlap portion) of the high potential pad opening 144.

[0129] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the multiple high potential coils 23, the multiple high potential terminals 12, the first high potential dummy pattern 87, the second high potential dummy pattern 88, and the floating dummy pattern 121.

[0130] The embodiment of the present invention can be embodied in further other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form having only the second functional device 60 without the first functional device 45 may be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0131] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the sealing conductor 61. Also, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the sealing conductor 61.

[0132] In the above embodiment, an example has been described in which the second functional device 60 is formed. However, the second functional device 60 is not necessarily required, and may be removed.

[0133] In the above embodiment, an example has been described in which the dummy pattern 85 is formed. However, the dummy pattern 85 is not necessarily required, and may be removed.

[0134] In the above embodiment, an example has been described in which the first functional device 45 is a multi-channel type device including a plurality of transformers 21. However, a first functional device 45 of a single-channel type device including a single transformer 21 may be adopted.

[0135] <Transformer arrangement> 9 is a plan view (top view) showing a schematic example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the above-mentioned semiconductor device 5). The transformer chip 300 in this figure has a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0136] In the transformer chip 300, pads a1 and b1 are connected to one end of a secondary coil L1s forming a first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of a secondary coil L2s forming a second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0137] Moreover, pads a3 and b3 are connected to one end of a secondary coil L3s forming the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of a secondary coil L4s forming the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0138] Note that the primary coil forming the first transformer 301, the primary coil forming the second transformer 302, the primary coil forming the third transformer 303, and the primary coil forming the fourth transformer 304 are not shown in the figure. However, the primary coils basically have the same configuration as the secondary coils L1s to L4s, and are arranged directly below the secondary coils L1s to L4s, respectively, so as to face the secondary coils L1s to L4s, respectively.

[0139] That is, pads a5 and b5 are connected to one end of the primary coil forming the first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Also, pads a6 and b6 are connected to one end of the primary coil forming the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0140] Moreover, pads a7 and b7 are connected to one end of a primary coil forming the third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Moreover, pads a8 and b8 are connected to one end of a primary coil forming the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0141] However, the above-mentioned pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are led out from the inside of the transformer chip 300 to the surface through vias (not shown).

[0142] Among the above-mentioned pads, pads a1 to a8 correspond to first current supply pads, pads b1 to b8 correspond to first voltage measurement pads, pads c1 to c4 correspond to second current supply pads, and pads d1 to d4 correspond to second voltage measurement pads.

[0143] Therefore, the transformer chip 300 of this configuration example can accurately measure the series resistance component of each coil during the defective product inspection. Therefore, it is possible to not only reject defective products in which each coil has a break in wiring, but also to appropriately reject defective products in which each coil has an abnormal resistance value (for example, a short circuit between coils), and ultimately to prevent defective products from being released onto the market.

[0144] For the transformer chip 300 that has passed the defective product inspection, the above-mentioned multiple pads may be used as a means for connecting the primary chip and the secondary chip (for example, the above-mentioned controller chip 210 and driver chip 220).

[0145] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input or output terminals of the secondary chip, respectively, and pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0146] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input or output terminals of the primary chip, respectively, and pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0147] Here, the first transformer 301 to the fourth transformer 304 are arranged in a manner of being coupled for each signal transmission direction, as shown in Fig. 9. In accordance with this figure, for example, the first transformer 301 and the second transformer 302 which transmit signals from the primary side chip to the secondary side chip are made into a first pair by a first guard ring 305. Also, for example, the third transformer 303 and the fourth transformer 304 which transmit signals from the secondary side chip to the primary side chip are made into a second pair by a second guard ring 306.

[0148] The reason for such coupling is to ensure a withstand voltage between the primary coil and the secondary coil when the primary coil and the secondary coil forming each of the first transformer 301 to the fourth transformer 304 are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0149] The first guard ring 305 and the second guard ring 306 may be connected to a low impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0150] In the transformer chip 300, the pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. The pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. The pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. The pads c4 and d4 are shared between the corresponding primary coils. With this configuration, the number of pads can be reduced, and the transformer chip 300 can be made smaller.

[0151] 9, the primary coil and secondary coil forming each of the first transformer 301 to the fourth transformer 304 are desirably wound in a rectangular shape (or a track shape with rounded corners) in a plan view of the transformer chip 300. With this configuration, the area of ​​the overlapping portion between the primary coil and the secondary coil becomes larger, and the transmission efficiency of the transformer can be improved.

[0152] Of course, the transformer arrangement in this figure is merely one example, and the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to semiconductor devices in general in which coils are integrated on a semiconductor chip.

[0153] <Signal transmission device (detailed configuration)> 10 is a diagram showing a detailed configuration of a signal transmission device. As shown in this diagram, a signal transmission device 400 of this configuration example can be mounted in an electronic device A together with various discrete components (such as a switch element TR1 to be driven). The signal transmission device 400 is formed by sealing a first die 410, a second die 420, and a third die 430 in a single package.

[0154] Like the previously described signal transmission device 200 (FIG. 1), the signal transmission device 400 may be a semiconductor integrated circuit device (a so-called insulated gate driver IC) that generates an output pulse signal OUT in response to an input pulse signal IN to drive the switch element TR1 while isolating the primary circuit system 400p from the secondary circuit system 400s.

[0155] In addition, the signal transmission device 400 can be widely applied to general applications (such as motor drivers, DC / DC converters, AC / DC converters or inverters that handle high voltages) that require signal transmission between the primary circuit system 400p and the secondary circuit system 400s while isolating them from each other.

[0156] The first die 410 is provided in the primary circuit system 400p. The first die 410 corresponds to the controller chip 210 (=first chip) described above. In accordance with this figure, the first die 410 includes logic 411, a transmitting circuit 412, and a receiving circuit 413.

[0157] The logic 411 (corresponding to a signal processing circuit) performs bidirectional insulated communication with the second die 420 via a transmitting circuit 412 and a receiving circuit 413.

[0158] The transmitting circuit 412 drives an insulating element (not shown) of the third die 430 in response to an instruction from the logic 411 to transmit a pulse signal to the second die 420.

[0159] The receiving circuit 413 receives the pulse signal transmitted from the second die 420 via the third die 430 and transmits it to the logic 411 .

[0160] The second die 420 is provided in the secondary circuit system 400s. The second die 420 corresponds to the driver chip 220 (=second chip) described above. In accordance with this figure, the second die 420 includes a logic 421, a transmitting circuit 422, and a receiving circuit 423.

[0161] The logic 421 performs bidirectional isolated communication with the first die 410 via a transmitting circuit 422 and a receiving circuit 423 .

[0162] The transmitting circuit 422 drives an insulating element (not shown) of the third die 430 in response to an instruction from the logic 421 to transmit a pulse signal to the first die 410.

[0163] The receiving circuit 423 receives a pulse signal transmitted from the first die 410 through an insulating element (not shown) of the third die 430 and transmits the signal to the logic 421 .

[0164] The third die 430 is a semiconductor chip that integrates an insulating element (not shown) for bidirectional signal transmission while insulating the first die 410 and the second die 420. For example, the insulating element may be a transformer. That is, the third die 430 corresponds to the aforementioned transformer chip 230 (=third chip).

[0165] When a signal is transmitted from the first die 410 to the second die 420, a first signal transmission path is formed from the logic 411 to the logic 421 via the transmitting circuit 412 and the receiving circuit 423. When a signal is transmitted from the second die 420 to the first die 410, a second signal transmission path is formed from the logic 421 to the logic 411 via the transmitting circuit 422 and the receiving circuit 413.

[0166] The signal transmission device 400 of this configuration example includes a third die 430 that mounts only insulating elements, separately from the first die 410 and the second die 420. With this configuration, the first die 410 and the second die 420 can both be formed by a general low to medium voltage process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage process (withstand voltage of several kV), making it possible to reduce manufacturing costs.

[0167] In addition, both the first die 410 and the second die 420 can be manufactured using existing processes with a proven track record, and there is no need to conduct new reliability tests, which can contribute to shortening development time and reducing development costs.

[0168] The switch element TR1 may be, for example, an upper switch element and a lower switch element of a half-bridge output stage or a full-bridge output stage. The half-bridge output stage or the full-bridge output stage may be used as a load driving means such as a motor driver, or may be used as a power conversion means such as an inverter. As shown in this figure, the switch element TR1 may be an IGBT. The switch element TR1 may also be replaced with a MOSFET [metal oxide semiconductor field effect transistor] or the like.

[0169] <Electronic equipment> 11 is a diagram showing an example of the configuration of an electronic device equipped with a signal transmission device 400. Electronic device A of this example has an upper gate driver IC1H(u / v / w), a lower gate driver IC1L(u / v / w), upper power transistors 2H(u / v / w), lower power transistors 2L(u / v / w), an ECU [electronic control unit] 3, and a motor 4.

[0170] The upper gate drivers IC1H(u / v / w) drive the upper power transistors 2H(u / v / w) by generating upper gate drive signals in response to upper gate control signals input from the ECU 3 while insulating the ECU 3 from the upper power transistors 2H(u / v / w).

[0171] The lower gate drivers IC1L(u / v / w) drive the lower power transistors 2L(u / v / w) by generating lower gate drive signals in response to lower gate control signals input from the ECU 3 while insulating the ECU 3 from the lower power transistors 2L(u / v / w).

[0172] Note that as the above upper gate driver ICs 1H (u / v / w) and lower gate driver ICs 1L (u / v / w), the previously described signal transmission device 400 can be preferably used.

[0173] The upper power transistors 2H (u / v / w) are each connected between the power supply terminal of the power system (= the terminal to which the load power supply voltage PVDD is applied) and each phase input terminal of the motor 4 as the upper switches forming the half-bridge output stages of three phases (U phase / V phase / W phase).

[0174] The lower power transistors 2L (u / v / w) are each connected between each phase input terminal of the motor 4 and the power system ground terminal as the lower switches forming the half-bridge output stages of three phases (U phase / V phase / W phase).

[0175] In this figure, IGBTs [insulated gate bipolar transistors] are used as the upper power transistors 2H (u / v / w) and the lower power transistors 2L (u / v / w) respectively. However, for example, it is also possible to use MOSFETs instead of IGBTs.

[0176] The ECU 3 controls the rotational drive of the motor 4 by driving the upper power transistors 2H (u / v / w) and the lower power transistors 2L (u / v / w) respectively via the upper gate driver ICs 1H (u / v / w) and the lower gate driver ICs 1L (u / v / w). Further, the ECU 3 also has a function of monitoring the abnormality detection states and self-diagnosis results of the upper gate driver ICs 1H (u / v / w) and the lower gate driver ICs 1L (u / v / w) respectively.

[0177] The motor 4 is a three-phase motor that is rotationally driven according to the three-phase drive voltages U / V / W respectively input from the half-bridge output stages of three phases (U phase / V phase / W phase).

[0178] <PWM Mode and SPI Communication Mode> 12 is a diagram showing switching control of the operation mode. More specifically, in this diagram, in the signal transmission device 400, the isolation elements 431-434 integrated in the third die 430 are shared by both the PWM [pulse width modulation] mode and the SPI [serial peripheral interface] communication mode. The isolation elements 431-434 may be transformers.

[0179] In the PWM mode, the first die 410 generates a rise signal INH and a fall signal INL from an externally inputted input pulse signal IN. For example, the rise signal INH is pulse-driven in response to the rising edge of the input pulse signal IN. On the other hand, the fall signal INL is pulse-driven in response to the falling edge of the input pulse signal IN. The rise signal INH and the fall signal INL are each transmitted from the first die 410 to the second die 420 via the third die 430 (particularly, the insulating elements 431 and 432).

[0180] The second die 420 generates an output pulse signal OUT from the rise signal INH and the fall signal INL. For example, the output pulse signal OUT is raised to a high level in response to the pulse driving of the rise signal INH. On the other hand, the output pulse signal OUT is lowered to a low level in response to the pulse driving of the fall signal INL. The output pulse signal OUT is externally output to a control end of a switch element TR1 (not shown).

[0181] Also, the second die 420 generates a rise signal OSFBH and a fall signal OSFBL in response to the on / off state of the switch element TR1. For example, the rise signal OSFBH is pulse-driven in response to the on transition of the switch element TR1. Meanwhile, the fall signal OSFBL is pulse-driven in response to the off transition of the switch element TR1. The rise signal OSFBH and the fall signal OSFBL are respectively transmitted from the second die 420 to the first die 410 via the third die 430 (particularly, the insulating elements 433 and 434).

[0182] The first die 410 generates a feedback pulse signal OSFB from the rise signal OSFBH and the fall signal OSFBL and outputs the feedback pulse signal OSFB to the outside. The feedback pulse signal OSFB is a pulse signal according to the on / off state of the switch element TR1 driven by the output pulse signal OUT.

[0183] In addition, a microcomputer (e.g., an ECU) provided outside the signal transmission device 400 can monitor the feedback pulse signal OSFB to check whether the switch element TR1 is turned on / off as intended in response to the input pulse signal IN.

[0184] Thus, in the PWM mode, the input pulse signal IN is input to the outside and the output pulse signal OUT is output to the outside. Also, in the PWM mode, the feedback pulse signal OSFB corresponding to the on / off state of the switch element TR1 driven by the output pulse signal OUT is output to the outside. Note that, in the PWM mode, the rise signal INH, the fall signal INL, the rise signal OSFBH, and the fall signal OSFBL are transmitted bidirectionally between the first die 410 and the second die 420 via the third die 430. The PWM mode can be understood as, for example, a first operation mode used during normal driving of the switch element TR1.

[0185] The first die 410 also has a function of serial communication with the microcomputer described above. For example, the first die 410 transmits and receives a chip select signal CSB, an input data signal MOSI, an output data signal MISO, and a clock signal SCLK in accordance with the SPI protocol.

[0186] Therefore, in the SPI communication mode, the data signal DATA12, the clock signal CLK12, the data signal DATA21, and the clock signal CLK21 are transmitted bidirectionally between the first die 410 and the second die 420 via the third die 430 (particularly the insulating elements 431 to 434). The SPI communication mode can be understood as, for example, a second operation mode used when setting the drive parameters of the switch element TR1.

[0187] Here, the PWM mode and the SPI communication mode are switched exclusively. That is, the PWM mode and the SPI communication mode are not used at the same time. Therefore, in the signal transmission device 400, the insulating elements 431 to 434 integrated in the third die 430 are shared by both the PWM mode and the SPI communication mode.

[0188] In accordance with this figure, the isolation element 431 is used as a transmission means for the rise signal INH and the data signal DATA12. The isolation element 432 is used as a transmission means for the fall signal INL and the clock signal CLK12. The isolation element 433 is used as a transmission means for the rise signal OSFBH and the data signal DATA21. The isolation element 434 is used as a transmission means for the fall signal OSFBL and the clock signal CLK21.

[0189] In this way, if the isolation elements 431-434 are shared between the PWM mode and the SPI communication mode, it is possible to reduce the number of isolation elements integrated on the third die 430. For example, if an isolation element is provided as a one-to-one correspondence for each of the eight signals (INH, INL, OSFBH, OSFBL, DATA12, CLK12, DATA21, and CLK21), eight isolation elements are required. In contrast, with the configuration shown in the figure, four isolation elements 431-434 are sufficient.

[0190] The signal transmission device 400 may be in the PWM mode when a chip select signal CSB, which is externally input to select a communication target of the microcomputer, is at a high level (=a logic level when a chip is not selected).

[0191] <Considerations regarding erroneous transitions of operation modes> 13 is a diagram showing an erroneous transition of the operation mode. First, a normal state in which the signal transmission device 400 is correctly switched to the PWM mode is considered (see the upper left frame). In this case, the first die 410 transmits a PWM signal as a transmission pulse signal. Also, the second die 420 receives the reception pulse signal as a PWM signal. Therefore, the PWM signal is normally transmitted.

[0192] Next, a normal state in which the signal transmission device 400 is correctly switched to the SPI communication mode is considered (see the lower right frame). In this case, the first die 410 transmits a serial communication signal as a transmission pulse signal. Also, the second die 420 receives the reception pulse signal as a serial communication signal. Therefore, the serial communication signal is normally transmitted.

[0193] By switching the operation mode in this way, the insulating elements 431 to 434 can be shared by both the PWM mode and the serial communication mode. However, in a configuration in which the PWM mode and the serial communication mode can be switched, there is a risk that the operation mode may transition to an abnormal state due to noise or the like as a trigger (see the hatched lower left and upper right frames).

[0194] For example, a case is assumed in which noise causes a transition from the PWM mode (upper left frame) to an abnormal state (lower left frame). In this case, the first die 410 transmits a PWM signal as a transmission pulse signal. However, the second die 420 attempts to receive the reception pulse signal as a serial communication signal. As a result, the PWM signal is not transmitted normally.

[0195] Also, for example, a case may be assumed in which noise causes a transition from the SPI communication mode (upper right frame) to an abnormal state (lower right frame). In this case, the first die 410 transmits a serial communication signal as a transmission pulse signal. However, the second die 420 attempts to receive the reception pulse signal as a PWM signal. As a result, the serial communication signal is not transmitted normally.

[0196] Furthermore, once a transition occurs from a normal state (PWM mode or SPI communication mode) to an abnormal state, there is no way to return to the normal state.

[0197] In view of the above considerations, an embodiment capable of eliminating erroneous transitions of operation modes is proposed below.

[0198] <Signal Transmission Device (First Embodiment)> 14 is a diagram showing a first embodiment of a signal transmission device 400. The signal transmission device 400 of this embodiment includes a first die 410, a second die 420, and a third die 430, similar to the above-mentioned FIG.

[0199] The first die 410 receives an input pulse signal IN and a slew rate selection signal GRSEL from a microcomputer (e.g., ECU) not shown. Meanwhile, the first die 410 outputs an interrupt signal INTB (=feedback pulse signal OSFB) to the microcomputer. The first die 410 also has a serial communication function with the microcomputer. For example, the first die 410 transmits and receives a chip select signal CSB, an input data signal MOSI, an output data signal MISO, and a clock signal SCLK in accordance with a predetermined communication protocol (e.g., SPI protocol).

[0200] The first die 410 has integrated thereon a transmitting circuit 412 and a receiving circuit 413. Although not explicitly shown in this figure, the first die 410 may also have integrated thereon the aforementioned logic 411.

[0201] The transmission circuit 412 pulse-drives one of the rise signal INH1 and the fall signal INL1 if the slew rate selection signal GRSEL is at a low level when the logical level of the input pulse signal IN is switched, and pulse-drives one of the rise signal INH2 and the fall signal INL2 if the slew rate selection signal GRSEL is at a high level when the logical level of the input pulse signal IN is switched.

[0202] For example, the rise signals INH1 and INH2 are pulse-driven in response to the rising edge of the input pulse signal IN, while the fall signals INL1 and INL2 are pulse-driven in response to the falling edge of the input pulse signal IN.

[0203] The receiving circuit 413 switches the logic level of the interrupt signal INTB (=feedback pulse signal OSFB) in response to the rise signal OSFBH and the fall signal OSFBL.

[0204] A transmitting circuit 422 and a receiving circuit 423 are integrated on the second die 420. Although not explicitly shown in this figure, the aforementioned logic 421 may also be integrated on the second die 420.

[0205] The transmission circuit 422 pulse-drives one of the rise signal OSFBH and the fall signal OSFBL when the logic level of the output pulse signal OUT is switched, that is, when the on / off state of the switch element TR1 is switched. For example, the rise signal OSFBH is pulse-driven in response to the on transition of the switch element TR1 (=the rising edge of the output pulse signal OUT). On the other hand, the fall signal OSFBL is pulse-driven in response to the off transition of the switch element TR1 (=the falling edge of the output pulse signal OUT).

[0206] The receiving circuit 423 switches the logic level of the output pulse signal OUT at a slew rate SR1 in response to the rise signal INH1 and the fall signal INL1, and also switches the logic level of the output pulse signal OUT at a slew rate SR2 different from the slew rate SR1 in response to the rise signal INH2 and the fall signal INL2.

[0207] For example, the output pulse signal OUT is raised to a high level in response to the pulse driving of the rise signal INH1 or INH2. On the other hand, the output pulse signal OUT is lowered to a low level in response to the pulse driving of the fall signal INL1 or INL2. The output pulse signal OUT is output to the outside via the control terminal of the switch element TR1 (not shown).

[0208] The third die 430 has isolation circuits 430A and 430B integrated thereon.

[0209] The isolation circuit 430A transmits the rise signals INH1 and INH2 and the fall signals INL1 and INL2 while providing insulation between the transmission circuit 412 and the reception circuit 423. The isolation circuit 430A may include four isolation elements corresponding to the above four signals (INH1, INH2, INL1, and INL2).

[0210] The isolation circuit 430B transmits the rise signal OSFBH and the fall signal OSFBL while providing insulation between the transmission circuit 422 and the reception circuit 413. The isolation circuit 430B may include two isolation elements corresponding to the above two signals (OSFBH and OSFBL).

[0211] In addition, the transmission circuits 412 and 422, and the reception circuits 413 and 423 each have a function of sharing the isolation circuits 430A and 430B as a means for transmitting serial communication signals without requiring switching control of the operation mode (PWM mode / SPI communication mode).

[0212] For example, the transmission circuit 412 pulse-drives the rise signal INH1 or INH2 in response to the rising edge of the input pulse signal IN, and then pulse-drives the rise signals INH1 and INH2 in accordance with a predetermined communication protocol when performing serial communication via the isolation circuit 430A. For example, the rise signals INH1 and INH2 correspond to the clock signal CLK1 and the data signal DAT1, respectively.

[0213] In addition, the transmission circuit 412 pulse-drives the fall signal INL1 or INL2 in response to the falling edge of the input pulse signal IN, and then pulse-drives the fall signals INL1 and INL2 in accordance with a predetermined communication protocol when performing serial communication via the isolation circuit 430A. For example, the fall signals INL1 and INL2 correspond to the clock signal CLK2 and the data signal DAT2, respectively.

[0214] When the rise signals INH1 and INH2 are pulse-driven after the output pulse signal OUT rises to a high level in response to the rise signal INH1 or INH2, the receiving circuit 423 detects whether the rise signals INH1 and INH2 comply with a predetermined communication protocol. Then, the receiving circuit 423 determines whether to establish or cancel serial communication via the isolation circuit 430A in response to the detection result.

[0215] Furthermore, when the fall signals INL1 and INL2 are pulse-driven after the output pulse signal OUT falls to a low level in response to the fall signal INL1 or INL2, the receiving circuit 423 detects whether the fall signals INL1 and INL2 comply with a predetermined communication protocol. Then, the receiving circuit 423 determines whether to establish or cancel serial communication via the isolation circuit 430A.

[0216] In addition, the transmission circuit 422 pulse-drives the rise signal OSFBH in response to the ON transition of the switch element TR1 (=the rising edge of the output pulse signal OUT) and then pulse-drives the rise signal OSFBH in accordance with a predetermined communication protocol when performing serial communication via the isolation circuit 430B. For example, the rise signal OSFBH corresponds to the data signal DA1. The data signal DA1 is synchronized with the clock signal CLK1 or CLK2.

[0217] In addition, the transmission circuit 422 pulse-drives the fall signal OSFBL in response to the off transition of the switch element TR1 (=the falling edge of the output pulse signal OUT) and then pulse-drives the fall signal OSFBL in accordance with a predetermined communication protocol when performing serial communication via the isolation circuit 430B. The fall signal OSFBL corresponds to the data signal DA2. The data signal DA2 is synchronized with the clock signal CLK1 or CLK2.

[0218] The receiving circuit 413 raises the interrupt signal INTB (=feedback pulse signal OSFB) to a high level in response to the rise signal OSFBH, and then detects whether the rise signal OSFBH complies with a predetermined communication protocol when the rise signal OSFBH is pulse-driven. Then, the receiving circuit 413 determines whether to establish or cancel serial communication via the isolation circuit 430B in response to the detection result.

[0219] Furthermore, when the fall signal OSFBL is pulse-driven after the interrupt signal INTB (=feedback pulse signal OSFB) falls to a low level in response to the fall signal OSFBL, the receiving circuit 413 detects whether the fall signal OSFBL complies with a predetermined communication protocol. Then, the receiving circuit 413 determines whether to establish or cancel serial communication via the isolation circuit 430B in response to the detection result.

[0220] The receiving circuit 413 may determine whether to establish or cancel serial communication via the isolation circuit 430B depending on whether serial communication via the isolation circuit 430A is being performed.

[0221] In this way, the transmission circuits 412 and 422 sequentially transmit a plurality of types of signals (e.g., PWM signals and serial communication signals) for each signal path of one system. The reception circuits 413 and 423 then discard any signals other than serial communication signals that comply with a predetermined communication protocol, thereby determining whether or not serial communication is established.

[0222] Therefore, in the signal transmission device 400 of this embodiment, the isolation circuits 430A and 430B can be used in common as a means for transmitting the PWM signal and the SPI communication signal, respectively, without the need for switching control of the operation mode (PWM mode / SPI communication mode). In addition, since there are no operation modes, erroneous transition of the operation mode can be fundamentally eliminated.

[0223] 15 is a diagram showing the signal transmission operation of the first embodiment. In this diagram, from the top, the slew rate selection signal GRSEL, the input pulse signal IN, the serial input signal SPI_IN (including the chip select signal CSB, the input data signal MOSI, and the clock signal SCLK), the rise signals INH1 and INH2, the fall signals INL1 and INL2, the output pulse signal OUT, the rise signal OSFBH, the fall signal OSFBL, the interrupt signal INTB (= the feedback pulse signal OSFB), and the serial output signal SPI_OUT (including the output data signal MISO) are depicted.

[0224] At time t1, when the input pulse signal IN rises to a high level during a low-level period of the slew rate selection signal GRSEL, the rise signal INH1 is pulse-driven. Therefore, the output pulse signal OUT rises to a high level at the slew rate SR1. In addition, the rise signal OSFBH is pulse-driven in response to the rise of the output pulse signal OUT. Therefore, the interrupt signal INTB (=feedback pulse signal OSFB) rises to a high level.

[0225] Thereafter, the signal transmission device 400 is in a state in which it can input and output the serial input signal SPI_IN and the serial output signal SPI_OUT until the input pulse signal IN falls to a low level. In accordance with this figure, the signal transmission device 400 is in a state in which it can perform bidirectional serial communication between the first die 410 and the second die 420 using the rise signals INH1, INH2, and OSFBH.

[0226] For example, after the rise signal INH1 is pulse-driven in response to the rising edge of the input pulse signal IN, the rise signals INH1 and INH2 are pulse-driven as the subsequent serial communication signals (clock signal CLK1 and data signal DAT1). The clock signal CLK1 and the data signal DAT1 may be the serial input signal SPI_IN (SCLK and MOSI) itself. The clock signal CLK1 and the data signal DAT1 may be internally generated in response to the serial input signal SPI_IN (SCLK and MOSI).

[0227] Even if the rise signals INH1 and INH2 are pulse-driven during serial communication, there is no problem because the output pulse signal OUT has already been raised to a high level. In other words, the logic level of the output pulse signal OUT should continue to reflect the reception results of the rise signals INH1 and INH2 as they are.

[0228] In addition, after the rise signal OSFBH is pulse-driven in response to the rising edge of the output pulse signal OUT, the rise signal OSFBH is pulse-driven as the subsequent serial communication signal (data signal DA1). The serial output signal SPI_OUT (MISO) may be the data signal DA1 itself. The serial output signal SPI_OUT (MISO) may be internally generated in response to the data signal DA1.

[0229] Even if the rise signal OSFBH is pulse-driven during serial communication, there is no problem because the interrupt signal INTB (=feedback pulse signal OSFB) has already risen to a high level. In other words, the logic level of the interrupt signal INTB (=feedback pulse signal OSFB) should continue to reflect the result of receiving the rise signal OSFBH as is.

[0230] A start pulse SP and an end pulse EP may be added before and after each of the data signals DAT1 and DA1. The start pulse SP corresponds to a start trigger for the data signals DAT1 and DA1. The end pulse EP corresponds to an end trigger for the data signals DAT1 and DA1.

[0231] At time t2, when the input pulse signal IN falls to a low level during the high level period of the slew rate selection signal GRSEL, the fall signal INL2 is pulse-driven. Therefore, the output pulse signal OUT falls to a low level at the slew rate SR2. In addition, the fall signal OSFBL is pulse-driven in response to the falling edge of the output pulse signal OUT. Therefore, the interrupt signal INTB (=feedback pulse signal OSFB) falls to a low level.

[0232] After that, the signal transmission device 400 is in a state where it can input and output the serial input signal SPI_IN and the serial output signal SPI_OUT until the input pulse signal IN is raised to a high level. In accordance with this figure, the signal transmission device 400 is in a state where it can perform bidirectional serial communication between the first die 410 and the second die 420 by the fall signals INL1, INL2, and OSFBL.

[0233] For example, after the fall signal INL2 is pulse-driven in response to the falling edge of the input pulse signal IN, the fall signals INL1 and INL2 are pulse-driven as the subsequent serial communication signals (clock signal CLK2, data signal DAT2). The clock signal CLK2 and the data signal DAT2 may be the serial input signal SPI_IN (SCLK and MOSI) itself. The clock signal CLK2 and the data signal DAT2 may be internally generated in response to the serial input signal SPI_IN (SCLK and MOSI).

[0234] Even if the fall signals INL1 and INL2 are pulse-driven during serial communication, there is no problem because the output pulse signal OUT has already been lowered to a low level. In other words, the logic level of the output pulse signal OUT should continue to reflect the reception results of the fall signals INL1 and INL2 as they are.

[0235] In addition, after the fall signal OSFBL is pulse-driven in response to the falling edge of the output pulse signal OUT, the fall signal OSFBL is pulse-driven as the subsequent serial communication signal (data signal DA2). The serial output signal SPI_OUT (MISO) may be the data signal DA2 itself. The serial output signal SPI_OUT (MISO) may be internally generated in response to the data signal DA2.

[0236] Even if the fall signal OSFBL is pulse-driven during serial communication, there is no problem because the interrupt signal INTB (=feedback pulse signal OSFB) has already been lowered to a low level. In other words, the logic level of the interrupt signal INTB (=feedback pulse signal OSFB) should continue to reflect the reception result of the fall signal OSFBL as is.

[0237] The above-mentioned start pulse and end pulse may be added before and after each of the data signals DAT2 and DA2.

[0238] At time t3, when the input pulse signal IN rises to a high level during the high level period of the slew rate selection signal GRSEL, the rise signal INH2 is pulse-driven. Therefore, the output pulse signal OUT rises to a high level at the slew rate SR2. In addition, the rise signal OSFBH is pulse-driven in response to the rise of the output pulse signal OUT. Therefore, the interrupt signal INTB (=feedback pulse signal OSFB) rises to a high level.

[0239] After that, the signal transmission device 400 is in a state in which it can input and output the serial input signal SPI_IN and the serial output signal SPI_OUT until the input pulse signal IN falls to a low level. For example, the signal transmission device 400 is in a state in which it can perform bidirectional serial communication between the first die 410 and the second die 420 by the rise signals INH1, INH2, and OSFBH.

[0240] Although not shown in the figure, when the input pulse signal IN falls to a low level during a low-level period of the slew rate selection signal GRSEL, the fall signal INL1 is pulse-driven. Therefore, the output pulse signal OUT falls to a low level at the slew rate SR1. Also, the fall signal OSFBL is pulse-driven in response to the falling edge of the output pulse signal OUT. Therefore, the interrupt signal INTB (=feedback pulse signal OSFB) rises to a low level.

[0241] After that, the signal transmission device 400 is in a state in which it can input and output the serial input signal SPI_IN and the serial output signal SPI_OUT until the input pulse signal IN is raised to a high level. For example, the signal transmission device 400 is in a state in which it can perform bidirectional serial communication between the first die 410 and the second die 420 by the fall signals INL1, INL2, and OSFBL.

[0242] According to the above series of operations, even during PWM driving of the switch element TR1, it is possible to perform serial communication safely while sharing the insulating element (transformer).

[0243] The receiving circuit 423 (or logic 421) of the second die 420 may recognize the above-mentioned start pulse as a start trigger of the serial communication, and process the subsequent pulse input as a serial communication signal. However, if the above-mentioned pulse input does not comply with a predetermined communication protocol, the contents of the serial communication may be discarded at any time.

[0244] Furthermore, the transmitting circuit 412 (or logic 411) of the first die 410 knows what kind of input pulse signal IN has been input and what kind of transmission pulse signal (= rise signals INH1 and INH2, and fall signals INL1 and INL2) has been output. Therefore, the transmitting circuit 412 may immediately transmit a reset pulse if the transmission pulse signal unintentionally satisfies a predetermined communication protocol. The reset pulse may be a start pulse that does not accompany a data signal. In this way, if the reset pulse and the start pulse comply with a common communication protocol, the implementation of the reset pulse becomes simple.

[0245] In this way, when the transmitting circuit 412 has a reset pulse output function, the receiving circuit 423 can discard the serial communication not only when the pulse input to itself does not comply with a specified communication protocol, but also when a reset pulse is input from the transmitting circuit 412.

[0246] Also, a function of transmitting a pulse while automatically switching the communication path for each serial communication may be provided. If such a function is implemented, for example, even if the logic level of the input pulse signal IN is switched during serial communication and the contents of the serial communication are discarded, a retry (retransmission of the same contents) can be easily performed thereafter.

[0247] In addition, in this embodiment, the rise signal OSFBH and fall signal OSFBL for generating the interrupt signal INTB (=feedback pulse signal OSFB) are shared as a serial communication path from the second die 420 to the first die 410.

[0248] After serial communication is established with the receiving circuit 423, the transmitting circuit 422 of the second die 420 pulse-drives the rise signal OSFBH or the fall signal OSFBL. By such pulse driving, a serial communication signal (DA1 or DA2) is returned to the receiving circuit 413 of the first die 410.

[0249] Here, the receiving circuit 413 (or logic 411) may know whether or not serial communication is being performed from the first die 410 to the second die 420. Therefore, the receiving circuit 413 may process the rise signal OSFBH or the fall signal OSFBL as a serial communication signal (DA1 or DA2) when serial communication is being performed from the first die 410 to the second die 420. On the other hand, when serial communication is not being performed, the rise signal OSFBH and the fall signal OSFBL may be discarded.

[0250] However, when the rise signal OSFBH and the fall signal OSFBL are shared as serial communication signals (DA1 and DA2), it is desirable for the transmission circuit 412 to pulse-drive either the rise signals INH1 and INH2 or the fall signals INL1 and INL2 in response to the rising or falling edge of the input pulse signal IN, and then wait to start serial communication until the logical level of the interrupt signal INTB (=feedback pulse signal OSFB) switches.

[0251] Alternatively, the timing specifications on the microcomputer side may be determined so that the start of serial communication waits until the logic level of the interrupt signal INTB (=feedback pulse signal OSFB) switches after the logic level of the input pulse signal IN is switched.

[0252] In addition, the transmission circuit 412 may pulse-drive either the rise signals INH1 and INH2 or the fall signals INL1 and INL2 in response to the rising or falling edge of the input pulse signal IN, and then wait until a predetermined time (so-called setup hold time) has elapsed before starting serial communication.

[0253] The receiving circuit 413 may have a function of turning on / off the output function of the interrupt signal INTB (=feedback pulse signal OSFB). For example, when the output function of the interrupt signal INTB is turned off, the rise signal OSFBH and the fall signal OSFBL can each be exclusively used as a serial communication path without being subject to the above-mentioned timing constraints.

[0254] Furthermore, the serial communication path from the second die 420 to the first die 410 is not limited to the above.

[0255] <Signal Transmission Device (Second Embodiment)> 16 is a diagram showing a second embodiment of a signal transmission device 400. In the signal transmission device 400 of this embodiment, the first die 410 (particularly, the transmission circuit 412) sequentially transmits a plurality of types of signals (e.g., a PWM signal and a serial communication signal) for each signal path, as in the first embodiment (FIG. 14) described above. Then, the second die 420 (particularly, the reception circuit 423) discards signals other than serial communication signals conforming to a predetermined communication protocol, thereby determining whether serial communication is established or not.

[0256] However, in the signal transmission device 400 of this embodiment, unlike the first embodiment (FIG. 14), the serial communication is performed asynchronously. That is, the serial communication signal includes the data signals DAT1 and DAT2 described above, but does not include the clock signals CLK1 and CLK2 described above. Therefore, if there are two systems of the rise signal INH and the fall signal INL, PWM drive and serial communication can be compatible.

[0257] 17 is a diagram showing a signal transmission operation (establishment of communication) of the second embodiment. In this diagram, from the top, an input pulse signal IN, a rise signal INH, a fall signal INL, an output pulse signal OUT, a pulse extension signal EXP, a clock-on signal CLKON, and an internal clock signal INTCLK are depicted.

[0258] The pulse stretched signal EXP, the clock-on signal CLKON, and the internal clock signal INTCLK are each internal signals of the second die 420 (described in detail below).

[0259] When the input pulse signal IN rises to a high level, the transmission circuit 412 generates a PWM driving pulse P1 in the rise signal INH. The PWM driving pulse P1 may include x pulses at a driving frequency fa (driving period Ta). fa may be 10 MHz (Ta = 100 ns). x may be 4 pulses. The pulse width (= high level period) of each pulse may be 10 ns or less.

[0260] Upon receiving the PWM drive pulse P1, the receiving circuit 423 raises the output pulse signal OUT to a high level.

[0261] The receiving circuit 423 also receives the logical sum of the rise signal INH and the fall signal INL to generate a pulse expansion signal EXP. The pulse expansion signal EXP may be a signal that is maintained at a high level for an expansion period Texp (>Ta) every time a pulse is generated in either the rise signal INH or the fall signal INL. Texp may be 120 ns.

[0262] Therefore, when x PWM driving pulses P1 are generated in the rise signal INH at a driving frequency fa (driving period Ta), a pulse stretched signal EXP with a pulse width T1 (=Ta×(x-1)+Texp) is generated. When the receiving circuit 423 detects a pulse stretched signal EXP with a pulse width T1 longer than a predetermined threshold, it regards this as a start trigger (or a reset trigger) for the serial communication period T0. As a result, the signal transmission device 400 is in a state in which serial communication can be performed between the first die 410 and the second die 420 by the rise signal INH.

[0263] During the serial communication period T0, the transmission circuit 412 transmits an n-bit data pulse DAT and a start pulse SP and an end pulse EP added before and after the data pulse DAT, respectively.

[0264] The start pulse SP may include y pulses at a drive frequency fb (drive period Tb, where Tb>Texp). For example, fb=5 MHz (Tb=200 ns). Also, y=2 pulses may be generated. In this case, y pulses with a pulse width T2 (=Texp) are generated in the pulse expansion signal EXP.

[0265] When y pulses are generated in the pulse stretched signal EXP as described above, the clock-on signal CLKON is raised to a high level in the second die 420. As a result, generation of the internal clock signal INTCLK starts at the drive frequency fc (drive period Tc). For example, fc may be 10 MHz (Tc=100 ns).

[0266] The data pulse DAT may be generated at a drive frequency fb (drive period Tb) like the start pulse SP. For example, when a data value "1" is transmitted, a pulse is generated in the data pulse DAT. At this time, a pulse with a pulse width T2 (=Texp) is generated in the pulse expansion signal EXP. On the other hand, when a data value "0" is transmitted, no pulse is generated in the data pulse DAT. Therefore, the pulse expansion signal EXP remains at a low level.

[0267] The receiving circuit 423 acquires an n-bit data value from the pulse stretched signal EXP in synchronization with the internal clock signal INTCLK, and discards the contents of the data pulse DAT if the data length is not n bits.

[0268] The end pulse EP may be generated at a drive frequency fa (drive period Ta) like the PWM drive pulse P1. The end pulse EP may include z pulses. z may be greater than or equal to 2 pulses.

[0269] Therefore, when an end pulse EP is generated in the rise signal INH, a pulse stretched signal EXP with a pulse width T3 (=Ta×(z-1)+Texp) is generated. When the receiving circuit 423 detects a pulse stretched signal EXP with a pulse width T3 longer than a predetermined threshold, it regards this as an end trigger (or a reset trigger) of the serial communication period T0. As a result, the above series of serial communications is terminated.

[0270] However, there is a tolerance between the reference clocks (SCLK and INTCLK) of the transmitting circuit 412 and the receiving circuit 423. Therefore, if the internal clock signal INTCLK of the receiving circuit 423 is started at the clock timing of the transmitting circuit 412 and the data pulse DAT is taken in synchronously with the internal clock signal INTCLK, the receiving circuit 423 may not be able to determine whether the data pulse DAT is the mth bit or the (m+1)th bit.

[0271] In particular, when the data value "0" is transmitted consecutively, that is, when the data pulse DAT is maintained at a low level over a number of periods, the above-mentioned problem is likely to occur.

[0272] In order to eliminate the above-mentioned problems, it is desirable that the maximum allowable value of the design tolerance is determined. The transmission circuit 412 should transmit the data value "1" every m bits so that the accumulated error after the start of the internal clock signal INTCLK does not exceed the maximum allowable value of the design tolerance (for one clock). In this way, if the data pulse DAT is designed to rise to a high level periodically, the reception circuit 423 can reset the internal clock signal INTCLK at the rising edge of the data pulse DAT transmitted every m bits. Therefore, even if the reference clocks of the transmission circuit 412 and the reception circuit 423 have a tolerance, the restriction on the transmission data length caused by the tolerance can be relaxed.

[0273] Although not shown in the figure, during the low level period of the input pulse signal IN, serial communication similar to that described above is performed via the fall signal INL.

[0274] Fig. 18 is a diagram showing a first example of communication failure. In this diagram, like Fig. 17, from the top, an input pulse signal IN, a rise signal INH, a fall signal INL, an output pulse signal OUT, a pulse extension signal EXP, a clock-on signal CLKON, and an internal clock signal INTCLK are depicted.

[0275] As shown in the figure, when the input pulse signal IN falls to a low level during the serial communication period T0, a PWM drive pulse P2 is generated in the fall signal INL. The PWM drive pulse P2 may include x pulses at a drive frequency fa (drive period Ta) like the previously mentioned PWM drive pulse P1.

[0276] At this time, the receiving circuit 423 detects a pulse-stretched signal EXP having a pulse width T3 longer than a predetermined threshold value. As a result, the serial communication period T0 ends prematurely. That is, the serial communication may not be established due to an interruption of the PWM control.

[0277] In this case, however, the data length of the data pulse DAT is less than n bits, so the data pulse DAT is discarded. Therefore, even if serial communication is not established, unintended malfunctions will not occur.

[0278] Fig. 19 is a diagram showing a second example of communication failure. In this diagram, like Fig. 17, from the top, the input pulse signal IN, the rise signal INH, the fall signal INL, the output pulse signal OUT, the pulse extension signal EXP, the clock-on signal CLKON, and the internal clock signal INTCLK are depicted.

[0279] As shown in the figure, noise may be superimposed on the pulse extension signal EXP during transmission of the data pulse DAT, causing the serial communication to fail. Therefore, the data pulse DAT may include a parity bit or an error correction code (ECC). With this configuration, an incorrect data pulse DAT can be discarded by the receiving circuit 423. Therefore, the noise resistance of the serial communication is improved.

[0280] Fig. 20 is a diagram showing a third example of communication failure. In this diagram, as in Fig. 17, from the top, the input pulse signal IN, the rise signal INH, the fall signal INL, the output pulse signal OUT, the pulse extension signal EXP, the clock-on signal CLKON, and the internal clock signal INTCLK are depicted.

[0281] As shown in the figure, noise may be superimposed on the pulse expansion signal EXP during the transmission of the start pulse SP, which may result in failure of serial communication.

[0282] In this case, the start timing of the internal clock signal INTCLK may be delayed. In such a case, the first bit of the data pulse DAT is missing. As a result, the data length of the data pulse DAT is less than n bits, so the data pulse DAT is discarded. Therefore, even if serial communication is not established, unintended malfunctions do not occur.

[0283] <Application to vehicles> 21 is a diagram showing the exterior of a vehicle B. Vehicle B of this configuration example is equipped with various electronic devices that operate by receiving power supply from a battery.

[0284] Vehicle B includes not only engine vehicles but also electric vehicles (BEVs [battery electric vehicles], HEVs [hybrid electric vehicles], PHEVs / PHVs (plug-in hybrid electric vehicle / plug-in hybrid vehicle), or xEVs such as FCEVs / FCVs (fuel cell electric vehicle / fuel cell vehicle)).

[0285] The signal transmission device 200 or 400 described above can be incorporated into any of the electronic devices mounted on the vehicle B.

[0286] <Additional Notes> The following is a supplementary note regarding the present disclosure: According to the present disclosure, the number of insulating elements can be reduced without switching between modes.

[0287] [Appendix 1] A transmission circuit (412 or 422) configured to pulse drive one of a second pulse signal (INH or OSFBH) and a third pulse signal (INL or OSFBL) when the logic level of a first pulse signal (IN or OUT) is switched; A receiving circuit (423 or 413) configured to switch a logic level of a fourth pulse signal (OUT or INTB) in response to the second pulse signal (INH or OSFBH) and the third pulse signal (INL or OSFBL); an isolation circuit (430) configured to transmit the second pulse signal (INH or OSFBH) and the third pulse signal (INL or OSFBL) while isolating the transmission circuit (412 or 422) from the reception circuit (423 or 413); Equipped with the transmission circuit (412 or 422) pulse-drives one of the second pulse signal (INH or OSFBH) and the third pulse signal (INL or OSFBL) when the logic level of the first pulse signal (IN or OUT) is switched, and then pulse-drives the one of the second pulse signal (INH or OSFBH) and the third pulse signal (INL or OSFBL) in accordance with a predetermined communication protocol when performing serial communication; The receiving circuit (423 or 413) switches the logical level of the fourth pulse signal (OUT or INTB) in response to the one of the second pulse signal (INH or OSFBH) and the third pulse signal (INL or OSFBL), and then detects whether the one of the second pulse signal (INH or OSFBH) and the third pulse signal (INL or OSFBL) complies with the communication protocol, and determines whether to establish or abandon the serial communication. A signal transmission device (400).

[0288] [Appendix 2] The signal transmission device (400) according to claim 1, wherein the receiving circuit (423 or 413) also discards the serial communication when the one of the second pulse signal (INH or OSFBH) and the third pulse signal (INL or OSFBL) is a reset pulse.

[0289] [Appendix 3] a first transmission circuit (412) configured to pulse-drive one of a first rise signal (INH1) and a first fall signal (INL1) if a slew rate selection signal (GRSEL) is at a first logic level when a logic level of an input pulse signal (IN) is switched, and to pulse-drive one of a second rise signal (INH2) and a second fall signal (INL2) if the slew rate selection signal (GRSEL) is at a second logic level; a first receiving circuit (423) configured to switch a logic level of an output pulse signal (OUT) at a first slew rate in response to the first rise signal (INH1) and the first fall signal (INL1) and to switch a logic level of the output pulse signal (OUT) at a second slew rate different from the first slew rate in response to the second rise signal (INH2) and the second fall signal (INL2); a first isolation circuit (430A) configured to transmit the first rise signal (INH1), the second rise signal (INH2), the first fall signal (INL1), and the second fall signal (INL2) while isolating between the first transmitting circuit (412) and the first receiving circuit (423); Equipped with the first transmission circuit (412) pulse-drives the first rise signal (INH1) or the second rise signal (INH2) in response to a rising edge of the input pulse signal (IN), and then pulse-drives the first rise signal (INH1) and the second rise signal (INH2) in accordance with a predetermined communication protocol when performing first serial communication via the first isolation circuit (430A); and pulse-drives the first fall signal (INL1) or the second fall signal (INL2) in response to a falling edge of the input pulse signal (IN), and then pulse-drives the first fall signal (INL1) and the second fall signal (INL2) in accordance with the communication protocol when performing the first serial communication; The first receiving circuit (423), after switching the logical level of the output pulse signal (OUT) in response to the first rise signal (INH1) or the second rise signal (INH2), detects whether the first rise signal (INH1) and the second rise signal (INH2) conform to the communication protocol and determines whether to establish or abandon the first serial communication, and, after switching the logical level of the output pulse signal (OUT) in response to the first fall signal (INL1) or the second fall signal (INL2), detects whether the first fall signal (INL1) and the second fall signal (INL2) conform to the communication protocol and determines whether to establish or abandon the first serial communication. This is a signal transmission device (400).

[0290] [Appendix 4] a second transmission circuit (422) configured to pulse one of a third rise signal (OSFBH) and a third fall signal (OSFBL) when the logic level of the output pulse signal (OUT) switches; a second receiving circuit (413) configured to switch a logic level of a feedback pulse signal (INTB) in response to the third rise signal (OSFBH) and the third fall signal (OSFBL); a second isolation circuit (430B) configured to transmit the third rise signal (OSFBH) and the third fall signal (OSFBL) while isolating between the second transmission circuit (422) and the second reception circuit (413); Further equipped with the second transmission circuit (422) pulse-drives one of the third rise signal (OSFBH) and the third fall signal (OSFBL) when the logic level of the output pulse signal (OUT) is switched, and then pulse-drives the one of the third rise signal (OSFBH) and the third fall signal (OSFBL) in accordance with the communication protocol when performing second serial communication via the second isolation circuit (430B); The signal transmission device (400) described in Appendix 3, wherein the second receiving circuit (413) switches the logical level of the feedback pulse signal (INTB) in response to the one of the third rise signal (OSFBH) and the third fall signal (OSFBL), and then determines whether to establish or discard the second serial communication in response to whether the first serial communication is being performed.

[0291] [Appendix 5] The signal transmission device (400) described in Appendix 4, wherein the first transmission circuit (412) pulse-drives any one of the first rise signal (INH1), the second rise signal (INH2), the first fall signal (INL1), and the second fall signal (INL2) when the logic level of the input pulse signal (IN) switches, and then waits for the start of the first serial communication until the logic level of the feedback pulse signal (INTB) switches.

[0292] [Appendix 6] The signal transmission device (400) described in Appendix 4, wherein the first transmission circuit (412) pulse-drives any one of the first rise signal (INH1), the second rise signal (INH2), the first fall signal (INL1), and the second fall signal (INL2) when the logical level of the input pulse signal (IN) switches, and then waits for a predetermined time to elapse before starting the first serial communication.

[0293] [Appendix 7] 7. The signal transmission device (400) according to any one of appendixes 4 to 6, wherein the second receiving circuit (413) has an output function of the feedback pulse signal (INTB) turned on / off.

[0294] [Appendix 8] a first die (410) on which the first transmitting circuit (412) and the second receiving circuit (413) are integrated; a second die (420) on which the second transmitting circuit (422) and the first receiving circuit (423) are integrated; a third die (430) on which the first isolation circuit (430A) and the second isolation circuit (430B) are integrated; Equipped with The signal transmission device (400) according to any one of claims 5 to 7, wherein the first die (410), the second die (420), and the third die (430) are sealed in a single package.

[0295] [Appendix 9] An electronic device (A) comprising: a power transistor (2); and an insulated gate driver IC (1) configured to drive a gate of the power transistor (2), the insulated gate driver IC (1) being a signal transmission device (400) according to any one of Appendices 1 to 8.

[0296] [Appendix 10] A vehicle (B) equipped with an electronic device (A) according to appendix 9.

[0297] <Other> In addition, various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation, in addition to the above-mentioned embodiment. In other words, the above-mentioned embodiment should be considered to be illustrative and not restrictive in all respects. In addition, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0298] 1H(u / v / w) High-side gate driver IC 1L(u / v / w) Lower side gate driver IC 2H(u / v / w) Upper power transistor 2L(u / v / w) Lower power transistor 3 ECU 4 Motor 5. Semiconductor Devices 11, 11A~11F Low potential terminal 12, 12A~12F high potential terminal 21, 21A~21D Transformer 22 Low potential coil (primary coil) 23 High potential coil (secondary coil) 24 1st medial end 25 First outer end 26 1st spiral part 27 Second medial end 28 Second outer end 29 Second spiral part 31 1st low potential wiring 32 2nd low potential wiring 33 1st high potential wiring 34 2nd high potential wiring 41 Semiconductor Chip 42 First main surface 43 Second main surface 44A~44D Chip side wall 45 First Functional Device 51 Insulating layer 52 Insulating surface 53A~53D Insulated sidewall 55 Bottom insulation layer 56 Top insulation layer 57 Interlayer insulation layer 58 First insulating layer 59 Second insulating layer 60 Second Function Device 61 Sealed conductor 62 Device Area 63 Outer area 64 Seal plug conductor 65 Seal via conductor 66 1st medial area 67 Second medial area 71 Through Wiring 72 Low-potential connection wiring 73 Lead Wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrode 77 Board plug electrode 78 1st electrode layer 79 Second electrode layer 80 Wiring plug electrode 81 High potential connection wiring 82 Pad plug electrode 85 Dummy Pattern 86 High potential dummy pattern 87 First high potential dummy pattern 88 Second high potential dummy pattern 89 First area 90 Second area 91 Third area 92 First connection part 93 First Pattern 94 2nd Pattern 95 3rd Pattern 96 First Outer Line 97 2nd Outer Line 98 1st Intermediate Line 99 First connecting line 100 Slits 130 Separation structure 140 Inorganic insulating layer 141 First inorganic insulating layer 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic Insulating Layer 146 Part 1 147 Part 2 148 Low potential terminal opening 149 High potential terminal opening 200 Signal transmission device 200p primary circuit system 200s Secondary circuit system 210 Controller chip (first chip) 211 Pulse transmission circuit (pulse generator) 212, 213 Buffer 220 Driver Chip (2nd Chip) 221, 222 Buffer 223 Pulse receiving circuit (RS flip-flop) 224 Driver 230 Trans Chip (3rd Chip) 230a 1st wiring layer (lower layer) 230b 2nd wiring layer (upper layer) 231, 232 Transformers 231p, 232p Primary coil 231s, 232s Secondary coil 300 Trans Chip 301 1st transformer 302 2nd Transformer 303 3rd Transformer 304 4th Transformer 305 1st Guard Ring 306 2nd Guard Ring 400 Signal transmission device 400p primary circuit system 400s secondary circuit system 410 First Die 411 Logic (signal processing circuit) 412 Transmitting circuit 413 Receiving circuit 420 2nd Die 421 Logic 422 Transmitting circuit 423 Receiver Circuit 430 3rd Die 431~434 Isolation elements (transformers) a1 to a8 pads (corresponding to the first current supply pads) b1~b8 Pads (corresponding to the first voltage measurement pads) c1~c4 Pads (corresponding to the second current supply pads) d1~d4 Pads (corresponding to the second voltage measurement pads) e1, e2 pads A Electronic equipment B Vehicle L1p, L2p Primary coil L1s, L2s, L3s, L4s Secondary coil T21, T22, T23, T24, T25, T26 External terminals TR1 Switching element X 1st direction X21, X22, X23 internal terminals Y Second direction Y21, Y22, Y23 wiring Z normal direction Z21, Z22, Z23 vias

Claims

1. a transmission circuit configured to pulse drive one of the second pulse signal and the third pulse signal when the logic level of the first pulse signal is switched; a receiving circuit configured to switch a logic level of a fourth pulse signal in response to the second pulse signal and the third pulse signal; an isolation circuit configured to transmit the second pulse signal and the third pulse signal while insulating the transmission circuit from the reception circuit; Equipped with the transmission circuit pulse-drives one of the second pulse signal and the third pulse signal when a logical level of the first pulse signal is switched, and then pulse-drives the one of the second pulse signal and the third pulse signal in accordance with a predetermined communication protocol when performing serial communication; the receiving circuit switches the logical level of the fourth pulse signal in response to the one of the second pulse signal and the third pulse signal, and then detects whether the one of the second pulse signal and the third pulse signal complies with the communication protocol, and determines whether to establish or abandon the serial communication.

2. 2. The signal transmission device according to claim 1, wherein the receiving circuit also discards the serial communication when the one of the second pulse signal and the third pulse signal is a reset pulse.

3. a first transmission circuit configured to pulse-drive one of a first rise signal and a first fall signal if a slew rate selection signal is at a first logic level when the logic level of an input pulse signal is switched, and to pulse-drive one of a second rise signal and a second fall signal if the slew rate selection signal is at a second logic level; a first receiving circuit configured to switch a logic level of an output pulse signal at a first slew rate in response to the first rise signal and the first fall signal, and to switch a logic level of the output pulse signal at a second slew rate different from the first slew rate in response to the second rise signal and the second fall signal; a first isolation circuit configured to transmit the first rise signal, the second rise signal, the first fall signal, and the second fall signal while providing insulation between the first transmitting circuit and the first receiving circuit; Equipped with the first transmission circuit pulse-drives the first rise signal or the second rise signal in response to a rising edge of the input pulse signal, and then pulse-drives the first rise signal and the second rise signal in accordance with a predetermined communication protocol when performing first serial communication via the first isolation circuit; and pulse-drives the first fall signal or the second fall signal in response to a falling edge of the input pulse signal, and then pulse-drives the first fall signal and the second fall signal in accordance with the communication protocol when performing the first serial communication; a first receiving circuit that detects whether the first rise signal and the second rise signal conform to the communication protocol and determines whether to establish or discard the first serial communication after switching the logical level of the output pulse signal in response to the first rise signal or the second rise signal, and that detects whether the first fall signal and the second fall signal conform to the communication protocol and determines whether to establish or discard the first serial communication after switching the logical level of the output pulse signal in response to the first fall signal or the second fall signal.

4. a second transmission circuit configured to pulse one of a third rise signal and a third fall signal when the logic level of the output pulse signal changes; A second receiving circuit configured to switch a logic level of a feedback pulse signal in response to the third rise signal and the third fall signal; a second isolation circuit configured to transmit the third rise signal and the third fall signal while providing insulation between the second transmitting circuit and the second receiving circuit; Further equipped with the second transmission circuit pulse-drives one of the third rise signal and the third fall signal when the logical level of the output pulse signal is switched, and then pulse-drives the one of the third rise signal and the third fall signal in accordance with the communication protocol when performing second serial communication via the second isolation circuit; The signal transmission device of claim 3, wherein the second receiving circuit switches the logical level of the feedback pulse signal in response to one of the third rise signal and the third fall signal, and then determines whether to establish or abandon the second serial communication in response to whether the first serial communication is in progress.

5. The signal transmission device of claim 4, wherein the first transmission circuit pulse-drives any one of the first rise signal, the second rise signal, the first fall signal, and the second fall signal when the logical level of the input pulse signal switches, and then waits to start the first serial communication until the logical level of the feedback pulse signal switches.

6. 5. The signal transmission device of claim 4, wherein the first transmission circuit pulse-drives any one of the first rise signal, the second rise signal, the first fall signal, and the second fall signal when the logical level of the input pulse signal is switched, and then waits to start the first serial communication until a predetermined time has elapsed.

7. 5. The signal transmission device according to claim 4, wherein the second receiving circuit has an output function of the feedback pulse signal that can be turned on and off.

8. a first die on which the first transmitting circuit and the second receiving circuit are integrated; a second die on which the second transmitting circuit and the first receiving circuit are integrated; a third die on which the first isolation circuit and the second isolation circuit are integrated; Equipped with The signal transmission device of claim 5 , wherein the first die, the second die, and the third die are sealed in a single package.

9. 9. An electronic device comprising: a power transistor; and an insulated gate driver IC configured to drive a gate of the power transistor, the insulated gate driver IC being the signal transmission device according to claim 1.

10. A vehicle comprising the electronic device according to claim 9.

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