Semiconductor module

Abstract

To improve the short-circuit tolerance of a semiconductor chip.SOLUTION: A semiconductor module includes an insulating circuit board 11 including a plurality of wiring boards having a thickness of 600 μm or more and 900 μm or less, a semiconductor chip 12 with a wide gap disposed over an upper surface of the wiring board with a first bonding material 14a therebetween and having a thickness of 50 μm or more and 120 μm or less, and a conductive member 13a. The conductive member 13a includes a first bonding part 13a1 connected onto the semiconductor chip 12 through a second bonding material 14b, having a thickness of 0.1 mm or more and 0.8 mm or less, and having an area of 25% or more and 60% or less of the area of an upper surface of the semiconductor chip 12 in a plan view, a beam part 13a3 extending continuously from the first bonding part 13a1 through a first bent part 13a2, and a second bonding part 13a5 extending continuously from the beam part 13a3 through a second bent part 13a4 and connected to another wiring board 11b3 adjacent to a wiring board 11b2 where the semiconductor chip 12 is mounted.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present invention relates to a semiconductor module. [Background technology]

[0002] In a semiconductor module, when an overcurrent flows between the drain and source of a semiconductor element, the voltage applied between the gate and source is reduced by the parasitic inductance of the connection member and the conductive layer (see, for example, Patent Document 1). Also, an intermediate plate is provided in the solder between the electrode substrate and the semiconductor chip, and the strength of the intermediate plate is greater than the strength of the electrode substrate and the solder within the operating temperature range of the semiconductor device (see, for example, Patent Document 2).

[0003] Furthermore, thick-film electrodes are formed on the front and back electrodes of the semiconductor element to thicken the electrodes of the semiconductor element (see, for example, Patent Document 3). Also, the front electrode provided on the front surface of the semiconductor substrate includes a first metal electrode and a second metal electrode with a roughened surface formed on the first metal electrode, and a wire wiring is joined to the second metal electrode (see, for example, Patent Document 4). Furthermore, a wiring member is joined with a bonding layer made of Ag sintered material, and heat generated in the semiconductor chip is transferred to the wiring member (see, for example, Patent Document 5). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2021 / 010210 [Patent Document 2] International Publication No. 2018 / 020640 [Patent Document 3] International Publication No. 2018 / 163599 [Patent Document 4] JP 2017-005100 A [Patent Document 5] JP 2018-26417 A Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to improve the short circuit resistance of a semiconductor chip. [Means for solving the problem]

[0006] In order to solve the above problem, a semiconductor module is provided. The semiconductor module includes an insulating circuit board having an insulating plate, a plurality of circuit pattern layers with a thickness of 600 μm to 900 μm arranged on the upper surface of the insulating plate, and a heat sink arranged on the lower surface of the insulating plate, a wide gap semiconductor chip with a thickness of 50 μm to 120 μm arranged on the upper surface of the circuit pattern layer via a first bonding material, and a conductive member. The conductive member has a first bonding portion connected to the wide gap semiconductor chip via a second bonding material, a thickness of 0.1 mm to 0.8 mm, and an area of ​​25% to 60% of the area of ​​the upper surface of the wide gap semiconductor chip in a plan view, a beam portion continuously extending from the first bonding portion via a first bend, and a second bonding portion continuously extending from the beam portion via a second bend and connecting to another circuit pattern layer adjacent to the circuit pattern layer on which the wide gap semiconductor chip is mounted. Effect of the Invention

[0007] According to one aspect, it is possible to improve the short circuit resistance of a semiconductor chip. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view of a semiconductor device. [Diagram 2] FIG. 2 is a side view of the semiconductor device. [Diagram 3] FIG. 1 is a cross-sectional view of a semiconductor device. [Figure 4] FIG. [Diagram 5] 1 is a diagram showing the relationship between the active volume and short circuit withstand capability of a semiconductor chip; [Figure 6] FIG. 2 is a plan view of a semiconductor unit included in the semiconductor module. [Figure 7] 2 is a cross-sectional view of a semiconductor unit included in a semiconductor module. [Figure 8] 1A and 1B are diagrams illustrating an example of the configuration of a first bonding portion of a lead frame, where (a) is a diagram illustrating the thickness of the first bonding portion, and (b) is a diagram illustrating the bonding area of ​​the first bonding portion. [Figure 9] FIG. 13 is a diagram showing an example of the height of a lead frame. [Figure 10] 11A and 11B are diagrams showing differences in width of bent portions of lead frames; [Figure 11] 11A and 11B are diagrams showing an example of the effect of reducing thermal resistance by lead frame wiring; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiment will be described with reference to the drawings. In the following description, the "front surface" and "top surface" refer to the XY surface facing upward (+Z direction) in the semiconductor device 1 in the figure. Similarly, "upper" refers to the upward (+Z direction) direction in the semiconductor device 1 in the figure. The "back surface" and "bottom surface" refer to the XY surface facing downward (-Z direction) in the semiconductor device 1 in the figure. Similarly, "bottom" refers to the downward (-Z direction) direction in the semiconductor device 1 in the figure. The same directionality as above is also meant in other figures as necessary. "High position" refers to the upper (+Z direction) position in the semiconductor device 1 in the figure. Similarly, "low position" refers to the lower (-Z direction) position in the semiconductor device 1 in the figure. The "front surface", "top surface", "upper" and "back surface", "bottom surface", "lower" and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical idea of ​​the present invention. For example, "upper" and "bottom" do not necessarily mean a vertical direction with respect to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. In the following description, "main component" refers to a content of 80 vol% or more. "Almost the same" means within a range of ±10%. "Perpendicular", "orthogonal" and "parallel" means within a range of ±10°.

[0010] The semiconductor device 1 will be described with reference to Figs. 1 to 4. Fig. 1 is a plan view of the semiconductor device, and Fig. 2 is a side view of the semiconductor device. Fig. 3 is a cross-sectional view of the semiconductor device, and Fig. 4 is a back view of the semiconductor device. Note that Fig. 1 does not show a sealing member. Fig. 2 is a side view of the YZ plane in Fig. 1 as viewed in the X direction. Fig. 3 is a cross-sectional view taken along dashed dotted line XX in Fig. 1. Fig. 4 is a back view of the semiconductor device 1 of Fig. 1 rotated about a center line passing through the centers of side walls 21a, 21c.

[0011] The semiconductor device 1 includes a semiconductor module 2 and a cooling device 3. The semiconductor module 2 includes semiconductor units 10a, 10b, and 10c, and a case 20 that houses the semiconductor units 10a, 10b, and 10c. The semiconductor units 10a, 10b, and 10c each include a semiconductor chip (wide-gap semiconductor chip), and are arranged in a row in the cooling device 3. The case 20 is arranged in the cooling device 3, and the semiconductor units 10a, 10b, and 10c are housed in the case 20. The semiconductor units 10a, 10b, and 10c housed in the case 20 are sealed by a sealing member 27. The semiconductor units 10a, 10b, and 10c all have the same configuration. When the semiconductor units 10a, 10b, and 10c are not distinguished from each other, they will be described as the semiconductor unit 10. The details of the semiconductor unit 10 will be described later.

[0012] First, case 20 includes outer frame 21, first connection terminals 22a, 22b, 22c, second connection terminals 23a, 23b, 23c, U-phase output terminal 24a, V-phase output terminal 24b, W-phase output terminal 24c, and control terminals 25a, 25b, 25c.

[0013] The outer frame 21 has a rectangular shape in a plan view, and is surrounded on all four sides by side walls 21a, 21b, 21c, and 21d. The side walls 21a and 21c are the long sides of the outer frame 21, and the side walls 21b and 21d are the short sides of the outer frame 21. In addition, the corners at which the side walls 21a, 21b, 21c, and 21d are connected in a plan view do not necessarily have to be right angles. Such connection points may be rounded, for example, as shown in FIG. 1. The back surfaces of the outer frame 21 (side walls 21a, 21b, 21c, and 21d) may be flush with each other and parallel to the XY plane.

[0014] Mounting holes 21i penetrating the outer frame 21 are formed at the corners of the front surface of the outer frame 21. Note that these mounting holes 21i may be formed lower than the front surface of the outer frame 21. Further mounting holes 21i penetrating the outer frame 21 may be formed on the side walls 21a and 21c of the outer frame 21.

[0015] The outer frame 21 includes unit storage sections 21e, 21f, and 21g along the side walls 21a and 21c (±X directions) at the center of the ±Y direction of the front surface. The unit storage sections 21e, 21f, and 21g are defined in a rectangular shape in a plan view on the front surface of the outer frame 21, and are open. The unit storage sections 21e, 21f, and 21g store the semiconductor units 10a, 10b, and 10c, respectively. Therefore, the size of the unit storage sections 21e, 21f, and 21g may be a size that can store the semiconductor units 10a, 10b, and 10c.

[0016] The outer frame 21 includes first connection terminals 22a, 22b, 22c and second connection terminals 23a, 23b, 23c on the side wall 21a side of the front surface along the side wall 21a (±X direction) in a plan view. The first connection terminals 22a, 22b, 22c may be positive input terminals (P terminals). The second connection terminals 23a, 23b, 23c may be negative input terminals (N terminals).

[0017] Furthermore, the outer frame 21 has a U-phase output terminal 24a, a V-phase output terminal 24b, and a W-phase output terminal 24c on the side wall 21c side of the front surface along the side wall 21c (±X direction). In this case, the first connection terminal 22a, the second connection terminal 23a, and the U-phase output terminal 24a are provided to sandwich the unit storage section 21e. The first connection terminal 22b, the second connection terminal 23b, and the V-phase output terminal 24b are provided to sandwich the unit storage section 21f. The first connection terminal 22c, the second connection terminal 23c, and the W-phase output terminal 24c are provided to sandwich the unit storage section 21g.

[0018] In addition, nuts facing the openings of the first connection terminals 22a, 22b, 22c and the second connection terminals 23a, 23b, 23c are stored below (-Z direction) on the front surface of the outer frame 21. Similarly, nuts facing the openings of the U-phase output terminal 24a, the V-phase output terminal 24b, and the W-phase output terminal 24c are stored below (-Z direction) on the front surface of the outer frame 21. Furthermore, in a plan view, control terminals 25a, 25b, 25c are provided between the unit storage sections 21e, 21f, 21g on the front surface of the outer frame 21 and the first connection terminals 22a, 22b, 22c and the second connection terminals 23a, 23b, 23c. Here, the control terminals 25a, 25b, 25c may be provided in two parts for each of the unit storage sections 21e, 21f, 21g.

[0019] The outer frame 21 includes the first connection terminals 22a, 22b, and 22c, the second connection terminals 23a, 23b, and 23c, the U-phase output terminal 24a, the V-phase output terminal 24b, the W-phase output terminal 24c, and the control terminals 25a, 25b, and 25c, and is integrally molded by injection molding using a thermoplastic resin. This forms the case 20. The thermoplastic resin is, for example, polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, or acrylonitrile butadiene styrene resin.

[0020] The first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the U-phase output terminal 24a, the V-phase output terminal 24b, the W-phase output terminal 24c, and the control terminals 25a, 25b, 25c are made of a metal with excellent electrical conductivity. Such metals are, for example, copper, aluminum, or an alloy containing at least one of these as a main component. The surfaces of the first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the U-phase output terminal 24a, the V-phase output terminal 24b, the W-phase output terminal 24c, and the control terminals 25a, 25b, 25c may be plated. In this case, the plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy. The plated first connection terminals 22a, 22b, 22c, second connection terminals 23a, 23b, 23c, U-phase output terminal 24a, V-phase output terminal 24b, W-phase output terminal 24c, and control terminals 25a, 25b, 25c have improved corrosion resistance. In the following description, when the first connection terminals 22a, 22b, 22c are not particularly distinguished from each other, they are referred to as first connection terminals 22. The second connection terminals 23a, 23b, 23c are similarly referred to as second connection terminals 23, and the U-phase output terminal 24a, V-phase output terminal 24b, and W-phase output terminal 24c are similarly referred to as output terminals 24.

[0021] The sealing member 27 may be a thermosetting resin. The thermosetting resin is, for example, an epoxy resin, a phenol resin, a maleimide resin, or a polyester resin. An epoxy resin is preferable. Furthermore, a filler may be added to the sealing member 27. The filler may be a ceramic having insulating properties and high thermal conductivity. Furthermore, the sealing member 27 may be a silicone gel.

[0022] The cooling device 3 includes an inlet 33a through which the refrigerant flows into the inside and an outlet 33b through which the refrigerant that has flowed through the inside flows out to the outside. The cooling device 3 cools the semiconductor unit 10 by discharging heat from the semiconductor unit 10 through the refrigerant. The refrigerant used here is, for example, water, antifreeze (aqueous ethylene glycol solution), or long-life coolant. The cooling device 3 may include a pump and a heat dissipation device (radiator). The pump introduces the refrigerant into the inlet 33a of the cooling device 3, and causes the refrigerant that flows out from the outlet 33b to flow back into the inlet 33a, thereby circulating the refrigerant. The heat dissipation device receives the refrigerant that flows out from the cooling device 3, and dissipates the heat of the refrigerant to which the heat of the semiconductor unit 10 has been transferred to the outside.

[0023] Such a cooling device 3 has a top plate 31, a side wall 32 connected to the back surface of the top plate 31 in an annular shape, and a cooling bottom plate 33 connected to the back surface of the side wall 32, facing the top plate 31. The top plate 31 has a rectangular shape surrounded by long and short sides in a plan view, and fastening holes 30e are formed at each of the four corners. The corners of the top plate 31 in a plan view may be rounded. The semiconductor units 10a, 10b, and 10c are joined to the front surface of the top plate 31 along the ±X direction. The side wall 32 is formed continuously in an annular shape on the back surface of the top plate 31. A plurality of heat dissipation fins 34 are formed in an area on the back surface of the top plate 31 corresponding to the area in which the semiconductor units 10a, 10b, and 10c are arranged.

[0024] The cooling bottom plate 33 is flat and has the same shape as the top plate 31 in plan view. That is, the cooling bottom plate 33 has a rectangular shape surrounded by long sides 30a, 30c and short sides 30b, 30d in plan view, and fastening holes 30e corresponding to the top plate 31 are formed at the four corners. The corners of the cooling bottom plate 33 may also be rounded. The front surface and bottom surface 33d of the cooling bottom plate 33 are parallel. The bottom surface 33d of the cooling bottom plate 33 is a flat surface without any steps and forms the same plane. Furthermore, the bottom surface 33d of the cooling bottom plate 33 and the front surface of the top plate 31 may also be parallel.

[0025] The bottom surface 33d of the cooling bottom plate 33 is formed with an inlet 33a and an outlet 33b through which the refrigerant flows in and out. The bottom surface 33d of the cooling bottom plate 33 is surrounded by sealing areas 33a1 and 33b1 around the inlet 33a and the outlet 33b. A water distribution head is attached to the inlet 33a and the outlet 33b via annular rubber packing in the sealing areas 33a1 and 33b1 surrounding the inlet 33a and the outlet 33b. A water distribution pipe connected to a pump is attached to the water distribution head.

[0026] Next, we will explain the decrease in short circuit resistance caused by the miniaturization of semiconductor chips. In semiconductor modules, the semiconductor chips are being made smaller as the modules are made smaller, but the miniaturization of the semiconductor chip reduces the chip active volume (the effective area through which current flows). A reduction in the chip active volume reduces the heat capacity, and a reduction in the chip surface area increases the thermal resistance. Therefore, in order to prevent a decrease in the performance of the semiconductor module, it is important to take measures to keep the junction temperature below a specified value during operation and to increase the heat dissipation from the semiconductor chip.

[0027] On the other hand, when a semiconductor chip is short-circuited, a large current of several thousand amperes flows under the condition that a high voltage is applied, which places a large stress on the semiconductor chip, and if this condition continues, the semiconductor chip will be destroyed. The time it takes for a semiconductor chip to be destroyed when it is short-circuited is specified as the short-circuit withstand capability. One of the causes of short circuit failure is a sudden rise in the internal temperature of a semiconductor chip due to thermal runaway caused by an abnormal leakage current that occurs after the short circuit is cut off. In a state where such short circuit failure occurs, the short circuit resistance decreases as semiconductor chips become smaller (thinner).

[0028] Figure 5 shows the relationship between the active volume of a semiconductor chip and short circuit withstand voltage. The vertical axis is short circuit withstand voltage, and the horizontal axis is active volume. The active volume of a semiconductor chip is proportional to the short circuit withstand voltage, and the smaller the active volume, the lower the short circuit withstand voltage. In a thinned semiconductor chip, the active volume is reduced and the heat capacity is small, so the chip temperature is likely to rise due to thermal runaway after a short circuit is cut off, which causes a decrease in short circuit resistance. The present invention has been made in consideration of these points, and aims to suppress the temperature rise and improve the short circuit resistance by increasing the bonding area between the semiconductor chip and the wiring and improving the heat dissipation even if the heat capacity decreases as the semiconductor chip is thinned.

[0029] Next, a semiconductor module 2 of the present invention that has improved short-circuit resistance will be described. Fig. 6 is a plan view of a semiconductor unit included in the semiconductor module, and Fig. 7 is a cross-sectional view of the semiconductor unit included in the semiconductor module. Fig. 6 shows a case in which a first connection terminal 22, a second connection terminal 23, and an output terminal 24, which include a case 20, are connected to a semiconductor unit 10. Fig. 7 is a cross-sectional view taken along dashed line XX in Fig. 6.

[0030] The semiconductor unit 10 includes an insulating circuit board 11, a semiconductor chip 12, and lead frames 13a and 13b (conductive members). The semiconductor chip 12 is a wide-gap semiconductor chip having a thickness of 50 μm or more and 120 μm or less, and is bonded to a wiring board 11b2 of the insulating circuit board 11 via a bonding material 14a (first bonding material). The lead frames 13a and 13b are bonded to the semiconductor chip 12 via a bonding material 14b (second bonding material).

[0031] The insulating circuit board 11 includes an insulating plate 11a, wiring plates 11b1, 11b2, and 11b3 that are circuit pattern layers, and a metal plate 11c for heat dissipation. The insulating plate 11a and the metal plate 11c are rectangular in plan view. The insulating plate 11a and the metal plate 11c may have corners that are rounded or chamfered. The size of the metal plate 11c is smaller than the size of the insulating plate 11a in plan view, and is formed inside the insulating plate 11a.

[0032] The insulating plate 11a is made of a material having insulating properties and excellent thermal conductivity, and is a ceramic plate having a thickness of 200 μm to 400 μm, mainly composed of silicon nitride. Alternatively, the main component may be aluminum oxide, aluminum nitride, or silicon nitride. The insulating plate 11a may also be made of insulating resin. Examples of insulating resin include a paper phenol substrate, a paper epoxy substrate, a glass composite substrate, and a glass epoxy substrate.

[0033] The wiring boards 11b1, 11b2, and 11b3 are formed on the front surface of the insulating plate 11a. The wiring boards 11b1, 11b2, and 11b3 are 600 μm or more and 900 μm or less in thickness and are made of a metal with excellent conductivity. Such metals are, for example, copper, aluminum, or an alloy containing at least one of these as a main component. The surfaces of the wiring boards 11b1, 11b2, and 11b3 may be plated. In this case, the plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy. The plated wiring boards 11b1, 11b2, and 11b3 have improved corrosion resistance.

[0034] Wiring board 11b1 occupies half of the area on the +X side of the front surface of insulating plate 11a, and occupies the entire area from the -Y side to the +Y side. Wiring board 11b2 occupies half of the -X side of the front surface of insulating plate 11a. Furthermore, wiring board 11b2 is formed from the +Y side to the -Y side with a gap between it and the -Y side. Wiring board 11b3 occupies the area surrounded by wiring boards 11b1 and 11b2 on the front surface of insulating plate 11a.

[0035] Such wiring boards 11b1, 11b2, and 11b3 are formed on the front surface of insulating plate 11a as follows. A metal plate is formed on the front surface of insulating plate 11a, and the metal plate is subjected to a process such as etching to obtain wiring boards 11b1, 11b2, and 11b3 of a predetermined shape. Alternatively, wiring boards 11b1, 11b2, and 11b3 cut out in advance from a metal plate may be pressure-attached to the front surface of insulating plate 11a. Note that wiring boards 11b1, 11b2, and 11b3 are merely examples. The number, shape, size, and position of wiring boards 11b1, 11b2, and 11b3 may be appropriately selected as necessary.

[0036] The metal plate 11c is formed on the back surface of the insulating plate 11a. The metal plate 11c is rectangular. The area of ​​the metal plate 11c in plan view is smaller than that of the insulating plate 11a and is larger than the area of ​​the region in which the wiring plates 11b1, 11b2, and 11b3 are formed. The corners of the metal plate 11c may be R-chamfered or C-chamfered. The metal plate 11c is smaller than the size of the insulating plate 11a and is formed on the entire surface of the insulating plate 11a except for the edge portion. The metal plate 11c is mainly composed of a metal having excellent thermal conductivity. The metal may be, for example, copper, aluminum, or an alloy containing at least one of these, and the surface of the metal plate 11c may be plated. In this case, the plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy. The plated metal plate 11c has improved corrosion resistance.

[0037] Examples of insulating circuit board 11 having such a configuration include a DCB (Direct Copper Bonding) board, an AMB (Active Metal Brazed) board, and a resin insulating board. Insulating circuit board 11 may be attached to the front surface of top plate 31 of cooling device 3 via a bonding material (not shown). Heat generated in semiconductor chip 12 can be dissipated by being conducted to cooling device 3 via wiring boards 11b1 and 11b2, insulating plate 11a, and metal plate 11c.

[0038] The bonding materials 14a and 14b are, for example, solder, brazing material, or metal sintered body. Lead-free solder is used as the solder. Lead-free solder is mainly composed of an alloy containing at least two of tin, silver, copper, zinc, antimony, indium, and bismuth. Furthermore, the solder may contain additives. Examples of additives include nickel, germanium, cobalt, and silicon. When the solder contains additives, the wettability, gloss, and bonding strength are improved, and the reliability can be improved. The brazing material is mainly composed of at least one of an aluminum alloy, a titanium alloy, a magnesium alloy, a zirconium alloy, and a silicon alloy. The insulating circuit board 11 may be bonded to the cooling device 3 by brazing using such bonding materials. The metal sintered body is mainly composed of, for example, silver and a silver alloy. Alternatively, the bonding material may be a thermal interface material. The thermal interface material is, for example, an adhesive material including an elastomer sheet, RTV (Room Temperature Vulcanization) rubber, gel, a phase change material, etc. By attaching the semiconductor unit 10 to the cooling device 3 via such a brazing material or thermal interface material, the heat dissipation performance of the semiconductor unit 10 can be improved.

[0039] The semiconductor chip 12 includes a power device element made of silicon. The power device element may be an RC (Reverse-Conducting)-IGBT (Insulated Gate Bipolar Transistor). The RC-IGBT includes an IGBT, which is a switching element, and a diode element electrically connected in reverse parallel to the IGBT, and the diode element has a function of a FWD (Free Wheeling Diode).

[0040] The front surface of the semiconductor chip 12 is rectangular in plan view, and includes a control electrode 12a (gate electrode) and an output electrode 12b (main electrode: source electrode) which is an upper surface electrode. The thickness of the semiconductor chip 12 is 50 μm or more and 120 μm or less.

[0041] A plurality of control electrodes 12a are provided along one short side of the front surface of the semiconductor chip 12. A control signal is input to the control electrodes 12a. The output electrode 12b has a rectangular shape in a plan view. The positions of the longitudinal direction of the electrode side surface of the output electrode 12b are represented by positions E1 and E2, respectively.

[0042] The output electrode 12b is provided adjacent to the control electrode 12a on the other short side of the front surface of the semiconductor chip 12. If the center of the output electrode 12b is center C, the center C is located in the middle between the electrode side surfaces (positions E1 and E2). The shortest distance from the center C to position E1 on one of the electrode side surfaces is, for example, distance D. Similarly, the shortest distance from the center C to position E2 on the other electrode side surface is also distance D.

[0043] The output electrode 12b further includes an electrode region 12c and a wiring structure portion 12d. The electrode region 12c is a region where a current is output from the semiconductor chip 12. A plating layer may be formed in the electrode region 12c, and the electrode region 12c may include a gate runner. The wiring structure portion 12d is provided on the upper surface of the output electrode 12b so as to continuously surround the outer periphery of the electrode region 12c. In addition, the back surface of the semiconductor chip 12 is provided with an input electrode (main electrode: collector electrode) whose reference number is omitted.

[0044] The semiconductor chip 12 may use a pair of switching elements and diode elements instead of the RC-IGBT. The switching elements are, for example, IGBTs and power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The front surface of the semiconductor chip 12 including the switching elements is provided with a control electrode (gate electrode) and an output electrode (main electrode: source electrode or emitter electrode). The back surface of the semiconductor chip 12 is provided with an input electrode (main electrode: drain electrode or collector electrode). The semiconductor chip 12 including the diode elements may use, for example, an SBD (Schottky Barrier Diode) or a PiN (P-intrinsic-N) diode as the FWD. The front surface of such a semiconductor chip 12 is provided with an input electrode (main electrode: anode electrode). The back surface of the semiconductor chip 12 is provided with an output electrode (main electrode: cathode electrode).

[0045] Also, the semiconductor chip 12 may use a power MOSFET made of silicon carbide instead of the RC-IGBT. The body diode of the power MOSFET may perform the same function as the FWD of the RC-IGBT. The front surface of such a semiconductor chip 12 is provided with a control electrode (gate electrode) and an output electrode (main electrode: source electrode). The back surface of the semiconductor chip 12 is provided with an input electrode (main electrode: drain electrode).

[0046] The back side of the semiconductor chip 12 is bonded to the predetermined wiring boards 11b2, 11b1 via a bonding material 14a. The bonding material 14a is a sintered material mainly composed of silver or copper, and has a thickness of 10 μm or more and 300 μm or less. In addition, solder or a metal sintered body may be used as the bonding material 14a. Lead-free solder is used as the solder. Lead-free solder is mainly composed of an alloy containing at least two of tin, silver, copper, zinc, antimony, indium, and bismuth. Furthermore, the solder may contain an additive. The additive is, for example, nickel, germanium, cobalt, or silicon. By containing the additive, the wettability, gloss, and bonding strength of the solder are improved, and the reliability can be improved. The metal used in the metal sintered body is, for example, silver and a silver alloy.

[0047] Lead frames 13a and 13b electrically connect and wire semiconductor chip 12 and wiring boards 11b2 and 11b3. Semiconductor unit 10 may be a device that configures a one-phase inverter circuit. Lead frame 13a directly connects output electrode 12b of semiconductor chip 12 (on wiring board 11b2) to wiring board 11b3. Lead frame 13b connects output electrode 12b of semiconductor chip 12 (on wiring board 11b1) to wiring board 11b2.

[0048] Moreover, the lead frame 13a includes a first joint portion (main electrode joint portion) 13a1, a first bent portion 13a2, a beam portion 13a3, a second bent portion 13a4, and a second joint portion (wiring joint portion) 13a5.

[0049] The first bonding portion 13a1 has a rectangular front surface in a plan view, and is surrounded on all four sides by terminal side surfaces. The four terminal side surfaces include a terminal side surface P that corresponds to a short side of the first bonding portion 13a1. The first bonding portion 13a1 is bonded to the output electrode 12b via a bonding material 14b, with the terminal side surface P facing the chip side surface of the short side of the semiconductor chip 12.

[0050] Furthermore, the terminal side P of the first joint 13a1 is spaced from the center C of the output electrode 12b toward the position E1 by 40% or more of the length of the distance D. For example, when the length between the electrode sides (positions E1, E2) of the output electrode 12b is about 20 mm, the distance D is about 10 mm. Therefore, the terminal side P of the first joint 13a1 is spaced from the center C of the output electrode 12b toward the position E1 by 4 mm or more. Furthermore, the terminal side P of the first joint 13a1 may be located more inward (toward the center C) than the wiring structure portion 12d of the output electrode 12b.

[0051] The first bent portion 13a2 is integrally joined to the terminal side surface P of the first joint portion 13a1 and extends upward from the terminal side surface P toward the first joint portion 13a1. In this embodiment, the first bent portion 13a2 is substantially perpendicular to the first joint portion 13a1. The height (in the ±Z direction) of the first bent portion 13a2 is a predetermined length. In addition, the outside of the connection portion (corner portion) of the first bent portion 13a2 to the first joint portion 13a1 is separated a predetermined distance from the chip side surface on the electrode side surface side of the position E1 of the semiconductor chip 12. This distance is the distance from the guard ring to the lead frame 13a, and is, for example, 0.4 mm or more and 1.5 mm or less. This can reduce distortion occurring in the lead frame 13a and the semiconductor chip 12.

[0052] Beam portion 13a3 is integrally connected to the upper end portion in the +Z direction of first bent portion 13a2, is parallel to the front surface of insulating circuit board 11, and extends (in the -Y direction) to wiring board 11b3 in a plan view.

[0053] The second bent portion 13a4 is integrally connected to the end of the beam portion 13a3 on the wiring board 11b3 side (-Y direction) and extends to the wiring board 11b3 (-Z direction). The second joint portion 13a5 has, for example, a rectangular shape in a plan view and is joined to the wiring board 11b3. The end of the second joint portion 13a5 on the wiring board 11b2 side and the end of the beam portion 13a3 on the wiring board 11b3 side (-Y direction) are integrally connected by the second bent portion 13a4. At this time, the second bent portion 13a4 is approximately perpendicular to the second joint portion 13a5.

[0054] Although detailed description is omitted, lead frame 13b may also include a first joint, a first bent portion, a beam portion, a second bent portion, and a second joint portion, similar to lead frame 13a. Similarly to lead frame 13a, the first joint of lead frame 13b has a terminal side surface of the first joint spaced from center C of output electrode 12b by 40% or more of the length of distance D toward position E1. Also, in lead frame 13b, the first bent portion is connected to terminal side surface P on the short side of output electrode 12b of the first joint. The beam portion of lead frame 13b extends from the first bent portion to wiring board 11b2 in plan view.

[0055] Such a semiconductor unit 10 is stored in the unit storage section 21e, 21f, 21g. An inner end of the first connection terminal 22 extending into the unit storage section 21e, 21f, 21g is directly connected to the wiring board 11b1. An inner end of the second connection terminal 23 extending into the unit storage section 21e, 21f, 21g is directly connected to the wiring board 11b3. An inner end of the output terminal 24 extending into the unit storage section 21e, 21f, 21g is directly connected to the wiring board 11b2. The first connection terminal 22, the second connection terminal 23, and the output terminal 24 may be bonded to the wiring boards 11b1, 11b3, 11b2 by the bonding material described above.

[0056] Alternatively, the first connection terminal 22, the second connection terminal 23, and the output terminal 24 may be directly joined to the wiring boards 11b1, 11b3, and 11b2 by, for example, laser welding or ultrasonic welding. Also, the control electrodes of the semiconductor chips 12 housed in the unit housing sections 21e, 21f, and 21g are directly connected to the control terminals 25a, 25b, and 25c by wires 26. The wires 26 may be made of, for example, aluminum, an aluminum alloy, copper, or a copper alloy.

[0057] Such lead frames 13a, 13b are made of a metal with excellent electrical conductivity. Such metal is, for example, copper, aluminum, or an alloy containing at least one of these. Furthermore, the surfaces of the lead frames 13a, 13b may be plated to improve corrosion resistance. In this case, the plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy. The plated metal plate 11c has improved corrosion resistance.

[0058] The bonding material 14b that bonds the first bonding portion 13a1 of the lead frame 13a to the semiconductor chip 12 is lead-free solder, and the thickness of the lead-free solder is 10 μm or more and 300 μm or less, or the bonding material 14b may be a sintered material whose main component is silver or copper, and in this case, the thickness of the sintered material is also 10 μm or more and 300 μm or less.

[0059] The lead frames 13a and 13b may be bonded to the wiring boards 11b3 and 11b2 by a bonding material 14c. The bonding material may be the above-mentioned solder or sintered body. Alternatively, the lead frames 13a and 13b may be directly bonded to the wiring boards 11b3 and 11b2 by, for example, laser welding or ultrasonic welding. The lead frames 13a and 13b are bonded to the output electrodes of the semiconductor chip 12 by a bonding material 14b. The bonding material 14b may be made of the same material as the bonding material 14a.

[0060] 8 is a diagram showing an example of the configuration of the first bonding portion of a lead frame. (a) is a diagram showing the thickness of the first bonding portion, and (b) is a diagram showing the bonding area of ​​the first bonding portion. The thickness of the first bonding portion 13a1 is 0.1 mm or more and 0.8 mm or less. Also, the area of ​​the first bonding portion 13a1 is 25% or more and 60% or less of the area of ​​the upper surface of the semiconductor chip 12 in a plan view. The reason why the thickness is set to 0.8 mm or less is that if it is made thicker than that, distortion will increase and there is a concern of a decrease in power cycle.

[0061] 9 is a diagram showing an example of the height of the lead frame. In the lead frame 13a, the height in the Z direction from the bonding surface of the first bent portion 13a1 to the upper surface of the beam portion 13a3 is 5 mm or less. If the height exceeds 5 mm, distortion increases, which may cause a decrease in the power cycle.

[0062] 10 is a diagram showing the difference in width of the bent portion of the lead frame. In the lead frame 13a, the second bent portion 13a4 that is bent and extends from the second joint portion 13a5 that is joined to the circuit pattern side is wider than the first bent portion 13a2 that is bent and extends from the first joint portion 13a1 that is joined to the semiconductor chip side. With this configuration, the heat dissipation of the semiconductor chip 12 can be further improved.

[0063] 11 is a diagram showing an example of the effect of reducing thermal resistance by lead frame wiring. When the back surface of the semiconductor chip 12 is bonded to a copper circuit pattern (wiring board 11b2) and aluminum wire is bonded to the front surface, when the thickness of the aluminum wire + copper pattern is 0.9 mm, a 6% reduction in thermal resistance (°C / W) is obtained compared to when the thickness of the aluminum wire + copper pattern is 0.45 mm. On the other hand, when the back surface of the semiconductor chip 12 is bonded to a copper circuit pattern and a lead frame having the characteristics of the present invention is bonded to the front surface, when the lead frame + copper pattern thickness is 0.9 mm, a 10% reduction in thermal resistance (°C / W) is obtained compared to when the aluminum wire + copper pattern thickness is 0.45 mm.

[0064] As described above, according to the present invention, a wiring configuration is provided in which a lead frame having a first bonding portion with a thickness of 0.1 mm to 0.8 mm and an area of ​​25% to 60% of the area of ​​the top surface of the semiconductor chip in a plan view and a second bonding portion connected to the first bonding portion and bonded to a circuit pattern layer is bonded to the front surface of the semiconductor chip. This makes it possible to suppress the decrease in heat capacity that accompanies the miniaturization (thinning) of the semiconductor chip and improve the short circuit resistance. Although the embodiments have been described above, the configurations of the parts shown in the embodiments can be replaced with other parts having similar functions. Any other components or steps may be added. Furthermore, any two or more configurations (features) of the above-mentioned embodiments may be combined. [Explanation of symbols]

[0065] 1 Semiconductor device 2. Semiconductor Module 3 Cooling device 10, 10a, 10b, 10c Semiconductor unit 11 Insulated circuit board 11a Insulating plate 11b1,11b2,11b3 Wiring board 11c metal plate 12. Semiconductor Chips 12a Control electrode 12b Output electrode (main electrode / output electrode) 12c electrode area 12d Wiring structure section 13a, 13b Lead frame 13a1 1st joint 13a2 1st bending part 13a3 Beam section 13a4 2nd bending part 13a5 2nd joint 14a,14b,14c Bonding material 20 cases 21 Outer Frame 21a,21b,21c,21d Side wall 21e, 21f, 21g Unit storage area 21i Mounting hole 22, 22a, 22b, 22c First connection terminal 23, 23a, 23b, 23c Second connection terminal 24 Output terminal 24a U phase output terminal 24b V phase output terminal 24c W phase output terminal 25a, 25b, 25c control terminals 26 Wire 27 Sealing member 30a, 30c long side 30b,30d short side 30e fastening hole 31 Tabletop 32 Side wall 33 Cooling bottom plate 33a Inlet 33a1, 33b1 Sealing area 33b Outlet 33d Bottom 34 Heat dissipation fin

Claims

1. an insulating circuit board including an insulating plate, a plurality of circuit pattern layers each having a thickness of 600 μm or more and 900 μm or less, which are disposed on an upper surface of the insulating plate, and a heat sink disposed on a lower surface of the insulating plate; a wide gap semiconductor chip having a thickness of 50 μm or more and 120 μm or less, the wide gap semiconductor chip being disposed on an upper surface of the circuit pattern layer via a first bonding material; a conductive member having a first bonding portion connected to the wide gap semiconductor chip via a second bonding material, the first bonding portion having a thickness of 0.1 mm or more and 0.8 mm or less and an area of ​​25% or more and 60% or less of an area of ​​an upper surface of the wide gap semiconductor chip in a planar view, a beam portion extending continuously from the first bonding portion via a first bend, and a second bonding portion extending continuously from the beam portion via a second bend and connecting to another circuit pattern layer adjacent to the circuit pattern layer on which the wide gap semiconductor chip is mounted.

2. 2. The semiconductor module according to claim 1, wherein said insulating plate is a ceramic plate having a thickness of 200 [mu]m to 400 [mu]m and containing silicon nitride as a main component.

3. 2. The semiconductor module according to claim 1, wherein a height from a joint surface of said first bent portion to an upper surface of said beam portion is 5 mm or less.

4. The semiconductor module according to claim 1 , wherein the second bent portion is wider than the first bent portion.

5. The semiconductor module according to claim 1 , wherein the first bent portion is perpendicular to the first joint portion.

6. 2. The semiconductor module according to claim 1, wherein the wide gap semiconductor chip incorporates a field effect transistor and a diode electrically connected in anti-parallel to the field effect transistor.

7. 2. The semiconductor module according to claim 1, wherein the first bonding material below the wide gap semiconductor chip is a sintered material containing silver or copper as a main component.

8. The semiconductor module according to claim 7 , wherein the first bonding material has a thickness of 10 μm or more and 300 μm or less.

9. The semiconductor module according to claim 1 , wherein the second bonding material on the wide gap semiconductor chip is a lead-free solder.

10. 10. The semiconductor module according to claim 9, wherein the lead-free solder has a thickness of 10 [mu]m or more and 300 [mu]m or less.

11. 2. The semiconductor module according to claim 1, wherein the second bonding material on the wide gap semiconductor chip is a sintered material containing silver or copper as a main component.

12. The semiconductor module according to claim 11 , wherein the second bonding material has a thickness of 10 μm or more and 300 μm or less.

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