Semiconductor device, circuit board, and method for manufacturing semiconductor device

Abstract

To provide a semiconductor device and a circuit board which can prevent unexpected short circuit between wires formed on a circuit board, and a method for manufacturing a semiconductor device.SOLUTION: A semiconductor device 1 includes a circuit board 2 having a first surface 2s and a second surface 2b opposite to each other, a memory chip 3 provided on the first surface 2s, a capacitor 4 which is connected to a pad 80 provided on the first surface 2s through a solder 41, a sealing resin for coating the first surface 2s, and the surfaces of the memory chip 3 and the capacitor 4, and a solder ball 5 which is provided on the second surface 2b, wherein a trench TT is formed on the first surface 2s along at least a part of the circumference of the pad 80, and a plated layer 100 is formed on the inner wall of the trench TT.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor device, a circuit board, and a method for manufacturing the semiconductor device. [Background technology]

[0002] 2. Description of the Related Art There has been proposed a semiconductor device in which passive components such as a capacitor are provided on a circuit board together with a semiconductor chip. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2007 / 0176303 [Patent Document 2] US Patent Application Publication No. 2009 / 0071700 [Patent Document 3] US Patent Application Publication No. 2005 / 0224934 [Patent Document 4] US Patent Application Publication No. 2005 / 0029666 [Patent Document 5] US Patent Application Publication No. 2005 / 0017740 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present embodiment is to provide a semiconductor device, a circuit board, and a method for manufacturing a semiconductor device that can prevent unexpected short circuits between wirings formed on a circuit board. [Means for solving the problem]

[0005] The semiconductor device of the present embodiment includes a circuit board having a first surface and a second surface opposite to the first surface, a semiconductor chip provided on the first surface of the circuit board, a passive component connected to an electrode provided on the first surface of the circuit board via solder, a sealing resin covering the first surface of the circuit board and surfaces of the semiconductor chip and the passive component, and an external device connection terminal provided on the second surface of the wiring board. A trench is formed on the first surface along at least a portion of the periphery of the electrode, and a plating layer is formed on the inner wall of the trench. [Brief description of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view illustrating an example of a semiconductor device according to an embodiment; [Diagram 2] 1A and 1B are diagrams illustrating an example of an arrangement of memory chips and capacitors mounted on a circuit board. [Diagram 3] FIG. 2 is a cross-sectional view illustrating an example of a circuit board according to an embodiment. [Figure 4A] 4A to 4C are diagrams illustrating a manufacturing process of the circuit board shown in FIG. [Figure 4B] 4A to 4C are diagrams illustrating a manufacturing process of the circuit board shown in FIG. [Figure 4C] 4A to 4C are diagrams illustrating a manufacturing process of the circuit board shown in FIG. [Figure 4D] 4A to 4C are diagrams illustrating a manufacturing process of the circuit board shown in FIG. [Figure 4E] 4A to 4C are diagrams illustrating a manufacturing process of the circuit board shown in FIG. [Figure 4F] 4A to 4C are diagrams illustrating a manufacturing process of the circuit board shown in FIG. [Figure 4G] 4A to 4C are diagrams illustrating a manufacturing process of the circuit board shown in FIG. [Figure 4H] 4A to 4C are diagrams illustrating a manufacturing process of the circuit board shown in FIG. [Figure 4I] 4A to 4C are diagrams illustrating a manufacturing process of the circuit board shown in FIG. [Diagram 5] FIG. 4 is a cross-sectional view illustrating another example of a circuit board according to an embodiment. [Figure 6] 4 is a flowchart illustrating an example of a manufacturing process of the semiconductor device according to the embodiment. [Figure 7A] 3 is an enlarged plan view of a rectangular area B enclosed by a dotted line in FIG. 2. FIG. [Figure 7B] 7B is a cross-sectional view taken along line CC' of the circuit board shown in FIG. 7A. [Figure 7C] 7B is a cross-sectional view taken along the line DD' of the circuit board shown in FIG. 7A. [Figure 7D] FIG. 7B is a cross-sectional view taken along line CC' of the circuit board shown in FIG. 7A, showing the cross section after reflow treatment. [Figure 8] 7B is another cross-sectional view taken along line CC' of the circuit board shown in FIG. 7A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment will be described with reference to the drawings.

[0008] In the following description, an XYZ coordinate system, which is an example of a Cartesian coordinate system, is used. That is, a plane parallel to the surface of the circuit board 2 constituting the semiconductor device 1 is defined as the XY plane, and a direction perpendicular to the XY plane is defined as the Z axis. The X axis and the Y axis are defined as two perpendicular directions in the XY plane. For convenience of explanation, the vertical direction of the wiring board is described below using a relative vertical relationship in which the positive Z-axis side (the surface on which the semiconductor chip is provided) is the upper side, but does not represent a vertical relationship according to the vertical direction.

[0009] FIG. 1 is a cross-sectional view for explaining an example of a semiconductor device according to an embodiment. Note that FIG. 1 is a schematic diagram showing the cross-sectional structure of the semiconductor device according to the embodiment, and the ratio between components is different from the actual ratio. The semiconductor device 1 according to the embodiment is, for example, a semiconductor package in which a semiconductor chip and passive components mounted on a wiring board are sealed with a molded resin. The semiconductor device 1 includes a circuit board 2, a NAND type flash memory chip (hereinafter, referred to as a memory chip) 3 as a semiconductor chip, a capacitor 4 as a passive component, a solder ball 5, and a molded resin 6. The molded resin 6 is an example of a sealing resin. Note that the semiconductor device 1 may include passive components other than the capacitor 4, such as a resistive element or a coil. The semiconductor device 1 may also include a semiconductor chip other than the memory chip 3, such as a controller chip.

[0010] The circuit board 2 is, for example, an insulating resin circuit board or a ceramic circuit board with a wiring layer provided on the surface or inside. The circuit board 2 has a first surface 2s and a second surface 2b. A memory chip 3 and a capacitor 4 are provided on the first surface 2s. The memory chip 3 is physically attached to the first surface 2s via a film-like adhesive 31. The film-like adhesive 31 is a non-conductive tape-like adhesive containing a resin adhesive component containing a thermosetting resin (for example, an epoxy resin, a polyimide resin, an acrylic resin, or a resin mixture of these). The film-like adhesive 31 adheres objects attached above and below it by applying heat and load. The memory chip 3 is electrically connected to the wiring layer via a pad 32 provided on the circuit board 2 using a conductive wire 33 or the like. The capacitor 4 is physically and electrically connected to a pad 80 provided on the first surface 2s of the circuit board 2 via a solder 41. Lead-free solder is used as the solder 41. For example, the solder 41 has a composition (Su-Ag-Cu) with Sn (tin) as the main component and Ag (silver) or Cu (copper) added thereto. When the solder 41 has Sn as the main component, it may have a composition (Sn-Bi) with Bi (bismuth) added thereto, a composition (Sn-Zn) with Zn (zinc) added thereto, or a composition (Sn-Ag) with Ag added thereto. On the second surface 2b, solder balls 5 are formed as external terminals for a BGA package. The solder balls 5 are an example of terminals for connecting an external device. The solder balls 5 are physically and electrically connected to lands 90 provided on the second surface 2b of the circuit board 2.

[0011] Fig. 2 is a diagram for explaining an example of the arrangement of memory chips and capacitors mounted on a circuit board. Fig. 2 is a top view of the circuit board on which the memory chips and capacitors are arranged, viewed from above the first surface (positive side in the Z direction). Fig. 1 shows a cross section of the semiconductor device 1 taken at the position indicated by A-A' in Fig. 2.

[0012] 2, a memory chip 3 and a capacitor 4 are mounted on the circuit board 2. The memory chip 3 is a thin plate having a rectangular planar shape. The memory chip 3 is disposed on the first surface 2s of the circuit board 2 such that the thickness direction of the thin plate is parallel to the Z direction.

[0013] The capacitor 4 has a rectangular parallelepiped shape. The capacitor 4 is disposed on the first surface 2s of the circuit board 2 such that its bottom surface faces the first surface 2s. The capacitor 4 is disposed at a predetermined distance from the memory chip 3 so as not to overlap with the memory chip 3 in the Z direction. The capacitor 4 has a pair of external electrodes 4a formed on a pair of surfaces (hereinafter referred to as end surfaces) that are perpendicular to the bottom surface and face each other in the long side direction of the bottom surface.

[0014] Next, the structure of the circuit board 2 will be described with reference to Fig. 3. Fig. 3 is a cross-sectional view illustrating an example of a circuit board according to an embodiment. Fig. 3 shows a cross-sectional view of the circuit board along line E-E' on which a memory chip and a capacitor are to be arranged as shown in Fig. 2. The circuit board 2 has an internal circuit IC and an external circuit OC.

[0015] The external circuit OC is composed of wiring layers L1 and L3 formed on the first surface 2s and the second surface 2b. The wiring layer L1 formed on the first surface 2s has a pad 32 electrically connected to the terminal 34 of the memory chip 3, a pad 80 electrically connected to the capacitor 4, and the like. The wiring layer L1 also has a wiring 60a formed thereon. The wiring 60a includes, for example, a wiring that electrically connects the pad 32 connected to the terminal 34 of the memory chip 3 and the pad 80 electrically connected to the capacitor 4. The surface of the wiring layer L1 is covered with a solder resist 70. An opening is provided in the solder resist 70 so that the surface of the pad 80 is exposed. The internal circuit IC is formed under the wiring layer L1 via the prepreg layer 50. A trench TT is formed in the prepreg layer 50. The trench TT is formed to capture solder particles that are unintentionally scattered when the solder 41 is formed on the upper surface of the pad 80. Therefore, the trench TT is formed close to the periphery of the pad 80, which is a location where solder particles are likely to scatter. Fig. 3 shows, as an example, a structure in which a trench TT is formed between two pads 80. A plating layer 100 is formed on the inner wall of the trench TT. The plating layer 100 can prevent the solder particles trapped in the trench TT from penetrating into the prepreg layer 50 and reaching the wiring layer L2.

[0016] The internal circuit IC is composed of a multi-layer wiring layer formed by laminating a plurality of wiring layers L2. FIG. 3 shows an internal circuit IC formed by laminating two wiring layers L2 as an example. The pads 80 and wiring 60a formed in the wiring layer L1 and the wiring 20a formed in the wiring layer L2 are electrically connected through vias (not shown). A core layer 10 is formed between the wirings 20a and 20b (between adjacent wirings above and below) formed by laminating on the wiring layer L2. The core layer 10 is, for example, a hard plate-like member made of glass fiber and epoxy resin. The wirings 20a and 20b formed on the upper and lower surfaces of the core layer 10 are electrically connected through through-hole wiring (not shown). Although FIG. 3 shows the circuit board 2 having the core layer 10, a so-called coreless circuit board not having the core layer 10 can also be used. In this case, the plurality of wirings 20a and 20b formed in the wiring layer L2 are laminated with a prepreg layer 50 sandwiched therebetween.

[0017] The wiring layer L3 formed on the second surface 2b has a plurality of lands 90 and wiring 60b for electrically connecting the solder balls 5 as external terminals. The surface of the wiring layer L3 is covered with a solder resist 70. The solder resist 70 has openings so that the surfaces of all the lands 90 are exposed. The wiring 20b and the lands 90 formed on the wiring layer L2 are electrically connected through vias (not shown). With this configuration, the memory chip 3 is electrically connected to the solder balls 5 through each part of the circuit board 2. In addition, the circuit board 2 also has through holes TH that penetrate from the surface of the solder resist 70 covering the wiring layer L1 to the surface of the solder resist 70 covering the wiring layer L3.

[0018] 4A to 4I are diagrams illustrating the manufacturing process of the circuit board shown in FIG. 3. First, as shown in FIG. 4A, copper foil 201 is attached to the upper and lower surfaces of core layer 10, and heat and pressure are applied. A circuit board in which copper foil is attached to the upper and lower surfaces of the core layer in this manner is also called a copper clad laminate (CCL). Copper clad laminates are widely used in internal circuits.

[0019] Next, photoresist 30 is applied to the surface of the copper foil 201 attached to the upper surface of the core layer 10. A template 40 on which a wiring pattern of an internal circuit IC is formed is placed above the photoresist 30. Ultraviolet rays are irradiated from above the template 40 using a UV light source (such as a high-pressure mercury lamp) not shown, and the wiring pattern of the internal circuit IC formed on the template 40 using photolithography technology is transferred to the photoresist 30 as shown in FIG. 4B.

[0020] Next, the copper foil 201 is etched using the patterned photoresist 30 as a mask, for example, by anisotropic etching. After etching is completed, the photoresist 30 is removed using a cleaning technique, for example, to complete the formation of the wiring 20a as shown in Fig. 4C. The copper foil 201 on the lower surface of the core layer 10 is also processed using photolithography and anisotropic etching techniques to form the wiring 20b as shown in Fig. 4D.

[0021] Next, copper foil 201 is bonded to the surfaces of wiring 20a, 20b via prepreg layer 50. The prepreg constituting prepreg layer 50 is a semi-cured resin sheet in which resin is contained in glass fiber. The top and bottom of the copper-clad laminate are sandwiched between prepreg layers 50, and copper foil 201 is superimposed on the surface of each prepreg layer 50. When these laminates are heated and pressurized from above and below in this state, the prepreg is cured, and the copper-clad laminate and copper foil 201 can be bonded together as shown in FIG. 4E.

[0022] Next, the copper foil 201 adhered to the top surface of the upper prepreg layer 50 is processed using photolithography technology, anisotropic etching technology, etc. to form wiring 60a and pads 80. Moreover, the copper foil 201 adhered to the bottom surface of the lower prepreg layer 50 is processed using photolithography technology, anisotropic etching technology, etc. to form wiring 60b and lands 90, as shown in FIG. 4F.

[0023] Next, a solder resist 70 is formed as a protective film on the surfaces of the wiring layers L1 and L3 that are the external circuit OC. For example, a sheet-like solder resist is attached, and only the parts to be cured are exposed to ultraviolet light using a photolithography technique or the like. Then, the uncured parts are removed using an anisotropic etching technique or the like. That is, as shown in FIG. 4G, the solder resist covering the surfaces of the pads 80 and lands 90 is removed, and the solder resist 70 is processed so that openings are formed.

[0024] Next, a through hole TH is formed penetrating from the surface of one solder resist 70 to the surface of the other solder resist 70. The through hole TH is formed using a micromachining drill. When forming the through hole TH in the circuit board 2, a trench TT is also formed as shown in FIG. 4H. The trench TT is formed at a position a predetermined distance away from the pad 80 using a micromachining drill. The trench TT is formed to a depth that does not penetrate the prepreg layer 50 and does not reach the wiring layer L2. The position and shape of the trench TT will be described in detail later.

[0025] Next, as shown in FIG. 4I, the inner wall of the trench TT is plated to form a plating layer 100. For plating, a material with low wettability to solder (for example, Ni (nickel)) is used. Since Ni cannot be directly plated onto the prepreg layer 50, Ni plating is performed using palladium as a catalyst. Specifically, first, the upper surface of the first surface 2s is covered with a mask (not shown) having an opening in the trench TT formation region, and a dilute palladium solution is applied to the inner wall of the trench TT using a sputtering technique or the like. The dilute palladium solution may be immersed in the trench TT. Then, Ni is plated onto the inner wall of the trench TT using an electroless plating method. Note that the material for forming the plating layer 100 may be any material that has low wettability to solder, and may be a material other than Ni, such as Cr (chromium). The thickness of the plating layer 100 thus formed is, for example, about 3 μm. After Ni plating, the mask (not shown) is removed, and the inside of the trench TT is washed to completely remove the palladium solution. If the palladium solution remains inside the trench TT, Cu (copper) may be precipitated on the surface of the plating layer 100 formed of Ni, which increases the wettability with solder. To prevent this, it is necessary to perform cleaning after plating.

[0026] Finally, the inner walls of the through holes TH are plated with a material such as Cu (copper) to form a plating layer 110, completing the manufacture of the circuit board 2 shown in FIG.

[0027] Fig. 5 is a cross-sectional view for explaining another example of the circuit board of the embodiment. In the above-mentioned method, when forming an opening in the solder resist 70 on the first surface 2s side so that the surface of the pad 80 is exposed, the solder resist 70 is processed so that the size of the opening is larger than the size of the pad 80 (see Figs. 3 and 4G). In contrast, as shown in Fig. 5, the opening may be formed smaller than the size of the pad 80, and the solder resist 70 may be processed so that a part of the solder resist 70 covers the upper surface of the pad 80. In the case of the structure shown in Fig. 5, the trench TT is also formed to a depth that does not penetrate the prepreg layer 50 and does not reach the wiring layer L2.

[0028] Next, a method for manufacturing the semiconductor device 1 of the embodiment will be described. Fig. 6 is a flow chart for explaining an example of a manufacturing process of the semiconductor device of the embodiment. First, the capacitor 4 is soldered to the pad 80 formed on the circuit board 2 (S1). In S1, a solder paste is applied to the first surface 2s of the circuit board 2, for example, by using a squeegee printing technique, and the solder 41 is formed on the pad 80. For example, if the squeegee printing is not performed well, solder particles may scatter from the solder paste and adhere to unintended locations other than the pad 80.

[0029] 7A is an enlarged plan view of a rectangular region B surrounded by a dotted line in FIG. 2. FIG. 7A shows a plan view before the capacitor 4 is mounted, that is, when the solder 41 is formed on the pad 80. The solder particles 41a are captured inside a trench TT formed between the two pads 80. Here, the shape of the trench TT will be described in detail. The trench TT is formed in the gap between the two pads 80. The upper surface of the trench TT has a rectangular shape. In the direction in which the opposing sides of the two pads 80 extend (Y direction in FIG. 7A), the length of the trench TT is formed longer than the length of the pad 80.

[0030] FIG. 7B is a cross-sectional view taken along line C-C' of the circuit board shown in FIG. 7A. FIG. 7C is a cross-sectional view taken along line D-D' of the circuit board shown in FIG. 7A. FIG. 7B and FIG. 7C show a structure above the wiring layer L2. As shown in FIG. 7B, the trench TT is formed between two opposing sides of the two pads 80 in the X direction. The two sides of the trench TT extending in the Y direction are formed at positions spaced apart by a distance L1 from the two opposing sides of the two pads 80. If the diameter of the scattered solder grain 41a is length Ds, the distance L1 is preferably equal to or less than half the length Ds. This is because, by making the distance between the trench TT and the pad 80 equal to or less than the radius of the solder grain 41a, even if the solder grain 41a is scattered on the prepreg layer 50 between the pad 80 and the trench TT in the X direction, it becomes easier for the solder grain 41a to roll down into the trench TT, and the trench TT is more likely to capture the solder grain 41a.

[0031] As shown in FIG. 7B and FIG. 7C, the width of the trench TT is not uniform in the depth direction (Z direction), but is narrower as the depth increases. The bottom of the trench TT may be flat, but is preferably curved downward. By forming such a shape, the solder grains 41a that roll down into the trench TT are captured in the center of the bottom of the trench TT, reducing the possibility of the solder grains 41a falling off the trench TT. Thus, by providing the trench TT, the solder grains 41a are prevented from scattering on the upper surface of the solder resist 70 or the upper surface of the prepreg layer 50, and unintended short circuits in the wiring layer L1 can be prevented.

[0032] When the formation of the solder 41 on the pad 80 is completed, the pair of electrodes 4a formed on the capacitor 4 and the solder 41 formed on the pair of pads 80 are aligned with each other. Then, reflow is performed to fix the solder 41 and the capacitor 4. In the reflow, the solder 41 is heated and melted, and then cooled, so that the capacitor 4 is fixed to the pad 80 using the solder 41 as an adhesive. FIG. 7D is a cross-sectional view taken along line C-C' of the circuit board shown in FIG. 7A, showing the cross-section after the reflow process. By heating the solder 41 in the reflow process, the solder particles 41a scattered and captured in the trench TT are also melted. The melted solder particles 41a may penetrate the prepreg layer 50 and reach the wiring layer L2.

[0033] However, the inner wall of the trench TT is formed with a plating layer 100 having low wettability to the solder particles 41a such as Ni. Therefore, as shown in FIG. 7D, even if the solder particles 41a melt, the plating layer 100 can prevent the solder particles 41a from penetrating into the prepreg layer 50. Therefore, it is possible to prevent unexpected short circuits between the wiring layers L1 and L2 caused by the scattered solder particles 41a. As described above, when lead-free solder containing Sn as the main component is used as the solder, the wettability between Ni and the solder is reduced by Sn. Therefore, regardless of the components added to Sn, the plating layer 100 can prevent the solder particles 41a from penetrating into the prepreg layer 50.

[0034] In order to prevent the solder particles 41a captured in the trench TT from scattering again outside the trench TT, the trench TT may be shaped as shown in FIG. 8. FIG. 8 is another cross-sectional view taken along the line C-C' of the circuit board shown in FIG. 7A. The trench TT is formed so that the width of the trench TT becomes wider as the depth increases from the entrance of the trench TT to a predetermined depth, and when the predetermined depth is exceeded, the width of the trench TT becomes narrower as the depth increases, as in FIG. 7B. That is, a so-called barb structure TTa is provided at the entrance of the trench TT. By providing the barb structure TTa, the solder particles 41a captured in the trench TT can be further suppressed from scattering again, and unintended short circuits can be further prevented.

[0035] Returning to the flow of FIG. 6, after the capacitor 4 and the pad 80 are physically and electrically connected in S1, the memory chip 3 is attached onto the first surface 2s of the circuit board 2 (S2). S2 is a process called die bonding. A predetermined area on the first surface 2s of the circuit board 2 and the back surface of the memory chip 3 are attached using a film-like adhesive 31 such as a die attach film (DAF). Next, the circuit board 2 is heated in an oven to harden the film-like adhesive 31. Furthermore, the terminal 34 of the memory chip 3 and the pad 32 formed on the wiring layer L1 of the circuit board 2 are connected using a metal wire 33 such as gold (Au) (S3). S3 is a process called wire bonding.

[0036] Next, the circuit board 2 is sealed with resin (S4). S4 is a process called molding. In S4, the trench TT is also filled with the molding resin 6, so that the captured solder particles 41a are fixed in the trench TT. Next, solder balls 5, which are external terminals, are bonded to lands 90 formed on the wiring layer L3 of the circuit board 2 using a conductive adhesive such as solder paste. Then, the circuit board 2 is heated by a reflow process to fix the lands 90 and the solder balls 5 (S5). By carrying out the above processes, the semiconductor device 1 of the embodiment is manufactured.

[0037] Thus, according to this embodiment, the trench TT is formed along the pad 80 formed on the first surface 2s of the circuit board 2. With this structure, even if a part of the solder 41 becomes granular and scatters to a place other than the pad when the solder 41 is formed on the upper surface of the pad 80, it can be captured in the trench TT. Therefore, it is possible to prevent an unexpected short circuit in the wiring layer L1. In addition, a plating layer 100 using a metal having low wettability with respect to the solder 41 is formed on the inner wall of the trench TT. Therefore, even if the solder 41 is melted by a heat treatment such as reflow, it is possible to prevent the solder 41 from penetrating into the wiring layer L2 below the trench TT, and it is also possible to prevent an unexpected short circuit in the wiring layer L2 and between the wiring layers L1 and L2.

[0038] The number of wiring layers laminated on the circuit board 2 is not limited to four. The circuit board 2 may be composed of only the external circuit OC, i.e., only two wiring layers L1 and L3, or may be composed of a multi-layer wiring layer of five or more layers. In the above description, the trench TT is formed in the gap between the pair of pads 80, but the trench TT may be formed to correspond to each side of the pad 80. For example, the trench TT may be formed to surround the periphery of the pad 80. Furthermore, when an electronic component such as a memory chip 3 is connected to a pad using solder as in the flip chip method, the trench TT may be formed in the pad that electrically connects the electronic component to the circuit board 2.

[0039] Although the embodiment of the present invention has been described, this embodiment is shown as an example and is not intended to limit the scope of the invention. This new embodiment can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0040] REFERENCE SIGNS LIST 1...semiconductor device, 2...circuit board, 2s...first surface, 2b...second surface, 3...memory chip, 4...capacitor, 5...solder ball, 6...molding resin, 41...solder, 80...pad, TT...trench

Claims

1. a circuit board having a first surface and a second surface opposite to the first surface, a semiconductor chip provided on the first surface of the circuit board, a passive component connected via solder to an electrode provided on the first surface of the circuit board, a sealing resin covering the first surface of the circuit board and a surface of the semiconductor chip and the passive component, and a terminal for connecting an external device provided on the second surface of the circuit board; A semiconductor device comprising: a trench is formed in the first surface along at least a portion of a periphery of the electrode; A plating layer is formed on the inner wall of the trench.

2. Two of the electrodes are provided on the first surface, The trench is formed between the two electrodes. The semiconductor device according to claim 1 .

3. the passive component is a capacitor having two external electrodes; The two electrodes are connected to the two external electrodes, respectively. The semiconductor device according to claim 2 .

4. The plating layer is formed of a metal material having low wettability with respect to the solder. The semiconductor device according to claim 1 .

5. 5. The semiconductor device according to claim 4, wherein said metallic material is nickel.

6. The trench is formed so that its width becomes narrower as its depth increases. The semiconductor device according to claim 1 .

7. The semiconductor device according to claim 1 , wherein the solder is attached to an inner wall of the trench.

8. A circuit board having a first surface and a second surface opposite to the first surface, and an electrode capable of being electrically connected to a passive component formed on the first surface, a trench is formed in the first surface along at least a portion of a periphery of the electrode; A plated layer is formed on the inner wall of the trench.

9. Two of the electrodes are provided on the first surface, The trench is formed between the two electrodes. The circuit board according to claim 8.

10. an internal circuit is formed between the first surface and the second surface; a depth of the trench is shallower than a depth from the first surface to the internal circuit; The circuit board according to claim 8.

11. The plating layer is formed of a metal material having low wettability with tin. The circuit board according to claim 8.

12. The circuit board of claim 11 , wherein the metallic material is nickel.

13. A circuit board having a first surface and a second surface opposite to the first surface, an electrode electrically connected to a passive component formed on the first surface, a trench formed on the first surface along at least a portion of a periphery of the electrode, and a plating layer formed on an inner wall of the trench, Attaching a passive component to the electrode using solder; electrically connecting the circuit board and the semiconductor chip; covering the first surface of the circuit board, surfaces of the semiconductor chip and the passive components, and an inside of the trench with a sealing resin; connecting an external device connection terminal to the second surface of the circuit board using a conductive adhesive; A method for manufacturing a semiconductor device comprising the steps of:

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