Solid-state imaging element and manufacturing method of solid-state imaging element

Abstract

To provide a solid-state imaging element capable of suppressing a formation defect of a connection part, and a manufacturing method of the solid-state imaging element.SOLUTION: A solid-state imaging element 100 comprises: a semiconductor substrate 5 including a first region 51 having a first conductivity type and a plurality of second regions 52 having a second conductivity type; and a plurality of joint terminals 40 electrically connected to the second regions 52 and connected to different external terminals. The joint terminal 40 includes a second terminal 42 which is connected to the first region 51 by a third path Q3 via a PN junction 53 between the second region 52 and the first region 51 by being connected to the second region 52, is connected to the first region 51 by a different fourth path Q4 via a second resistor Z2 different from a first resistor Z1, and configures a portion different from a read-out circuit 30.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present disclosure relates to a solid-state imaging device and a method for manufacturing a solid-state imaging device. [Background technology]

[0002] Patent Document 1 describes a back-illuminated solid-state imaging device. In this solid-state imaging device, a horizontal shift register is provided at the end of the charge transfer direction in the imaging region. Charge transfer electrodes are arranged in the horizontal shift register, and a charge readout circuit is provided at the final position of the charge transfer. The charge readout circuit includes a signal gate region located at the end of the horizontal shift register connected to an electrode pad. Next to this signal gate region, a floating diffusion region is provided via a transistor having a MOS-FET structure. The floating diffusion region is connected to a reset drain electrode pad via a reset transistor Q2, and is also connected to the gate electrode of an output transistor Q3. One terminal of the output transistor Q3 is connected to an overflow drain electrode pad, and the other terminal constitutes an output terminal. A load resistor is connected to the output terminal. A reset gate electrode pad is connected to the gate electrode of the transistor Q2. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2010-232495 A Summary of the Invention [Problem to be solved by the invention]

[0004] As described in the above Patent Document 1, a solid-state imaging device is provided with a plurality of connection terminals such as an output terminal and a reset drain electrode pad. When connecting these connection terminals to external connection terminals, it is considered to form connection parts such as solder bumps or wires on the plating layer (UBM (Under Bump Metal)) of the connection terminals. In this case, defective formation of the connection parts may occur in some of the connection terminals.

[0005] In view of the above, an object of the present disclosure is to provide a solid-state imaging element capable of suppressing defective formation of a connection portion, and a method for manufacturing the solid-state imaging element. [Means for solving the problem]

[0006] As a result of intensive research by the present inventors to solve the above problems, the inventors have come to the following knowledge regarding one of the causes of defective connection in some joint terminals. That is, in joint terminals with defective connection, the amount of Ni detected on the surface of the plating layer tends to be large. Normally, the presence of Au on the outermost surface of a joint terminal prevents the oxidation of Ni, but the presence of oxidized Ni on the outermost surface inhibits the formation of an alloy layer with solder on the surface of the plating layer, which is thought to result in defective connection.

[0007] On the other hand, it was confirmed that among the multiple joining terminals, some are more likely to have defective connections than others. For example, among the multiple joining terminals, joining terminals constituting a readout circuit, such as an output source (OS) terminal or an output drain (OD) terminal, are less likely to have defective connections, whereas joining terminals not constituting a readout circuit, such as a reset drain (RD) terminal or an overflow drain (OFD) terminal, tend to have defective connections.

[0008] The reasons for this tendency are believed to be as follows: The junction terminals constituting the readout circuit are connected to a semiconductor region including a PN junction, and are also connected to a constant potential such as GND via a path other than the PN junction, so that the potential is stabilized when the plating layer is formed, suppressing Ni deposition on the Au, and thus making it difficult for defects to occur in the formation of the connection. On the other hand, in the case of junction terminals not constituting the readout circuit, conventionally they are not connected to a constant potential via a path other than the PN junction, so that the stabilization of the potential when the plating layer is formed does not sufficiently suppress Ni deposition on the Au, and thus making it easy for defects to occur in the formation of the connection.

[0009] In response to this, the present inventor connected a junction terminal, which was not previously connected to a constant potential via a path other than a PN junction, to a constant potential via a polysilicon resistor, and the formation failure of the connection was suppressed. One of the reasons for this is believed to be that, as described above, in addition to the connection to a constant potential via a PN junction, a connection to a constant potential via a polysilicon resistor is formed, thereby stabilizing the potential when forming a plating layer. The present disclosure is the result of further investigation by the present inventor based on the above findings.

[0010] That is, the solid-state imaging element according to the present disclosure is [1] "a solid-state imaging element comprising: a semiconductor substrate having a first region having a first conductivity type and a plurality of second regions having a second conductivity type different from the first conductivity type; a plurality of junction terminals electrically connected to the second regions and connected to different external terminals, and a gate terminal electrically insulated from the second regions, wherein the plurality of junction terminals are connected to a portion of the second regions of the plurality of second regions, thereby being connected to the first region by a first path via a PN junction between the second region and the first region and connected to the first region by a second path via a first resistance generated in a transistor constituting a readout circuit, and a first terminal constituting a readout circuit; and a second terminal connected to another portion of the second regions of the plurality of second regions, thereby being connected to the first region by a third path via a PN junction between the second region and the first region and connected to the first region by another fourth path via a second resistance different from the first resistance, and constituting a portion different from the readout circuit."

[0011] This solid-state imaging device includes a plurality of junction terminals connected to a second region of a second conductivity type in a semiconductor substrate. The plurality of junction terminals include a first terminal constituting a readout circuit and a second terminal not constituting the readout circuit. The first terminal constituting the readout circuit is connected to the first region of the semiconductor substrate (i.e., the constant potential of the first region) by a first path via a PN junction formed in the semiconductor substrate, and is further connected to the first region by a second path via a first resistor generated in a transistor of the readout circuit. Thus, as described above, in the first terminal, the potential is stabilized when the plating layer is formed. Furthermore, the second terminal not constituting the readout circuit is connected to the first region by a third path via a PN junction formed in the semiconductor substrate, and is separately connected to the first region by a fourth path via a second resistor. Thus, in the second terminal, the potential is stabilized when the plating layer is formed. Thus, in this solid-state imaging device, defective formation of a connection part such as a solder bump or a wire in the junction terminal is suppressed. In this solid-state imaging device, since the connecting terminals are connected to different external terminals, it is possible to apply an optimal potential to each of the connecting terminals.

[0012] The solid-state imaging device according to the present disclosure may be [2] "the solid-state imaging device according to the above [1], in which the second resistor is made of a polysilicon resistor." In this case, it becomes possible to easily form a connection to the first region via the second resistor having a suitable resistance value.

[0013] The solid-state imaging element according to the present disclosure may be [3] "the solid-state imaging element according to the above [1] or [2], in which the resistance value of the second resistor is 1 kΩ or more and 100 kΩ or less." In this case, it is possible to preferably stabilize the potential at the first terminal and the second terminal when the plating layer is formed, and it is also possible to suppress instability of operation due to a low resistance value between the second terminal and the first region.

[0014] The solid-state imaging element according to the present disclosure may be [4] "the solid-state imaging element according to any one of the above [1] to [3], in which the second terminal includes at least one of a reset drain terminal, a scupper drain terminal, and an overflow drain terminal." In this way, various terminals can be applied as the second terminal.

[0015] The solid-state imaging element according to the present disclosure may be [5] "the solid-state imaging element according to any one of the above [1] to [4], in which the joining terminal is connected to the external terminal by bump bonding." In this case, it is more effective to suppress formation defects of the connection portion (e.g., solder bump) than in the case where the joining terminal is connected to the external terminal by wire bonding.

[0016] The solid-state imaging element according to the present disclosure may be [6] "the solid-state imaging element according to any one of the above [1] to [5], in which the joining terminal includes a plurality of the second terminals." In this case, in the joining terminal including the plurality of second terminals, defective formation of the connection portion is suppressed.

[0017] The solid-state imaging element according to the present disclosure may be [7] "the solid-state imaging element according to the above [6], in which each of the second terminals is connected to the first region by a fourth path different from each other." In this way, the second terminals do not need to share the fourth path to the first region.

[0018] The solid-state imaging element according to the present disclosure may be [8] "the solid-state imaging element according to the above [7], in which the second resistors present in the respective fourth paths different from each other have different resistance values ​​from each other." In this case, it is possible to set an appropriate resistance value of the second resistor for the second terminals having different allowable current values ​​from each other.

[0019] The solid-state imaging element according to the present disclosure may be [9] "the solid-state imaging element according to any one of the above [1] to [8], in which a wiring portion from the second terminal to the PN junction of the third path is made of only metal wiring." In this way, it is not necessary to interpose a resistive element in the wiring portion between the second terminal and the PN junction.

[0020] The solid-state imaging element according to the present disclosure may be

[10] "the solid-state imaging element according to any one of [1] to [9] above, in which the thickness of the first region is greater than the thickness of the second region." In this case, the potential of the first region is likely to be stabilized, so that poor formation of the connection portion can be reliably suppressed.

[0021] The solid-state imaging element according to the present disclosure may be

[11] "the solid-state imaging element according to any one of [1] to

[10] above, wherein the semiconductor substrate has the first conductivity type and further has a third region having an impurity concentration higher than an impurity concentration of the first region, and the first terminal is connected to the first region through the third region in the second path." In this case, it is possible to connect the first terminal and the semiconductor region with lower resistance.

[0022] A method for manufacturing a solid-state imaging device according to the present disclosure includes,

[12] "a first step of preparing a semiconductor substrate having a first region having a first conductivity type and a plurality of second regions having a second conductivity type different from the first conductivity type; a second step of forming, after the first step, a plurality of bonding terminals electrically connected to the second region; and a third step of forming, after the second step, a plating layer on surfaces of the plurality of bonding terminals, the bonding terminals being connected to a portion of the plurality of second regions, so that the bonding terminals are connected to the first region by a first path via a PN junction between the second region and the first region. and a fifth step of forming, as the junction terminal, a second terminal that constitutes a part different from the readout circuit, the second terminal being connected to another second region of the plurality of second regions, the second terminal being connected to the first region by a third path via a PN junction between the second region and the first region, and the first region by a fourth path not via the first resistor.

[0023] This method of manufacturing a solid-state imaging device includes a second step of forming a plurality of junction terminals connected to a second region of a second conductivity type in a semiconductor substrate. The second step includes a fourth step of forming a first terminal constituting a readout circuit, and a fifth step of forming a second terminal not constituting a readout circuit. In the fourth step, the first terminal constituting the readout circuit is formed so as to be connected to a first region of the semiconductor substrate (i.e., a constant potential of the first region) by a first path via a PN junction formed in the semiconductor substrate, and further connected to the first region by a second path via a first resistance generated in a transistor of the readout circuit. Thus, as described above, in the first terminal, the potential is stabilized when the plating layer is formed in the third step. Furthermore, in the fifth step, the second terminal not constituting a readout circuit is formed so as to be connected to the first region by a third path via a PN junction formed in the semiconductor substrate, and separately connected to the first region by a fourth path. Thus, in the second terminal, the potential is stabilized when the plating layer is formed in the third step. Therefore, in this method for manufacturing a solid-state imaging device, defective formation of connections such as solder bumps or wires at the joining terminals is suppressed.

[0024] The method for manufacturing a solid-state imaging element according to the present disclosure may be

[13] "the method for manufacturing a solid-state imaging element according to the above [5], in which in the fifth step, a second resistor is formed so as to be interposed in the fourth path between the second terminal and a constant potential." In this way, by interposing an appropriate second resistor between the second terminal and the first region, it is possible to appropriately stabilize the potential when forming the plating layer while suppressing instability of the operation.

[0025] The method for manufacturing a solid-state imaging element according to the present disclosure may be

[14] "the method for manufacturing a solid-state imaging element according to the above

[12] or

[13] , including a sixth step of cutting the fourth path between the second terminal and a constant potential after the third step." In this way, by connecting the second terminal and the first region via the fourth path when the plating layer is formed in the third step, and then cutting the fourth path, it is possible to preferably stabilize the potential when the plating layer is formed while suppressing instability in operation. Therefore, even if there is no space to provide a second resistor (or high resistor) such as a polysilicon resistor in the fourth path, it is possible to preferably stabilize the potential when the plating layer is formed while suppressing instability in operation.

[0026] The method for manufacturing a solid-state imaging element according to the present disclosure may be

[15] "the method for manufacturing a solid-state imaging element according to any one of

[12] to

[14] above, including a seventh step of cutting the second path between the first terminal and the first region after the third step." In this way, by keeping the first terminal and the first region connected by the second path when the plating layer is formed in the third step, and then cutting the second path, it is possible to preferably stabilize the potential when the plating layer is formed while suppressing instability in operation. Effect of the Invention

[0027] According to the present disclosure, it is possible to provide a solid-state imaging element capable of suppressing defective formation of a connection portion, and a method for manufacturing a solid-state imaging element. [Brief description of the drawings]

[0028] [Figure 1] 1 is a perspective view of a solid-state imaging element according to an embodiment of the present invention. [Diagram 2] 2 is a bottom view of the solid-state imaging device shown in FIG. [Diagram 3] 3 is a schematic cross-sectional view showing a mounting state of the solid-state imaging element shown in FIG. 1 and FIG. 2. [Figure 4] FIG. 3 is a diagram showing an imaging area and a horizontal shift register shown in FIGS. 1 and 2. [Diagram 5] FIG. 5 is a circuit diagram including the readout circuit shown in FIG. 4. [Figure 6] 6 is a cross-sectional view of a semiconductor substrate corresponding to a portion AR of the circuit diagram shown in FIG. 5. [Figure 7] FIG. 2 is a schematic diagram showing the connection relationship between each terminal and ground. [Figure 8] 4 is a flowchart showing a method for manufacturing the solid-state imaging device according to the present embodiment. [Figure 9] 13 is a flowchart showing a method for manufacturing a solid-state imaging device according to a modified example. [Figure 10] 10A to 10C are schematic circuit diagrams illustrating the steps shown in FIG. 9. [Figure 11] FIG. 13 is a circuit diagram according to a modified example. [Figure 12] 12 is a cross-sectional view of a semiconductor substrate corresponding to a portion AR of FIG. 11. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Hereinafter, a solid-state imaging device according to an embodiment will be described with reference to the drawings. In the description of each drawing, the same or overlapping elements are given the same reference numerals, and overlapping descriptions may be omitted. In addition, each drawing may illustrate an orthogonal coordinate system consisting of an X-axis, a Y-axis, and a Z-axis.

[0030] Fig. 1 is a perspective view of a solid-state imaging element according to this embodiment. Fig. 2 is a bottom view (a plan view seen from the side opposite to the light incidence direction) of the solid-state imaging element shown in Fig. 1. The solid-state imaging element 100 shown in Figs. 1 and 2 includes a semiconductor substrate 5. The semiconductor substrate 5 includes a front surface 5s and a back surface 5r opposite to the front surface 5s.

[0031] As an example, the solid-state imaging device 100 is a BT-CCD (charge-coupled device) in which the back surface 5r side of the semiconductor substrate 5 is thinned by etching with a KOH solution or the like. In the solid-state imaging device 100, a recess TD formed by etching and a relatively thick frame portion TT around the recess TD are formed on the back surface 5r of the semiconductor substrate 5. Note that the entire region of the semiconductor substrate 5 may be thinned by removing the frame portion TT by etching.

[0032] An imaging region 10, which is a photosensitive region, is formed in the recess TD of the semiconductor substrate 5. A light image L from an object is incident on the imaging region 10 from the negative direction of the Z axis. A bottom surface 101 of the recess TD of the semiconductor substrate 5 is a light incident surface. As described later, imaging CCDs consisting of a plurality of vertical shift registers are formed as pixels in the imaging region 10. In the imaging region 10, charges corresponding to the light image L are generated, and the charges are transferred along the negative direction of the Y axis. A horizontal shift register 20 is provided at the end of the charge transfer direction of the imaging region 10. The charges transferred vertically toward the horizontal shift register 20 are sequentially transferred in the positive direction of the X axis in the horizontal shift register 20. The charges transferred by the horizontal shift register 20 are read out by a readout circuit 30 provided at the end of the horizontal shift register 20.

[0033] Known charge transfer methods for CCDs include frame transfer, interline transfer, full frame transfer, etc. Many such CCD structures are known, and although there is no particular limitation, the solid-state imaging device 100 uses a full frame transfer CCD as an example.

[0034] A plurality of terminals (electrode pads) are provided at positions corresponding to the frame portion TT on the front surface 5s of the semiconductor substrate 5. The plurality of terminals include terminals P1V, P2V for applying a two-phase transfer voltage to the charge transfer electrodes in the vertical shift register, terminals P1H, P2H for applying a two-phase transfer voltage to the charge transfer electrodes in the horizontal shift register 20, a terminal SS for connecting the semiconductor substrate 5 to ground (constant potential), terminals SG, OG, RG, OD, RD for reading out the charges transferred in the horizontal direction, and a terminal OS for extracting the output.

[0035] The multiple terminals provided on the surface 5s of the semiconductor substrate 5 include a terminal TG for functioning as a charge transfer gate to the horizontal shift register 20, terminals ISV and ISH for inputting test signals, and terminals 1G1V, 1G2V, 1G1H and 1G2H for functioning as charge transfer gates for these test signals. Furthermore, the multiple terminals include terminals SD and OFD.

[0036] As shown in FIG. 3, the solid-state imaging element 100 is mounted on the package T1 so that the surface 5s of the semiconductor substrate 5 faces the package T1. At this time, each of the above-mentioned terminals is electrically connected to the package T1 via the solder bump B, and is also connected to an external sensor driving circuit (external load resistor and power supply) via the pins of the socket T2 attached to the package T1. In other words, each of the above-mentioned terminals is connected to a plurality of external terminals different from each other. Note that in FIG. 3, the above-mentioned terminals are shown as a bonding terminal 40 including a first terminal 41 and a second terminal 42, and a gate terminal 45. The details of the bonding terminal 40 and the gate terminal 45 will be described later. As shown in FIG. 3, the bonding terminal 40 and the gate terminal 45 are connected to the external terminals by bump bonding via the solder bump B. However, the bonding terminal 40 and the gate terminal 45 may be connected to the external terminals by wire bonding.

[0037] Fig. 4 is a diagram showing the imaging region and horizontal shift register shown in Fig. 1 and Fig. 2. Note that Fig. 4 is a schematic diagram in which the shape of each transfer electrode extending in the X-axis direction is rectangular and is illustrated as if there are gaps between them, but in reality, they overlap partly or entirely, and their shapes are set to have openings for light transmission, as described later.

[0038] As shown in FIG. 4, in the imaging area 10, a plurality of vertical shift registers n1 to n N (N is an integer of 2 or more), that is, vertical charge transfer CCDs are aligned. The actual imaging area is the central area of ​​the imaging area 10, and the peripheral pixels may be shaded as necessary. The pixels in the vertical direction are aligned along the Y axis, and the charge transfer electrodes m1 to m M (M is an integer of 2 or more) each extends along the X-axis. M A two-phase transfer voltage is applied from terminals P1V and P2V to the charge transfer electrodes m1 to m M The charge stored in the semiconductor region directly below is transferred vertically (negative Y-axis direction).

[0039] In addition, the vertical shift registers n1 to n N Between the vertical CCD channels (semiconductor charge transfer regions) that make up the CCD array, there are isolation regions of the opposite conductivity type to the charges flowing through the CCD channels, and these isolation regions prevent charges from coming from different pixel columns from mixing together.

[0040] At the final position of the vertical charge transfer, a transfer gate electrode m T is provided, and a transfer gate electrode m T The charge flows into the horizontal shift register 20 through the potential directly below the horizontal charge transfer CCDs. The horizontal shift register 20 is a CCD array along the X axis that transfers charge in the horizontal direction (positive direction of the X axis). Charge transfer electrodes h1 to h K (K is an integer of 2 or more) are provided, and these charge transfer electrodes are arranged along the X-axis direction.

[0041] Charge transfer electrodes h1~h K A two-phase transfer voltage is applied from terminals P1H and P2H to the charge transfer electrodes h1 to h K The charge stored in the semiconductor region directly below the pixel is transferred in the horizontal direction (X-axis direction). A readout circuit 30 is provided at the final position of the charge transfer on the X-axis.

[0042] FIG. 5 is a circuit diagram including the readout circuit shown in FIG. 4 and a circuit different from the readout circuit. As shown in FIG. 5, the readout circuit 30 includes terminals OS and OD. The terminal OS is an output source terminal for outputting a signal, and the terminal OD is an output drain terminal which is a terminal of an output circuit section. The terminal OS is connected to the source terminal of the transistor L6. More specifically, the source terminal of the transistor L6 is connected to an external load resistor Zr connected to the ground (constant potential), and the terminal OS is connected between the source terminal and the external load resistor Zr. The external load resistor Zr is mounted in the sensor driving circuit described above. The transistors L1 to L6 have, for example, a MOS-FET structure.

[0043] The terminal OD is connected to the drain terminals of the transistors L2, L4, and L6. The source terminal of the transistor L2 is connected to the ground (constant potential) via the transistor L3, and the source terminal of the transistor L4 is connected to the ground (constant potential) via the transistor L5. The connection relationship of the terminal OD will be described in more detail.

[0044] FIG. 6 is a cross-sectional view of a semiconductor substrate corresponding to a portion AR of the circuit diagram shown in FIG. 5. FIG. 7 is a schematic diagram showing the connection relationship between each terminal and the ground. FIG. 7(a) is a schematic cross-sectional view, and FIG. 7(b) and FIG. 7(c) are schematic circuits. As shown in FIG. 6 and FIG. 7, the semiconductor substrate 5 has a first region 51 of a first conductivity type (e.g., P type) and a plurality of second regions 52 (one second region 52 is shown in FIG. 6 and two second regions 52 are shown in FIG. 7) of a second conductivity type (e.g., N type) different from the first conductivity type. In a direction intersecting the front surface 5s and rear surface 5r of the semiconductor substrate 5, the thickness of the first region 51 is greater than the thickness of the second region 52. In addition, the semiconductor substrate 5 has a first region 51 of a second conductivity type (e.g., N type) provided in the second region 52. + Third regions 54, 55, and 56 are provided in the first region 51 and have a first conductivity type (e.g., P + The fourth region 57 has a higher impurity concentration than the first region 51.

[0045] A gate electrode 61 is provided between the third region 54 and the third region 55, and another gate electrode 62 is provided between the third region 55 and the third region 56. As a result, a transistor L2 (MOS-FET) is formed in the region immediately below the third region 54, the third region 55, and the gate electrode 61, and a transistor L3 is formed in the region immediately below the third region 55, the third region 56, and the gate electrode 62. Furthermore, a metal wiring (e.g., Al wiring) 71 is connected to the third region 55, and the third region 56 is connected to the fourth region 57 via a metal wiring (e.g., Al wiring) 72. The terminal OD is connected to the third region 54.

[0046] 5 to 7, the terminal OD is connected to the first region 51 (i.e., the constant potential of the first region 51, here, ground (the same applies below)) via at least the transistor L2, the transistor L3, the metal wiring 72, and the fourth region 57. The terminal OD is also connected to the first region 51 via a PN junction 53 generated between the first region 51 and the second region 52.

[0047] That is, the terminal OD is connected to a second region 52 (third region 54) of the second regions 52 of the junction terminals 40, and is connected to the first region 51 by a first path Q1 via a PN junction 53 between the second region 52 and the first region 51, and is connected to the first region 51 by a second path Q2 via a first resistance Z1 generated in the transistors L2 and L3 constituting the readout circuit 30, and is the first terminal 41 constituting the readout circuit 30. The first resistance Z1 is a resistance generated between the source and drain of the transistor. The terminal OD is connected to the first region 51 by the second path Q2 via a fourth region 57 having a higher impurity concentration.

[0048] Similarly, the terminal OS is connected to the terminal OD via the transistor L6, and therefore, like the terminal OD, is connected to a part of the second regions 52 (the third region 54) of the plurality of second regions 52, and is connected to the first region 51 by a first path Q1 via a PN junction 53 between the second region 52 and the first region 51, and is also connected to the first region 51 by a second path Q2 via a first resistance Z1 generated in the transistors L2 and L3 constituting the readout circuit 30, and is a first terminal 41 constituting the readout circuit 30. Note that, between a part of the fourth region 57 to which the metal wiring 72 is connected and the second region 52 adjacent to the part, a LOCOS (Local Oxidation of Silicon) region 58 is formed on the remaining region of the fourth region 57.

[0049] 5, the terminal RD is connected to the drain terminal of the transistor L1 and is connected to the floating diffusion region FD through the transistor L1. The terminal RD is a reset drain terminal for resetting the floating diffusion region FD. The terminal RG is connected to the gate terminal of the transistor L1.

[0050] 5 to 7, like the terminals OS and OD, the terminal RD is connected to the second region 52 and is connected to the first region 51 by a third path Q3 via a PN junction 53 between the second region 52 and the first region 51, but does not have a path to ground via a first resistance Z1 generated in a transistor constituting the readout circuit 30. However, the terminal RD is connected to the first region 51 via a second resistance Z2 different from the first resistance Z1. The second resistance Z2 is not particularly limited, but is composed of, for example, a polysilicon resistance.

[0051] That is, the terminal RD is connected to another part of the second regions 52 among the plurality of second regions 52, and is connected to the first region 51 by a third path Q3 via a PN junction 53 between the second region 52 and the first region 51, and is also connected to the first region 51 by another fourth path Q4 via a second resistor Z2 different from the first resistor Z1, and is the second terminal 42 constituting a part different from the readout circuit 30. As an example, the resistance value of the first resistor Z1 is 0.1 kΩ or more and 50 kΩ or less, and the resistance value of the second resistor Z2 is 1 kΩ or more and 100 kΩ or less. Note that, as described above, the resistance value of the first resistor Z1 is 0.1 kΩ or more and 50 kΩ or less when the readout circuit 30 is not driven, but is in a conductive state when the readout circuit 30 is driven. When the readout circuit 30 is driven, a positive voltage is applied to the terminals RD and OD (when the readout circuit 30 is not driven, the solid-state imaging device 100 itself is turned off, so no voltage is applied). Furthermore, in the third path Q3, the wiring portion from the terminal RD to the PN junction 53 may be made of only metal wiring.

[0052] The terminal SD is a second conductivity type (e.g., N + The terminals are connected to a pixel region (see FIG. 2) of a pixel type, and are scupper drain terminals for discharging signal charges that become a noise source from the outer periphery of the imaging region 10. The terminal OFD is an overflow drain terminal for discharging charges overflowing from the pixels (see FIG. 2). The terminal ISV is a vertical input source terminal for evaluating vertical charge transfer, and the terminal ISH is a horizontal input source terminal for evaluating horizontal charge transfer and amplifier characteristics.

[0053] Like terminal RD, these terminals SD, OFD, ISV, and ISH are connected to another part of the multiple second regions 52, and are therefore connected to the first region 51 by a third path Q3 via a PN junction 53 between the second region 52 and the first region 51, and are also connected to the first region 51 by another fourth path Q4 via a second resistor Z2 different from the first resistor Z1, thereby forming second terminals 42 that constitute a part different from the readout circuit 30.

[0054] In this manner, the junction terminal 40 includes a plurality of second terminals 42 (terminals RD, SD, OFD, ISV, and ISH). Each of the plurality of second terminals 42 may be connected to the first region 51 by a fourth path Q4 that is different from the others (i.e., the fourth path Q4 may not be shared). Furthermore, the second resistors Z2 intervening in each of the fourth paths Q4 that are different from the others may be set to have resistance values ​​that are different from each other.

[0055] Furthermore, the terminals SG, OG, and RG are each a gate terminal 45 that is provided on the semiconductor substrate 5 via an insulating film made of, for example, silicon oxide, and is thereby electrically insulated from the second region 52. The terminal SG is a summing gate terminal that is configured in the final stage of the horizontal shift register 20 and contributes to the horizontal transfer drive of charges. The terminal OG is an output gate terminal that is located between the horizontal shift register 20 and the floating diffusion region FD and contributes to the charge transfer from the horizontal shift register 20 to the floating diffusion region FD. The terminal RG is a reset gate terminal that contributes to resetting the charges in the floating diffusion region FD.

[0056] As described above, the solid-state imaging element 100 includes a plurality of bonding terminals 40 including the first terminals 41 (terminals OD, OS) and the second terminals 42 (terminals RD, SD, OFD, ISV, ISH), and the gate terminals 45 (terminals SG, OG, RG). The plurality of bonding terminals 40 and the gate terminals 45 are bonded to the solder bumps B via the plating layers 46 (see FIG. 3) formed on the respective surfaces, and are connected to different external terminals. The plating layer 46 is formed, for example, by UBM (Under Bump Metal) processing, and is an Au layer with a thickness of about 0.05 μm formed on a Ni layer with a thickness of about 5 μm.

[0057] Next, an example of a method for manufacturing the solid-state imaging element 100 will be described. Fig. 8 is a flowchart showing a method for manufacturing the solid-state imaging element according to this embodiment. As shown in Fig. 8, in this manufacturing method, first, a semiconductor substrate 5 having a first region 51 having a first conductivity type and a plurality of second regions 52 having a second conductivity type different from the first conductivity type is prepared (step S101: first step).

[0058] Next, by going through processes such as forming metal wiring (e.g., Al wiring) from the second region 52 of the semiconductor substrate 5 to the surface 5s of the semiconductor substrate 5, a plurality of bonding terminals 40 electrically connected to the second region 52 are formed on the surface 5s of the semiconductor substrate 5 (steps S102, S103: second step).

[0059] More specifically, by connecting to a part of the second regions 52 out of the multiple second regions 52 of the semiconductor substrate 5, the first region 51 is connected to the first region 51 by a first path Q1 via a PN junction 53 between the second region 52 and the first region 51, and is also connected to the first region 51 by a second path Q2 via a first resistance Z1 generated in a transistor (e.g., transistors L2, L3) constituting the readout circuit 30, thereby forming the first terminal 41 constituting the readout circuit 30 as the junction terminal 40 (step S102: fourth step).

[0060] On the other hand, the second terminal 42, which is connected to another part of the second regions 52 of the semiconductor substrate 5, is connected to the first region 51 by a third path Q3 via a PN junction 53 between the second region 52 and the first region 51, and is connected to a constant potential by a fourth path Q4 not via the first resistor Z1, and constitutes a part different from the readout circuit 30, is formed as the junction terminal 40 (step S103: fifth step). Here, the fourth path Q4 not via the first resistor Z1 is a path via the second resistor Z2, which is, for example, a polysilicon resistor. That is, in step S103, the second resistor Z2 is formed so as to be interposed in the fourth path Q4 between the second terminal 42 and the first region 51.

[0061] The order of steps S102 and S103 is not limited. At this time, the gate terminal 45 can be formed on the surface 5s of the semiconductor substrate 5 by a similar method. Furthermore, at this point, the external load resistor Zr shown in FIG. 5 is not connected.

[0062] Next, a plating layer 46 made of, for example, Ni / Al is formed on the surface of each of the bonding terminals 40 (for example, the Al surface of the metal wiring) by, for example, UBM processing (step S104: third step). Similarly, the plating layer 46 can also be formed on the surface of the gate terminal 45. In this manner, the solid-state imaging element 100 is obtained.

[0063] As described above, the solid-state imaging element 100 according to this embodiment includes a plurality of junction terminals 40 connected to the second region 52 of the second conductivity type in the semiconductor substrate 5. The plurality of junction terminals 40 include a first terminal 41 constituting the readout circuit 30 and a second terminal 42 not constituting the readout circuit 30. The first terminal 41 constituting the readout circuit 30 is connected to the first region 51 of the semiconductor substrate 5 (i.e., a constant potential of the first region 51) by a first path Q1 via a PN junction 53 formed in the semiconductor substrate 5, and is further connected to the first region 51 by a second path Q2 via a first resistance Z1 generated in a transistor (e.g., transistors L2 and L3) of the readout circuit 30.

[0064] Therefore, as described above, in the first terminal 41, the potential is stabilized when the plating layer 46 is formed. Furthermore, the second terminal 42, which does not constitute the readout circuit 30, is connected to the first region 51 by a third path Q3 via a PN junction 53 formed in the semiconductor substrate 5, and is also connected to the first region 51 by a fourth path Q4 via a second resistor Z2. Therefore, in the second terminal 42, the potential is stabilized when the plating layer 46 is formed. Therefore, in the solid-state imaging device 100, defective formation of the connection portion (solder bump B in this embodiment) in the joining terminal 40 is suppressed.

[0065] In the solid-state imaging device 100 according to the present embodiment, the second resistor Z2 may be made of a polysilicon resistor. In this case, it is possible to easily form a connection to a constant potential via the second resistor Z2 having a suitable resistance value.

[0066] In the solid-state imaging element 100 according to the present embodiment, the resistance value of the second resistor Z2 may be 1 kΩ or more and 100 kΩ or less. In this case, it is possible to preferably stabilize the potential at the first terminal 41 and the second terminal 42 when the plating layer 46 is formed, and it is also possible to suppress instability of the operation caused by a low resistance value between the second terminal 42 and the first region 51.

[0067] In the solid-state imaging device 100 according to the present embodiment, the second terminal 42 may include at least one (in the present embodiment, all) of a reset drain terminal (terminal RD), a scupper drain terminal (terminal SD), and an overflow drain terminal (terminal OFD). In this manner, various terminals may be used as the second terminal 42.

[0068] In addition, in the solid-state imaging device 100 according to the present embodiment, the bonding terminal 40 is connected to the external terminal by bump bonding. In this way, when the bonding terminal 40 is connected to the external terminal by bump bonding, it is more effective to suppress defective formation of the connection portion than when the bonding terminal 40 is connected to the external terminal by wire bonding, for example. More specifically, while wire bonding may allow re-strike (re-forming of the connection portion) at another location in the same pad (plating layer 46) where Ni is not precipitated, such re-strike is not possible with bump bonding. For this reason, when the bonding terminal 40 is connected to the external terminal by bump bonding, it is more effective to suppress defective formation of the connection portion.

[0069] Moreover, in the solid-state imaging element 100 according to this embodiment, the joining terminal 40 includes a plurality of second terminals 42. Therefore, in the joining terminal 40 including the plurality of second terminals 42, defective formation of the connection portion is suppressed.

[0070] Furthermore, in the solid-state imaging element 100 according to the present embodiment, each of the second terminals 42 may be connected to the first region 51 by a fourth path Q4 different from each other. In this manner, the second terminals 42 do not need to share the fourth path Q4 to the first region 51.

[0071] In the solid-state imaging device 100 according to the present embodiment, the second resistors Z2 disposed in the different fourth paths Q4 may have different resistance values. In this case, it is possible to set an appropriate resistance value of the second resistor Z2 for the second terminals 42 having different allowable current values.

[0072] Furthermore, in the solid-state imaging device 100 according to the present embodiment, the wiring portion of the third path Q3 from the second terminal 42 to the PN junction 53 may be made of only metal wiring. In this manner, it is not necessary to interpose a resistive element in the wiring portion between the second terminal 42 and the PN junction 53.

[0073] In addition, in the solid-state imaging element 100 according to the present embodiment, the thickness of the first region 51 is greater than the thickness of the second region 52. As a result, the potential of the first region 51 tends to be stable, and therefore it is possible to reliably prevent defective formation of the connection portion.

[0074] Furthermore, in the solid-state imaging element 100 according to this embodiment, the semiconductor substrate 5 has the first conductivity type and further has a third region (fourth region 57) having an impurity concentration higher than the impurity concentration of the first region 51, and the first terminal 41 is connected to the first region 51 through the fourth region 57 in the second path Q2. This makes it possible to connect the first terminal 41 and the semiconductor region with lower resistance.

[0075] Here, the manufacturing method of the solid-state imaging device 100 according to the present embodiment includes steps S102 and 103 of forming a plurality of junction terminals 40 connected to the second region 52 of the second conductivity type in the semiconductor substrate 5. More specifically, the manufacturing method includes step 102 of forming a first terminal 41 constituting the readout circuit 30, and step S103 of forming a second terminal 42 not constituting the readout circuit 30. In step S102, the first terminal 41 constituting the readout circuit 30 is formed so as to be connected to the first region 51 by a first path Q1 via a PN junction 53 formed in the semiconductor substrate 5, and further connected to the first region 51 by a second path Q2 via a first resistance Z1 generated in a transistor (e.g., transistors L2 and L3) of the readout circuit 30. Therefore, as described above, in the first terminal 41, the potential is stabilized when the plating layer 46 is formed in step S104.

[0076] Furthermore, in step S103, the second terminal 42 not constituting the readout circuit 30 is formed so as to be connected to the first region 51 by a third path Q3 via a PN junction 53 formed in the semiconductor substrate 5, and is also formed so as to be connected to the first region 51 by a fourth path Q4 separately. Thus, even in the second terminal 42, the potential is stabilized when the plating layer 46 is formed in step S104. Therefore, in the manufacturing method for the solid-state imaging element 100, defective formation of the connection portion (solder bump B in this embodiment) in the joining terminal 40 is suppressed.

[0077] In the manufacturing method of the solid-state imaging device 100 according to the present embodiment, in step S103, the second resistor Z2 is formed so as to be interposed in the fourth path Q4 between the second terminal 42 and the first region 51. In this manner, by interposing an appropriate second resistor Z2 between the second terminal 42 and the first region 51, it is possible to appropriately stabilize the potential during the formation of the plating layer 46 while suppressing instability in operation.

[0078] The above embodiment has been described as an embodiment according to one aspect of the present invention. Therefore, the present invention is not limited to the above embodiment and can be modified as desired. Next, modified examples will be described.

[0079] Fig. 9 is a flowchart showing a method for manufacturing a solid-state imaging device according to a modified example. Fig. 10 is a schematic circuit diagram showing each step shown in Fig. 9. As shown in Fig. 9, in the method according to this modified example, steps S101 and S102 are performed in the same manner as in the method according to the above embodiment. On the other hand, in the method according to this modified example, in step S103, the second terminal 42 and the first region 51 are directly connected by a fourth path Q4 made of a metal wiring W1 as a fourth path Q4 that does not pass through the first resistor Z1 (see (a) of Fig. 10).

[0080] Then, after forming the plating layer 46 in step S104 in the same manner as in the method according to the above embodiment, the fourth path Q4 is cut between the second terminal 42 and the first region 51 (step S105: sixth step). In step S105, after the plating layer 46 is formed, the metal wiring W1 is cut by, for example, laser irradiation, and an insulating portion W0 is formed in the fourth path Q4, thereby cutting the fourth path Q4.

[0081] In this way, by connecting the second terminal 42 and the constant potential via the metal wiring W1 (fourth path Q4) when forming the plating layer 46 in step S104, and then disconnecting the fourth path Q4, it is possible to preferably stabilize the potential when forming the plating layer 46 while suppressing instability in operation.

[0082] Note that step S105 can also be applied to the method according to the above embodiment. That is, in step S103, while the second terminal 42 is connected to a constant potential via the fourth path Q4 through which the second resistor Z2 is interposed, if the second resistor Z2, such as a polysilicon resistor, is not necessary for driving the sensor, step S105 may be applied to cut off the fourth path Q4.

[0083] Here, Fig. 11 is a circuit diagram according to a modified example, and Fig. 12 is a cross-sectional view of a semiconductor substrate corresponding to a portion AR of Fig. 11. As shown in Fig. 11 and Fig. 12, the terminal OD (and the terminal OS) is connected to the terminal Vret via the transistors L2 and L3 (and the transistors L4 and L5), and there are cases where the connection portion 72a with the fourth region 57 in the metal wiring 72 is not provided. The terminal Vret is a terminal for stabilizing the potential of the constant current source configured in the output circuit section.

[0084] In this case, the terminal OD is connected to the second region 52, and is thereby connected to the first region 51 by a first path Q1 via a PN junction 53 between the second region 52 and the first region 51, while, like the terminals RD, SD, and OFD, it does not have a path to the first region 51 via a first resistance Z1 generated in a transistor (e.g., transistors L2 and L3) constituting the readout circuit 30. Therefore, like the terminals RD, SD, and OFD, it is conceivable to form a path other than the first path Q1 connecting to the first region 51 via, for example, a polysilicon resistor or metal wiring in the terminal OD. In this case, after forming a plating layer 46 on the terminal OD, step S105 can be applied to cut off the other path.

[0085] That is, in step S102, when the terminal OD is formed, a connection portion 72a of the metal wiring 72 is provided so that the terminal OD is further connected to the first region 51 by a second path Q2 via a first resistance Z1 generated in a transistor of the readout circuit 30. The connection portion 72a may include, for example, a metal wiring or a polysilicon resistor (resistance Zp in the illustrated example). Then, after the plating layer 46 is formed in step S104, the second path Q2 is cut between the terminal OD and the first region 51 by, for example, cutting the connection portion 72a. That is, the manufacturing method of the solid-state imaging element 100 may include, after step S104, a seventh step of cutting the second path Q2 between the first terminal 41 and the first region 51. This makes it possible to preferably stabilize the potential when the plating layer 46 is formed while suppressing instability in operation.

[0086] Although polysilicon resistors have been exemplified as the second resistor Z2 and resistor Zp above, the second resistor Z2 and resistor Zp are not limited to this and may be diode-connected resistors such as MOS-FETs. [Explanation of symbols]

[0087] 5...semiconductor substrate, 40...junction terminal, 41...first terminal, 42...second terminal, 45...gate terminal, 46...plating layer, 51...first region, 52...second region, 53...PN junction, 100...solid-state imaging element, Z1...first resistor, Z2...second resistor, Q1...first path, Q2...second path, Q3...third path, Q4...fourth path, RD...terminal (reset drain terminal), SD...terminal (scupper drain terminal), OFD...terminal (overflow drain terminal).

Claims

1. a semiconductor substrate having a first region having a first conductivity type and a plurality of second regions having a second conductivity type different from the first conductivity type; a plurality of bonding terminals electrically connected to the second region and each connected to a different external terminal; a gate terminal electrically isolated from the second region; Equipped with The plurality of joining terminals include a first terminal constituting a readout circuit, the first terminal being connected to a part of the second regions among the plurality of second regions, and thereby being connected to the first region by a first path via a PN junction between the second region and the first region, and being connected to the first region by a second path via a first resistance generated in a transistor constituting a readout circuit; a second terminal that is connected to another part of the second regions among the plurality of second regions, and is connected to the first region by a third path via a PN junction between the second region and the first region, and is connected to the first region by another fourth path via a second resistor different from the first resistor, and that constitutes a part different from the readout circuit; Including, Solid-state imaging element.

2. The second resistor is made of a polysilicon resistor. The solid-state imaging device according to claim 1 .

3. The resistance value of the second resistor is 1 kΩ or more and 100 kΩ or less. The solid-state imaging device according to claim 1 .

4. the second terminal includes at least one of a reset drain terminal, a scupper drain terminal, and an overflow drain terminal; The solid-state imaging device according to claim 1 .

5. The joining terminals are connected to the external terminals by bump bonding. The solid-state imaging device according to claim 1 .

6. The joining terminal includes a plurality of the second terminals. The solid-state imaging device according to claim 1 .

7. Each of the second terminals is connected to the first region by a fourth path different from the others. The solid-state imaging device according to claim 6 .

8. the second resistors present in the fourth paths different from each other have resistance values ​​different from each other; The solid-state imaging device according to claim 7 .

9. a wiring portion of the third path from the second terminal to the PN junction is made of only metal wiring; The solid-state imaging device according to claim 1 .

10. The thickness of the first region is greater than the thickness of the second region. The solid-state imaging device according to claim 1 .

11. the semiconductor substrate further includes a third region having the first conductivity type and an impurity concentration higher than an impurity concentration of the first region; The first terminal is connected to the first region through the third region in the second path. The solid-state imaging device according to any one of claims 1 to 10.

12. A first step of preparing a semiconductor substrate having a first region having a first conductivity type and a plurality of second regions having a second conductivity type different from the first conductivity type; a second step of forming a plurality of bonding terminals electrically connected to the second region after the first step; a third step of forming a plating layer on the surfaces of the plurality of joining terminals after the second step; Equipped with The second step comprises: a fourth step of forming, as the junction terminal, a first terminal constituting a readout circuit, the first terminal being connected to a part of the second regions among the plurality of second regions, and thereby being connected to the first region by a first path via a PN junction between the second region and the first region, and being connected to the first region by a second path via a first resistance generated in a transistor constituting a readout circuit; a fifth step of forming, as the junction terminal, a second terminal that is connected to another part of the second regions among the plurality of second regions, and is connected to the first region by a third path via a PN junction between the second region and the first region, and is connected to the first region by a fourth path not via the first resistor, and that constitutes a part different from the readout circuit; Including, A method for manufacturing a solid-state imaging device.

13. In the fifth step, a second resistor is formed between the second terminal and the first region so as to be interposed in the fourth path. The method for manufacturing the solid-state imaging device according to claim 12 .

14. a sixth step of cutting the fourth path between the second terminal and the first region after the third step, The method for manufacturing the solid-state imaging device according to claim 12 .

15. a seventh step of cutting the second path between the first terminal and the first region after the third step; The method for manufacturing the solid-state imaging device according to any one of claims 12 to 14.

Images