Flyback power supply device, and switching control circuit

Abstract

To provide a downsized flyback power supply device, and to provide a switching control circuit thereof.SOLUTION: An off time control circuit 5 outputs a turn-on signal SON1 for controlling an off time of a transistor MN1 in such a manner that a feedback voltage Vfb in accordance with an output voltage VOUT becomes constant. A timing control circuit 10 outputs to the transistor MN1 a delayed turn-on signal SON2 in timing when a current flowing through a primary winding L1 becomes 0, m times out of n cycles, after outputting the turn-on signal SON1; and outputs the turn-on signal SON1 to the transistor MN1, (n-m) times out of n cycles.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a flyback power supply device and a switching control circuit. [Background technology]

[0002] A conventional flyback power supply device has been proposed that controls the off time of a transistor connected in series to a primary winding magnetically coupled to a transformer so as to keep the output voltage constant, and sets the on time of the transistor so that the peak current of the primary winding is equal to or less than a threshold (for example, Patent Document 1). By keeping the peak current flowing through the primary winding equal to or less than a threshold as described above, the current flowing through the primary winding can be suppressed, and the transformer can be made smaller.

[0003] However, in the conventional flyback power supply described above, when the input voltage is high, the on-time of the transistor becomes short, making it difficult to accurately control the peak current of the primary winding.

[0004] Therefore, a constant on-time method has been proposed, which fixes the on-time to a preset time, but the constant on-time method may not be able to output sufficient power if the input voltage drops. Therefore, it is also possible to detect the input voltage and control the on-time of the transistor according to the detected input voltage. However, if the input voltage is high, sensing it with a voltage dividing resistor requires the use of multiple high-voltage resistors, which may increase the size of the power supply module. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 9-131057 Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention has been made in consideration of the above-mentioned circumstances, and an object of the present invention is to provide a flyback power supply device and a switching control circuit that are miniaturized. [Means for solving the problem]

[0007] In order to achieve the above-mentioned object, a flyback power supply device and a switching control circuit according to the present invention are characterized by the following [1] to [6]. [1] a transformer having a primary winding and a secondary winding magnetically coupled to each other; a first switch element that turns on and off an input voltage supplied to the primary winding; a switching control circuit that controls the on / off of the first switch element to control an output voltage that is output from the secondary winding side and is obtained by stepping up or stepping down the input voltage. 1. A flyback power supply comprising: an auxiliary winding is magnetically coupled to the transformer, the auxiliary winding inducing a voltage of the same polarity as the induced voltage of the secondary winding; an off-time control circuit that sets an off-time of the first switch element based on a feedback voltage corresponding to the output voltage, and outputs a first turn-on signal that turns on the first switch element at a timing when the set off-time has elapsed since the first switch element was turned off; a timing control circuit that outputs a second turn-on signal to turn on the first switch element at a timing when the current flowing through the primary winding becomes zero after the first turn-on signal is output; a current-flow time determination circuit that measures a current-flow time of the auxiliary winding while the first switch element is in an OFF period based on an induced voltage of the auxiliary winding, and determines whether the measured current-flow time is within a predetermined time width, is equal to or smaller than a lower limit of the time width, or is equal to or larger than an upper limit of the time width; a determination result holding circuit that holds the determination result output from the energization time determination circuit during the OFF period of the first switch element until the determination result is output next from the energization time determination circuit; an on-time switching circuit that switches an on-time of the first switch element in a stepwise manner based on the determination result held by the determination result holding circuit, the on-time switching circuit increases the on-time of the first switch element by one step when the current flow time is equal to or less than the lower limit of the time width, decreases the on-time of the first switch element by one step when the current flow time is equal to or more than the upper limit of the time width, and does not change the on-time of the first switch element when the current flow time is within the time width. It is a flyback power supply. [2] In the flyback power supply device according to [1], The timing control circuit determines that the current flowing through the primary winding has become zero when the induced voltage of the auxiliary winding is equal to or lower than a threshold value. It is a flyback power supply. [3] In the flyback power supply device according to [1], the timing control circuit performs a first control of turning on the first switch element in response to the output of the second turn-on signal m times (m is an integer equal to or greater than 1) out of n periods (n is an integer equal to or greater than 2) of a switching period, turning on the first switch element in response to the output of the first turn-on signal (nm) times, and outputting only the determination result determined by the current-flow time determination circuit during the off period after turning on the first switch element in response to the output of the second turn-on signal to the determination result holding circuit; It is a flyback power supply. [4] In the flyback power supply device according to [3], the switching control circuit performs the first control when the switching period is less than a certain period, and performs a second control to turn on the first switch element in response to the output of the first turn-on signal for each switching period when the switching period is equal to or greater than the certain period, and to output the determination result determined by the current application time determination circuit to the determination result holding circuit for each switching period. It is a flyback power supply. [5] In the flyback power supply device according to [3], the switching control circuit performs the first control when the induced voltage of the auxiliary winding is outside a predetermined range centered around 0, and performs a second control to turn on the first switch element in response to the output of the first turn-on signal in each switching cycle when the induced voltage of the auxiliary winding is within the predetermined range for a certain period of time or more, and to output the determination result determined by the current application time determination circuit in each switching cycle to the determination result holding circuit. It is a flyback power supply. [6] A switching control circuit for controlling a first switch element that turns on and off an input voltage supplied to a primary winding of a transformer included in a flyback power supply device, and for controlling an output voltage output from a secondary winding side of the transformer, an auxiliary winding is magnetically coupled to the transformer, the auxiliary winding inducing a voltage of the same polarity as the induced voltage of the secondary winding; an off-time control circuit that sets an off-time of the first switch element based on a feedback voltage corresponding to the output voltage, and outputs a first turn-on signal that turns on the first switch element at a timing when the set off-time has elapsed since the first switch element was turned off; a timing control circuit that outputs a second turn-on signal to turn on the first switch element at a timing when the current flowing through the primary winding becomes zero after the first turn-on signal is output; a current-flow time determination circuit that measures a current-flow time of the auxiliary winding while the first switch element is in an OFF period based on an induced voltage of the auxiliary winding, and determines whether the measured current-flow time is within a predetermined time width, is equal to or smaller than a lower limit of the time width, or is equal to or larger than an upper limit of the time width; a determination result holding circuit that holds the determination result output from the energization time determination circuit during the OFF period of the first switch element until the determination result is output next from the energization time determination circuit; an on-time switching circuit that switches an on-time of the first switch element in a stepwise manner based on the determination result held by the determination result holding circuit, the on-time switching circuit increases the on-time of the first switch element by one step when the current flow time is equal to or less than the lower limit of the time width, decreases the on-time of the first switch element by one step when the current flow time is equal to or more than the upper limit of the time width, and does not change the on-time of the first switch element when the current flow time is within the time width. It is a switching control circuit. Effect of the Invention

[0008] According to the present invention, it is possible to provide a flyback power supply device and a switching control circuit that are miniaturized.

[0009] The present invention has been briefly described above. Furthermore, the details of the present invention will be further clarified by reading the following description of the preferred embodiment of the present invention (hereinafter, referred to as "embodiment") with reference to the accompanying drawings. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a circuit diagram showing a flyback converter as a flyback power supply device according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a time chart of each part of the flyback converter shown in FIG. 1 when the switching period is long. [Diagram 3] FIG. 3 is a timing chart of each part of a flyback converter that has a short switching period and does not have a timing control circuit. [Figure 4] FIG. 4 is a time chart of each part of the flyback converter shown in FIG. 1 when the switching period is short. [Diagram 5] FIG. 5 is a circuit diagram showing details of the energization time determination circuit shown in FIG. [Figure 6]FIG. 6 is a time chart of the voltage VCDCT across the capacitor CDCT, the output of the comparator Cp2, the output of the comparator Cp3, and the output of the NAND circuit. [Figure 7] FIG. 7 is a circuit diagram showing details of the determination result holding circuit, the on-time switching circuit, and the driver circuit shown in FIG. [Figure 8] FIG. 8 is a circuit diagram showing details of the timing control circuit shown in FIG. [Figure 9] FIG. 9 is a graph showing the relationship between the input voltage, the on-time, and the peak current. [Figure 10] FIG. 10 is a circuit diagram showing details of the current source shown in FIG. 5 used in the second embodiment. [Figure 11] FIG. 11 is a circuit diagram showing a flyback converter as a flyback power supply device according to the third embodiment of the present invention. [Figure 12] FIG. 12 is a circuit diagram showing details of the voltage determination circuit shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Specific embodiments of the present invention will be described below with reference to the accompanying drawings.

[0012] (First embodiment) First, a flyback converter 1 as a flyback power supply device in the first embodiment will be described. As shown in FIG. 1, the flyback converter 1 receives an input voltage V IN The transformer TR steps up or steps down the DC output voltage V OUT The output is as follows:

[0013] The flyback converter 1 includes a transformer TR in which a primary winding L1, a secondary winding L2, and an auxiliary winding L3 are electromagnetically coupled, and an input voltage V INa transistor MN1 as a first switch element for turning on and off the transistor MN1; a sense resistor Rs connected between the transistor MN1 and ground; a diode D for rectifying the current flowing through the secondary winding L2; and a smoothing output capacitor C OUT and a switching control circuit 2 that controls the on / off state of the transistor MN1.

[0014] The primary winding L1, the secondary winding L2, and the auxiliary winding L3 are wound around the core of the transformer TR. The primary winding L1 and the secondary winding L2 are wound around the core so that they have opposite polarities. The secondary winding L2 and the auxiliary winding L3 are wound around the core so that they have the same polarity. The primary winding L1 is connected to the input voltage V IN The transistor MN1 is connected between the positive electrode of a DC power supply 3 that outputs a voltage Vcc and the drain of the transistor MN1. The transistor MN1 is composed of an Nch field effect transistor. The drain of the transistor MN1 is connected to the primary winding L1, and the source is connected to a sense resistor Rs. The sense resistor Rs is connected between the source of the transistor MN1 and ground.

[0015] One end of the secondary winding L2 is connected to the anode of the diode D. The diode D is connected between one end of the secondary winding L2 and the output capacitor C OUT The output capacitor C OUT The other end of the auxiliary winding L3 is connected between the ground and the voltage detection resistors Rfb1 and Rfb2.

[0016] In this embodiment, for the sake of simplicity, the number of turns of the secondary winding L2 is set to be the same as that of the auxiliary winding L3, so that the same voltage as that generated across the secondary winding L2 is generated across the auxiliary winding L3.

[0017] Next, before describing the switching control circuit 2, the basic operation of the flyback converter 1 will be described with reference to Fig. 2. As shown in the figure, when the gate voltage Vg of the transistor MN1 becomes H level and the transistor MN1 is turned on, the input voltage V INis supplied to the primary winding L1, and a current I1 flows through the primary winding L1. This current I1 stores magnetic energy in the core of the transformer TR. At this time, the output capacitor C OUT is discharged by the load 4 (see Figure 1).

[0018] The current I1 flowing through the primary winding L1 increases according to the time that has elapsed since the transistor MN1 was turned on, and reaches its peak around the time the transistor MN1 is switched off. Also, while a current is flowing through the primary winding L1, an induced electromotive force is generated in the secondary winding L2, but this is blocked by the diode D, so no current flows through the secondary winding L2 and no energy flows out of the transformer TR. While a current is flowing through the primary winding L1, an induced electromotive force is also generated in the auxiliary winding L3, and the induced voltage V3 of the auxiliary winding L3 becomes negative. Note that since the resistance values ​​of the voltage detection resistors Rfb1 and Rfb2 are set to large values, almost no current flows through the auxiliary winding L3 even if an induced electromotive force is generated, and almost no energy flows out of the transformer TR.

[0019] Next, when the gate voltage Vg becomes L level and the transistor MN1 is turned off, the magnetic energy stored in the core of the transformer TR flows as a current through the secondary winding L2 and the diode D to the output capacitor C OUT The output is then connected to the output capacitor C OUT is charged. Because the resistance values ​​of the voltage detection resistors Rfb1 and Rfb2 are set to large values, the current flowing through the voltage detection resistors Rfb1 and Rfb2 is negligibly small compared to the current flowing through the load 4. Therefore, most of the magnetic energy stored in the core of the transformer TR is consumed as the current flowing through the secondary winding L2.

[0020] The current I2 flowing through the secondary winding L2 decreases according to the time that has elapsed since transistor MN1 was turned off, and when the magnetic energy stored in the core becomes zero, the current also becomes zero. While a current flows through the secondary winding L2, a voltage similar to that of the secondary winding L2 is generated in the auxiliary winding L3, so the induced voltage V3 in the auxiliary winding L3 becomes a positive voltage. When the current flowing through the secondary winding L2 becomes zero, the induced voltage V3 in the auxiliary winding L3 becomes negative once and then converges to zero.

[0021] Next, the transistor MN1 is turned on again, and this process is repeated. In other words, the current output from the secondary winding L2 flows through the output capacitor C OUT The DC output voltage V OUT will be output as:

[0022] Next, the switching control circuit 2 will be described in detail. The switching control circuit 2 controls the output voltage V OUT 1, the switching control circuit 2 includes voltage detection resistors Rfb1 and Rfb2, an off-time control circuit 5, a conduction time determination circuit 6, a determination result holding circuit 7, an on-time switching circuit 8, a driver circuit 9, and a timing control circuit 10.

[0023] The voltage detection resistors Rfb1 and Rfb2 are connected in series between the auxiliary winding L3 and ground, and a feedback voltage Vfb obtained by dividing the induced voltage V3 of the auxiliary winding L3 is output from the connection point of the voltage detection resistors Rfb1 and Rfb2.

[0024] The off-time control circuit 5 controls the output voltage V OUT The off-time control circuit 5 sets the off-time of the transistor MN1 (the time from off to on) so that the off-time becomes the target value. The off-time control circuit 5 outputs a turn-on signal S as a first turn-on signal that turns on the transistor MN1 when the set off-time has elapsed since the transistor MN1 was turned off. ON1 to the timing control circuit 10. The induced voltage V3 in the auxiliary winding L3 while the current I2 flows in the secondary winding L2 is equal to the output voltage V OUT In this embodiment, the feedback voltage Vfb is supplied to the off-time control circuit 5, and the off-time control circuit 5 sets the off-time so that the feedback voltage Vfb during the time when the current I2 flows through the secondary winding L2 becomes a target value, and controls the output voltage V OUT is controlled to a constant target value.

[0025] The power supply time determination circuit 6, the determination result holding circuit 7, and the ON time switching circuit 8 are connected to the input voltage V IN The turn-off signal S gradually increases the on-time (the time from on to off) of the transistor MN1 as OFF to the driver circuit 9 to suppress the shortage of output power. IN Instead of detecting the input voltage V IN The point is that the current flow time T2 (see FIG. 2) of the secondary winding L2, which is proportional to the induced voltage V3 of the auxiliary winding L3, is measured based on the induced voltage V3 of the auxiliary winding L3.

[0026] As shown in the following equation (1), the peak current I PK and the input voltage V IN In addition, as shown in the following equation (2), the peak current I PK The relationship between the input voltage V and the energization time T2 during which the induced voltage V3 of the auxiliary winding L3 becomes positive is also proportional. IN It is seen that there is a proportional relationship with

[0027]

number

[0028] T ON : ON time of transistor MN1 L1: Inductance of the primary winding L1

[0029]

number

[0030] L2: Inductance of the secondary winding L2 and auxiliary winding L3

[0031] The current flow time determination circuit 6 determines whether the current flow time T2 of the auxiliary winding L3, measured based on the induced voltage V3 of the auxiliary winding L3 while the transistor MN1 is off, is within a predetermined time width, is equal to or smaller than a lower limit value of the time width, or is equal to or larger than an upper limit value of the time width, and outputs the determination result.

[0032] The judgment result holding circuit 7 is a circuit that holds the judgment result output by the current flow time judgment circuit 6 during the off period of transistor MN1 until the next judgment result is output from the current flow time judgment circuit 6, and switches the on time of the on time switching circuit 8 in accordance with the judgment result.

[0033] The on-time switching circuit 8 switches the on-time stepwise based on the judgment result held by the judgment result holding circuit 7, and outputs a turn-off signal S OFF to the driver circuit 9. The driver circuit 9 receives a turn-on signal S ON The transistor MN1 is switched from off to on in response to the output of the ON time switching circuit 8, and the turn-off signal S OFF This is a circuit that outputs a gate voltage Vg to the gate of transistor MN1, which switches transistor MN1 from on to off in response to the output of

[0034] Incidentally, as shown in Figure 2, after the current-flow time T2 ends, the current I1 flowing through the primary winding L1 is a current resonating with the primary winding L1 and the parasitic capacitance between the source and drain of the transistor MN1. For this reason, as shown in Figure 2, if the switching period of the transistor MN1 is long and the transistor MN1 turns on after the resonance has subsided and the current I1 in the primary winding L1 has become zero, there is no problem. However, as shown in Figure 3, if the switching period of the transistor MN1 is short and the transistor MN1 turns on before the current I1 in the primary winding L1 has converged to zero, the current I1 flows through the primary winding L1 with ΔIpk superimposed on it. In other words, the peak current I PK is expressed by the following formula (3). Therefore, the next current application time T2 is precisely determined based on the input voltage V IN Since the on-time is no longer proportional to the on-time, it is not possible to control the on-time with high precision.

[0035]

number

[0036] Therefore, in this embodiment, a timing control circuit 10 is provided. As shown in Fig. 4, when the switching period is short, the timing control circuit 10 (Fig. 8, details will be described later) outputs the turn-on signal S once (=m times: m is an integer of 1 or more) in every four switching periods (=n periods: n is an integer of 2 or more). ON1 After the current I1 flowing through the primary winding L1 becomes zero, the delayed turn-on signal S ON2 Turn-on signal S ON to the driver circuit 9. The delayed turn-on signal S ON2 is the turn-on signal S ON1 is output with a delay of the time (delay time Td) from when the induced voltage V3 of the auxiliary winding L3 is output until the current I1 flowing through the primary winding L1 becomes 0. In this embodiment, the timing control circuit 10 regards the current I1 flowing through the primary winding L1 as being 0 or nearly 0 when the induced voltage V3 of the auxiliary winding L3 becomes equal to or lower than a threshold value Vth3.

[0037] In addition, the timing control circuit 10 outputs the turn-on signal S output from the off-time control circuit 5 three times (=mn) out of every four switching periods. ON1 Turn-on signal S ON The timing control circuit 10 outputs the delayed turn-on signal S ON2 Turn-on signal S ON The timing control circuit 10 outputs only the determination result determined by the energization time determination circuit 6 during the OFF period after outputting the turn-on signal S to the driver circuit 9 as the turn-on signal S. ON1 Turn-on signal S ON The result of the determination made by the energization time determination circuit 6 during the off period after the output to the transistor MN1 as the power supply voltage Vpp is not output to the determination result holding circuit 7.

[0038] Next, the energization time determination circuit 6 will be described in detail with reference to Fig. 5. The energization time determination circuit 6 includes a comparator Cp1 as a first comparator, and a one-shot pulse circuit 61. The inverting input of the comparator Cp1 is connected to the connection point of the voltage detection resistors Rfb1 and Rfb2, and receives the feedback voltage Vfb. The non-inverting input of the comparator Cp1 is connected to the ground. The comparator Cp1 outputs a Lo level while the feedback voltage Vfb is higher than the ground and is a positive voltage, and outputs a Hi level while the feedback voltage Vfb is lower than the ground and is a negative voltage.

[0039] As shown in FIG. 5, the current supply time determination circuit 6 includes a current source 62 and a capacitor C DCT and capacitor C DCT The input terminal includes a transistor MN2 for discharging the input terminal Vp2, two comparators Cp2 and Cp3 serving as second and third comparators, and a NAND circuit 63 and an AND circuit 64 serving as logic circuits.

[0040] Current source 62 and capacitor C DCT and are connected in series with each other, and a current I DCT This causes the capacitor C DCT The transistor MN2 is composed of an Nch field effect transistor. The transistor MN2 is connected to the capacitor C DCT In more detail, the drain of the transistor MN2 is connected in parallel to the capacitor C DCT and the current source 62, and its source is connected to the ground. The gate of the transistor MN2 is connected to the gate of the transistor MN1 and is supplied with a gate voltage Vg.

[0041] According to the above configuration, when the transistor MN1 is turned off, the transistor MN2 is turned off and the capacitor C DCT is the current I DCT When the transistor MN1 turns on, the transistor MN2 turns on and the capacitor C DCT is discharged.

[0042] The non-inverting input of the comparator Cp2 is connected to the capacitor C DCT and the current source 62 are connected, and the capacitor C DCT The voltage V CDCT The inverting input of comparator Cp2 is connected to the lower limit voltage V TLDCT As shown in Figure 6, the lower limit voltage V TLDCT is the lower limit T of the predetermined time span. 2MIN Only the capacitor C DCT current I DCT When charging with CDCT In this embodiment, as shown in FIG. TLDCT is the voltage V output from the DC power supply 65 RDCT Resistance R CDT1 ,R CDT2 It can be obtained by dividing the pressure by

[0043] The inverting input of the comparator Cp3 is connected to a capacitor C DCT and the current source 62 are connected, and the capacitor C DCT The voltage V CDCT The non-inverting input of comparator Cp3 is connected to the upper limit voltage V THDCT As shown in Figure 6, the upper limit voltage V THDCT is the upper limit T of the time span 2MAX Only the capacitor C DCT current I DCT When charging with CDCT In this embodiment, as shown in FIG. THDCT is the voltage V output from the DC power supply 65 RDCT (i.e., V THDCT =V RDCT ).

[0044] The outputs of the comparators Cp2 and Cp3 are respectively connected to two inputs of the NAND circuit 63. The output of the NAND circuit 63 and the output of the one-shot pulse circuit 61 are respectively connected to two inputs of the AND circuit 64.

[0045] According to the above configuration, as shown in FIGS. 5 and 6, the time elapsed since the transistors MN1 and MN2 are turned off reaches the lower limit T 2MIN When the time elapsed since the transistors MN1 and MN2 are turned off reaches the upper limit T 2MAX When the time elapsed since the transistors MN1 and MN2 are turned off reaches the lower limit T 2MIN The level is Hi for the time below, and Lo for the time within a predefined time range. 2MAX Above this level it becomes Hi level.

[0046] Therefore, when the energization time T2 of the auxiliary winding L3 is within a predetermined time width, the one-shot pulse P1 is output while the output of the NAND circuit 63 is at a Lo level, and the AND circuit 64 outputs a Hi-level trigger signal S TRIG On the other hand, the current supply time T2 of the auxiliary winding L3 is lower than the lower limit T 2MIN Below, the upper limit T 2MAX In the above case, the one-shot pulse P1 is output while the output of the NAND circuit 63 is at Hi level. Therefore, the AND circuit 64 outputs a Hi-level trigger signal S TRIG will be output.

[0047] In addition, the current application time T2 is the lower limit T 2MIN In the following cases, the trigger signal S TRIG When the comparator Cp2 outputs the up / down signal S UP / DOWN becomes Lo level. When the current supply time T2 exceeds the upper limit T 2MAX In the above cases, the trigger signal S TRIG When the comparator Cp2 outputs the up / down signal S UP / DOWN is the Hi level.

[0048] Next, the determination result holding circuit 7 will be described with reference to Fig. 7. The determination result holding circuit 7 includes an up / down counter 71. The up / down counter 71 receives a trigger signal S TRIG When is output, the up / down signal S UP / DOWN When the trigger signal S is at Lo level, the up / down counter 71 counts down the count value by one bit. TRIG When is output, the up / down signal S UP / DOWN When the count is at Hi level, the count value is increased by one bit.

[0049] Next, the on-time switching circuit 8 will be described with reference to Fig. 7. The on-time switching circuit 8 includes a current mirror circuit 81 and a capacitor C TON , a transistor MN3, a NOT circuit 82, and a comparator Cp4 serving as a fourth comparator.

[0050] The current mirror circuit 81 can switch the output current in stages according to the count value from the up / down counter 71. The current mirror circuit 81 includes a transistor MP1 as a first transistor, transistors MP21 to MP2N as second transistors, and a resistor R MINON The amplifier Amp1 and switches S1 to SN serving as second switching elements.

[0051] The transistors MP1, MP21 to MP2N are each composed of a Pch field effect transistor. The source of the transistor MP1 is connected to the positive electrode of the DC power supply, and the drain is connected to the resistor R MINON The non-inverting input of the amplifier Amp1 is connected to the ground through the transistor MP1 and the resistor R MINON The inverting input of the amplifier Amp1 is connected to a DC power supply 84, and the voltage V RION Transistor MP1 is supplied with a voltage V RION , resistance RMINON Current I according to MIN When the switching control circuit 2 is composed of an IC chip, a resistor R MINON By using an external resistor, the resistance R can be adjusted to match the specifications of the transformer TR. MINON The on-time can be set by changing the resistance value of

[0052] The sources of the transistors MP21 to MP2N are connected to the positive electrode of the DC power supply, and the drains are connected to the capacitors C TON The gates of the transistors MP21 to MP2N are connected to the gate of the transistor MP1. The transistors MP21 to MP2N each have a current I MIN Fold it back to make capacitor C TON Therefore, by controlling the on / off of the switches S1 to SN, the current is supplied from the current mirror circuit 81 to the capacitor C TON The currents of the transistors MP21 to MP2N are determined according to the ratio of the gate width of the transistor MP1 to that of the transistor MP21. For example, when the ratio of the gate width of the transistor MP1 to that of the transistor MP21 is m 21 If so, the current flowing through the transistor MP21 is current I MIN ×m 21 It is possible to obtain a desired output current by setting the gate width.

[0053] Capacitor C TON is connected between the current mirror circuit 81 and the ground. The transistor MN3 is an Nch field effect transistor. The drain of the transistor MN3 is connected to the capacitor C TON and a current mirror circuit 81, and its source is connected to the ground. The gate of transistor MN3 is connected to the gate of transistor MN1 via a NOT circuit 82, and is supplied with an inverted gate voltage Vg.

[0054] The non-inverting input of the comparator Cp4 is connected to a capacitor C TON The junction point between the inverting input of the comparator Cp4 and the current mirror circuit 81 is connected. A DC power supply 83 is connected to the inverting input of the comparator Cp4, and a voltage V RCTON is supplied.

[0055] According to the above configuration, when the transistor MN1 is on, the transistor MN3 is off, and the output current from the current mirror circuit 81 drives the capacitor C TON is charged. Capacitor C TON The voltage across both ends is V RCTON When this limit is exceeded, the comparator Cp4 outputs a high-level turn-off signal S OFF Therefore, as the output current from the current mirror circuit 81 increases, the turn-off signal S OFF When transistor MN1 turns off, transistor MN3 turns on, and capacitor C TON is discharged.

[0056] Next, the driver circuit 9 will be described with reference to Fig. 7. The driver circuit 9 includes a D flip-flop 91 and a buffer circuit 92. A DC power supply 93 is connected to a D terminal of the D flip-flop 91, and a voltage V H The clock terminal CK is connected to the output of the timing control circuit 10 as described above, and a turn-on signal S ON The output of the ON time switching circuit 8 is connected to the reset terminal R, and the turn-off signal S OFF is supplied to the input of the buffer circuit 92. The Q terminal of the D flip-flop 91 is connected to the input of the buffer circuit 92. The output of the buffer circuit 92 is connected to the gate of the transistor MN1.

[0057] Next, the timing control circuit 10 will be described with reference to Fig. 8. The timing control circuit 10 shown in Fig. 8 outputs the delayed turn-on signal S once every four switching periods as described above. ON2 Turn-on signal S ONto the driver circuit 9. The timing control circuit 10 includes a delayed turn-on signal output circuit 11, a NOT circuit 12, a pulse counter 13, a NAND circuit 14, a turn-on signal control circuit 15, an up-down signal control circuit 16, a trigger signal control circuit 17, and a switching period detection circuit 18.

[0058] The delayed turn-on signal output circuit 11 outputs the turn-on signal S ON1 After the output, when it is detected that the feedback voltage Vfb falls below the threshold and the induced voltage V3 of the auxiliary winding L3 remains below the threshold Vth3 for a certain period of time, the delayed turn-on signal S ON2 The NOT circuit 12 receives the gate voltage Vg of the transistor MN1, inverts the gate voltage Vg, and inputs it to a clock terminal CLK of a pulse counter 13, which will be described later.

[0059] As described above, the induced voltage V3 in the auxiliary winding L3 has a waveform that resonates with the parasitic capacitance between the primary winding L1 and the source-drain of the transistor MN1 (see FIG. 2). Even if the induced voltage V3 is equal to or lower than the threshold Vth3 in a period shorter than a half cycle of this resonance, it may exceed the threshold Vth3 in one cycle of the resonance, and there is a possibility that a false detection will occur when the current I1 in the primary winding L1 converges to 0. For this reason, when the induced voltage V3 continues to be equal to or lower than the threshold Vth3 for a certain period of time or more, the delayed turn-on signal S ON2 By outputting the constant time, it is possible to control the on-time with higher accuracy. Note that the constant time is not limited to a half cycle of the resonance, and may be a half cycle of the switching cycle of the transistor MN1.

[0060] The pulse counter 13 counts up every time the inverted gate voltage Vg becomes H level, and outputs the result from output terminals D0 and D1. In this embodiment, the pulse counter 13 has two output terminals D0 and D1 and repeatedly counts from "0" to "3".

[0061] The output terminals D0 and D1 are connected to two inputs of the NAND circuit 14. That is, the NAND circuit 14 outputs an L-level signal every time the count value becomes "3." The turn-on signal control circuit 15 keeps the turn-on signal S low while the NAND circuit 14 is outputting an H-level signal. ON1 Turn-on signal S ON While the NAND circuit 14 is outputting a low-level signal, the turn-on signal control circuit 15 outputs the delayed turn-on signal S ON2 Turn-on signal S ON to the driver circuit 9.

[0062] The up-down signal control circuit 16 has a NOR circuit 161 and an AND circuit 162. The output terminals D0 and D1 are connected to two inputs of the NOR circuit 161. The output of the NOR circuit 161 and the up-down signal S from the energization time determination circuit 6 are UP / DOWN and are connected to two inputs of an AND circuit 162. The output of the AND circuit 162 is connected to the determination result holding circuit 7. That is, the NOR circuit 161 outputs an H-level signal every time the count value of the pulse counter 13 becomes "0". While the NOR circuit 161 outputs an H-level signal, the AND circuit 162 receives the up / down signal S UP / DOWN While the NOR circuit 161 is outputting a low-level signal, the AND circuit 162 outputs the up / down signal S UP / DOWN Do not output.

[0063] The trigger signal control circuit 17 has a NOR circuit 171 and an AND circuit 172. The output terminals D0 and D1 are connected to two inputs of the NOR circuit 171. The output of the NOR circuit 171 and the trigger signal S from the energization time determination circuit 6 are TRIG and are connected to two inputs of an AND circuit 172. The output of the AND circuit 172 is connected to the determination result holding circuit 7. That is, the NOR circuit 171 outputs an H-level signal every time the count value of the pulse counter 13 becomes "0". While the NOR circuit 171 is outputting an H-level signal, the AND circuit 172 holds the trigger signal S TRIGWhile the NOR circuit 171 is outputting a low-level signal, the AND circuit 172 outputs the trigger signal S TRIG Do not output.

[0064] That is, the driver circuit 9 receives a delayed turn-on signal S once every four periods. ON2 is output to the driver circuit 9. The determination result holding circuit 7 also receives a delayed turn-on signal S ON2 The trigger signal S from the current supply time determination circuit 6 is output only at the timing after TRIG and up / down signal S UP / DOWN (=judgment result) is output.

[0065] The switching cycle detection circuit 18 detects the switching cycle of the transistor MN1, and outputs an H level to the reset terminal R of the pulse counter 13 described above if the switching cycle is equal to or longer than a certain period, and outputs an L level to the reset terminal R of the pulse counter 13 described above if the switching cycle is shorter than the certain period. As a result, if the switching cycle is longer than the certain period, both output terminals D0 and D1 become L level, and the timing control circuit 10 generates a trigger signal S every switching cycle. TRIG and up / down signal S UP / DOWN to the determination result holding circuit 7. On the other hand, when the switching period is short and less than a certain period, the timing control circuit 10 outputs the trigger signal S once every four periods. TRIG and up / down signal S UP / DOWN is output to the determination result holding circuit 7.

[0066] Next, the operation of the flyback converter 1 having the above-mentioned configuration will be described. First, the input voltage V IN is high enough, the output voltage V OUT Assume that the input voltage V is controlled to a constant value. IN When the ON time of the transistor MN1 is sufficiently high, all of the switches S1 to SN constituting the ON time switching circuit 8 are turned on and conducting. This causes the ON time of the transistor MN1 to be at its minimum value.

[0067] Next, the input voltage V INWhen the peak current I flows through the secondary winding L2 during the off-period of the transistor MN1, PK decreases, and the current application time T2 becomes the lower limit T 2MIN The current flow time T2 is the lower limit T 2MIN When the current supply to the auxiliary winding L3 is completed, the current supply time determination circuit 6 generates a high-level trigger signal S TRIG At this time, the up / down signal S UP / DOWN becomes Lo level.

[0068] Therefore, the trigger signal S TRIG In response to the output of the up / down counter 71, the up / down counter 71 counts down the count value by one bit. In response to this signal, the on-time switching circuit 8 decreases the number of conductive switches S1 to SN by one. As a result, the output current from the current mirror circuit 81 is incremented by one step (=current I MIN ×m 2N ) decreases, and the turn-off signal S output from the comparator Cp4 OFF The on-time can be increased by lengthening the time until the output switches to the Hi level.

[0069] If the on-time is increased, the peak current I PK Next, when the transistor MN1 turns off, the peak current I PK The current-carrying time T2 of the auxiliary winding L3 also increases by the amount of increase in current. A series of operations is repeated each time the transistor MN1 is turned on until the current-carrying time T2 of the auxiliary winding L3 falls within a predetermined time width.

[0070] When the energization time T2 falls within a predetermined time range, the energization time determination circuit 6 outputs a trigger signal S TRIG is not output. Therefore, the count value of up / down counter 71 is held. In response to this signal, on-time switching circuit 8 holds the number of conductive switches S1 to SN. As a result, the output current from current mirror circuit 81 is held, and the on-time when transistor MN1 is next turned on does not change.

[0071] In addition, after the on-time is increased, the input voltage VIN When the current I returns to a sufficiently high state, the peak current I flows through the secondary winding L2 during the off-period of the transistor MN1. PK increases further, and the current flow time T2 reaches the upper limit T 2MAX The current supply time T2 is the upper limit T 2MAX When the current supply to the auxiliary winding L3 is completed, the current supply time determination circuit 6 generates a high-level trigger signal S TRIG At this time, the up / down signal S UP / DOWN is the Hi level.

[0072] Therefore, the trigger signal S TRIG In response to the output of the up / down counter 71, the up / down counter 71 counts up the count value by one bit. In response to this signal, the on-time switching circuit 8 increases the number of conductive switches S1 to SN by one. As a result, the output current from the current mirror circuit 81 increases by one step (=current I MIN ×m 2N ) increases, and the turn-off signal S OFF This shortens the time it takes for the output to switch to the Hi level, thereby shortening the on-time.

[0073] By shortening the on-time, the peak current I PK Next, when the transistor MN1 turns off, the peak current I PK The current-carrying time T2 of the auxiliary winding L3 is also reduced by the amount of the reduction in current. A series of operations is repeated each time the transistor MN1 is turned on until the current-carrying time T2 of the auxiliary winding L3 falls within a predetermined time width.

[0074] In the above-described current mirror circuit 81, the output current of the current mirror circuit 81 is controlled by increasing / decreasing or maintaining the number of conductive switches S1 to SN, but the present invention is not limited to this circuit, and any configuration may be used that provides an output current of 1 to N steps. For example, the gate widths of the transistors MP21 to MP2N may be set so that the currents of the transistors MP21 to MP2N respectively provide output currents of 1 to N steps, and any one of the switches S1 to SN may be made conductive. By controlling the output current of the current mirror circuit 81 in this manner, as shown in FIG. 9, IN The on-time of transistor MN1 can be adjusted according to the

[0075] The dotted line in Figure 9 indicates the peak current I PK The input voltage V to keep constant IN 1 is a graph showing the relationship between the peak current I PK To keep the input voltage V constant, IN As the input voltage V decreases, the on-time needs to be increased. As shown by the solid line, the flyback converter 1 of this embodiment operates in a manner similar to the ideal dotted line. IN As the on-time decreases, the peak current I PK can also be within a certain range.

[0076] This allows the winding of the transformer TR to be made of thin copper wire, thereby enabling the transformer TR to be miniaturized. IN The ON time is switched in stages according to the current-carrying time T2, which corresponds to the input voltage V IN Even if the input voltage V IN The on-time can be set according to the input voltage V IN This eliminates the need for voltage dividing resistors for detecting the voltage, and allows the flyback converter 1 to be made smaller.

[0077] According to the above-described embodiment, the timing control circuit 10 generates a turn-on signal S ON1 After the output, the delay turn-on signal S ON2 is output to the driver circuit 9. As a result, the transistor MN1 can be turned on in a state in which the error component ΔIpk is reduced, so that the subsequent conduction time T2 is precisely determined based on the input voltage V IN Therefore, the on-time can be controlled with high precision.

[0078] According to the above-described embodiment, the timing control circuit 10 determines that the current flowing through the primary winding L1 becomes 0 when the induced voltage V3 of the auxiliary winding L3 is equal to or lower than the threshold value. As a result, the delayed turn-on signal S ON2 can be output.

[0079] By the way, the output voltage V OUT is inversely proportional to the switching period Ts as shown in the following equation (4). ON2 When the energization time determination circuit 6 outputs the determination result to the determination result holding circuit 7, the switching period becomes a discrete value. In this embodiment, the timing control circuit 10 outputs the delayed turn-on signal S ON2 to the driver circuit 9, and outputs a delayed turn-on signal S ON2 The first control is performed in which only the judgment result judged by the energization time judgment circuit 6 during the OFF period after the input of the power supply voltage V is output to the judgment result holding circuit 7. OUT It is possible to reduce the discreteness of

[0080]

number

[0081] V OUT : Output voltage T ON : ON time of transistor MN1 L1: Inductance of the primary winding L1 I O : Output current Ts: switching period η: Efficiency

[0082] In addition, in the above-mentioned flyback converter 1, the output voltage V OUT When the switching period is long, if the timing control circuit 10 performs the first control in which the ON time is set according to the conduction time T2 only once every four periods, the interval for measuring the conduction time T2 becomes wider, and the input voltage V IN In this embodiment, the timing control circuit 10 does not perform the first control when the switching period is longer than a certain period, and instead, changes the turn-on signal S ON1 to the transistor MN1, and outputs the judgment result judged by the energization time judgment circuit 6 to the judgment result holding circuit 7 for each switching period. As a result, even if the switching period becomes longer, the input voltage V IN In addition, if the switching period is long, as shown in Figure 2, the transistor MN1 can be turned on after the current in the primary winding L1 becomes zero, so the on-time can be controlled with precision.

[0083] Second embodiment In the first embodiment described above, the current source 62 supplies a constant current I DCT However, at start-up, the output voltage V OUT When is low, the peak current I PK Even if the peak current I PK The operation is the same as when the input voltage V is high, and the count value of the up / down counter 71 is decreased to control the ON time to the minimum value. Therefore, the energy transferred from the primary side to the secondary side at start-up is low, and the inverter starts up. IN When V is low, the output voltage OUTThere is a risk that the value will only rise to a certain value and will not reach the target value.

[0084] Therefore, in the second embodiment, a current source 62B shown in Fig. 10 is used instead of the current source 62 (see Fig. 5) in the first embodiment. The current source 62B includes a sample-and-hold (S / H) circuit 621, an amplifier Amp2, and transistors MN5, MP5, and MP6. The S / H circuit 621 samples the feedback voltage Vfb when the transistor MN1 is in an off period and the secondary winding L2 and the auxiliary winding L3 are conducting, and holds the sampled feedback voltage Vfb.

[0085] The non-inverting input of the amplifier Amp2 is connected to the output of the S / H circuit 621. The inverting input of the amplifier Amp2 is connected to the source of the transistor MN5 and the resistor R DCT The connection points of the amplifier Amp2 and the transistor MP5 are connected to each other. The output of the amplifier Amp2 is connected to the gate of the transistor MN5. The transistor MN5 is composed of an Nch field effect transistor. The transistor MN5 is connected in series to the transistor MP5.

[0086] The transistors MP5 and MP6 are configured as Pch field effect transistors. The sources of the transistors MP5 and MP6 are connected to the positive electrode of the DC power supply. The gate and drain of the transistor MP5 are connected together. The gate of the transistor MP6 is connected to the gate and drain of the transistor MP5. The drain of the transistor MP6 is connected to the capacitor C DCT is connected to.

[0087] According to the above configuration, a current corresponding to the feedback voltage Vfb held by the S / H circuit 621 flows through the transistors MN5 and MP5. The transistor MP6 turns back the current flowing through the transistor MP5 to generate a current I DCT As the capacitor C DCT The feedback voltage Vfb held by the S / H circuit 621 is supplied to the output voltage V OUT Therefore, the output voltage V OUTWhen Vfb is low, the sampled and held feedback voltage Vfb is also low, and the current I DCT The current I DCT When decreases, the capacitor C DCT The voltage V CDCT is the upper limit voltage V THDCT , lower limit voltage V TLDCT Therefore, as described above, the decrease in the ON time at the time of startup can be suppressed.

[0088] In the case of the above circuit configuration, the lower limit voltage V TLDCT and peak current I PK The relationship is as shown in the following equation (5).

[0089]

number

[0090] I PKMIN : The current flow time T2 is the lower limit T 2MIN The peak current I PK C DCT : Capacitor C DCT Conductance of R DCT :Resistance R DCT Resistance value of K: Rfb2 / (Rfb1+Rfb2)

[0091] According to equation (5), the resistance R DCT By appropriately setting the value of , the output voltage V OUT The secondary winding L2 current is not affected by the current flow from time T2 to peak current I PK The on-time can be switched by estimating the value of

[0092] Third embodiment Next, a flyback converter 1C according to a third embodiment will be described with reference to Fig. 11. In Fig. 11, the same parts as those in the flyback converter 1 shown in Figs. 1 to 8 already described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0093] A major difference between the first and third embodiments is the configuration of a switching control circuit 2C that controls the on / off of transistor MN1. The switching control circuit 2C of the third embodiment includes a voltage judgment circuit 20 and a switching circuit 21 in addition to an off-time control circuit 5, a current flow determination circuit 6, a determination result holding circuit 7, an on-time switching circuit 8, a driver circuit 9, and a timing control circuit 10.

[0094] The voltage evaluation circuit 20 is connected to the connection point between the source of the transistor MN1 and the sense resistor Rs, and is supplied with the voltage across the sense resistor Rs. The sense resistor Rs is a resistor for detecting the current I1 flowing through the primary winding L1, and the voltage across the sense resistor Rs has a value that corresponds to the current flowing through the primary winding L1. The voltage evaluation circuit 20 samples the voltage across the sense resistor Rs when the transistor MN1 switches from on to off, and holds the sampled voltage across the sense resistor Rs. As is clear from FIG. 2, the held voltage across the sense resistor Rs is a value that corresponds to the peak current I PK The voltage determination circuit 20 determines whether the held voltage between both ends is within a predetermined voltage range or the lower limit voltage V TLPK Is the voltage range upper limit voltage V THPK It is judged whether the value is equal to or greater than the threshold value, and the judgment result is output.

[0095] The switching circuit 21 is a circuit that switches the judgment result to be input to the timing control circuit 10 between the energization time judgment circuit 6 and the voltage judgment circuit 20. The switching circuit 21 is a circuit that switches the judgment result to be input to the timing control circuit 10 between the energization time judgment circuit 6 and the voltage judgment circuit 20. OUT If V is low, the voltage judgment circuit 20 is switched to the output voltage V OUT If the output voltage V OUT The output voltage V is based on a feedback voltage Vfb that is proportional to OUT is judged as being high or low.

[0096] Next, the voltage evaluation circuit 20 will be described in detail with reference to Fig. 12. The voltage evaluation circuit 20 includes a sample-and-hold (S / H) circuit 101, a NOT circuit 102, comparators Cp6 and Cp7, a NAND circuit 103, and an AND circuit 104. The connection point between the source of the transistor MN1 and the sense resistor Rs is connected to the S / H circuit 101, and the voltage across the sense resistor Rs is input to the S / H circuit 101. The S / H circuit 101 is also connected to the gate of the transistor MN1 via the NOT circuit 102, and a signal obtained by inverting the gate voltage Vg of the transistor MN1 is input to the S / H circuit 101 as a sampling signal. The S / H circuit 101 samples the voltage across the sense resistor Rs when the transistor MN1 is turned off, and holds the sampled voltage across the sense resistor Rs.

[0097] The output of the S / H circuit 101 is connected to the non-inverting input of the comparator Cp6 and the inverting input of the comparator Cp7. Therefore, the held voltages are input to the non-inverting input of the comparator Cp6 and the inverting input of the comparator Cp7. The lower limit voltage V TLPK In this embodiment, the lower limit voltage V TLPK is the voltage V output from the DC power supply 105 RDCT2 Resistance R CDT3 ,R CDT4 It can be obtained by dividing the pressure by

[0098] The non-inverting input of the comparator Cp7 is connected to the upper limit voltage V THPK In this embodiment, the upper limit voltage V THPK is the voltage V output from the DC power supply 105 RDCT2 (i.e., V THPK =V RDCT2 ).

[0099] The two inputs of the NAND circuit 103 are connected to the outputs of the comparators Cp6 and Cp7, respectively. The two inputs of the AND circuit 104 are connected to the output of the NAND circuit 103 and the trigger input signal S IN The trigger input signal SIN is a pulse that is at Hi level while the transistor MN1 is off.

[0100] According to the above configuration, when the transistor MN1 is turned off, the voltage across the sense resistor Rs held at the time is equal to or lower than the lower limit voltage V TLPK In the following case, the output of the comparator Cp6 becomes Lo level and the output of the comparator Cp7 becomes Hi level. As a result, the output of the NAND circuit 103 becomes Hi level, and the trigger input signal S IN When the trigger signal S goes high, TRIG will be output.

[0101] When the transistor MN1 is turned off, the voltage across the sense resistor Rs held at the time is the upper limit voltage V THPK In the above case, the output of the comparator Cp6 becomes Hi level, and the output of the comparator Cp7 becomes Lo level. As a result, the output of the NAND circuit 103 becomes Hi level, and the trigger input signal S IN When the trigger signal S goes high, TRIG will be output.

[0102] If the voltage across the sense resistor Rs held at the time when the transistor MN1 is turned off is within a predetermined voltage range, the output of the comparator Cp6 becomes Hi level, and the output of the comparator Cp7 becomes Hi level. As a result, the output of the NAND circuit 103 becomes Lo level, and the trigger input signal S IN Even if the trigger signal S becomes Hi level, TRIG is not output.

[0103] In addition, the voltage across the sense resistor Rs held is the lower limit voltage V TLPK In the following cases, the trigger signal S TRIG When the comparator Cp6 outputs the up / down signal S UP / DOWNThe voltage across the sense resistor Rs held at the low level is the upper limit voltage V THPK In the above cases, the trigger signal S TRIG When the comparator Cp6 outputs the up / down signal S UP / DOWN is the Hi level.

[0104] As described above, the current-flow time determination circuit 6 determines whether the current-flow time T2 of the auxiliary winding L3 is within a predetermined time range based on the induced voltage V3 of the auxiliary winding L3, and outputs the determination result. OUT When the output voltage V is low, the induced voltage V3 of the auxiliary winding L3 is low and the feedback voltage Vfb input to the inverting input of the comparator Cp1 (see Figure 5) is also low, and the conduction time T2 during which the induced voltage V3 is a positive voltage may not be measured correctly. OUT When the current conduction time judgment circuit 6 is used when the output voltage V OUT In the third embodiment described above, the output voltage V OUT is lower, the result is switched to the result determined by the voltage determination circuit 20. PK is the output voltage V OUT Since it is not affected by the output voltage V OUT This can prevent the level from not rising from a low state.

[0105] On the other hand, the voltage determination circuit 20 calculates the voltage across the sense resistor Rs at the timing when the transistor MN1 is turned off as the peak current I PK However, the current I1 flowing through the primary winding L1 actually continues to flow due to parasitic capacitance and the like even after the transistor MN1 is turned off. For this reason, the current I1 flowing through the primary winding L1 may reach its peak a little after the transistor MN1 is turned off. Therefore, in this embodiment, the output voltage V OUT is higher, the judgment result is switched to that of the current-flow time judgment circuit 6, and the peak current I PK and accurately suppresses the input voltage V IN The on-time can be set according to the

[0106] The present invention is not limited to the above-described embodiment, and can be appropriately modified, improved, etc. In addition, the material, shape, size, number, arrangement location, etc. of each component in the above-described embodiment are arbitrary as long as the present invention can be achieved, and are not limited.

[0107] The current flow time determination circuit 6 shown in FIG. 5 described above is one example, and is not limited to this circuit. For example, a configuration may be used in which it is possible to determine whether the current flow time is within a predetermined time width, is equal to or less than a lower limit of the time width, or is equal to or more than an upper limit of the time width, using a timer or the like.

[0108] Moreover, the ON-time switching circuit 8 shown in FIG. 7 is also one example, and the present invention is not limited to this circuit. For example, the ON-time may be switched in stages using a timer or the like.

[0109] In the above-described embodiment, the off-time control circuit 5 inputs a voltage obtained by dividing the induced voltage V3 of the auxiliary winding L3 as the feedback voltage Vfb and controls the off-time so that the feedback voltage Vfb is constant, but this is not limited to the above. The off-time control circuit 5 may input a flyback voltage generated in the primary winding L1 when the transistor MN1 is off as the feedback voltage Vfb.

[0110] In the above embodiment, in the energization time determination circuit 6, the output of the comparator Cp2 is converted into an up-down signal S UP / DOWN However, the present invention is not limited to this. The output of the comparator Cp3 is judged to generate the up / down signal S UP / DOWN It is also possible to use the following.

[0111] In the above embodiment, in the voltage judgment circuit 20, the output of the comparator Cp6 is converted into an up-down signal S UP / DOWN However, the present invention is not limited to this. The output of the comparator Cp7 is judged to generate the up / down signal S UP / DOWN It is also possible to use the following.

[0112] In the above embodiment, the timing control circuit 10 determines that the current flowing through the primary winding L1 is 0 when the induced voltage V3 of the auxiliary winding L3 is equal to or lower than the threshold value, but this is not limited to the above. The timing control circuit 10 may determine that the current flowing through the primary winding L1 is 0 at the timing when the induced voltage V3 reaches a lower peak.

[0113] In the above embodiment, the timing control circuit 10 performs the first control when the switching period is less than a certain period, but the present invention is not limited to this. When the induced voltage V3 of the auxiliary winding L3 is within a predetermined range centered on 0, the timing control circuit 10 outputs the turn-on signal S every switching period. ON1 to the transistor MN1, and the result of the determination made by the current flow time determination circuit 6 for each switching period is output to the determination result holding circuit 7. If the induced voltage V3 of the auxiliary winding L3 is outside a predetermined range centered around 0, the first control may be performed. [Explanation of symbols]

[0114] 1. 1C Flyback Converter (Flyback Power Supply) 2. 2C switching control circuit 5. Off-time control circuit 6 Current flow time determination circuit 7 Judgment result holding circuit 8 ON time switching circuit 10 Timing control circuit L1 Primary winding L2 Secondary winding L3 Auxiliary winding MN1 Transistor (first switch element) S ON1 Turn-on signal (first turn-on signal) S ON2 Delayed turn-on signal (second turn-on signal) T2 Power-on Time TR Transformer V3 Induced voltage V IN Input voltage V OUT Output Voltage

Claims

1. a transformer having a primary winding and a secondary winding magnetically coupled to each other; a first switch element that turns on and off an input voltage supplied to the primary winding; a switching control circuit that controls the on / off of the first switch element to control an output voltage that is output from the secondary winding side and is obtained by stepping up or stepping down the input voltage.

1. A flyback power supply comprising: an auxiliary winding is magnetically coupled to the transformer, the auxiliary winding inducing a voltage of the same polarity as the induced voltage of the secondary winding; an off-time control circuit that sets an off-time of the first switch element based on a feedback voltage corresponding to the output voltage, and outputs a first turn-on signal that turns on the first switch element at a timing when the set off-time has elapsed since the first switch element was turned off; a timing control circuit that outputs a second turn-on signal to turn on the first switch element at a timing when the current flowing through the primary winding becomes zero after the first turn-on signal is output; a current-flow time determination circuit that measures a current-flow time of the auxiliary winding while the first switch element is in an OFF period based on an induced voltage of the auxiliary winding, and determines whether the measured current-flow time is within a predetermined time width, is equal to or smaller than a lower limit of the time width, or is equal to or larger than an upper limit of the time width; a determination result holding circuit that holds the determination result output from the energization time determination circuit during the OFF period of the first switch element until a next determination result is output from the energization time determination circuit; an on-time switching circuit that switches an on-time of the first switch element in a stepwise manner based on the determination result held by the determination result holding circuit, the on-time switching circuit increases the on-time of the first switch element by one step when the current flow time is equal to or less than the lower limit value of the time width, decreases the on-time of the first switch element by one step when the current flow time is equal to or more than the upper limit value of the time width, and does not change the on-time of the first switch element when the current flow time is within the time width. Flyback power supply.

2. 2. The flyback power supply according to claim 1, The timing control circuit determines that the current flowing through the primary winding has become zero when the induced voltage of the auxiliary winding is equal to or lower than a threshold value. Flyback power supply.

3. 2. The flyback power supply according to claim 1, the timing control circuit performs a first control of turning on the first switch element in response to the output of the second turn-on signal m times (m is an integer equal to or greater than 1) out of n periods (n is an integer equal to or greater than 2) of a switching period, turning on the first switch element in response to the output of the first turn-on signal (n-m) times, and outputting only the determination result determined by the current-flow time determination circuit during the off period after turning on the first switch element in response to the output of the second turn-on signal to the determination result holding circuit; Flyback power supply.

4. 4. The flyback power supply device according to claim 3, the switching control circuit performs the first control when the switching period is less than a certain period, and performs a second control to turn on the first switch element in response to the output of the first turn-on signal for each switching period when the switching period is equal to or greater than the certain period, and to output the determination result determined by the current application time determination circuit to the determination result holding circuit for each switching period. Flyback power supply.

5. 4. The flyback power supply device according to claim 3, the switching control circuit performs the first control when the induced voltage of the auxiliary winding is outside a predetermined range centered around 0, and performs a second control to turn on the first switch element in response to output of the first turn-on signal in each switching cycle when the induced voltage of the auxiliary winding is within the predetermined range for a certain period of time or more, and to output the determination result determined by the current application time determination circuit in each switching cycle to the determination result holding circuit. Flyback power supply.

6. A switching control circuit for controlling a first switch element that turns on and off an input voltage supplied to a primary winding of a transformer included in a flyback power supply device, and controlling an output voltage output from a secondary winding side of the transformer, an auxiliary winding is magnetically coupled to the transformer, the auxiliary winding inducing a voltage of the same polarity as the induced voltage of the secondary winding; an off-time control circuit that sets an off-time of the first switch element based on a feedback voltage corresponding to the output voltage, and outputs a first turn-on signal that turns on the first switch element at a timing when the set off-time has elapsed since the first switch element was turned off; a timing control circuit that outputs a second turn-on signal to turn on the first switch element at a timing when the current flowing through the primary winding becomes zero after the first turn-on signal is output; a current-flow time determination circuit that measures a current-flow time of the auxiliary winding while the first switch element is in an OFF period based on an induced voltage of the auxiliary winding, and determines whether the measured current-flow time is within a predetermined time width, is equal to or smaller than a lower limit of the time width, or is equal to or larger than an upper limit of the time width; a determination result holding circuit that holds the determination result output from the energization time determination circuit during the OFF period of the first switch element until a next determination result is output from the energization time determination circuit; an on-time switching circuit that switches an on-time of the first switch element in a stepwise manner based on the determination result held by the determination result holding circuit, the on-time switching circuit increases the on-time of the first switch element by one step when the current flow time is equal to or less than the lower limit value of the time width, decreases the on-time of the first switch element by one step when the current flow time is equal to or more than the upper limit value of the time width, and does not change the on-time of the first switch element when the current flow time is within the time width. Switching control circuit.

Images