Circuit device and display system

Abstract

To provide a circuit device, etc., capable of appropriately performing error detection regarding an image on which overlay processing, etc., is performed.SOLUTION: A circuit device 100 includes an overlay processing circuit 110 and an error detection circuit 120. The overlay processing circuit 110 overlay-processes first input image data IM1 into a first area AR1 of second input image data IM2 and outputs a result of the overlay processing as output image data IMQ. The error detection circuit 120 operates a first error code value corresponding to image data in the first area AR1 of the output image data IMQ and a second error code value corresponding to image data in a second area AR2, which does not overlay the first area AR1 of output image data IMQ2. The error detection circuit 120 compares the first error code value with a first expectation value EV1 and compares the second error code value with a second expectation value EV2, thereby performing error detection of the output image data IMQ.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a circuit device, a display system, and the like. [Background technology]

[0002] Patent Document 1 discloses a video processing device that detects image errors. The video processing device generates a composite image by replacing one or more areas of an input image with an image to be synthesized, and detects whether the composite image has an abnormality. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-153871 A Summary of the Invention [Problem to be solved by the invention]

[0004] In image error detection, an expected value of an error code value is compared with an error code value calculated from an image. When an input image is combined with another image, an expected value of an error code value cannot be obtained for the combined image. This causes a problem that an error cannot be properly detected for the combined image. Patent Document 1 describes that a CRC value is calculated for the OSD area of ​​the combined image, and the calculated CRC value is compared with the CRC expected value, but does not mention anything outside the OSD area. In addition, when an input image is split into two or more images, there is a problem that an error cannot be properly detected for the split image. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a circuit device that includes an overlay processing circuit that overlays first input image data onto a first region of second input image data and outputs the result of the overlay processing as output image data, and an error detection circuit that calculates a first error code value corresponding to image data of the first region of the output image data and a second error code value corresponding to image data of a second region that does not overlap with the first region of the output image data, and detects errors in the output image data by comparing the first error code value with a first expected value that is an expected value of the first error code value, and comparing the second error code value with a second expected value that is an expected value of the second error code value.

[0006] Another aspect of the present disclosure relates to a display system including the above circuit device and a display device on which the output image data is displayed. [Brief description of the drawings]

[0007] [Figure 1] 1 shows examples of configurations of electronic devices and display systems. [Diagram 2] 1 shows a first configuration example of a circuit device. [Diagram 3] 5A to 5C are diagrams illustrating the operation of the circuit device in the first configuration example. [Figure 4] 2 shows a second configuration example of a circuit device. [Diagram 5] 13 is a first example flowchart of a process performed by a circuit device in a second configuration example. [Figure 6] 13 is a second example flowchart of the processing performed by the circuit device in the second configuration example. [Figure 7] 11A to 11C are diagrams for explaining overlay processing and area determination when an α channel is used. [Figure 8] 3 shows a third configuration example of a circuit device. [Figure 9] 4 shows a fourth configuration example of a circuit device. [Figure 10] 13A to 13C are diagrams illustrating the operation of a circuit device in a fourth configuration example. [Figure 11] FIG. 4 is a diagram for explaining effective scanning lines in image division. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] A preferred embodiment of the present disclosure will be described in detail below. Note that the embodiment described below does not unduly limit the contents described in the claims, and all of the configurations described in the embodiment are not necessarily essential configurations.

[0009] 1. Electronic equipment and display systems 1 shows an example of the configuration of an electronic device and a display system including the circuit device of the present embodiment. The electronic device 500 includes a processing device 300 and a display system 400. The electronic device 500 is, for example, an in-vehicle display device including a meter panel, a center information display, a head-up display, or an electronic mirror, a television device, or an information processing device including a display.

[0010] The display system 400 includes the circuit device 100 and the display device 200. If the circuit device 100 has an image splitting function, the display system 400 may include a plurality of display devices.

[0011] Image data is input to the circuit device 100 from a processing device 300. The processing device 300 is a processor such as a CPU, a microcomputer, a DSP, an ASIC, or an FPGA. CPU is an abbreviation for Central Processing Unit. DSP is an abbreviation for Digital Signal Processor. ASIC is an abbreviation for Application Specific Integrated Circuit. FPGA is an abbreviation for Field Programmable Gate Array.

[0012] The circuit device 100 is a display controller that controls display of the display device 200. The circuit device 100 may further include a display driver that drives a display panel of the display device 200. The circuit device 100 is, for example, an integrated circuit device in which a plurality of circuit elements are integrated on a semiconductor substrate. Note that, in the following, a portion related to image error detection of this embodiment will be described, and a description of the display controller function and the display driver function will be omitted.

[0013] The circuit device 100 receives the first input image data and the second input image data from the processing device 300. The circuit device 100 performs an overlay process on the first input image data and the second input image data, and transmits the output image data after the overlay to the display device 200. The circuit device 100 performs an error detection of the output image data. Alternatively, the circuit device 100 receives the input image data from the processing device 300, and performs a split process on the input image data into a plurality of divided image data. In this case, the display system 400 includes a plurality of display devices. The circuit device 100 transmits each divided image data to a corresponding display device among the plurality of display devices. The circuit device 100 performs an error detection of each divided image data. In either of the above cases, image data corresponding to a plurality of images is input to the circuit device 100. A method for transmitting such image data corresponding to a plurality of images may be either single-stream transmission or multi-stream transmission.

[0014] The display device 200 is a liquid crystal display device or an EL display device. EL is an abbreviation for Electro-Luminescence. For example, when the display system 400 is mounted on a vehicle, the display device 200 is a cluster panel, a navigation display, a head-up display, or the like. The display device 200 includes, for example, a display driver, a display panel, and a backlight. Alternatively, when the display device 200 is a head-up display, the display device 200 further includes a projection optical system.

[0015] 2. First and second configuration examples FIG. 2 shows a first configuration example of a circuit device. The circuit device 100 includes an overlay processing circuit 110, an error detection circuit 120, an interface circuit 130, and an interface circuit 140. FIG. 3 is a diagram for explaining the operation of the circuit device in the first configuration example. Below, an example of overlaying one foreground image on a background image is shown, but two or more foreground images may be overlaid on a background image. In that case, error detection may be performed on the background image and each foreground image.

[0016] The interface circuit 130 receives the first input image data IM1, the second input image data IM2, the first expected value EV1, and the second expected value EV2 from the processing device 300. The interface circuit 130 includes an image interface circuit such as the Open LVDS Display Interface standard, the DisplayPort standard, or the Display Serial Interface 2 standard of the Mobile Industry Processor Interface. The interface circuit 130 may also include an interface circuit such as the Serial Peripheral Interface standard or the Inter-Integrated Circuit standard for communicating the expected values.

[0017] The overlay processing circuit 110 overlays the first input image represented by the first input image data IM1 on the first region AR1 of the second input image represented by the second input image data IM2, and outputs the result as output image data IMQ. The overlay processing here is a process in which the second input image is a background image, the first input image is a foreground image, and the first input image is a foreground image, and the first input image is superimposed on a part of the second input image. In the following, the "image represented by the image data" is also simply described as "image data". For example, the overlay processing circuit 110 is described as overlaying the first input image data IM1 on the first region AR1 of the second input image data IM2. The first region AR1 may be set, for example, from the processing device 300 via the interface circuit 130, or may be set in advance in a non-volatile memory (not shown) or the like. The region of the entire region of the output image data IMQ excluding the first region AR1 is defined as the second region AR2. The image of the first region AR1 is also called the foreground image, and the image of the second region AR2 is also called the background image. The second area AR2 need only be an area that does not overlap with the first area AR1. In other words, when there are multiple foreground images to be overlaid, the second area AR2 is an area of ​​the entire output image data IMQ excluding the areas of the multiple foreground images.

[0018] The interface circuit 140 outputs the output image data IMQ to the display device 200. The interface circuit 140 may be an image interface circuit of any of the various standards mentioned above.

[0019] The error detection circuit 120 performs error detection on the image of the first region AR1 in the output image data IMQ, using the first expected value EV1 received by the interface circuit 130. The error detection circuit 120 also performs error detection on the image of the second region AR2 in the output image data IMQ, using the second expected value EV2 received by the interface circuit 130. The first expected value EV1 and the second expected value EV2 are calculated by the processing device 300. For example, the processing device 300 performs a calculation similar to that of the expected value calculation circuit 150 in FIG. 4, which will be described later. The error detection circuit 120 includes an error detection region determination circuit 125, a first region error determination circuit 121, and a second region error determination circuit 122.

[0020] The error detection area determination circuit 125 determines which area each pixel of the output image data IMQ belongs to. The first area AR1 is specified by information capable of identifying the coordinates of the pixel. For example, when the first area AR1 is a rectangle, the first area AR1 is specified by the coordinates of one vertex of the rectangle, the width of the rectangle, and the height of the rectangle. The output image data IMQ is, for example, stream data in which each pixel data is transmitted sequentially. The error detection area determination circuit 125 receives pixel data sequentially as stream data, and determines whether the pixel belongs to the first area AR1 or the second area AR2 based on the coordinates of the pixel corresponding to the pixel data and the information specifying the first area AR1. The error detection area determination circuit 125 outputs the pixel data determined to belong to the first area AR1 as the first output image data IMQ1, and outputs the pixel data determined to belong to the second area AR2 as the second output image data IMQ2.

[0021] The first region error determination circuit 121 calculates a first error code value from the first output image data IMQ1 and compares the first error code value with a first expected value EV1. The first region error determination circuit 121 outputs the comparison result to the interface circuit 140 as a first error detection signal ER1. The second region error determination circuit 122 calculates a second error code value from the second output image data IMQ2 and compares the second error code value with a second expected value EV2. The second region error determination circuit 122 outputs the comparison result to the interface circuit 140 as a second error detection signal ER2.

[0022] The error code value and the expected value are both coded using the same data error check method. The data error check method may be any of a variety of methods, such as CRC, checksum, parity check, or Hamming code. CRC is an abbreviation for Cyclic Redundancy Check.

[0023] The interface circuit 140 stops outputting the output image data IMQ when at least one of the first error detection signal ER1 and the second error detection signal ER2 indicates an error. Note that the use of the error detection signal is not limited to this. For example, the circuit device 100 may have a register that stores the first error detection signal ER1 and the second error detection signal ER2. The processing device 300 may read the first error detection signal ER1 and the second error detection signal ER2 from the register via the interface circuit 130. Alternatively, the overlay processing circuit 110 may stop the overlay processing when at least one of the first error detection signal ER1 and the second error detection signal ER2 indicates an error.

[0024] 4 shows a second configuration example of a circuit device. The circuit device 100 includes an expected value calculation circuit 150, an overlay processing circuit 110, an error detection circuit 120, an interface circuit 130, and an interface circuit 140. The following mainly describes the parts that differ from the first configuration example.

[0025] The expected value calculation circuit 150 calculates a first expected value EV1 from the first input image data IM1, and calculates a second expected value EV2 from the second input image data IM2. The expected value calculation circuit 150 includes an expected value calculation area determination circuit 155, a first expected value calculation circuit 151, and a second expected value calculation circuit 152.

[0026] 5 is a first example of a flowchart of the processing performed by the circuit device in the second configuration example. Note that the processing other than steps S6 to S8 is also applicable to the first configuration example.

[0027] In step S1, an image is input to the circuit device 100. That is, the interface circuit 130 receives the first input image data IM1 and the second input image data IM2 from the processing device 300.

[0028] In step S2, the overlay processing circuit 110 performs overlay processing. That is, the overlay processing circuit 110 performs overlay processing on the first input image data IM1 and the second input image data IM2, and outputs the result as output image data IMQ.

[0029] In step S3, the error detection area determination circuit 125 determines the area to which each pixel of the output image data IMQ belongs based on the coordinates using the horizontal counter and the vertical counter. That is, the horizontal counter counts the coordinates of the pixel in the horizontal scanning line direction, and the vertical counter counts the coordinates of the pixel in the vertical scanning direction. The error detection area determination circuit 125 determines whether the coordinates of the pixel indicated by the output of the horizontal counter and the vertical counter belong to the first area AR1.

[0030] In step S4, the error detection area determination circuit 125 performs image division. That is, the error detection area determination circuit 125 divides the output image data IMQ into first output image data IMQ1 and second output image data IMQ2 based on the result of the area determination in step S3. The second output image data IMQ2 is image data obtained by excluding the image data of the first area AR1 from the output image data IMQ.

[0031] In step S5, a CRC value is calculated as the error code value. As described above, the error code value is not limited to the CRC value. Specifically, the first region error determination circuit 121 calculates a first error code value from the first output image data IMQ1, and the second region error determination circuit 122 calculates a second error code value from the second output image data IMQ2.

[0032] In step S6, the first expected value calculation circuit 151 generates an expected value by CRC calculation. As described above, the expected value is not limited to a CRC value. Specifically, the first expected value calculation circuit 151 calculates a first expected value EV1 from the first input image data IM1.

[0033] In step S7, the expected value calculation area determination circuit 155 determines the area to which each pixel of the second input image data IM2 belongs based on the coordinates using the horizontal counter and the vertical counter. That is, the expected value calculation area determination circuit 155 determines whether the coordinates of the pixel indicated by the output of the horizontal counter and the vertical counter belong to the second area AR2.

[0034] In step S8, the second expected value calculation circuit 152 generates an expected value by CRC calculation. As described above, the expected value is not limited to a CRC value. Specifically, the second expected value calculation circuit 152 calculates a second expected value EV2 from the image data of the second region AR2 in the second input image data IM2.

[0035] In step S9, the first region error judgment circuit 121 and the second region error judgment circuit 122 judge whether the CRC value matches the expected value. That is, the first region error judgment circuit 121 compares the first error code value with the first expected value EV1 and outputs the result as the first error detection signal ER1. The second region error judgment circuit 122 compares the first error code value with the first expected value EV1 and outputs the result as the first error detection signal ER1.

[0036] If the CRC value matches the expected value in step S9, the interface circuit 140 outputs the output image data IMQ in step S10. That is, if the first error code value matches the first expected value EV1 and the second error code value matches the second expected value EV2, the interface circuit 140 outputs the output image data IMQ.

[0037] If the CRC value does not match the expected value in step S9, the interface circuit 140 stops outputting the output image data IMQ in step S11. That is, if either the first error code value does not match the first expected value EV1 or the second error code value does not match the second expected value EV2 is satisfied, the interface circuit 140 stops outputting the output image data IMQ.

[0038] 6 is a second example flowchart of the process performed by the circuit device in the second configuration example. Note that the processes other than steps S31 to S34 are also applicable to the first configuration example. In the second example flowchart, in detecting an error in a background image, an error code value and an expected value are calculated from an image in which a first region of a foreground image is filled.

[0039] Steps S21 to S23 are similar to steps S1 to S3 in FIG.

[0040] In step S24, the error detection area determination circuit 125 performs image division. That is, the error detection area determination circuit 125 divides the image data of the first area AR1 of the output image data IMQ as small-screen image data based on the result of the area determination in step S23. As shown in step S25, the error detection area determination circuit 125 outputs the small-screen image data as the first output image data IMQ1.

[0041] As shown in step S26, the error detection area determination circuit 125 uses the output image data IMQ as full-screen image data.

[0042] In step S27, the error detection area determination circuit 125 determines the area to which each pixel of the full screen image data belongs based on the coordinates using the horizontal counter and the vertical counter. That is, the error detection area determination circuit 125 determines whether the coordinates of the pixel indicated by the output of the horizontal counter and the vertical counter belong to the first area AR1. The result of step S23 may be used.

[0043] In step S28, the error detection area determination circuit 125 fills the first area AR1 of the full screen image data, and outputs the result as the second output image data IMQ2. Specifically, the error detection area determination circuit 125 embeds specific image data of the same image size as the first area AR1 in the first area AR1. The specific image data may be any image data as long as it is known image data for which an expected value can be calculated. As an example, the error detection area determination circuit 125 replaces pixel data belonging to the first area AR1 with pixel data of a predetermined color. The predetermined color is, for example, black, but is not limited thereto.

[0044] In step S29, the first region error determination circuit 121 calculates a first error code value from the small screen image data, that is, the first output image data IMQ1.

[0045] In step S30, the second region error determination circuit 122 calculates a second error code value from the filled-in full-screen image data, that is, the second output image data IMQ2.

[0046] In step S31, the first expected value calculation circuit 151 calculates a first expected value EV1 from the first input image data IM1.

[0047] In step S32, the expected value calculation area determination circuit 155 determines whether or not each pixel of the second input image data IM2 belongs to the first area AR1, based on the coordinates using the horizontal counter and the vertical counter.

[0048] In step S33, the expected value calculation area determination circuit 155 fills in the first area AR1 of the second input image data IM2. Specifically, the expected value calculation area determination circuit 155 embeds specific image data in the first area AR1 of the second input image data IM2. The specific image data here is the same as the specific image data in step S28.

[0049] In step S34, the second expected value calculation circuit 152 calculates a second expected value EV2 from the filled-in second input image data IM2.

[0050] Steps S35 to S37 are similar to steps S9 to S11 in FIG.

[0051] 7 is a diagram for explaining overlay processing and area determination when the α channel is used. This method can be applied to both the first and second configuration examples.

[0052] The interface circuit 130 receives the first input image data IM1, the second input image data IM2, and the α channel. The α channel is added to the first input image data IM1 of the foreground image, for example. The overlay processing circuit 110 generates an α channel with the same number of pixels as the second input image data IM2 of the background image, based on the information indicating the position of the foreground image and the α channel. Note that the α channel may be added to the second input image data IM2 from the beginning.

[0053] The overlay processing circuit 110 uses the α channel to overlay the first input image data IM1 onto the second input image data IM2. For example, the α channel has a first value set in the foreground portion and a second value set in the background portion. The second value is different from the first value. FIG. 7 shows an example where the first value is "1" and the second value is "0". The overlay processing circuit 110 uses pixel data of the first input image data IM1 for pixels where the α channel has the first value set, and uses pixel data of the second input image data IM2 for pixels where the α channel has the second value set.

[0054] The error detection area determination circuit 125 and the expected value calculation area determination circuit 155 determine the area to which each pixel belongs based on the α channel. When the α channel in Fig. 7 is used, the error detection area determination circuit 125 and the expected value calculation area determination circuit 155 determine that a pixel with a first value "1" set in the α channel is a pixel in the first area AR1, and that a pixel with a second value "0" set in the α channel is a pixel in the second area AR2.

[0055] In this embodiment, the circuit device 100 includes an overlay processing circuit 110 and an error detection circuit 120. The overlay processing circuit 110 overlays the first input image data IM1 onto the first region AR1 of the second input image data IM2, and outputs the result of the overlay processing as output image data IMQ. The error detection circuit 120 calculates a first error code value corresponding to the image data of the first region AR1 of the output image data IMQ, and a second error code value corresponding to the image data of the second region AR2 that does not overlap with the first region AR1 of the output image data IMQ. The error detection circuit 120 detects an error in the output image data IMQ by comparing the first error code value with a first expected value EV1 that is an expected value of the first error code value, and by comparing the second error code value with a second expected value EV2 that is an expected value of the second error code value.

[0056] According to this embodiment, an error can be appropriately detected in an image after overlay processing. That is, an error is detected in the image data of the first area AR1 where overlay has been performed among the output image data IMQ by comparing a first error code value with a first expected value EV1. Also, an error is detected in the image data of the second area AR2 where overlay has not been performed among the output image data IMQ by comparing a second error code value with a second expected value EV2. By these error detections, an error can be substantially detected in the entire image after overlay.

[0057] As described in FIG. 6, the error detection circuit 120 may also calculate a second error code value from the image data in the second area AR2 of the output image data IMQ and the specific image data embedded in the first area AR1 of the output image data IMQ.

[0058] According to this embodiment, an error can be detected in the second region AR2 of the output image data IMQ by calculating the second error code value from the output image data IMQ in which the specific image data is embedded in the first region AR1. That is, the specific image data is known image data used to calculate the second expected value EV2, and the second expected value is calculated from the output image data IMQ in which the specific image data is embedded in the first region AR1. Then, an error can be detected in the second region AR2 by comparing the second error code value with the second expected value EV2.

[0059] As described with reference to FIG. 5, the error detection circuit 120 may calculate a second error code value from image data in a second area AR2 obtained by excluding the image data in the first area AR1 from the output image data IMQ.

[0060] According to this embodiment, the output image data IMQ excluding the image data of the first area AR1 is the image data of the second area AR2 itself. The second error code value calculated from the image data of the second area AR2 is compared with the second expected value EV2, thereby enabling error detection in the second area AR2.

[0061] In this embodiment, the error detection circuit 120 includes an error detection region determination circuit 125, a first region error determination circuit 121, and a second region error determination circuit 122. The error detection region determination circuit 125 determines whether each pixel of the output image data IMQ belongs to the first region AR1 or the second region AR2. The first region error determination circuit 121 calculates a first error code value for a pixel determined to belong to the first region AR1, and compares the first error code value with a first expected value EV1. The second region error determination circuit 122 calculates a second error code value for a pixel determined to belong to the second region AR2, and compares the second error code value with a second expected value EV2.

[0062] According to this embodiment, the error detection area determination circuit 125 performs area determination, so that the output image data IMQ can be divided into image data of the first area AR1 and image data of the second area AR2. Then, the first area error determination circuit 121 can calculate a first error code value based on the result of the area determination, and the second area error determination circuit 122 can calculate a second error code value based on the result of the area determination.

[0063] As described with reference to FIG. 3 etc., the error detection area determination circuit 125 may determine whether each pixel of the output image data IMQ belongs to the first area AR1 or the second area AR2 based on the coordinate information of the first area AR1.

[0064] The coordinate information of the first region AR1 is information specifying the coordinates to overlay the first input image data IM1. Since the region where the first input image data IM1 is overlaid is the first region AR1, the error detection region determination circuit 125 can determine the region to which each pixel belongs based on the coordinate information of the first region AR1.

[0065] As described in FIG. 7, the error detection area determination circuit 125 may determine whether each pixel of the output image data IMQ belongs to the first area AR1 or the second area AR2 based on an alpha channel in which a first value is set to pixels belonging to the first area AR1 and a second value is set to pixels belonging to the second area AR2.

[0066] According to this embodiment, an image of an arbitrary shape can be overlaid by using the α channel. Then, a first area AR1 of an arbitrary shape on which the image is overlaid can be determined by using the α channel.

[0067] In addition, in this embodiment, the circuit device 100 may include an interface circuit 130. As described with reference to FIG. 2 etc., the interface circuit 130 may receive the first input image data IM1, the second input image data IM2, the first expected value EV1, and the second expected value EV2 from the outside.

[0068] According to this embodiment, the interface circuit 130 receives the first expected value EV1 and the second expected value EV2 calculated externally, and the error detection circuit 120 can detect errors in the output image data IMQ using the received first expected value EV1 and second expected value EV2.

[0069] 4 and the like, the circuit device 100 may include an expected value calculation circuit 150. The expected value calculation circuit 150 may calculate a first expected value EV1 and a second expected value EV2 based on the first input image data IM1 and the second input image data IM2.

[0070] According to this embodiment, the first expected value EV1 and the second expected value EV2 are calculated inside the circuit device 100, and the error detection circuit 120 can detect errors in the output image data IMQ using the calculated first expected value EV1 and second expected value EV2.

[0071] In this embodiment, the expected value calculation circuit 150 includes a first expected value calculation circuit 151, an expected value calculation area determination circuit 155, and a second expected value calculation circuit 152. The first expected value calculation circuit 151 calculates a first expected value EV1 from the first input image data IM1. The expected value calculation area determination circuit 155 determines whether each pixel of the second input image data IM2 belongs to the second area AR2. The second expected value calculation circuit 152 calculates a second expected value EV2 for pixels of the second input image data IM2 determined to belong to the second area AR2.

[0072] According to this embodiment, the expected value calculation area determination circuit 155 performs area determination, so that the image data of the second area AR2 can be divided from the output image data IMQ. Then, the second expected value calculation circuit 152 can calculate the second expected value EV2 based on the result of the area determination.

[0073] In this embodiment, the display system 400 includes the circuit device 100 and a display device 200 on which the output image data IMQ is displayed. The display device 200 may be a head-up display, a meter panel, a center information display, or an electronic mirror.

[0074] A head-up display, a meter panel, a center information display, or an electronic mirror is mounted on a moving object such as an automobile. In a display device mounted on a moving object, a so-called picture-in-picture technique is used in which an image is superimposed on another image. For example, another image is inserted in a partial area of ​​an image, or an object such as an icon is superimposed on an image or picture. According to the present embodiment, even when picture-in-picture is used, an error in a displayed image can be appropriately detected.

[0075] 3. Third and fourth configuration examples 8 shows a third configuration example of the circuit device. The circuit device 100 includes an image split circuit 160, an error detection circuit 120, an interface circuit 130, an interface circuit 141, and an interface circuit 142. An example in which the input image data IM is separated into image data for two screens will be described below, but the input image data IM may be separated into image data for three or more screens. Hereinafter, it is assumed that the display device 200 in FIG. 1 includes a first display device and a second display device.

[0076] The interface circuit 130 receives the input image data IM, the first expected value EV1, and the second expected value EV2 from the processing device 300. The first expected value EV1 and the second expected value EV2 are calculated by the processing device 300. For example, the processing device 300 performs a calculation similar to that of an expected value calculation circuit 150 in Fig. 9, which will be described later.

[0077] The image split circuit 160 performs image split processing. That is, the image split circuit 160 separates the input image data IM into the first divided image data IMD1 and the second divided image data IMD2. For example, the interface circuit 130 receives the input image data IM in which the first divided image and the second divided image are connected to one image by single-stream transmission. The image split circuit 160 separates the first divided image data IMD1 and the second divided image data IMD2 from the single-stream input image data IM. Alternatively, the interface circuit 130 receives the input image data IM by multi-stream transmission. The multi-stream input image data IM includes the first divided image data IMD1 and the second divided image data IMD2 transmitted in a time-division manner. The image split circuit 160 separates the first divided image data IMD1 and the second divided image data IMD2 from the multi-stream input image data IM.

[0078] The interface circuit 141 outputs the first divided image data IMD1 to the first display device. The interface circuit 142 outputs the second divided image data IMD2 to the second display device.

[0079] The error detection circuit 120 includes a first divided image error judgment circuit 123 and a second divided image error judgment circuit 124. The first divided image error judgment circuit 123 calculates a first error code value from the first divided image data IMD1, compares the first error code value with a first expected value EV1, and outputs the result as a first error detection signal ER1 to the interface circuit 141. The second divided image error judgment circuit 124 calculates a second error code value from the second divided image data IMD2, compares the second error code value with a second expected value EV2, and outputs the result as a second error detection signal ER2 to the interface circuit 142.

[0080] The error code value and the expected value are both coded using the same data error check method, which may be any of a variety of methods as described above, such as CRC, checksum, parity check, or Hamming code.

[0081] The interface circuit 141 stops outputting the first divided image data IMD1 when the first error detection signal ER1 indicates an error. The interface circuit 142 stops outputting the second divided image data IMD2 when the second error detection signal ER2 indicates an error. Note that the use of the error detection signal is not limited to this. For example, the circuit device 100 may have a register that stores the first error detection signal ER1 and the second error detection signal ER2. The processing device 300 may read the first error detection signal ER1 and the second error detection signal ER2 from the register via the interface circuit 130. Alternatively, the image split circuit 160 may stop the image split process when at least one of the first error detection signal ER1 and the second error detection signal ER2 indicates an error.

[0082] FIG. 9 is a fourth configuration example of the circuit device. The circuit device 100 includes an expected value calculation circuit 150, an image split circuit 160, an error detection circuit 120, an interface circuit 130, an interface circuit 141, and an interface circuit 142. FIG. 10 is a diagram for explaining the operation of the circuit device in the fourth configuration example. Here, an example in which the first divided image data and the second divided image data have different effective scanning lines is shown, but the first divided image data and the second divided image data may have the same effective scanning lines. Below, the parts different from the third configuration example are mainly explained.

[0083] The expected value calculation circuit 150 includes a first expected value calculation circuit 153, a second expected value calculation circuit 154, and an image split circuit 156 for calculating an expected value.

[0084] The image split circuit 156 for expected value calculation separates the input image data IM into divided image data IMV1 for a first expected value and divided image data IMV2 for a second expected value. The separation method is the same as that of the image split circuit 160. Specifically, the image split circuit 160 separates the first region ARD1 of the input image data IM as the first divided image data IMD1, and separates the second region ARD2 of the input image data IM as the second divided image data IMD2. At this time, the image split circuit 160 separates the first region ARD1 of the input image data IM as divided image data IMV1 for a first expected value, and separates the second region ARD2 of the input image data IM as divided image data IMV2 for a second expected value.

[0085] The first expected value calculation circuit 153 calculates a first expected value EV1 from the first expected value divided image data IMV1. The second expected value calculation circuit 154 calculates a second expected value EV2 from the second expected value divided image data IMV2.

[0086] 11 is a diagram for explaining effective scanning lines in image division. The number of scanning lines of the first display device on which the first divided image data IMD1 is displayed is m, and the number of scanning lines of the second display device on which the second divided image data IMD2 is displayed is n. Both m and n are integers of 1 or more, and m <nである。

[0087] The number of effective scanning lines of the input image data IM is n. The input image data IM is divided into left and right halves by a predetermined number of horizontal pixels, with the left side designated as the first region ARD1 and the right side designated as the second region ARD2. The number of scanning lines of the first region ARD1 is n, of which m is the number of effective scanning lines. The number of effective scanning lines of the second region ARD2 is n, the same as the number of effective scanning lines of the input image data IM.

[0088] At this time, the first divided image error determination circuit 123 uses the data of the effective scanning lines m excluding the non-effective scanning lines nm in the first region ARD1 as the first divided image data IMD1. Similarly, the first expected value calculation circuit 153 uses the data of the effective scanning lines m excluding the non-effective scanning lines nm in the first region ARD1 as the first expected value divided image data IMV1.

[0089] The second divided image error determination circuit 124 uses the data of the effective scanning line n of the second region ARD2 as the second divided image data IMD2. Similarly, the first expected value calculation circuit 153 uses the data of the effective scanning line n of the second region ARD2 as the second expected value divided image data IMV2.

[0090] In this embodiment, the circuit device 100 includes an image split circuit 160 and an error detection circuit 120. The image split circuit 160 splits the input image data IM into first divided image data IMD1 and second divided image data IMD2. The error detection circuit 120 calculates a first error code value from the first divided image data IMD1 and performs error detection on the first divided image data IMD1 by comparing the first error code value with a first expected value EV1 which is an expected value of the first error code value. The error detection circuit 120 calculates a second error code value from the second divided image data IMD2 and performs error detection on the second divided image data IMD2 by comparing the second error code value with a second expected value EV2 which is an expected value of the second error code value.

[0091] According to this embodiment, an error can be appropriately detected for the image after splitting. That is, an error is detected for the first divided image data IMD1 separated from the input image data IM by comparing the first error code value with the first expected value EV1. Also, an error is detected for the second divided image data IMD2 separated from the input image data IM by comparing the second error code value with the second expected value EV2. As a result, an error is detected for each image after splitting, which means that an error is substantially detected for the entire input image data IM.

[0092] In this embodiment, the circuit device 100 also includes an interface circuit 130. As described in Fig. 8, the interface circuit 130 may receive the input image data IM, the first expected value EV1, and the second expected value EV2 from the outside.

[0093] According to this embodiment, the interface circuit 130 receives the first expected value EV1 and the second expected value EV2 calculated externally, and the error detection circuit 120 performs error detection on the first divided image data IMD1 using the received first expected value EV1, and performs error detection on the second divided image data IMD2 using the received second expected value EV2.

[0094] 9, the circuit device 100 may include an expected value calculation circuit 150 that calculates the first expected value EV1 and the second expected value EV2. As described in Fig. 11, the number m of effective scanning lines of the first divided image data IMD1 may be less than the number n of effective scanning lines of the second divided image data IMD2. The expected value calculation circuit 150 may exclude pixels of non-effective scanning lines of the first divided image data IMD1 among the input image data IM from the calculation of the first expected value EV1.

[0095] According to this embodiment, even if the number m of effective scanning lines of the first display device that displays the first divided image data IMD1 is less than the number n of effective scanning lines of the second display device that displays the second divided image data IMD2, the first expected value EV1 can be calculated from the pixels of the effective scanning lines.

[0096] Although the present embodiment has been described in detail as above, it will be easily understood by those skilled in the art that many modifications are possible without substantially departing from the novel matters and effects of the present disclosure. Therefore, all such modifications are intended to be included in the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader meaning or synonymy can be replaced with that different term anywhere in the specification or drawings. In addition, all combinations of the present embodiment and modifications are also included in the scope of the present disclosure. In addition, the configurations and operations of the overlay processing circuit, image split circuit, error detection circuit, expected value calculation circuit, interface circuit, circuit device, display device, processing device, display system, etc. are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0097] 100...circuit device, 110...overlay processing circuit, 120...error detection circuit, 121...first region error judgment circuit, 122...second region error judgment circuit, 123...first divided image error judgment circuit, 124...second divided image error judgment circuit, 125...error detection region judgment circuit, 130...interface circuit, 140...interface circuit, 141...interface circuit, 142...interface circuit, 150...expected value calculation circuit, 151...first expected value calculation circuit, 152...second expected value calculation circuit, 153...first Wait value calculation circuit, 154...second expected value calculation circuit, 155...area determination circuit for expected value calculation, 156...image split circuit for expected value calculation, 160...image split circuit, 200...display device, 300...processing device, 400...display system, 500...electronic device, AR1...first area, AR2...second area, EV1...first expected value, EV2...second expected value, IM...input image data, IM1...first input image data, IM2...second input image data, IMD1...first divided image data, IMD2...second divided image data, IMQ...output image data

Claims

1. an overlay processing circuit that overlays the first input image data onto a first region of the second input image data and outputs a result of the overlay processing as output image data; an error detection circuit that calculates a first error code value corresponding to image data in the first region of the output image data and a second error code value corresponding to image data in a second region of the output image data that does not overlap the first region, and detects an error in the output image data by comparing the first error code value with a first expected value that is an expected value of the first error code value and comparing the second error code value with a second expected value that is an expected value of the second error code value; A circuit device comprising:

2. 2. The circuit device according to claim 1, The error detection circuit includes: A circuit device which calculates the second error code value from image data in the second area of ​​the output image data and specific image data embedded in the first area of ​​the output image data.

3. 2. The circuit device according to claim 1, The error detection circuit includes: a circuit device for calculating the second error code value from image data of the second region obtained by excluding image data of the first region from the output image data.

4. 2. The circuit device according to claim 1, The error detection circuit includes: an error detection region determination circuit for determining whether each pixel of the output image data belongs to the first region or the second region; a first region error determination circuit that calculates the first error code value for the pixel determined to belong to the first region and compares the first error code value with the first expected value; a second region error determination circuit that calculates the second error code value for the pixel determined to belong to the second region and compares the second error code value with the second expected value; A circuit device comprising:

5. 5. The circuit device according to claim 4, The error detection area determination circuit includes: A circuit device comprising: a circuit for determining whether each pixel of the output image data belongs to the first region or the second region, based on coordinate information of the first region.

6. 5. The circuit device according to claim 4, The error detection area determination circuit includes: A circuit device characterized in that it determines whether each pixel of the output image data belongs to the first region or the second region based on an alpha channel in which a first value is set to pixels belonging to the first region and a second value is set to pixels belonging to the second region.

7. 2. The circuit device according to claim 1, A circuit device comprising an interface circuit that receives the first input image data, the second input image data, the first expected value, and the second expected value from an external device.

8. 2. The circuit device according to claim 1, a first input image data outputting unit outputting the first expected value and the second expected value based on the first input image data and the second input image data;

9. 9. The circuit arrangement according to claim 8, The expected value calculation circuit includes: a first expected value calculation circuit that calculates the first expected value from the first input image data; an expected value calculation region determination circuit for determining whether each pixel of the second input image data belongs to the second region; a second expected value calculation circuit that calculates the second expected value for a pixel of the second input image data that is determined to belong to the second region; A circuit device comprising:

10. an image splitting circuit for splitting the input image data into a first divided image data and a second divided image data; an error detection circuit that detects an error in the first divided image data by calculating a first error code value from the first divided image data and comparing the first error code value with a first expected value that is an expected value of the first error code value, and that detects an error in the second divided image data by calculating a second error code value from the second divided image data and comparing the second error code value with a second expected value that is an expected value of the second error code value; A circuit device comprising:

11. 11. A circuit arrangement according to claim 10, a circuit device including an interface circuit that receives the input image data, the first expected value, and the second expected value from an external device.

12. 11. A circuit arrangement according to claim 10, an expected value calculation circuit that calculates the first expected value and the second expected value based on the input image data, the number of effective scanning lines of the first divided image data is smaller than the number of effective scanning lines of the second divided image data, The expected value calculation circuit includes: a circuit device that excludes pixels of non-effective scanning lines of the first divided image data among the input image data from a calculation of the first expected value.

13. A circuit arrangement according to any one of claims 1 to 9; a display device on which the output image data is displayed; and A display system comprising:

14. 14. A display system according to claim 13, The display device includes: A display system which is a head-up display, a meter panel, a center information display, or an electronic mirror.

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