Cell balancing device

Abstract

To provide a cell balancing device that suppresses leakage current in a balancing switch connected in parallel with a battery cell without using a high-voltage element and blocks operating the balancing switch when a reverse voltage occurs.SOLUTION: A cell balancing device includes: a balancing switching section in which source terminals of a first switch and a second switch are commonly connected in series, and drain terminals of the respective switches are connected in parallel with both ends of a battery cell; a latching section that is interposed between the source terminal of the balancing switching section and a detection pin of the battery cell, receives an enable signal and a reverse enable signal, and outputs a drive voltage to the gate terminal of the balancing switching section to drive the balancing switching section; and a reverse voltage protection section interposed between the source terminal of the balancing switching section and the detection pin of the battery cell.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a cell balancing device, and more particularly to a cell balancing device that suppresses leakage current of a balancing switch connected in parallel to battery cells connected in series, and cuts off operation of the balancing switch when a reverse voltage occurs. [Background technology]

[0002] Recently, interest in electrical products that can be powered by secondary batteries has been growing due to the depletion of fossil energy and environmental pollution caused by the use of fossil energy. As a result, the demand for secondary batteries as an energy source is rapidly increasing along with the technological development and increasing demand for mobile devices, electric vehicles (EVs), hybrid vehicles (HVs), energy storage systems (ESSs), and uninterruptible power supplies (UPSs).

[0003] Such secondary battery cells are attracting attention as a new energy source that is environmentally friendly and increases energy efficiency, not only because of the primary benefit of dramatically reducing the use of fossil energy, but also because they do not produce any by-products from energy use.

[0004] In particular, secondary batteries used in electric vehicles, hybrid vehicles, energy storage systems, and uninterruptible power supplies are configured by connecting a plurality of battery cells in order to charge or discharge high-output, large-capacity power.

[0005] Although the battery cells of such a secondary battery should ideally have the same characteristics, they have deviations in capacity, impedance and internal resistance, and as the secondary battery is charged and discharged, the deviations between the battery cells increase. Due to the deviations between the battery cells, certain battery cells are overcharged or overdischarged, shortening the life of the battery cells and ultimately shortening the life of the secondary battery.

[0006] Accordingly, a balancing technique for maintaining a uniform voltage between battery cells is applied to the secondary battery in order to improve the stability and life span of the battery cells.

[0007] More specifically, methods for evenly balancing the voltages of each battery cell included in a secondary battery include active balancing, which supplies a charging current to a battery cell with a relatively low voltage to increase the voltage, and passive balancing, which discharges a battery cell with a relatively high voltage to decrease the voltage.

[0008] The background art of the present invention is disclosed in Patent Document 1. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Korean Patent Publication No. 10-2018-0013574 Summary of the Invention [Problem to be solved by the invention]

[0010] Such a cell balancing device configures one channel for each battery cell connected in series, and a balancing switch is connected in parallel to the battery. A battery cell and a balancing resistor are interposed between the upper and lower pins of the balancing switch, and cell balancing is performed by turning the balancing switch on and off.

[0011] At this time, the upper pin maintains a higher voltage than the lower pin, but if a resistive bus bar is interposed between the battery cells connected in series, a reverse voltage occurs in the channel, in which a lower voltage is applied to the upper pin than to the lower pin.

[0012] When a reverse voltage occurs, not only is there a problem that leakage current or failure may occur in the balancing switch, but also the elements that make up the driver circuit that drives the balancing switch are large, high-voltage elements such as EDMOS (Enhancement Driver depletion load MOS) / LDMOS (Lateral Double Diffused MOS), which occupy a large chip area.

[0013] In addition, since NMOS cannot be used at the top end of the battery and PMOS cannot be used at the bottom end, the channel configuration is not uniform, which makes mass production management and design difficult.

[0014] The present invention has been made to improve the above-mentioned problems, and an object of the present invention in one aspect is to provide a cell balancing device that suppresses leakage current of a balancing switch connected in parallel to a battery cell without using a high-voltage element, and cuts off operation of the balancing switch when reverse voltage occurs. [Means for solving the problem]

[0015] According to an aspect of the present invention, a cell balancing device includes a balancing switching unit in which source terminals of a first switch and a second switch are commonly connected in series and respective drain terminals are connected in parallel to both ends of a battery cell; a latch unit interposed between a source terminal of the balancing switching unit and a detection pin of the battery cell, receiving an enable signal and an inverted enable signal, and outputting a driving voltage to a gate terminal of the balancing switching unit to drive the balancing switching unit; and a reverse voltage protection unit interposed between the source terminal of the balancing switching unit and the detection pin of the battery cell.

[0016] In the present invention, the reverse voltage protection unit is characterized by including a protective resistor and a reverse Zener diode.

[0017] In the present invention, the latch unit includes a first PMOS and a first NMOS in series between a detection pin and a source terminal of the balancing switching unit, a second PMOS and a second NMOS in series, a gate terminal of the first PMOS is connected to a source terminal of the second PMOS, a gate terminal of the second PMOS is connected to a source terminal of the first PMOS, a common node of the first PMOS and the first NMOS is connected to a gate terminal of the balancing switching unit, an inverted enable terminal is connected to a gate terminal of the first NMOS via a first high voltage capacitor, and an enable terminal is connected to a gate terminal of the second NMOS via a second high voltage capacitor.

[0018] In the present invention, the latch unit further includes a first diode and a first resistor in opposite directions respectively interposed between a gate terminal of the first NMOS and a source terminal of the balancing switching unit, and a second diode and a second resistor in opposite directions respectively interposed between a gate terminal of the second NMOS and a source terminal of the balancing switching unit.

[0019] In the present invention, the latch unit further includes a first Zener diode interposed in a reverse direction between a gate terminal of the first PMOS and a source terminal of the balancing switching unit, and a second Zener diode interposed in a reverse direction between a gate terminal of the second PMOS and a source terminal of the balancing switching unit.

[0020] The present invention is characterized in that it further includes a buffer for buffering the driving voltage output from the latch unit and outputting the buffered driving voltage to a gate terminal of the balancing switching unit.

[0021] In the present invention, the balancing switching unit includes a first switch and a forward diode connected in series to each other and connected in parallel to both ends of the battery cell.

[0022] The present invention is characterized in that it further includes an SR latch that receives the driving voltage and the inverted driving voltage output from the latch unit and outputs the driving voltage to a gate terminal of the balancing switching unit.

[0023] The present invention is characterized in that it further includes balancing resistors respectively interposed between both ends of the battery cell and the balancing switching unit. Effect of the Invention

[0024] A cell balancing device according to an embodiment of the present invention suppresses leakage current of a balancing switch connected in parallel to a battery cell without using a high-voltage element, and when a reverse voltage occurs, it can prevent a breakdown by cutting off the operation of the balancing switch. By configuring a switching driver circuit using general MOS elements, all channels can be configured in the same shape, making design and mass production easy and reducing the circuit area. [Brief description of the drawings]

[0025] [Figure 1] 1 is a circuit configuration diagram showing a cell balancing device according to a first embodiment of the present invention. [Diagram 2] FIG. 11 is a circuit diagram showing a cell balancing device according to a second embodiment of the present invention. [Diagram 3] FIG. 11 is a circuit diagram showing a cell balancing device according to a third embodiment of the present invention. [Figure 4] FIG. 11 is a circuit diagram showing a cell balancing device according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Hereinafter, a cell balancing device according to the present invention will be described with reference to the accompanying drawings. In the process, the thickness of lines and the size of components shown in the drawings may be exaggerated for clarity and convenience of the description. In addition, the terms used below are defined in consideration of the functions of the present invention, and may vary depending on the intention or practice of a user or operator. Therefore, the definitions of such terms should be based on the contents of this specification as a whole.

[0027] FIG. 1 is a circuit configuration diagram showing a cell balancing device according to a first embodiment of the present invention, FIG. 2 is a circuit configuration diagram showing a cell balancing device according to a second embodiment of the present invention, FIG. 3 is a circuit configuration diagram showing a cell balancing device according to a third embodiment of the present invention, and FIG. 4 is a circuit configuration diagram showing a cell balancing device according to a fourth embodiment of the present invention.

[0028] As shown in FIGS. 1 to 4, a cell balancing device according to an embodiment of the present invention may include a balancing switching unit 20, a latch unit 30, a reverse voltage protection unit 40, a buffer, and an SR latch.

[0029] As shown in FIG. 1, the balancing switching unit 20 is configured such that the source terminals VS of the first switch S1 and the second switch S2 are commonly connected in series and the drain terminals of each switch are connected in parallel to both ends BAL[N] and BAL[N-1] of the battery cell 10, thereby suppressing leakage current when a reverse voltage occurs.

[0030] At this time, by including a balancing resistor BAL_R interposed between both ends BAL[N], BAL[N-1] of the battery cell 10 and the balancing switching unit 20, when the balancing switching unit 20 is energized, the current output from the battery cell 10 flows through the balancing resistor BAL_R, thereby discharging the battery cell 10 that has been charged above a reference voltage value, thereby reducing the voltage of the battery cell 10.

[0031] On the other hand, the second switch S2 of the balancing switching unit 20 can be configured with a diode D0 as shown in FIG. 4 to suppress leakage current in response to a reverse voltage.

[0032] The latch unit 30 is interposed between the source terminal VS of the balancing switching unit 20 and the detection pin SEN[N] of the battery cell 10, and receives an enable signal EN and an inverted enable signal ENB, and outputs a driving voltage to the gate terminal VG of the balancing switching unit 20 to drive the balancing switching unit 20.

[0033] Here, in the latch section 30, a first PMOS (P1) and a first NMOS (N1) are connected in series between the detection pin SEN[N] and the source terminal VS of the balancing switching section 20, and a second PMOS (P2) and a second NMOS (N2) are connected in series.

[0034] At this time, the gate terminal of the first PMOS (P1) is connected to the source terminal of the second PMOS (P2), the gate terminal of the second PMOS (P2) is connected to the source terminal of the first PMOS (P1), a common node of the first PMOS (P1) and the first NMOS (N1) is connected to the gate terminal VG of the balancing switching unit 20, the inversion enable terminal ENB is connected to the gate terminal of the first NMOS (N1) via a first high-voltage capacitor C1, and the enable terminal EN is connected to the gate terminal of the second NMOS (N2) via a second high-voltage capacitor C2.

[0035] Here, the first high voltage capacitor C1 and the second high voltage capacitor C2 can transmit an enable signal and an inverted enable signal of the low voltage LV to the high voltage HV domain.

[0036] In addition, the latch unit 30 may further include a first diode D1 and a first resistor R1 in the opposite directions, respectively interposed between the gate terminal of the first NMOS (N1) and the source terminal VS of the balancing switching unit 20, and may further include a second diode D2 and a second resistor R2 in the opposite directions, respectively interposed between the gate terminal of the second NMOS (N2) and the source terminal VS of the balancing switching unit 20.

[0037] At this time, the first and second resistors R1, R2 and the first and second diodes D1, D2 can keep the voltages of the HVP and HVN nodes, which are the gate terminals of the first and second NMOS (N1, N2), at the lower voltage of the battery cell 10.

[0038] Therefore, the latch unit 30 receives the enable signal EN and the inverted enable signal ENB, and separates the peak voltage signals input to the HVP and HVN nodes to output a driving voltage that generates a voltage difference between the gate terminal VG and the source terminal VS of the balancing switching unit 20, thereby driving the balancing switching unit 20.

[0039] As shown in FIG. 2, the latch unit 30 further includes a first Zener diode ZD1 arranged in the reverse direction between the gate terminal of the first PMOS (P1) and the source terminal VS of the balancing switching unit 20, and a second Zener diode ZD2 arranged in the reverse direction between the gate terminal of the second PMOS (P2) and the source terminal VS of the balancing switching unit 20. This prevents the internal voltage of the latch unit 30 from increasing beyond a certain level, thereby protecting elements within the latch unit 30, even when the battery cell 10 is attached or detached or when an abnormal operation occurs.

[0040] The reverse voltage protection unit 40 is interposed between the source terminal VS of the balancing switching unit 20 and the detection pin SEN[N] of the battery cell 10, and when a reverse voltage occurs, it stops the operation of the balancing switching unit 20 and can adjust the voltage of the source terminal VS of the balancing switching unit 20 to the voltage of the detection pin SEN[N] in order to suppress leakage current.

[0041] In this case, the reverse voltage protection unit 40 may be configured with a protective resistor R0 as shown in FIG. 1, or may be configured with a reverse Zener diode ZD0 as shown in FIG.

[0042] On the other hand, as shown in FIG. 3, a buffer 50 may be added between the latch section 30 and the balancing switching section 20.

[0043] The buffer 50 buffers the driving voltage output from the latch unit 30 and outputs the buffered driving voltage to the gate terminal VG of the balancing switching unit 20, thereby reducing the load on the latch unit 30 and increasing the operating speed.

[0044] Furthermore, as shown in FIG. 4, an SR latch 60, which is a digital logic circuit, may be added between the latch section 30 and the balancing switching section 20.

[0045] The SR latch 60 receives the driving voltage OP and the inverted driving voltage ON output from the latch unit 30, outputs a driving voltage to the gate terminal VG of the balancing switching unit 20, and cuts off the feedback between the source terminal VS and the gate terminal VG of the balancing switching unit 20 to improve noise resistance.

[0046] Meanwhile, the balancing switching unit 20, the latch unit 30, the buffer 50, the SR latch 60, and the reverse voltage protection unit 40 according to the embodiment of the cell balancing device shown in FIGS. 1 to 4 may be configured in a cross-application manner.

[0047] As described above, according to the cell balancing device according to the embodiment of the present invention, it is possible to suppress leakage current of a balancing switch connected in parallel to a battery cell without using a high voltage element, and when a reverse voltage occurs, it is possible to prevent a breakdown by cutting off the operation of the balancing switch. Also, by configuring a switching driver circuit using general MOS elements, it is possible to configure all channels in the same form, which makes it easy to design and mass-produce, and reduces the circuit area.

[0048] Although the present invention has been described with reference to the embodiments shown in the drawings, this is by way of example only, and those having ordinary skill in the art will recognize that various modifications and equivalent alternative embodiments are possible.

[0049] Therefore, the true technical scope of the present invention should be defined by the following claims.

Claims

1. a balancing switching unit in which the source terminals of the first switch and the second switch are commonly connected in series and the drain terminals of the first switch and the second switch are connected in parallel to both ends of the battery cell; a latch unit interposed between a source terminal of the balancing switching unit and a detection pin of the battery cell, receiving an enable signal and an inverted enable signal, and outputting a driving voltage to a gate terminal of the balancing switching unit to drive the balancing switching unit; a reverse voltage protection unit interposed between a source terminal of the balancing switching unit and a detection pin of the battery cell.

2. The cell balancing device according to claim 1 , wherein the reverse voltage protection unit includes a protection resistor and a reverse Zener diode.

3. The latch portion is a first PMOS and a first NMOS are connected in series between the detection pin and a source terminal of the balancing switching unit, and a second PMOS and a second NMOS are connected in series between the detection pin and a source terminal of the balancing switching unit; 2. The cell balancing device of claim 1, wherein a gate terminal of the first PMOS is connected to a source terminal of the second PMOS, a gate terminal of the second PMOS is connected to a source terminal of the first PMOS, a common node of the first PMOS and the first NMOS is connected to a gate terminal of the balancing switching unit, an inverted enable terminal is connected to a gate terminal of the first NMOS via a first high voltage capacitor, and an enable terminal is connected to a gate terminal of the second NMOS via a second high voltage capacitor.

4. The latch portion is a first diode and a first resistor in a reverse direction, respectively interposed between a gate terminal of the first NMOS and a source terminal of the balancing switching unit, 4. The cell balancing device of claim 3, further comprising a second diode and a second resistor in a reverse direction, respectively interposed between a gate terminal of the second NMOS and a source terminal of the balancing switching unit.

5. The latch portion is a first Zener diode arranged in a reverse direction between a gate terminal of the first PMOS and a source terminal of the balancing switching unit, 4. The cell balancing device of claim 3, further comprising a second Zener diode arranged in a reverse direction between a gate terminal of the second PMOS and a source terminal of the balancing switching unit.

6. 2. The cell balancing device of claim 1, further comprising a buffer that buffers the driving voltage output from the latch unit and outputs the buffered driving voltage to a gate terminal of the balancing switching unit.

7. The cell balancing device of claim 1 , wherein the balancing switching unit comprises the first switch and a forward diode connected in series to each other and connected in parallel to both ends of the battery cell.

8. 2. The cell balancing device of claim 1, further comprising an SR latch receiving the driving voltage and an inverted driving voltage output from the latch unit and outputting the driving voltage to a gate terminal of the balancing switching unit.

9. The cell balancing device of claim 1 , further comprising balancing resistors respectively interposed between both ends of the battery cells and the balancing switching unit.

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