Occupant protection device

Abstract

To provide an occupant protection device capable of protecting occupants without delay.SOLUTION: An image captured by an imaging device is analyzed to determine whether there is an object approaching the vehicle. When it is determined that a collision between the object and the vehicle is unavoidable, an occupant can be protected without delay by activating an airbag device before the collision. By using selenium in a light receiving element of the imaging device, accurate images can be obtained even under low illumination. By capturing images using the global shutter method, accurate images with little distortion can be obtained. This allows for more accurate image analysis.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One aspect of the present invention relates to an occupant protection device. Or, one aspect of the present invention relates to an occupant protection device Regarding the method of operation.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. It is about the nature of matter.

[0003] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor characteristics. Therefore, semiconductor elements such as transistors and diodes and semiconductor circuits are considered semiconductor devices. The present invention also relates to a display device, a light-emitting device, a lighting device, an electro-optical device, an imaging device, and an electronic device. The above may include semiconductor elements and semiconductor circuits. Devices, electro-optical devices, imaging devices, electronic equipment, and the like may also include semiconductor devices. [Background technology]

[0004] In recent years, airbag devices that protect occupants from impacts during vehicle collisions have come into practical use. In general, the bag device detects the collision of the vehicle with an acceleration sensor and activates the gas supply device (inflation The airbag is inflated by the gas that is suddenly generated from the inflator. It has the function of protecting the occupants.

[0005] Airbag devices are steering wheel-mounted and instrument-mounted devices that are used to protect the driver. In addition to the ment panel mounted type, passenger seat airbags for the protection of passengers, rear seat airbags, Airbags for the rear seats are known for their protection of seat occupants. Side airbags protect passengers from sudden impacts, and airbags that deploy on the ceiling and seat Air belts with built-in airbags are also known.

[0006] In addition, the physique of the occupant, the relative position of the occupant and the airbag, the state of the seat belt, the child seat Detects the seat installation status and other factors to determine whether or not the airbag is deployed, its deployment status, and the method of deployment. Progress is also being made in putting so-called "smart airbags" into practical use.

[0007] Patent Document 1 discloses a side airbag device for a side collision, which is used when opening and closing a door. In order to prevent malfunction of the acceleration sensor due to collisions, an airbag that predicts collisions using electromagnetic waves and ultrasonic waves is being developed. Patent Document 2 discloses a collision prediction device that uses an image sensor to capture images. The impact force of the collision is estimated from the target, and the timing of the airbag device deployment and the inside of the airbag are also determined. The technical idea of ​​optimizing the pressure is disclosed. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 5-345556 [Patent Document 2] JP 2003-182508 A Summary of the Invention [Problem to be solved by the invention]

[0009] The collision prediction using electromagnetic waves or ultrasonic waves in Patent Document 1 can predict the distance between the vehicle and the object to be hit. Since it is not possible to estimate the collision target itself using only the vehicle speed, it is difficult to estimate the impact force that will occur during a collision. The method disclosed in Patent Document 2 is particularly difficult to image under low illumination conditions such as at night, as compared to existing images. This is difficult to achieve with a camera sensor (image capture device), so the accuracy of collision prediction is reduced. Compared to the front and rear views in the direction of travel, the view from the side changes at a faster rate. Therefore, side images taken while a vehicle is moving are easily distorted, making image analysis difficult. When the method disclosed in Patent Document 2 is used to predict a side collision, the accuracy of the collision prediction is There is a problem that

[0010] One aspect of the present invention is a vehicle seat that can protect an occupant without delay from an impact that occurs during a vehicle collision. One of the objectives is to provide an occupant protection device, etc. One of the objectives of the present invention is to provide an occupant protection device that can operate accurately even if the vehicle is in a collision. One of the objectives of the present invention is to provide a passenger protection device that can operate accurately even when the vehicle is moving. Alternatively, one of the objectives is to provide an occupant protection device capable of safely protecting occupants. Another object of the present invention is to provide a novel passenger protection device.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0012] One aspect of the present invention is an occupant protection device having an imaging device, a control device, and an airbag device. the imaging device includes a light receiving element including selenium and a transistor including an oxide semiconductor. The control device includes a means for predicting a collision using an image captured by the imaging device, and an airbag. and means for activating the locking device.

[0013] One aspect of the present invention is an occupant protection device having an imaging device, a control device, and an airbag device. the imaging device includes a light receiving element including selenium and a transistor including an oxide semiconductor. The control device includes a means for predicting a collision using an image captured by the imaging device, and a means for predicting the collision. and means for activating the airbag device before a collision based on the detected collision risk.

[0014] In the passenger protection device according to one embodiment of the present invention, it is preferable to use a plurality of image capture devices. It is preferable that the imaging device operates in a global shutter mode. It is preferable that the metal oxide contains at least one of In and Zn.

[0015] Note that one aspect of the present invention is not limited to vehicles such as automobiles and buses, but can be applied to any type of moving object. For example, railway vehicles such as trains and locomotives, and civil engineering vehicles such as cranes and bulldozers. Vehicles, manned robots, aircraft such as airplanes and helicopters, ships, submarines, spacecraft, etc. , can be applied to various moving objects. Effect of the Invention

[0016] Passenger protection devices that can quickly protect passengers from the impact that occurs during a vehicle collision. It is also possible to provide a passenger safety system that can operate accurately even under low light conditions such as at night. It is possible to provide a passenger protection device that can operate accurately even when the vehicle is moving. It is possible to provide a passenger protection device capable of safely protecting passengers. Alternatively, a novel passenger protection device or the like can be provided.

[0017] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. Effects other than these may also be included. The above is self-evident from the description, drawings, claims, etc. Other effects can be extracted from the claims and other descriptions. [Brief description of the drawings]

[0018] [Figure 1] FIG. 1 is a diagram illustrating a vehicle 100. [Diagram 2] FIG. 1 is a block diagram illustrating an occupant protection device according to one embodiment of the present invention. [Diagram 3] FIG. 2 is a diagram for explaining an example of the arrangement of imaging devices. [Figure 4] 4 is a flowchart illustrating an example of the operation of the passenger protection device. [Diagram 5] 4 is a flowchart illustrating an example of the operation of the passenger protection device. [Figure 6] 5A to 5C are diagrams illustrating an example of the operation of the passenger protection device. [Figure 7] 5A to 5C are diagrams illustrating an example of the operation of the passenger protection device. [Figure 8] 5A to 5C are diagrams illustrating an example of the operation of the passenger protection device. [Figure 9] 5A to 5C are diagrams illustrating an example of the operation of the passenger protection device. [Figure 10] 5A to 5C are diagrams illustrating an example of the operation of the passenger protection device. [Figure 11] 5A to 5C are diagrams illustrating an example of the operation of the passenger protection device. [Figure 12] 5A to 5C are diagrams illustrating an example of the operation of the passenger protection device. [Figure 13]5A to 5C are diagrams illustrating an example of the operation of the passenger protection device. [Figure 14] 5A to 5C are diagrams illustrating an example of the operation of the passenger protection device. [Figure 15] 5A to 5C are diagrams illustrating an example of the operation of the passenger protection device. [Figure 16] 5A to 5C are diagrams illustrating an example of the operation of the passenger protection device. [Figure 17] 5A to 5C are diagrams illustrating an example of the operation of the passenger protection device. [Figure 18] FIG. 1 is a diagram illustrating an example of the configuration of an imaging apparatus. [Figure 19] FIG. 2 is a diagram for explaining a configuration example of a peripheral circuit. [Figure 20] FIG. 1 is a diagram illustrating an example of the configuration of an imaging apparatus. [Figure 21] FIG. 2 illustrates an example of a circuit configuration. [Figure 22] FIG. 1 is a diagram illustrating an example of the configuration of an imaging apparatus. [Diagram 23] 1A to 1C illustrate examples of a transistor and a capacitor. [Figure 24] FIG. 2 is a diagram for explaining an energy band structure. [Diagram 25] 1A to 1C illustrate an example of a transistor. [Figure 26] FIG. 1 is a diagram illustrating an example of the configuration of an imaging apparatus. [Figure 27] FIG. 1 is a diagram illustrating an example of the configuration of an imaging apparatus. [Figure 28] FIG. 1 is a diagram illustrating an example of the configuration of an imaging apparatus. [Figure 29] FIG. 3 is a cross-sectional view illustrating a connection form of photoelectric conversion elements. [Diagram 30] 1A and 1B are diagrams illustrating an example of a curved imaging device. [Diagram 31] 1A to 1C illustrate an example of a transistor. [Diagram 32] 1A to 1C illustrate an example of a transistor. [Diagram 33] 1A to 1C illustrate an example of a transistor. [Diagram 34] 1A to 1C illustrate an example of a transistor. [Diagram 35] 1A to 1C illustrate an example of a transistor. [Diagram 36] 1A to 1C illustrate an example of a transistor. [Figure 37] FIG. 2 is a diagram for explaining an energy band structure. [Figure 38] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 39] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Diagram 40] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Diagram 41] Electron diffraction pattern of CAAC-OS. [Diagram 42] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. The present invention is not limited to the description of the following embodiments. It is not something that can be done.

[0020] In each figure described in this specification, the size of each structure, layer thickness, or area is not necessarily intended to clarify the invention. The figures may have been exaggerated or abbreviated for clarity and are not necessarily to scale. In addition, in a top view (also called a "plan view"), a perspective view, etc., In order to make the description easier to understand, some components may be omitted. Lines and other details may be omitted.

[0021] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The numbers are merely given to indicate the order or sequence of steps or lamination. In addition, even if a term is not accompanied by an ordinal number in this specification, etc., it is not necessary to confuse the constituent elements. In order to clarify the scope of the invention, ordinal numbers may be used in the claims. Even if a term is numbered in the first place, it may be numbered in the second place if a different ordinal number is used in the claims. In addition, even if a term is given an ordinal number in this specification, etc., In the claims, etc., ordinal numbers may be omitted.

[0022] In addition, when it is explicitly stated in this specification that X and Y are connected, is when X and Y are electrically connected and when X and Y are functionally connected. and the case where X and Y are directly connected are considered to be disclosed in this specification and the like. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. Any connections other than those shown in the drawings or text shall be deemed to be described in the drawings or text. do.

[0023] In the present specification, "parallel" means that, for example, two straight lines are at an angle of -10° or more and 10° or more. This refers to a state in which the lens is arranged at an angle below 5°. Therefore, this includes cases where the angle is between -5° and 5°. In addition, "perpendicular" and "orthogonal" mean, for example, the angle between two straight lines of 80° or more and 100° or less. This refers to a state in which the two objects are arranged at an angle of 85° or more and 95° or less.

[0024] In this specification, the terms "same," "the same," and "equal" are used to refer to counting values ​​and measurement values. " or "uniform" (including their synonyms), unless expressly stated The measurements are subject to a margin of error of plus or minus 20%.

[0025] In addition, in this specification, a high power supply potential VDD (hereinafter, simply referred to as "VDD" or "H potential") The low power supply potential VSS is a power supply potential that is higher than the low power supply potential VSS. VSS (hereinafter simply referred to as "VSS" or "L potential") is the potential lower than the high power supply potential VDD. The lowest power supply potential is also referred to as VDD or VSS. For example, if VDD is at ground potential, VSS is at a potential lower than ground potential, and V When SS is at ground potential, VDD is at a potential higher than ground potential.

[0026] The words "membrane" and "layer" may be interchangeable depending on the situation. For example, the term "conductive layer" can be used interchangeably with the term "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0027] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0028] (Embodiment 1) An occupant protection device 110 according to one embodiment of the present invention will be described with reference to the drawings. FIG. 1B is a perspective view showing the exterior of a vehicle 100 having an occupant protection device 110. 1(B) and the like are top views of the vehicle 100. In FIG. 1C, the airbag 108 is inflated. FIG. 2 is a block diagram of the passenger protection device 110. .

[0029] <<Example of configuration of vehicle 100 and occupant protection device 110>> The vehicle 100 has an imaging device 111a and an imaging device 111b in the front. On the left side, the camera has an imaging device 112a and an imaging device 112b. and imaging device 113b. Also, imaging device 114a and imaging device 114 Has b.

[0030] The vehicle 100 also has an airbag device 131 in the steering wheel 101 and a dash board. The door 102 has an airbag device 132. The door 103a has an airbag device 1 33a, and an airbag device 133b is provided in the door 103b. and an airbag device 134b in the door 104b. The vehicle 100 also includes a control device 120 .

[0031] The passenger protection device 110 includes the above-mentioned imaging device, the above-mentioned airbag device, and the control device 1. Specifically, the imaging device 111a, the imaging device 111b, the imaging device 112a, imaging device 112b, imaging device 113a, imaging device 113b, imaging device 114a and the image pickup device 114b are connected to the control device 120, and the airbag device 13 1, airbag device 132, airbag device 133a, airbag device 133b, airbag The airbag device 134a and the airbag device 134b are connected to the control device 120. (See Figure 2(A)).

[0032] The image capturing devices and the airbag devices are connected to the control device 120 by wired connection. A wired connection using metal wiring or the like may be used. This connection method is less susceptible to noise than wireless connection methods that use wireless communication, etc. Instead of metal wiring, optical fibers or the like may be used. On the other hand, when a wireless connection method is used, In addition, the amount of wiring used for connection can be reduced. Therefore, the passenger protection device 110 can be easily installed. It is possible.

[0033] In addition, a sensor 119 other than an imaging device may be connected to the control device 120 (see FIG. 2(B)). The sensor 119 may be, for example, an electromagnetic wave sensor, an ultrasonic sensor, an infrared sensor, Or, an acceleration sensor, etc. Even if multiple types of sensors 119 are connected to the control device 120, good.

[0034] The imaging device 111a and the imaging device 111b each have a function of capturing an image of an external scene ahead of the vehicle 100. The imaging device 112a and the imaging device 112b are located on the outside of the right side of the vehicle 100. The imaging device 113a and the imaging device 113b each have a function of capturing an image of the vehicle. The left side of both 100 is imaged by the imaging device 114a and the imaging device 114. b, each have the function of capturing an image of the external scene behind the vehicle 100.

[0035] For example, the images captured by the image capture device 112a and the image capture device 112b are sent to the control device 120. The control unit 120 compares the images and determines whether the vehicle 100 is approaching from the right side. The position and speed of the object are determined. It is preferable that the installation heights h from above are equal. The distance L between b is 50 cm or more, preferably 1 m or more, and more preferably 2 m or more. The longer the distance L, the higher the accuracy of detecting the position, speed, etc. of an object approaching the vehicle 100. The above items can be realized by the imaging device 111a and the imaging device 111b, the imaging device 113a and the imaging device 114a. The same is true for imaging device 113b, imaging device 114a and imaging device 114b.

[0036] Moreover, each of the imaging devices may be installed near the roof of the vehicle 100. By installing it in a high position, it is possible to capture images from a greater distance. In FIG. 3A, an image pickup device 111a and an image pickup device 111b, imaging device 112a, and imaging device 112b are installed near the roof of the vehicle 100. This provides an example of how to do this.

[0037] In addition, by increasing the number of imaging devices used, it is possible to obtain information such as the position and speed of an object approaching the vehicle 100. This can further improve the detection accuracy. In FIG. 3B and FIG. 3C, the imaging device 111 An example in which the imaging device 111c is provided between the imaging device 112a and the imaging device 111b, and 1 shows an example in which an imaging device 112c is provided between the imaging devices 112b.

[0038] In this embodiment, an example in which a plurality of imaging devices are provided in one direction is shown. An embodiment is not limited to this. Depending on the purpose and method of use, one imaging device may be used in one direction. In some cases, a.

[0039] <<Example of Operation of Passenger Protection Device 110>> Next, an example of the operation of the passenger protection device 110 will be described with reference to the drawings.

[0040] FIG. 4 shows a flowchart for explaining the operation of the passenger protection device 110. First, The external scene is captured by using each of the plurality of imaging devices (step S310). Each captured image is sent to the control device 120. The control device 120 then calculates the distance between the image and the From the distance L, a three-dimensional image is synthesized using a triangulation method or the like (step S320). The device 120 determines whether there is an object approaching the vehicle 100 from a previously synthesized 3D image. (Step S330). If there is no object approaching the vehicle 100, the process returns to step S310. This allows a new three-dimensional image to be synthesized.

[0041] If there is an object approaching the vehicle 100, the object is recognized as a collision target. The shape of the collision target is compared with the database to identify the type of collision target (step S 340) For example, the collision prediction objects are animals, people, motorcycles, small vehicles, large vehicles, walls, utility poles, etc. Depending on the type of collision prediction object, the collision prediction object is identified. The magnitude of the impact that the elephant gives to the vehicle 100 varies. 2D imaging combines electromagnetic, ultrasonic and / or infrared sensors This allows for more accurate identification.

[0042] Next, the control device 120 calculates a collision time from the type of the collision-predicted object and the relative speed. The magnitude of the impact is estimated (step S350).

[0043] Next, the control device 120 calculates the collision probability based on the change in the distance and the relative speed between the vehicle 100 and the collision target. Then, it is determined whether the collision-predicted object will collide with the vehicle 100 (step S360). If it is determined that the possibility of a collision is low, the process returns to step S310. If so, the control device 120 sends a signal to the airbag device to activate the airbag device. The transmitting airbag device is activated (step S370).

[0044] The pressure that is reached in the airbag is determined according to the magnitude of the impact at the time of the collision that was estimated earlier. By properly controlling the pressure inside the bag, optimal occupant protection can be achieved. In addition, an acceleration sensor is used to detect the impact immediately after the collision and adjust the pressure inside the airbag. In addition, the airbag device can be activated before a collision occurs, protecting the occupants without delay. It is possible.

[0045] According to one aspect of the present invention, a sufficient time is provided between the activation of the airbag device and the collision. Therefore, before a collision, the airbag is inflated using a mechanical method such as a pump, and after the collision, the airbag is inflated. The airbag can also be inflated rapidly using an inflator.

[0046] In addition, a plurality of inflators are provided in the airbag device, and the inflators are operated in sequence. The pressure and inflation speed of the airbag may be adjusted by the above-mentioned means. When inflators are provided, the explosive power of each inflator may be the same or different. It may be possible.

[0047] If multiple inflators are installed in an airbag device, the amount of explosives used per inflator increases. This reduces the possibility of secondary accidents occurring due to the deployment of the airbag device. In addition, the explosion sound caused by the inflator's operation can be reduced, improving the psychological well-being of passengers. It is also possible to reduce burdens, etc.

[0048] In addition, by installing multiple inflators in the airbag device, Even if a malfunction occurs in one inflator, the airbag device can be operated reliably by another inflator. Therefore, the redundancy of the airbag device can be improved. According to one aspect of the present invention, the device can be operated reliably and with high reliability. A high level of passenger protection can be achieved.

[0049] In addition, the above-mentioned method of inflating the airbag using a mechanical method such as a pump before the collision is used. If the collision is avoided at the last moment or if the collision is minor enough that the inflator does not need to be activated, In the event of a serious collision, the airbag can be stored and reused. In the installed airbag system, unused inflators may be discharged after the airbag system is deployed. If any remain, the airbag can be stored and reused. Since there is no need to replace the vehicle 100, the maintenance costs for the vehicle 100 can be reduced.

[0050] In addition, the impact of the collision was estimated before the collision using an imaging device, and the collision was detected. The airbag may then be inflated with a pressure and an inflation speed according to the estimation. The inflators may be operated simultaneously or sequentially.

[0051] A flow chart for explaining the operation of the passenger protection device 110 at this time is shown in FIG. In this case, the operation is the same as in FIG. 4 up to step S350, and then the collision prediction target is the vehicle 100. It is determined whether or not a collision has occurred (step S365). If the control unit 120 determines that a collision has occurred, the control unit 120 A signal for activating the airbag device is transmitted to the airbag device, and the airbag device is operated. (Step S370).

[0052] [Example 1] 6 to 8, the passenger protection device 1 when a vehicle 900 collides in front of the vehicle 100 will be described. An example of operation of 10 will be described.

[0053] First, the control device 120 calculates the following from the images captured by the imaging devices 111a and 111b: It is detected that the vehicle 900 is approaching the vehicle 100 (see FIG. 6). The device 120 estimates that the type of the vehicle 900 is an automobile based on the shape of the vehicle 900. The magnitude of the impact at the time of the collision is calculated based on the type of the vehicle 900 and the relative speed between the vehicle 100 and the vehicle 900. Estimate the size.

[0054] When the control device 120 judges that a collision is unavoidable, the airbag device 131 and the airbag 132 are activated before the collision. Then, the airbags 108 start to inflate (see FIG. 7). Immediately after the collision, the inflation of each airbag 108 is completed (see FIG. 8). The pressure within each airbag 108 is determined by the estimated magnitude of the impact.

[0055] In this way, the passengers can be protected without delay from the impact that occurs in the event of a vehicle collision.

[0056] [Example 2] 9 to 11, a passenger protection device for a vehicle 900 colliding with the right side of the vehicle 100 will be described. An example of the operation of the device 110 will be described.

[0057] First, the control device 120 calculates the following from the images captured by the imaging devices 112a and 112b: It is detected that the vehicle 900 is approaching the vehicle 100 (see FIG. 9). The device 120 estimates that the type of the vehicle 900 is an automobile based on the shape of the vehicle 900. The magnitude of the impact at the time of the collision is calculated based on the type of the vehicle 900 and the relative speed between the vehicle 100 and the vehicle 900. Estimate the size.

[0058] When the control device 120 judges that a collision is unavoidable, the airbag device 133a and the airbag 133b are activated before the collision. Then, each airbag 108 starts to inflate ( (See FIG. 10.) Immediately after the collision, the inflation of both airbags 108 is completed (See FIG. 11.) The pressure in each airbag 108 at this time is determined by the estimated magnitude of the impact. can be.

[0059] In this way, the passengers can be protected without delay from the impact that occurs in the event of a vehicle collision.

[0060] [Operation example 3] 12 to 14, a vehicle occupant in a case where a vehicle 900 collides with the rear of a vehicle 100 will be described. An example of the operation of the protection device 110 will now be described.

[0061] First, the control device 120 calculates the following from the images captured by the imaging devices 114a and 114b: It is detected that the vehicle 900 is approaching the vehicle 100 (see FIG. 12). From the shape of the vehicle 900, the device 120 estimates that the type of the vehicle 900 is an automobile. In addition, the type of vehicle 900 and the relative speed between the vehicle 100 and the vehicle 900 are used to calculate the impact of the collision. Estimate the size.

[0062] When the control device 120 judges that a collision is unavoidable, the airbag device 131 and the airbag 132 are activated before the collision. The airbag device 132, the airbag device 135a, and the airbag device 135b are activated. Then, each airbag 108 starts to inflate (see FIG. 13). The inflation of each airbag 108 is completed (see FIG. 14). The pressure within the bucket 108 is determined by the estimated magnitude of the impact.

[0063] In this way, the passengers can be protected without delay from the impact that occurs in the event of a vehicle collision.

[0064] [Operation example 4] 15 to 17, a passenger protection device for a vehicle 900 colliding with the front of the vehicle 100 will be described. An example of the operation of the device 110 will be described.

[0065] First, the control device 120 calculates the following from the images captured by the imaging devices 111a and 111b: It is detected that the vehicle 900 is approaching the vehicle 100 (see FIG. 15). From the shape of the vehicle 900, the device 120 estimates that the type of the vehicle 900 is an automobile. In addition, the type of vehicle 900 and the relative speed between the vehicle 100 and the vehicle 900 are used to calculate the impact of the collision. Estimate the size.

[0066] Here, the airbag device 131 and the airbag device 132 each have a plurality of inflation In addition, the control device 120 determines that the two-stage operation is performed based on the above estimation. It is deemed to be optimal.

[0067] When the control device 120 detects a collision of the vehicle 100 or the vehicle 900, the airbag device 13 1 operates the first inflator of the airbag device 132. Operate the inflator (see Figure 16).

[0068] Next, the control device 120 controls the second inflator of the airbag device 131 and the air The second inflator of the bag device 132 is activated (see FIG. 17).

[0069] By inflating the airbag 108 in multiple steps, the internal pressure and inflation of the airbag 108 can be controlled. The speed can be optimized, and therefore optimal occupant protection can be achieved.

[0070] The control device 120 determines the magnitude of the estimated impact, the collision angle between the vehicle and the object to be hit, etc. Therefore, the airbag device to be operated can be determined. In the case of a collision from the side, in addition to the airbag device 133a and the airbag device 133b, The bag device 131 and the airbag device 132 can also be operated.

[0071] In addition, an airbag device that deploys an airbag on the ceiling or floor of the vehicle 100 is provided, These are operated based on the estimated magnitude of the impact and the collision angle between the vehicle and the object being hit. For example, if the control device 120 detects a rollover or a possibility of rollover of the vehicle 100, Alternatively, airbags may be deployed on the ceiling or floor.

[0072] In addition, sensors will be installed inside the vehicle to estimate the presence or absence of passengers, their seating position, height, weight, etc., and to determine their behavior. The controller 10 may determine the airbag device to be deployed, the internal pressure of the airbag to be deployed, and the inflation speed.

[0073] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0074] (Embodiment 2) In this embodiment, an imaging device 115 that can be used for the imaging device shown in the first embodiment is The following will explain this with reference to the drawings.

[0075] <Configuration example of imaging device 115> 18A is a plan view showing a configuration example of the imaging device 115. The imaging device 115 has a pixel 140, a first circuit 260, a second circuit 270, a third circuit 280, and a fourth circuit In this specification, the first circuit 260 to the fourth circuit 290 are These may be referred to as "peripheral circuits" or "drive circuits." For example, the first circuit 260 is It can be considered part of the peripheral circuit.

[0076] 18B is a diagram showing a configuration example of the pixel section 140. The pixel section 140 has p columns and q rows (p and q is a natural number of 2 or more), a plurality of pixels 141 (imaging element) arranged in a matrix form. In FIG. 18B, n is a natural number between 1 and p, and m is a natural number between 1 and q. is a natural number.

[0077] For example, if the pixels 141 are arranged in a 1920 x 1080 matrix, a so-called full-width Resolution of 1080p (also called "2K resolution", "2K1K", "2K", etc.) It is possible to realize an imaging device 115 capable of imaging. When arranged in a 6 x 2160 matrix, it becomes what is known as ultra-high definition (4K resolution). An imaging device 11 capable of imaging at a resolution of 1080p (1080p, 1024p, 1024p, 1080 ... 5 can be realized. Also, for example, the pixel 141 can be arranged in a matrix of 8192 x 4320. When arranged in a grid, it produces what is known as super high-definition (8K resolution, 8K4K, It is possible to realize an imaging device 115 capable of capturing images at a resolution of up to 8K. By increasing the number of pixels 141, it is possible to realize an imaging device 115 capable of imaging at a resolution of 16K or 32K. It is also possible to achieve this.

[0078] The first circuit 260 and the second circuit 270 are connected to the plurality of pixels 141 and The first circuit 260 has a function of supplying a signal for driving the pixel 141. The third circuit may have a function of processing the analog signal output from the third circuit. 280 may have a function of controlling the operation timing of peripheral circuits. The clock signal may be generated by the external clock. The third circuit 280 may have a function of converting a frequency. (e.g., a ramp signal, etc.) may be provided.

[0079] 19 shows a configuration example of the first circuit 260. The first circuit 260 shown in FIG. The signal processing circuit 261 includes a signal processing circuit 262, a column driving circuit 262, and an output circuit 263. The circuit 264 is provided for each column. Noise removal using Correlated Double Sampling (CDS) method a circuit 264a capable of performing the above (also called a "CDS circuit"), a counter circuit 264 b, and a latch circuit 264c. The circuit 264 also has an analog-to-digital conversion function. The signal processing circuit 261 is a column-type analog-to-digital conversion device. It can function as such.

[0080] The circuit 264a includes a comparator, a switch, and a capacitor. The two input terminals are connected via a switch. and MEMS (Micro Electro Mechanical Systems) One terminal of the comparator is connected to the wiring 2 via a capacitance element. The other terminal of the comparator is connected to the wiring 123 provided for each column. The other terminal of the comparator is connected to the wiring 123 via a capacitance element. Good too.

[0081] The circuit 264a receives an analog signal (image data) input from the wiring 123 and a The potential of the reference potential signal (e.g., a ramp wave signal) input from is compared, and the H potential or The counter circuit 264b receives a clock signal from a wiring 268. A signal is input to the counter 264, and the H potential or L potential output from the circuit 264a is input to the counter 264. The circuit 264b measures the period during which the H potential or the L potential is input, and outputs the measurement result as an N-bit signal. The counter circuit 264c outputs the digital signal having the digital value. A set signal or a reset signal is input to 264b from a wiring 265. The latch circuit 264c has a function of holding the digital signal. A set signal or a reset signal is input from a wiring 266.

[0082] The column driver circuit 262 is also called a column selection circuit, a horizontal driver circuit, etc. A selection signal is generated to select a column from which the imaging data held in the latch circuit 264c is to be read out. The column driver circuit 262 may be configured with a shift register or the like. The columns are sequentially selected by the latch circuit 264c, and the imaging data output from the latch circuit 264c of the selected column is is input to the output circuit 263 via the wiring 269. The wiring 269 functions as a horizontal transfer line. It can be done.

[0083] The imaging data input to the output circuit 263 is processed by the output circuit 263 and output to the imaging device 11. The output circuit 263 may be configured, for example, as a buffer circuit. In addition, the output circuit 263 can control the timing of outputting a signal to the outside of the imaging device 115. The present invention may have a function to

[0084] The second circuit 270 generates and outputs a selection signal for selecting the pixel 141 from which the signal is to be read out. The second circuit 270 is called a row selection circuit or a vertical driver circuit. In this way, the image data, which is an analog signal, is converted into an N-bit digital value. It can be converted into a digital signal and output to the outside.

[0085] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier circuit, or a converter circuit. The transistors and the like used in the peripheral circuits are connected to the pixel driving circuit 11 described later. It may be formed by using a part of the semiconductor formed for manufacturing 2. A semiconductor device such as an IC chip may be used in part or in whole.

[0086] In addition, the peripheral circuits may be omitted from among the first circuit 260 to the fourth circuit 290. For example, the function of either the first circuit 260 or the fourth circuit 290 may be omitted. In addition to the other of the first circuit 260 or the fourth circuit 290, One of the circuits 290 may be omitted. Also, for example, the second circuit 270 or the third circuit The function of one of the circuits 270 and 280 is added to the other of the second circuit 270 or the third circuit 280. Either the second circuit 270 or the third circuit 280 may be omitted. Adding the functions of other peripheral circuits to any one of the circuits 260 to 290 Other peripheral circuits may be omitted.

[0087] In addition, as shown in FIG. 20, a pixel 20A shows a top view of the first circuit 260 to the fourth circuit 290. 20B is a top view of an imaging device 115 in which a pixel portion 140 is formed on the substrate 111. 21 is a perspective view for explaining the configuration of the imaging device 115 shown in FIG. 20(A).

[0088] By providing the pixel portion 140 above the first circuit 260 to the fourth circuit 290, The area occupied by the pixel section 140 relative to the size of the image device 115 can be increased. This can improve the light receiving sensitivity of the imaging device 115. In addition, the resolution of the imaging device 115 can be improved. In addition, the quality of the image captured by the imaging device 115 can be improved. The integration density of the device 115 can be increased.

[0089] <Circuit configuration example of pixel 141> An example of a circuit that can be used in the pixel 114 is shown in FIG. 21(A) to FIG. 2(C). 1(C).

[0090] In this specification, the terms "above" and "below" refer to the positional relationship of components directly above or below each other. For example, "the electrode on insulating layer A" is not limited to being below and in direct contact with the insulating layer A. If the expression is "electrode B", it is not necessary for electrode B to be formed directly on insulating layer A. The inclusion of other components between the edge layer A and the electrode B is not excluded.

[0091] The source and drain functions may also be different in some cases, such as when transistors of different polarities are used, or when When the direction of the current changes during operation of the circuit, the two are interchangeable depending on the operating conditions. Therefore, it is difficult to determine which is the source and which is the drain. In this specification, the terms source and drain may be used interchangeably. It shall be so.

[0092] Voltage is the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage can be rephrased as electric potential.

[0093] [Pixel circuit example 1] The circuit 610 shown in FIG. 21A includes a photoelectric conversion element 601, a transistor 602, a transistor The source or drain of the transistor 602 is connected to the transistor 604, and the capacitance element 606. One of the electrodes is electrically connected to the photoelectric conversion element 601, and the other is connected to the source or The other drain is electrically connected to the gate of the transistor 604 through a node 607. is.

[0094] The transistor 602 is a transistor in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed. It is preferable to use an OS transistor (also referred to as an OS transistor).

[0095] In an OS transistor, when the transistor is in the off state, the current that flows between the source and drain Since the off-state current (also referred to as the off-state current) can be made extremely small, the capacitor 606 can be Alternatively, as shown in FIG. 21B, the capacitor 606 can be omitted. In addition, when an OS transistor is used as the transistor 602, Therefore, it is possible to realize an imaging device that is less susceptible to noise. This can be done.

[0096] Note that an OS transistor may be used as the transistor 602. In the figure, it is clearly shown that OS transistors are preferred transistors. In order to distinguish between different transistors, the circuit symbol for the transistor may be marked with "OS."

[0097] The photoelectric conversion element 601 is a diode in which a pn-type or pin-type junction is formed on a silicon substrate. Alternatively, an amorphous silicon film or a microcrystalline silicon film may be used. Alternatively, a diode-connected transformer may be used. A variable resistor utilizing the photoelectric effect may also be used. It may be formed using tungsten, selenium, etc.

[0098] In addition, materials capable of absorbing radiation and generating electric charges are used as photoelectric conversion elements. The material capable of absorbing radiation and generating a charge may be iodine. Examples include lead iodide, mercury iodide, gallium arsenide, CdTe, and CdZn.

[0099] [Pixel circuit example 2] The circuit 610 shown in FIG. 21C uses a photodiode as the photoelectric conversion element 601. The circuit 610 shown in FIG. 21C includes a photoelectric conversion element 601, a transistor, A capacitor 602, a transistor 603, a transistor 604, a transistor 605, and a capacitor The transistor 602 has a photoelectric conversion element 606. The other end is electrically connected to the cathode of 601, and the other end is electrically connected to node 607 (charge storage section). The anode of the photoelectric conversion element 601 is electrically connected to the wiring 611. One of the source and drain of the transistor 603 is electrically connected to a node 607. The other end is electrically connected to a wiring 608. The gate of the transistor 604 is connected to a node 6 607, and one of the source and drain is electrically connected to the node 607 and the wiring 609. The other end is electrically connected to either the source or drain of the transistor 605. The other of the source and the drain of the transistor 605 is electrically connected to the wiring 608. One electrode of the capacitor 606 is electrically connected to a node 607, and the other One electrode is electrically connected to a wiring 611 .

[0100] The transistor 602 can function as a transfer transistor. A transfer signal TX is supplied to the transistor 603. The transistor 603 functions as a reset transistor. A reset signal RST is supplied to the gate of the transistor 603. Transistor 604 can function as an amplifying transistor. Transistor 605 can function as a selection transistor. The gate of the transistor 605 is supplied with a selection signal SEL. Moreover, VDD is supplied to the wiring 608, and VSS is supplied to the wiring 611.

[0101] Next, the operation of the circuit 610 shown in FIG. 3 is turned on to supply VDD to node 607 (reset operation). When transistor 603 is turned off, VDD is held at node 607. When the transistor 602 is turned on, the node 607 The potential of the transistor 602 is then changed (storage operation). Next, when the transistor 605 is turned on, the potential of the node 6 A potential corresponding to the potential of the terminal 07 is output from the wiring 609 (selection operation). By detecting this, the amount of light received by the photoelectric conversion element 601 can be known.

[0102] The transistors 602 and 603 are preferably OS transistors. As described above, the off-state current of an OS transistor can be extremely small. Therefore, the capacitance element 606 can be made smaller. Alternatively, the capacitance element 606 can be omitted. In addition, the transistors 602 and 603 can be OS transistors. When the potential of the node 607 is used, the potential of the node 607 is unlikely to fluctuate. It is possible to realize an imaging device.

[0103] <Global shutter method, rolling shutter method> In this way, the image pickup device 115 performs a reset operation, a storage operation, and a selection operation for each pixel 141. The pixel unit 140 is controlled as a whole to capture an image. The global shutter method and the rolling shutter method are known as imaging methods for controlling the There are.

[0104] In the global shutter method, the reset operation and the accumulation operation are performed almost simultaneously in all pixels 141. The readout operation is performed row by row. Therefore, a good image with little distortion can be obtained.

[0105] On the other hand, in the rolling shutter method, the accumulation operation is not performed simultaneously in all pixels 141. This is done row by row. Therefore, the timing of imaging is different for the first row and the last row. Therefore, the simultaneous capture of images in all pixels 141 is not ensured. In this case, the image will be significantly distorted.

[0106] To realize the global shutter system, the signal readout from each pixel must be completed sequentially. It is necessary to maintain the potential of the charge storage section for a long time until the charge storage section is fully charged. By using OS transistors for the transistors 602 and 603, On the other hand, the transistors 602 and 603 have channel formation regions When a transistor with a silicon region is used, the off-state current is high, so the charge The potential of the storage section cannot be maintained for a long period of time, making it difficult to use the global shutter method.

[0107] As described above, the use of an OS transistor in the pixel 141 enables the global shutter system to be realized. This can be easily achieved.

[0108] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0109] (Embodiment 3) In this embodiment, the imaging device 115 shown in the above embodiment is a type of solid-state imaging device. An example of a configuration using a CMOS image sensor will be described with reference to the drawings. 1 is a cross-sectional view of a portion of a pixel 141 included in the imaging device 115. 2 is a cross-sectional view of a part of the peripheral circuit. FIG. 23B shows an enlarged view of the capacitor 606. FIG. 25(B) is an enlarged view of a transistor 282. Note that the structure of the transistor 602 in this embodiment is the same as that in the above embodiment. The present invention can be applied to other transistors shown in FIG.

[0110] The imaging device 115 exemplified in this embodiment uses an n-type semiconductor as the substrate 401 . In addition, a p-type semiconductor 221 of the photoelectric conversion element 601 is provided in the substrate 401. A part of the substrate 401 functions as the n-type semiconductor 223 of the photoelectric conversion element 601 .

[0111] The transistor 281 is provided on a substrate 401. The transistor 281 is a p-type In addition, a p-type semiconductor wafer is formed on a portion of the substrate 401. The well 220 is formed in the same manner as the formation of the p-type semiconductor 221. The well 220 and the p-type semiconductor 221 can be formed at the same time. The transistor 282 is disposed on the well 220. The transistor 282 is an n-channel The transistors 281 and 282 can function as transistors of the same type. The channels are formed in a substrate 401 .

[0112] In addition, an insulating layer is formed on the photoelectric conversion element 601, the transistor 281, and the transistor 282. 403 is formed, and an insulating layer 404 is formed on the insulating layer 403 .

[0113] The insulating layer 403 is made of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, or the like. gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide Oxide materials such as tantalum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as silicon nitride Nitride materials such as silicon oxynitride, aluminum nitride, and aluminum oxynitride The insulating layer 403 can be formed as a single layer or a multilayer. It can be formed by using a D method, a thermal oxidation method, a coating method, a printing method, or the like.

[0114] The insulating layer 404 can be formed using a material and a method similar to those of the insulating layer 403. The insulating layer 403 and the insulating layer 404 are formed of oxygen, hydrogen, water, an alkali metal, an alkaline earth metal, It is preferable to form the insulating layer using an insulating material having a function of preventing the diffusion of impurities such as Either the insulating layer 403 or the insulating layer 404 may be omitted, or an insulating layer may be further laminated. This is also fine.

[0115] In addition, the imaging device 115 shown in this embodiment has an insulating layer 404 having a flat surface. The insulating layer 405 is formed using a material and a method similar to those of the insulating layer 403. The insulating layer 405 can be made of a low dielectric constant material (low-k material), siloxane, Resins, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. may also be used. In addition, the surface of the insulating layer 405 is subjected to chemical mechanical polishing (CMP). A chemical mechanical polishing (CMP) process may be performed. By performing CMP, the unevenness of the sample surface is reduced, and the insulating layer and conductive layer that will be formed later are prevented from being damaged. The coverage of the layer can be improved.

[0116] In addition, in the region where the insulating layer 403 to the insulating layer 405 overlap with the substrate 401 (n-type semiconductor 223), An opening 224 is formed in a region where the insulating layers 403 to 405 overlap with the p-type semiconductor 221. An opening 225 is formed in the opening 224. In addition, a contact plate is formed in the opening 224 and the opening 225. The contact plug 406 is formed in an opening in the insulating layer. The conductive material is, for example, tungsten or polysilicon. A conductive material with high embeddability, such as silicon, can be used. The side and bottom surfaces of the material are covered with a burr made of a titanium layer, a titanium nitride layer, or a laminate of these layers. In this case, the contact plug including the barrier film can be covered with a diffusion prevention layer. There are no particular restrictions on the number or arrangement of the openings 224 and 225. Therefore, an imaging device with a high degree of freedom in layout can be realized.

[0117] In addition, a wiring 421 and a wiring 429 are formed on the insulating layer 405. is electrically connected to the n-type semiconductor 223 via a contact plug 406 provided in the opening 224. The wiring 429 is connected to the contact plug 40 provided in the opening 225. 6 and is electrically connected to the p-type semiconductor 221 .

[0118] In addition, an insulating layer 407 is formed to cover the wiring 421 and the wiring 429. The insulating layer 407 can be formed of the same material and by the same method as the insulating layer 405. 7 The surface may be subjected to CMP treatment. By performing CMP treatment, the unevenness of the sample surface is reduced. This can reduce the amount of deposition of the insulating layer and the conductive layer formed thereafter, thereby improving the coverage of the insulating layer and the conductive layer formed thereafter.

[0119] The wires 421 and 429 are made of aluminum, titanium, chromium, nickel, copper, or yttrium. Lithium, zirconium, molybdenum, manganese, silver, tantalum, or tungsten, etc. The metal or alloy containing this metal as the main component can be used as a single layer structure or a multilayer structure. For example, a single-layer structure of a copper film containing manganese, or an aluminum film laminated on a titanium film, Two-layer structure, a two-layer structure in which an aluminum film is laminated on a tungsten film, a copper-magnesium- Two-layer structure with copper film laminated on aluminum alloy film, two-layer structure with copper film laminated on titanium film A two-layer structure in which a copper film is laminated on a tungsten film, a titanium film or titanium nitride film and its titanium An aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and then the aluminum film or the copper film is laminated on the titanium film or the titanium nitride film. A three-layer structure in which a titanium film or titanium nitride film is formed on the A film and an aluminum film or a copper film are layered on the molybdenum film or the molybdenum nitride film. A three-layer structure in which a molybdenum film or molybdenum nitride film is formed on top of the laminated film. For example, a three-layer structure is used in which a copper film is laminated on a tungsten film, and a tungsten film is then formed on top of that. In addition, titanium, tantalum, tungsten, molybdenum, chromium, nickel, An alloy film made by combining one or more of the elements selected from chromium, chromium, and scandium, or a nitride film may also be used.

[0120] In addition, indium tin oxide (ITO) and zinc oxide , indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide Indium oxide with titanium oxide, indium tin oxide with titanium oxide, indium Conductive materials containing oxygen, such as indium zinc oxide and indium tin oxide with added silicon oxide. Alternatively, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. It is also possible to form a laminated structure by combining a material containing the metal element and a conductive material containing oxygen. In addition, the multilayer structure of the material containing the above-mentioned metal element and the conductive material containing nitrogen can be obtained. A layer structure may also be used. In addition, the above-mentioned materials containing metal elements and conductive materials containing oxygen may also be used. Alternatively, a laminated structure may be formed by combining a conductive material containing nitrogen and the like.

[0121] The transistor 602, the transistor 289, and the capacitor 606 are formed in the insulating layer 408 and the insulating It is formed on an insulating layer 407 via an edge layer 409. Other transistors, etc. (not shown) Similarly to the transistor 602, the insulating layer 407 is formed through the insulating layer 408 and the insulating layer 409. In this embodiment, the transistor 602 and the transistor The transistor 289 is an example of a top-gate transistor, but the bottom-gate transistor A gate structure transistor may also be used.

[0122] In addition, the transistor may be an inverted staggered transistor or a forward staggered transistor. It is also possible to use a gate electrode. It is also possible to use a dual-gate transistor with a structure in which the transistor is sandwiched between two gates. The present invention is not limited to a transistor having a double-gate structure, but may be applied to a multi-gate transistor having multiple channel formation regions. Alternatively, the transistor may be a gate type transistor, for example a double gate type transistor.

[0123] In addition, the above transistors are available in planar, FIN, and TRI-GATE types. It is possible to use transistors of various configurations, such as tri-gate type and tri-gate type.

[0124] The transistors may have the same structure or different structures. The size of the transistor (e.g., channel length and channel width) may be All of the transistors in the imaging device 115 can be adjusted as needed. If the transistors have the same structure, they can be manufactured simultaneously in the same process. do.

[0125] The transistor 602 includes an electrode 243 that can function as a gate electrode and a source electrode 2, an electrode 244 that can function as either a source or drain electrode; The other electrode 245 can function as the drain electrode, and the other electrode 246 can function as the gate insulating layer. The semiconductor layer 242 includes an insulating layer 117 that can be used for the semiconductor device (see FIG. 23A).

[0126] In FIG. 22, a transistor 602 having a function as the other of the source electrode and the drain electrode is An electrode 245 that can function as one electrode of a capacitor 606 is provided. Both are formed using the electrode 245. However, one embodiment of the present invention is not limited to this. An electrode serving as the other of the source electrode and the drain electrode of the transistor 602, The electrodes that can function as one electrode of the capacitor element 606 are different electrodes. It may be formed using.

[0127] The capacitor 606 has an electrode that can function as one electrode of the capacitor 606. 245 and an electrode 273 that can function as the other electrode are disposed between an insulating layer 277 and a semiconductor The electrodes 273 are overlapped with a layer 272c (see FIG. 23(B)). The insulating layer 277 and the semiconductor layer 272c can be formed at the same time as the electrode 243. The insulating layer 277 can function as a dielectric. In addition, the semiconductor layer 272c can be formed simultaneously with the semiconductor layer 242c. Note that one of the insulating layer 277 and the semiconductor layer 272c may be omitted.

[0128] The insulating layer 408 prevents the diffusion of impurities such as oxygen, hydrogen, water, alkali metals, and alkaline earth metals. It is preferable to form the insulating layer using an insulating material having a function of preventing oxidation. Silicon, silicon oxynitride, silicon nitride, silicon nitride oxide, gallium oxide, gallium oxide Examples include fluorine oxide, yttrium oxide, aluminum oxide, and aluminum oxynitride. The insulating material is silicon nitride, gallium oxide, hafnium oxide, yttrium oxide. By using aluminum oxide or the like, impurities diffusing from the photoelectric conversion element 601 side are prevented from It is possible to prevent the metal from reaching the conductor layer 242. Note that the insulating layer 408 is formed by sputtering. The insulating layer 408 can be formed by a method such as a ring method, a CVD method, a vapor deposition method, or a thermal oxidation method. These materials can be used in a single layer or in a laminated form.

[0129] The insulating layer 409 can be formed of the same material and by the same method as the insulating layer 403. When an oxide semiconductor is used as the conductor layer 242, the insulating layer 409 is required to have a stoichiometric composition. It is preferable to form the insulating layer by using an insulating layer containing more oxygen than oxygen. When an insulating layer contains more oxygen than the oxygen that fills it, some of the oxygen is released by heating. Insulation layers that contain more oxygen than meets the theoretical composition are TDS analysis performed at a temperature between 700°C and 700°C, preferably between 100°C and 500°C The amount of oxygen released is 1.0×10 18 atoms / cm 3 That's all, Preferably 3.0 x 10 20 atoms / cm 3 The insulating layer is as described above.

[0130] In addition, an insulating layer that contains more oxygen than the stoichiometric composition is The treatment of adding oxygen can be carried out under an oxygen atmosphere. Heat treatment, ion implantation equipment, ion doping equipment, or plasma processing equipment is used. The gas for adding oxygen is: 16 O2 or 18 Acids such as O2 The gas used in the present specification may be nitrogen gas, nitrous oxide gas, ozone gas, or the like. The process of adding oxygen is also called "oxygen doping process."

[0131] The semiconductor layers of the transistor 602, the transistor 289, etc. are made of a single crystal semiconductor or a polycrystalline semiconductor. , microcrystalline semiconductors, nanocrystalline semiconductors, semi-amorphous semiconductors, amorphous semiconductors, etc. For example, amorphous silicon, microcrystalline germanium, etc. can be used. In addition, silicon carbide, gallium arsenide, oxide semiconductors, nitride semiconductors, etc. Compound semiconductors, organic semiconductors, etc. can be used.

[0132] In this embodiment, an oxide semiconductor is used for the semiconductor layer 242. The semiconductor layer 242 may be a single layer or a laminate of multiple layers. In this case, the semiconductor layers may be made of the same type of semiconductor material or different types of semiconductor materials. In this embodiment, the semiconductor layer 242 is preferably a semiconductor layer 242a, a semiconductor layer 242b, and A case where a semiconductor layer 242c and a semiconductor layer 242b are laminated will be described.

[0133] In this embodiment, the semiconductor layer 242a, the semiconductor layer 242b, and the semiconductor layer 242c are It is formed of a material containing either In or Ga, or both. Typically, it is In-Ga oxide. oxides containing In and Ga, In-Zn oxides (oxides containing In and Zn), In -M-Zn oxide (In, element M, and Zn oxide. Element M is Al, Ti, Ga , Y, Zr, La, Ce, Nd or Hf, and more than In. It is a metallic element with strong bonding strength with oxygen.

[0134] The semiconductor layer 242a and the semiconductor layer 242c are formed by removing the metal elements constituting the semiconductor layer 242b. In particular, it is preferable that the material is made of a material containing one or more kinds of the same metal element. When the material is used, the interface between the semiconductor layer 242a and the semiconductor layer 242b and the semiconductor layer This can prevent the occurrence of interface states at the interface between the semiconductor layer 242c and the semiconductor layer 242b. This makes it difficult for carriers to be scattered or captured at the interface, and the field effect mobility of the transistor is improved. In addition, it is possible to reduce the variation in the threshold voltage of the transistor. Therefore, it is possible to realize a semiconductor device having good electrical characteristics. It becomes.

[0135] The thickness of the semiconductor layer 242a and the semiconductor layer 242c is preferably 3 nm or more and 100 nm or less. The thickness of the semiconductor layer 242b is set to be 3 nm or more and 50 nm or less. 0 nm or less, preferably 3 nm to 100 nm, and more preferably 3 nm to 50 nm m or less.

[0136] The semiconductor layer 242b is an In-M-Zn oxide, and the semiconductor layer 242a and the semiconductor When the layer 242c is also an In-M-Zn oxide, the semiconductor layer 242a and the semiconductor layer 242 c is In:M:Zn=x1:y1:z1 [atomic ratio], and the semiconductor layer 242b is In:M:Z If n=x2:y2:z2 [atomic ratio], then y1 / x1 is greater than y2 / x2. The semiconductor layer 242a, the semiconductor layer 242c, and the semiconductor layer 242b are selected so as to Alternatively, the semiconductor layer 242a is arranged so that y1 / x1 is 1.5 times or more larger than y2 / x2. , the semiconductor layer 242c, and the semiconductor layer 242b. More preferably, y1 / x The semiconductor layer 242a, the semiconductor layer 242c, and the semiconductor layer 242c are arranged so that 1 is at least twice as large as y2 / x2. and the semiconductor layer 242b. More preferably, y1 / x1 is 3 times smaller than y2 / x2. The semiconductor layers 242a, 242c, and 242b are formed so that the At this time, in the semiconductor layer 242b, if y1 is equal to or larger than x1, the transistor However, if y1 is three times or more larger than x1, , the field effect mobility of the transistor is reduced, so y1 must be less than three times x1. By configuring the semiconductor layer 242a and the semiconductor layer 242c as described above, The dielectric layer 242a and the semiconductor layer 242c are less susceptible to oxygen deficiency than the semiconductor layer 242b. It can be a layer.

[0137] When the semiconductor layer 242a and the semiconductor layer 242c are made of In-M-Zn oxide, Z The content of In and element M, excluding n and O, is preferably less than 50 atomic % In. More preferably, the element M is 50 atomic % or more, and more preferably, the element In is less than 25 atomic %. The element M is 75 atomic % or more. When the oxide is a Zn-based alloy, the content of In and the element M, excluding Zn and O, is preferably 25% by weight. atomic % or more, element M is less than 75 atomic %, and more preferably In is 34a at least 66 atomic %, and element M is less than 66 atomic %.

[0138] For example, a semiconductor layer 242a containing In or Ga and a semiconductor layer 242c: In:Ga:Zn=1:3:2, 1:3:4, 1:3:6, 1:6:4, Or In-Ga-Zn oxide formed using a target with an atomic ratio of 1:9:6, etc. In-Ga oxide formed using a target with an atomic ratio of In:Ga=1:9 In addition, the semiconductor layer 242b may be made of In:Ga Zn=3:1:2, 1:1:1, 5:5:6, or 4:2:4.1 atomic ratio The In-Ga-Zn oxide formed using a target can be used. The atomic ratios of the semiconductor layer 242a, the semiconductor layer 242b, and the semiconductor layer 242c are each The atomic ratios above may vary by ±20%.

[0139] In order to provide a transistor using the semiconductor layer 242b with stable electrical characteristics, The impurities and oxygen vacancies in the semiconductor layer 242b are reduced to make the semiconductor layer 242b highly intrinsic. It is preferable that the oxide semiconductor layer be an oxide semiconductor layer that can be regarded as intrinsic or substantially intrinsic. The channel forming region in the semiconductor layer 242b is a semiconductor layer that can be regarded as intrinsic or substantially intrinsic. It is preferable to set the above.

[0140] Note that an oxide semiconductor layer that can be regarded as substantially intrinsic is an oxide semiconductor layer having a carrier density of , 8×10 11 / cm 3 Less than or equal to 1 × 10 11 / cm 3 Less than 1×10 -9 / cm 3 The oxide semiconductor layer is an oxide semiconductor layer having the above structure.

[0141] [Energy band structure of oxide semiconductors] Here, the semiconductor layer 242a, the semiconductor layer 242b, and the semiconductor layer 242c are stacked. The function and effect of the semiconductor layer 242 formed in the above-mentioned manner will be described with reference to the energy band shown in FIG. The following description will be given using a structural diagram. FIG. 24 shows the structure of the portion indicated by the dashed line C1-C2 in FIG. 23(A). FIG. 24 shows the energy band structure of the channel formation region of the transistor 602. The energy band structure is shown.

[0142] In Figure 24, Ec382, Ec383a, Ec383b, Ec383c, and Ec386 are The insulating layer 409, the semiconductor layer 242a, the semiconductor layer 242b, the semiconductor layer 242c, and the insulating The energy of the conduction band minimum of layer 117 is shown.

[0143] Here, the difference between the vacuum level and the conduction band minimum energy (also called "electron affinity") is The energy difference between the vacant level and the top of the valence band (also called the ionization potential) The energy gap is calculated by subtracting the energy gap from the spectroscopic ellipsometer ( It can be measured using HORIBA JOBIN YVON UT-300. The energy difference between the unoccupied level and the top of the valence band was determined by ultraviolet photoelectron spectroscopy (UPS). iolet Photoelectron Spectroscopy (PHI) It can be measured using a VersaProbe.

[0144] The In-Ga target with an atomic ratio of In:Ga:Zn=1:3:2 was used. The energy gap of a-Zn oxide is about 3.5 eV and the electron affinity is about 4.5 eV. In addition, the In- The energy gap of Ga-Zn oxide is about 3.4 eV and the electron affinity is about 4.5 eV. In addition, the In was formed using a target with an atomic ratio of In:Ga:Zn=1:3:6. The energy gap of Ga-Zn oxide is about 3.3 eV, and the electron affinity is about 4.5 eV. In addition, the I was formed using a target with an atomic ratio of In:Ga:Zn=1:6:2. The energy gap of n-Ga-Zn oxide is about 3.9 eV, and the electron affinity is about 4.3 eV. In addition, the film was formed using a target with an atomic ratio of In:Ga:Zn=1:6:8. The energy gap of In-Ga-Zn oxide is about 3.5 eV, and the electron affinity is about 4.4 e V. In addition, a target with an atomic ratio of In:Ga:Zn=1:6:10 was used. The energy gap of the In-Ga-Zn oxide is about 3.5 eV and the electron affinity is about 4. The energy of the target is 5 eV. The atomic ratio of In:Ga:Zn is 1:1:1. The energy gap of the synthesized In-Ga-Zn oxide is about 3.2 eV, and the electron affinity is about 4 .7 eV. In addition, a target with an atomic ratio of In:Ga:Zn=3:1:2 was used. The energy gap of the formed In-Ga-Zn oxide is about 2.8 eV, and the electron affinity is about It is 5.0 eV.

[0145] Since the insulating layer 409 and the insulating layer 117 are insulators, Ec382 and Ec386 are Closer to the vacuum level (lower electron affinity) than 3a, Ec383b, and Ec383c .

[0146] Also, Ec383a is closer to the vacuum level than Ec383b. is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0 .15eV or more and 2eV or less, 1eV or less, 0.5eV or less, or 0.4eV or less It is preferable that the level is close to an unoccupied level.

[0147] Also, Ec383c is closer to the vacuum level than Ec383b. is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0 .15eV or more and 2eV or less, 1eV or less, 0.5eV or less, or 0.4eV or less It is preferable that the level is close to an unoccupied level.

[0148] In addition, in the vicinity of the interface between the semiconductor layer 242a and the semiconductor layer 242b, and in the vicinity of the interface between the semiconductor layer 242b and the semiconductor layer 242a, In the vicinity of the interface with the semiconductor layer 242c, a mixed region is formed, so that the energy of the conduction band minimum That is, at these interfaces, the levels are almost nonexistent or nonexistent. stomach.

[0149] Therefore, in the stacked structure having the above energy band structure, the electrons Therefore, the interface between the semiconductor layer 242a and the insulating layer 409, Or, even if a level exists at the interface between the semiconductor layer 242c and the insulating layer 117, the level In addition, the boundary between the semiconductor layer 242a and the semiconductor layer 242b is There is almost no level at the interface between the semiconductor layer 242c and the semiconductor layer 242b. Therefore, the movement of electrons in the region is not hindered. The transistor 602 having a stacked conductor structure can achieve high field effect mobility. Cut.

[0150] As shown in FIG. 24, the interface between the semiconductor layer 242a and the insulating layer 409 and the semiconductor layer 2 In the vicinity of the interface between 42c and the insulating layer 117, a trap level 390 due to impurities and defects is formed. However, the semiconductor layer 242a and the semiconductor layer 242c are provided to form a semiconductor This can keep the layer 242b away from the trap level.

[0151] For example, the upper surface and side surfaces of the semiconductor layer 242b formed on the semiconductor layer 242a are In this manner, the semiconductor layer 242b may be covered with the semiconductor layer 242a and the semiconductor layer 242c. By covering the layer 242c, the influence of the trapping order can be further reduced. Cut.

[0152] However, if the energy difference between Ec383a or Ec383c and Ec383b is small, In this case, electrons in the semiconductor layer 242b may exceed the energy difference and reach the trap level. When electrons are captured in the trap level, a negative fixed charge is generated at the interface of the insulating layer, The threshold voltage of the transistor is shifted in the positive direction.

[0153] Therefore, the energy difference between Ec383a and Ec383c and Ec383b is When each of these is set to 0.1 eV or more, preferably 0.15 eV or more, the threshold voltage of the transistor is Since the voltage fluctuation is reduced and the electrical characteristics of the transistor can be improved, I wish.

[0154] The band gaps of the semiconductor layer 242a and the semiconductor layer 242c are It is preferable that the band gap is wider than that of b.

[0155] According to one embodiment of the present invention, a transistor with little variation in electrical characteristics can be provided. Therefore, a semiconductor device with little variation in electrical characteristics can be realized. According to one embodiment of the present invention, a highly reliable transistor can be realized. Therefore, a semiconductor device with excellent performance can be realized.

[0156] In addition, the band gap of oxide semiconductors is 2 eV or more, so A transistor that uses an oxide semiconductor for a semiconductor layer can have an extremely small off-state current. Specifically, the off-current per 1 μm of channel width is 1×10 -20 A less than 1×10 -22 A, more preferably less than 1×10 -24 Less than A That is, the on / off ratio can be set to 20 digits or more and 150 digits or less.

[0157] According to one embodiment of the present invention, a transistor with low power consumption can be realized. As a result, an imaging device or semiconductor device with low power consumption can be realized.

[0158] In addition, since the off-state current of the OS transistor is extremely low, the transistor 602 is By using a transistor, the capacitance element 606 can be made smaller. In addition, the light receiving area of ​​the transistor 602 can be increased. By using a transistor, the current that unintentionally flows between the source and drain ("leakage current") (also called "leak current"). Therefore, the imaging device 115 It is possible to reduce power consumption. In addition, it is possible to prevent noise from being mixed into the electrodes 244 and 245. This can reduce the amount of data required to capture an image, thereby improving the quality of the image captured by the image capture device 115. Moreover, it is possible to provide a highly reliable imaging device 115.

[0159] According to one embodiment of the present invention, an imaging device or a semiconductor device with high light-receiving sensitivity can be realized. According to one embodiment of the present invention, an imaging device or a semiconductor device having a wide dynamic range can be realized. It can be realized.

[0160] In addition, since an oxide semiconductor has a wide band gap, a semiconductor device using an oxide semiconductor is not available. According to one aspect of the present invention, an imaging device having a wide operating temperature range is provided. and a semiconductor device.

[0161] The above-mentioned three-layer structure is an example. For example, the semiconductor layer 242a or the semiconductor layer 242c Alternatively, a two-layer structure in which one of the layers is not formed may be used.

[0162] [Oxide semiconductors] Here, oxide semiconductors that can be used for the semiconductor layer 242 will be described in detail.

[0163] <Structure of oxide semiconductor> The structure of an oxide semiconductor will be described below.

[0164] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide semiconductor Conductor, nc-OS (nanocrystalline oxide semiconductor) ctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous li ke oxide semiconductor), and amorphous oxide semiconductor.

[0165] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC-O S, polycrystalline oxide semiconductor, and nc-OS.

[0166] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angles are flexible and the bond length is short. In other words, it is a structure that has order but does not have long-range order.

[0167] On the other hand, in the case of an essentially stable oxide semiconductor, It cannot be called an oxide semiconductor. The oxide semiconductor (for example, having a periodic structure in a microscopic region) is transformed into a completely amorphous oxide. It cannot be called a semiconductor. However, a-like OS is a periodic Although it has a structure, it has voids and is an unstable structure. Its physical properties are similar to those of an amorphous oxide semiconductor.

[0168] <caac-os> First, let me explain about CAAC-OS.

[0169] CAAC-OS is an oxide semiconductor that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a conductor.

[0170] Transmission Electron Microscope (TEM) A composite analysis image (high resolution) of the bright-field image and the diffraction pattern of CAAC-OS was obtained by using a scope. When observing the high-resolution TEM image, multiple pellets can be confirmed. In the high-resolution TEM image, the boundaries between the pellets, i.e., grain boundaries, are not clearly visible. Therefore, it is not possible to clearly confirm the presence of the CAAC-OS. Therefore, it can be said that the decrease in electron mobility caused by the above phenomenon is unlikely to occur.

[0171] The CAAC-OS observed by TEM will be described below. This shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction (SAC) is required. The spherical aberration corrector function was used. In particular, it is called a Cs-corrected high-resolution TEM image. This was carried out using an atomic resolution analytical electron microscope, such as the JEM-ARM200F manufactured by Nippon Denki Co., Ltd. This can be done.

[0172] FIG. 38(B) shows an enlarged Cs-corrected high-resolution TEM image of region (1) in FIG. 38(A). From FIG. 38(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is the same as that of the surface on which the CAAC-OS film is formed (also called the surface on which the film is formed). The surface on which the CAAC-OS is formed or the top surface of the CAAC-OS reflects the unevenness of the surface on which the CAAC-OS is formed or the top surface of the CAAC-OS.

[0173] As shown in Figure 38(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines in Figure 38(B) and Figure 38(C). Therefore, the size of each pellet can be 1 nm or more, or 3 nm or more. It can be seen that the size of the gap caused by the tilt between the plate and the pellet is about 0.8 nm. Therefore, the pellets can also be called nanocrystals (nc). In addition, CAAC-OS is also used as a C-Axis Aligned Nanocry The semiconductor may also be referred to as an oxide semiconductor having a stals structure.

[0174] Here, based on the Cs-corrected high-resolution TEM image, the pellet of CAAC-OS on the substrate 5120 was The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 38(D)). The inclination between the pellets observed in FIG. 38(C) The location where the crack occurs corresponds to an area 5161 shown in FIG.

[0175] FIG. 39(A) shows the Cs Corrected high-resolution TEM images are shown for regions (1), (2), and (3) in FIG. 39(A). The enlarged Cs-corrected high-resolution TEM images are shown in Fig. 39(B), Fig. 39(C) and Fig. 39(D). From Fig. 39(B), Fig. 39(C) and Fig. 39(D), the pellet is It can be seen that the metal atoms are arranged in triangular, tetragonal or hexagonal shapes. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0176] Next, the CA analyzed by X-ray diffraction (XRD) We will explain AC-OS. For example, CAAC-OS with InGaZnO4 crystals When the out-of-plane method is used to analyze the structure, the results are as shown in Figure 40(A). A peak may appear at a diffraction angle (2θ) of about 31°. Since the crystal orientation of CAAC-OS is attributed to the (009) plane of nO4, the crystal orientation of CAAC-OS is considered to be c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0177] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31° In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks near the c-axis indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. The more preferable CAAC-OS is the structure solution by the out-of-plane method. In the analysis, a peak is observed at 2θ of approximately 31°, but no peak is observed at 2θ of approximately 36°.

[0178] On the other hand, in-plan X-ray irradiation is performed on CAAC-OS in a direction perpendicular to the c-axis. When the structure is analyzed by the δ method, a peak appears at 2θ of about 56°. This peak is due to In It is assigned to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was rotated around the normal vector of the sample surface as the axis (φ axis) while performing the analysis. Even if a φ scan is performed, no clear peak appears as shown in FIG. However, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ shift is In the case of scanning, as shown in FIG. 40(C), the peaks belonging to the crystal plane equivalent to the (110) plane Therefore, from the structural analysis using XRD, CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0179] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe with a diameter of 300 nm was placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern (selected area transmission electron diffraction) like that shown in Figure 41(A) is obtained. This diffraction pattern may show the InGaZnO4 This includes spots due to the (009) plane of the crystal. Therefore, even with electron diffraction, The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is approximately aligned on the surface to be formed or the upper surface. On the other hand, the same sample was probed perpendicular to the sample surface. The diffraction pattern when an electron beam with a diameter of 300 nm is incident is shown in FIG. (B) shows a ring-shaped diffraction pattern. Therefore, by electron diffraction, It is seen that the a-axis and b-axis of the pellets contained in the CAAC-OS have no orientation. In addition, the first ring in FIG. 41(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane and other factors. The second ring in Figure 41(B) This is thought to be due to the (110) plane, etc.

[0180] As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the inclusion of impurities or the formation of defects, so the opposite view is taken. CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0181] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more abundant than metal elements such as silicon that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor and rearrange the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and nitrogen Carbon oxide and other elements have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes the crystallinity to decrease.

[0182] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in an oxide semiconductor can become carrier traps or can displace carriers. In addition, oxygen vacancies in oxide semiconductors can become carrier traps. In some cases, they act as carrier generation sources by capturing hydrogen.

[0183] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 Less than More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than a career Such an oxide semiconductor can be a high-purity intrinsic or It is essentially a high-purity intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and In other words, it can be said that the oxide semiconductor has stable characteristics.

[0184] <nc-os> Next, we will explain nc-OS.

[0185] In the high-resolution TEM image, the nc-OS is divided into two groups: one where the crystals can be confirmed, and the other where the crystals can be clearly confirmed. The nc-OS has regions where no crystalline parts can be confirmed. The size is often between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor having a crystal size of 10 nm or more and 100 nm or less is called a microcrystalline oxide. For example, in high-resolution TEM images, nc-OS shows grain boundaries. In addition, the nanocrystals are different from the pellets in CAAC-OS. Therefore, in the following, the crystalline part of nc-OS is called pellets. There may be cases where this happens.

[0186] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). The nc-OS has periodic atomic arrangement in the sub-nm region. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be considered to be a-like OS or amorphous oxide semiconductor. For example, for nc-OS, the X-shaped pellets with a diameter larger than that of the pellets may not be distinguishable. When using the line, the peaks showing the crystal planes were not detected by the out-of-plane method. In addition, for nc-OS, a probe diameter larger than the pellet (e.g. 50n When electron diffraction is performed using an electron beam of 1000 nm or more, a halo-like diffraction pattern is observed. On the other hand, for nc-OS, the size of the pellet is close to or smaller than that of the pellet. When performing nanobeam electron diffraction using an electron beam with a diameter of n When nanobeam electron diffraction is performed on c-OS, bright spots appear in a circular (ring-like) pattern. In some cases, a ring-shaped area may be observed. In addition, multiple spots may be observed within the ring-shaped area. There are cases.

[0187] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0188] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0189] <a-like OS> The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a conductor.

[0190] In a-like OS, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where crystals can be clearly seen and areas where crystals cannot be seen. and areas where it is not possible to

[0191] Because of the porosity, the a-like OS is an unstable structure. To demonstrate that the OS has a less stable structure compared with CAAC-OS and nc-OS. , shows the change in structure due to electron irradiation.

[0192] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS ( Sample B) and CAAC-OS (sample C) are prepared. The sample in is also an In-Ga-Zn oxide.

[0193] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that each of the samples has a crystalline portion.

[0194] The determination of which part is regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, including six layers, stacked in layers in the c-axis direction. The spacing between adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The area where the spacing is 0.28 nm or more and 0.30 nm or less is considered to be the crystal part of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0195] Figure 42 shows the average crystal size (average crystal size) of each sample (22 to 45 points). This is an example of investigating the size of the crystal part. Note that the length of the lattice fringes mentioned above is the size of the crystal part. From Figure 42, the cumulative electron dose of the a-like OS is Specifically, the crystal part becomes larger according to the (1) in FIG. As shown in the figure, the crystal part (initial nucleus) which was about 1.2 nm in size at the beginning of the TEM observation ), but the cumulative exposure is 4.2 × 10 8 e - / nm 2 In the case of On the other hand, the nc-OS and CAAC-OS have grown to a size of 100 nm. The cumulative electron dose from the start of irradiation was 4.2×10 8 e - / nm 2 In the range of It can be seen that there is no change in size. Specifically, in (2) and (3) in Figure 42, As shown in the figure, the crystalline parts of the nc-OS and CAAC-OS are largely different regardless of the cumulative electron irradiation dose. The sizes are found to be approximately 1.4 nm and 2.1 nm, respectively.

[0196] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, the growth of the crystals in the nc-OS and CAAC-OS was hardly observed by electron irradiation. In other words, a-like OS is not seen in nc-OS and CAAC-OS. It can be seen that compared with S, it has a less stable structure.

[0197] In addition, because of the porosity, a-like OS is more resistant to vascular endothelial cell proliferation than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is lower than that of a single crystal of the same composition. The density of nc-OS is 78.6% or more and less than 92.3% of that of CAAC. The density of the -OS is 92.3% or more and less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0198] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a hexagonal crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It is less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0199] In addition, there are cases where single crystals with the same composition do not exist. In such cases, the composition may differ in any ratio. By combining single crystals, we estimate the density equivalent to a single crystal of the desired composition. The density corresponding to a single crystal of a desired composition can be determined by combining single crystals of different compositions. The weighted average of the proportion of It is preferable to estimate by combining different types of single crystals.

[0200] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, The CAAC-OS may be a laminated film having two or more kinds.

[0201] In addition, the oxide applicable to the semiconductor layer 242a, the semiconductor layer 242b, and the semiconductor layer 108c may be An example of a semiconductor is an oxide containing indium. For example, when indium is included, the carrier mobility (electron mobility) increases. The body preferably contains the element M. The element M is preferably aluminum, gallium, yttrium, or yttrium. Thorium or tin. Other elements that can be used for M include boron, Silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum , cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. However, the element M may be a combination of two or more of the above elements. is, for example, an element with high bond energy with oxygen. Element M is, for example, an oxide Zinc is an element that has the function of widening the energy gap. When the oxide contains zinc, for example, the oxide becomes easier to crystallize.

[0202] However, the oxide semiconductor is not limited to an oxide containing indium. For example, zinc tin oxide, gallium tin oxide, and gallium oxide may be used.

[0203] In addition, oxide semiconductors are made of oxides with a large energy gap. The energy gap is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more. The energy is set to 3.8 eV or less, and more preferably, to 3 eV or more and 3.5 eV or less.

[0204] The effect of impurities in an oxide semiconductor will be described below. In order to stabilize the electrical characteristics of the oxide semiconductor, it is necessary to reduce the impurity concentration in the oxide semiconductor and to achieve a low carrier density. In order to reduce the impurity concentration in the oxide semiconductor, it is effective to increase the purity of the oxide semiconductor. In order to achieve this, it is preferable to also reduce the impurity concentration in adjacent films.

[0205] For example, silicon in an oxide semiconductor can become a carrier trap or a carrier generation source. Therefore, the silicon concentration in the oxide semiconductor is measured by secondary ion mass spectrometry (SIMS). Secondary Ion Mass Spectrometry (1×1 0 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than, more Preferably 2 x 10 18 atoms / cm 3 Less than.

[0206] Furthermore, when hydrogen is contained in an oxide semiconductor, the carrier density may be increased. The hydrogen concentration of the oxide semiconductor was 2×10 20 atoms / cm 3 below, Preferably 5 x 10 19 atoms / cm 3 Less than or equal to 1×10 19 atom s / cm 3 Less than 5×10, more preferably 18 atoms / cm 3 The following applies. Also, When nitrogen is contained in an oxide semiconductor, the carrier density may increase. The nitrogen concentration of the semiconductor is 5×10 19 atoms / cm 3 Less than, preferred Or 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0207] In order to reduce the hydrogen concentration in the oxide semiconductor, the insulating layer 409 in contact with the semiconductor layer 242 is It is preferable to reduce the hydrogen concentration in the insulating layer 409 and the insulating layer 117. The hydrogen concentration in the sample was 2×10 20 atoms / cm 3 Less than or equal to 5x 10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 below , and more preferably 5 × 10 18 atoms / cm 3 In addition, the oxide semiconductor In order to reduce the nitrogen concentration, it is preferable to reduce the nitrogen concentration in the insulating layer 409 and the insulating layer 117. The nitrogen concentration of the insulating layer 409 and the insulating layer 117 is preferably 5×10 1 9 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 The following is more preferred: Or 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0208] In this embodiment, first, the semiconductor layer 242a is formed on the insulating layer 409, and the semiconductor layer 242 A semiconductor layer 242b is formed on the substrate 242a.

[0209] Note that the oxide semiconductor layer is preferably formed by a sputtering method. The sputtering methods include RF sputtering, DC sputtering, and AC sputtering. The DC sputtering method or the AC sputtering method can be used. It is possible to form a film with better uniformity than the F sputtering method.

[0210] In the present embodiment, the semiconductor layer 242a is formed using an In-Ga-Zn oxide target (In :Ga:Zn=1:3:2) was used to deposit a 20 nm thick In-Ga The semiconductor layer 242a is formed of a-Zn oxide. The constituent elements and composition applicable to the semiconductor layer 242a are This is not limited to the above.

[0211] In addition, oxygen doping treatment may be performed after the semiconductor layer 242a is formed.

[0212] Next, the semiconductor layer 242b is formed on the semiconductor layer 242a. As the layer 242b, an In-Ga-Zn oxide target (In:Ga:Zn=1:1:1 ) to form a 30 nm thick In-Ga-Zn oxide film by sputtering. However, the constituent elements and compositions applicable to the semiconductor layer 242b are not limited to those described above. stomach.

[0213] In addition, an oxygen doping treatment may be performed after the semiconductor layer 242b is formed.

[0214] Next, impurities such as moisture or hydrogen contained in the semiconductor layers 242a and 242b are removed. In order to further reduce the amount of fluorine and to highly purify the semiconductor layers 242a and 242b, A heat treatment may be carried out.

[0215] For example, the method may be carried out under a reduced pressure atmosphere, an inert atmosphere such as nitrogen or a rare gas, an oxidizing atmosphere, or an ultra-dry atmosphere. Dry air (measured using a CRDS (cavity ring down laser spectroscopy) type dew point meter The moisture content when the air is cooled should be 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less. The semiconductor layer 242a and the semiconductor layer 242b are exposed to a fluorine-containing gas (preferably air) atmosphere of 10 ppb or less. The oxidizing atmosphere is an oxidizing atmosphere such as oxygen, ozone, or nitrogen oxide. An inert atmosphere is an atmosphere containing 10 ppm or more of oxidizing gases. This refers to an atmosphere in which the gas concentration is less than 10 ppm and which is filled with nitrogen or a rare gas.

[0216] In addition, by performing heat treatment, impurities are released and oxygen contained in the insulating layer 409 is also removed. The semiconductor layer 242a and the semiconductor layer 242b are diffused. It is possible to reduce the oxygen deficiency of 242b. In addition, after heat treatment in an inert gas atmosphere, Heat treatment is performed in an atmosphere containing oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. Note that the heat treatment may be performed at any time after the formation of the semiconductor layer 242b. For example, heat treatment may be performed after selective etching of the semiconductor layer 242b.

[0217] The heat treatment is carried out at a temperature of 250° C. to 650° C., preferably 300° C. to 500° C. The treatment time should be within 24 hours. Heat treatment for more than 24 hours will lead to a decrease in productivity. Therefore, it is not desirable.

[0218] Next, a resist mask is formed on the semiconductor layer 242b. The insulating layer 242a and the semiconductor layer 242b are selectively etched. A part of 409 may be etched, forming a protrusion in insulating layer 409 .

[0219] The semiconductor layer 242a and the semiconductor layer 242b can be etched by a dry etching method or a wafer etching method. After etching is completed, the resist mask is removed. Remove.

[0220] The transistor 602 is provided on the semiconductor layer 242b and in contact with a part of the semiconductor layer 242b. , electrodes 244 and 245. Electrodes 244 and 245 (the same layer The other electrodes or wirings formed by the method described above are formed by using the same material as the wiring 421. It is possible.

[0221] The transistor 602 has a semiconductor layer 242b, an electrode 244, and an electrode 245. The semiconductor layer 242c includes a semiconductor layer 242b, an electrode 244, and a conductor layer 242c. It contacts a portion of each of the electrodes 245 .

[0222] In this embodiment, the semiconductor layer 242c is grown using an In-Ga-Zn oxide target (In:Ga The semiconductor layer 24 is formed by a sputtering method using a metal oxide film (Zn:Zn=1:3:2). The constituent elements and compositions applicable to 2c are not limited to those described above. For example, a semiconductor layer Gallium oxide may be used as the semiconductor layer 242c. may be carried out.

[0223] The transistor 602 further includes an insulating layer 117 over the semiconductor layer 242c. The insulating layer 117 can function as a gate insulating layer. The insulating layer 117 may be formed by performing oxygen doping treatment. good.

[0224] After the semiconductor layer 242c and the insulating layer 117 are formed, a mask is formed on the insulating layer 117, and the semiconductor layer 242c is The insulating layer 242c and a portion of the insulating layer 117 are selectively etched to form an island-shaped semiconductor layer 24 2c, and the insulating layer 117 may be an island-shaped layer.

[0225] The transistor 602 also has an electrode 243 on the insulating layer 117. The wiring 421 and the other electrodes or wirings (including other electrodes or wirings formed in the same layer) are made of the same material and It can be formed by the method.

[0226] In this embodiment, an example in which the electrode 243 is a laminate of the electrodes 243a and 243b is shown. For example, the electrode 243a is made of tantalum nitride, and the electrode 243b is made of copper. 243a acts as a barrier layer to prevent the diffusion of copper elements. Therefore, a high-performance semiconductor device can be realized.

[0227] The transistor 602 further includes an insulating layer 418 that covers the electrode 243. The insulating layer 418 can be formed using a material and a method similar to those of the insulating layer 409. An elemental doping process may be performed. Also, a CMP process may be performed on the surface of the insulating layer 418.

[0228] Further, an insulating layer 439 is provided over the insulating layer 418 , and an insulating layer 419 is provided over the insulating layer 439 . The insulating layer 439 and the insulating layer 419 are formed using a material and a method similar to those of the insulating layer 405. In addition, a CMP process may be performed on the surface of the insulating layer 419. This reduces the unevenness of the sample surface and improves the coverage of the insulating and conductive layers that will be formed later. In addition, openings may be formed in parts of the insulating layer 419, the insulating layer 439, and the insulating layer 418. A contact plug is formed in the opening.

[0229] In addition, on the insulating layer 419, a wiring 427 and a wiring 444 (formed in the same layer as these) are provided. The wiring 444 is formed on the insulating layer 419 and the insulating layer In the opening provided in 418, the electrode 273 is electrically connected via a contact plug. The wiring 427 is provided in an opening in the insulating layer 419 and the insulating layer 418. The semiconductor layer 242 is electrically connected to the electrode 243 via a contact plug.

[0230] The imaging device 115 also includes a wiring 427 and a wiring 444 (which are formed in the same layer as these wirings). The insulating layer 415 covers the insulating layer 40 (including the electrodes or wiring). The insulating layer 415 may be formed of the same material and by the same method as those for the insulating layer 415. By performing CMP, the unevenness of the sample surface is reduced, and the subsequent formation In addition, the insulating layer 415 can be formed with an opening. is formed.

[0231] In addition, on the insulating layer 415, the wiring 422, the wiring 423, and the wiring 266 (the same layer as these) are formed. In addition, other electrodes or wirings (including those formed by

[0232] In addition, the wiring 422, the wiring 423, and the wiring 266 (other electrodes formed in the same layer as these) Each of the insulating layers includes an opening and a contact plug. It can be electrically connected to wiring or electrodes in other layers via the insulating film.

[0233] In addition, an insulating layer 416 is provided to cover the wiring 422, the wiring 423, and the wiring 266. The insulating layer 416 can be formed using the same material and method as the insulating layer 405. 416 The surface may be subjected to CMP processing.

[0234] [Transistor 281, Transistor 282] As an example of a transistor constituting a peripheral circuit, the transistor 281 shown in FIG. A larger cross-sectional view is shown in FIG. 25(A). Also, an enlarged cross-sectional view of the transistor 282 shown in FIG. 25B. In this embodiment, as an example, the transistor 281 is a p-channel When transistor 281 is an n-channel transistor, I will explain it below.

[0235] The transistor 281 includes a channel forming region 283, a high concentration p-type impurity region 285, and an insulating The insulating layer 286 is connected to the side wall 288 via the electrode 287. The overlapping region has a low concentration p-type impurity region 284. The insulating layer 286 serves as a gate insulating layer. The electrode 287 can function as a gate electrode.

[0236] The low concentration p-type impurity region 284 is formed by forming the electrode 287 and then forming the side wall 288. It can be formed by introducing an impurity element using it as a mask. The lightly doped p-type impurity region 284 may be formed in a self-aligned manner. After the formation of the high concentration p-type impurity region 285, the high concentration p-type impurity region 285 is formed. The p-type semiconductor 221 of the photoelectric conversion element 601 can be formed at the same time in the same process. The low-concentration p-type impurity region 284 has the same conductivity type as the high-concentration p-type impurity region 285. The concentration of the impurity that imparts the conductivity type is lower than that of the high concentration p-type impurity region 285. The low concentration p-type impurity region 284 may not be provided depending on the situation.

[0237] In the transistor 282, a channel forming region 1283 is formed in the well 220. The transistor 282 includes a channel forming region 1283, a high concentration n-type impurity region 1285, and an insulating layer. The insulating layer 286 is formed on the side wall 288. The insulating layer 286 is formed on the side wall 288. A low concentration n-type impurity region 1284 is provided in the region overlapping with the

[0238] The low concentration n-type impurity region 1284 is formed by arranging the electrode 287 after the electrode 287 is formed and before the sidewall 288 is formed. The impurity element is introduced by using the mask as the mask. The low concentration n-type impurity region 1284 can be formed by a self-alignment method. After the formation of 88, a high concentration n-type impurity region 1285 is formed. 1284 has the same conductivity type as the high concentration n-type impurity region 1285, and is an impurity that imparts the conductivity type. The concentration of the low concentration n-type impurity region 128 is lower than that of the high concentration n-type impurity region 1285. Item 4 may not be provided depending on the circumstances.

[0239] The transistor 281 and the transistor 282 are electrically isolated by an element isolation layer 414. The element isolation region is formed by LOCOS (Local Oxidation ohmic contact). f Silicon) method and STI (Shallow Trench Isolatio) method. n) method, etc. can be used.

[0240] [Variation 1] An example of the configuration of an imaging device different from that shown in FIG. 22 is shown in FIG. 26. As shown in FIG. 26, an n-channel type The transistor 282 may not be provided. The CMOS circuit required for the peripheral circuit is The n-channel transistor 289 and the p-channel transistor 281 are combined. By not providing the n-channel transistor 282, Therefore, an imaging device with good productivity can be realized. Moreover, an imaging device can be realized with reduced manufacturing costs.

[0241] [Variation 2] An example of the configuration of an imaging device different from that shown in FIG. 22 and FIG. 26 is shown in FIG. The stator 602 and the transistor 289 overlap the semiconductor layer 242 via the insulating layer 409. An electrode 213 functioning as a back gate is provided in the region. The electrode 273 is provided in a region overlapping the electrode 245 with the insulating layer 409 interposed therebetween.

[0242] The electrode 213 functions as a back gate for the transistor 602 and the transistor 289. In the case where the electrode 273 is provided, a part of the conductive layer for forming the electrode 213 is used to form the electrode 273. The electrodes 213 and 273 can be formed on the same layer using the same fabrication method and materials. That is, the electrodes 213 and 273 can be fabricated simultaneously using the same film formation process. This layer is processed into an island shape through the same process and the same etching process.

[0243] The electrode 213 and the electrode 273 are formed using the same material and method as the electrode 243. However, in the case where the capacitor 606 is to have a light-transmitting property, the electrode 245 and the electrode It is preferable to use a light-transmitting conductive material for the capacitor 606. By providing the above property, the effective aperture ratio can be increased. Since there is no need to provide a process for performing the above-mentioned steps, the productivity of the imaging device can be improved.

[0244] In addition, various films such as metal films, semiconductor films, and inorganic insulating films disclosed in the present specification and the like are formed by sputtering. It can be formed by the ring method or plasma CVD method, but other methods such as thermal CV It may be formed by a Chemical Vapor Deposition (D) method. As an example of thermal CVD, MOCVD (Metal Organic Chemical Vapor Deposition) is apor deposition method and ALD (Atomic Layer Deposition) method ition) method may also be used.

[0245] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that the

[0246] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the pressure inside the chamber is raised to atmospheric pressure. The film is formed by reacting the reactants near or on the substrate under reduced pressure and depositing them on the substrate. It is also possible.

[0247] In addition, in the ALD method, the pressure inside the chamber is set to atmospheric pressure or reduced pressure, and the source gas for the reaction is sequentially The gas may then be introduced into the chamber, and the gas introduction sequence may be repeated to form a film. For example, by switching between two or more switching valves (also called high-speed valves), The source gases are sequentially supplied to the chamber, and the first source gas is supplied to the chamber so as not to mix the source gases. Inert gas (argon, nitrogen, etc.) is introduced simultaneously with or after the feed gas. In addition, when an inert gas is introduced at the same time, the inert gas is The second source gas may be introduced simultaneously with the introduction of the inert gas. Also, instead of introducing an inert gas, the first source gas is discharged by evacuation. The first source gas is adsorbed on the surface of the substrate to form a first layer. The second layer is deposited on the first layer by reacting with the second source gas introduced later. This process is repeated several times while controlling the gas introduction sequence until a thin film of the desired thickness is formed. By doing so, a thin film with excellent step coverage can be formed. The thickness of the thin film depends on the order of gas introduction. The thickness can be precisely adjusted by changing the number of times the process is repeated. Suitable for making thin FETs (Field Effect Transistors). is.

[0248] The thermal CVD method such as the MOCVD method or the ALD method may be used in the above-described embodiments. It can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, In-Ga When forming a -Zn-O film, trimethylindium (In(CH3)3), trime Tilgallium (Ga(CH3)3) and dimethylzinc (Zn(CH3)2) are used. In addition, the combination is not limited to these, and triethylgallium may be used in place of trimethylgallium. Zinc (Ga(C2H5)3) can also be used, and diethylzinc (Z n(C2H5)2) can also be used.

[0249] For example, when forming a hafnium oxide film using a deposition system that uses ALD, the solvent and Liquids containing hafnium precursor compounds (hafnium alkoxides, tetrakisdimethylamine, etc.) Midhafnium (TDMAH, hafnium amide such as Hf[N(CH3)2]4) Two types of gases are used: vaporized raw gas and ozone (O3) as an oxidizing agent. Examples include tetrakis(ethylmethylamido)hafnium.

[0250] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, a solvent and a liquid containing an aluminum precursor compound (trimethylaluminum (TMA, Al(CH 3) Two types of gases are used: the raw gas vaporized from 3) etc., and H2O as an oxidizer. Other materials include tris(dimethylamido)aluminum and triisobutylaluminum. Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedioate) Nath, etc.

[0251] For example, when forming a silicon oxide film using a deposition system that uses ALD, The chlorine contained in the adsorbed material is removed, and the oxidizing gas (O2 , nitrous oxide) radicals are supplied to react with the adsorbate.

[0252] For example, when forming a tungsten film using a deposition system that uses ALD, WF6 gas is used. The initial tungsten film is formed by repeatedly introducing B2H6 gas and WF6 The tungsten film is formed by repeatedly introducing B2H6 gas and H2 gas in sequence. Alternatively, SiH4 gas may be used.

[0253] For example, an oxide semiconductor film, such as In-Ga-Zn-O, can be formed by a film formation apparatus using ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced in sequence and repeatedly to form an In- Then, Ga(CH3)3 gas and O3 gas are repeatedly introduced to form a GaO Then, Zn(CH3)2 gas and O3 gas are repeatedly introduced to form a ZnO layer. The order of these layers is not limited to this example. By using this method, mixed oxide layers such as In-Ga-O, In-Zn-O, and Ga-Zn-O layers are formed. Alternatively, H obtained by bubbling water with an inert gas such as Ar instead of O3 gas may be used. Although 2O gas may be used, it is preferable to use O3 gas that does not contain H. Instead of the CH3)3 gas, In(C2H5)3 gas may be used. Ga(C2H5)3 gas may be used instead of Ga(C2H5)3 gas.

[0254] [Variation 3] FIG. 28 shows an example of the configuration of the imaging device 115 different from those shown in FIGS.

[0255] The imaging device 115 shown in FIG. 28 has a photoelectric conversion element 601 provided on an insulating layer 415. The photoelectric conversion element 601 shown in FIG. 28 includes an electrode 686 formed of a metal material or the like and a transparent conductive In FIG. 28, a selenium-based material is used as the photoelectric conversion layer 681 between the photoelectric conversion layer 682 and the selenium-based material. The photoelectric conversion element 601 using a selenium-based material converts visible light The photoelectric conversion element has a high external quantum efficiency against the avalanche phenomenon. This results in a highly sensitive sensor with a large amplification of electrons relative to the amount of incident light. In addition, since selenium-based materials have a high light absorption coefficient, they have the advantage that the photoelectric conversion layer 681 can be easily made thin. do.

[0256] The selenium-based material may be amorphous or crystalline selenium. For example, amorphous selenium can be obtained by forming a film of amorphous selenium and then performing a heat treatment. By making the grain size of the crystalline selenium smaller than the pixel pitch, the characteristic variation between pixels is reduced. Crystalline selenium also has a higher spectral sensitivity to visible light than amorphous selenium. It has the characteristics of high optical absorption coefficient.

[0257] Although the photoelectric conversion layer 681 is illustrated as a single layer, the selenium-based material is a material having a hole injection layer on the light receiving surface side. Gallium oxide or cerium oxide is provided as an electron injection blocking layer, and an electron injection blocking layer is provided on the electrode 686 side. The stop layer may be made of nickel oxide or antimony sulfide.

[0258] The photoelectric conversion layer 681 is a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, a layer containing a compound of copper, indium, gallium, and selenium (CIGS) may be used. In CIS and CIGS, the avalanche phenomenon can be utilized in the same way as in the case of a single layer of selenium. It is possible to form a photoelectric conversion element that can be used.

[0259] In addition, CIS and CIGS are p-type semiconductors, and sulfur from n-type semiconductors is used to form the junction. Cadmium oxide, zinc sulfide, or the like may be provided in contact with the metal.

[0260] In order to generate the avalanche phenomenon, a relatively high voltage (e.g., 10 It is preferable to apply a voltage of 100 V or more to the OS transistor. Because it has high withstand voltage characteristics, it is easy to apply a relatively high voltage to the photoelectric conversion element. Therefore, we have developed an OS transistor with high drain withstand voltage and a selenium-based material for photoelectric conversion. By combining this with a photoelectric conversion element with a layer of SiO2, a highly sensitive and reliable imaging device can be obtained. It is possible.

[0261] The transparent conductive layer 682 is made of, for example, indium tin oxide or indium stannate containing silicon. zinc oxide, zinc oxide, zinc oxide containing gallium, aluminum oxide, Zinc oxide containing fluorine, tin oxide, tin oxide containing antimony, or graphite The light-transmitting conductive layer 682 is not limited to a single layer, but may be a stack of different films. It may be.

[0262] In FIG. 28, the photoelectric conversion layer 681 and the light-transmitting conductive layer 682 are not separated for each pixel. However, as shown in FIG. 29(A), it may be separated for each pixel. In addition, a partition 477 made of an insulator is provided in the area not having the electrode 686 between adjacent pixels, and a photoelectric conversion It is preferable to prevent cracks from occurring in the conversion layer 681 and the transparent conductive layer 682. As shown in FIG. 29B, a structure without a partition 477 may be used. The transparent conductive layer 682 and the wiring 487 are connected via a wiring 488 and a contact plug 489. Although the electrical connection structure is illustrated, as shown in FIG. 29(C) and FIG. 29(D), The conductive layer 682 and the wiring 487 may be in direct contact with each other.

[0263] In addition, the electrode 686 and the wiring 487 may be configured by laminating a plurality of conductive layers. For example, as shown in FIG. 29(E), the electrode 686 is formed by forming a conductive layer 686a and a conductive layer 686b. The wiring 487 can be formed of two layers, a conductive layer 487a and a conductive layer 487b. In the configuration of 29(E), for example, the conductive layer 686a and the conductive layer 487a are made of low resistance A conductive layer 686b and a conductive layer 487b are formed by selecting a metal or the like. It is advisable to select a metal or the like having good contact characteristics. In addition, some metals can be used as the transparent conductive layer 68. Contact with the conductive layer 487a may cause electrolytic corrosion. Even if such a corrosion occurs, it is possible to prevent the occurrence of electrolytic corrosion by providing conductive layer 487b.

[0264] The conductive layer 686b and the conductive layer 487b are made of, for example, molybdenum or tungsten. The conductive layer 686a and the conductive layer 487a may be made of, for example, aluminum. Aluminum, titanium, or stacks such as aluminum sandwiched between titanium can be used.

[0265] The insulating layer 442 may have a multi-layer structure. The partition wall 477 can be formed using an organic resin or the like. To block light and / or to determine the area of ​​the light receiving part per pixel, It may be colored.

[0266] In FIG. 28, the transistor 289 and the transistor 602 have a back gate. However, a back gate may not be provided. Only the transistor, for example, transistor 289, has a back gate. The back gate may be electrically connected to a gate provided opposite the back gate. Alternatively, a fixed potential different from that of the gate may be supplied to the back gate. The presence or absence of the back gate is the same as that of the other imaging devices described in this embodiment. can also be applied.

[0267] In addition, the photoelectric conversion element 601 is made of a pi film using an amorphous silicon film or a microcrystalline silicon film. Alternatively, an n-type diode element may be used. The photodiode includes an n-type semiconductor layer, It has a structure in which an i-type semiconductor layer and a p-type semiconductor layer are laminated in this order. It is preferable to use amorphous silicon for the semiconductor layer. The conductor layers are made of amorphous silicon or microcrystalline silicon containing dopants that impart the respective conductivity types. Silicon can be used as the photoelectric conversion layer. The cathode has high sensitivity in the visible light wavelength range and can easily detect weak visible light.

[0268] In addition, pn-type and pin-type diode elements are arranged so that the p-type semiconductor layer becomes the light receiving surface. By using a p-type semiconductor layer as a light receiving surface, the output current of the photoelectric conversion element 601 is The flow can be increased.

[0269] The photoelectric conversion element 601 formed using the above-mentioned selenium-based material or amorphous silicon is Manufactured using general semiconductor manufacturing processes such as film processing, lithography processing, and etching processing In addition, selenium-based materials have high resistance, and as shown in FIG. It is also possible to configure 681 so that it is not separated between pixels.

[0270] Moreover, the imaging device may be curved as shown in FIG. 30(A1) and FIG. 30(B1). FIG. 30(A1) shows a state in which the imaging device is bent in the direction of the two-dot chain line X1-X2 in the same figure. FIG. 30(A2) is a cross-sectional view of the portion indicated by the two-dot chain line X1-X2 in FIG. 30(A1). FIG. 30(A3) is a cross-sectional view of the portion indicated by the two-dot chain line Y1-Y2 in FIG. FIG.

[0271] FIG. 30(B1) shows a case where the imaging device is bent in the direction of the two-dot chain line X3-X4 in the same figure, and FIG. 30(B2) shows a state where the lens is bent in the direction of the two-dot chain line Y3-Y4 in the figure. FIG. 30(B3) is a cross-sectional view of a portion indicated by a two-dot chain line X3-X4 in FIG. 30(B1) is a cross-sectional view of a portion indicated by a two-dot chain line Y3-Y4 in FIG.

[0272] By curving the imaging device, it is possible to reduce the field curvature and astigmatism. This makes it easier to design the optical elements such as lenses to be used in combination with the imaging device. For example, The number of lenses required for aberration correction can be reduced, making it possible to miniaturize semiconductor devices that use imaging devices. It is possible to easily reduce the size and weight of the camera. In addition, it is possible to improve the quality of the captured image. Cut.

[0273] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0274] (Embodiment 4) In this embodiment, a transistor that can be used for the transistor described in the above embodiment will be described. An example of the configuration of the star will be described with reference to the drawings.

[0275] [Bottom-gate transistor] The transistor 410 illustrated in FIG. 31A1 is a type of bottom-gate transistor. The transistor 410 is a channel protective transistor having an insulating layer 409. The semiconductor device has an electrode 246 that can function as a gate electrode. Also, an insulating layer 216 is formed on the electrode 246. The electrode 246 is formed of the same material and by the same method as the electrode 243. The insulating layer 216 can be formed using the same material and method as the insulating layer 117. Cut.

[0276] In addition, the transistor 410 includes a channel protection layer on the channel formation region of the semiconductor layer 242. The insulating layer 209 can function as a heat sink. The insulating layer 209 can be made of the same material as the insulating layer 216. Also, the insulating layer 242 can be formed by contacting a part of the semiconductor layer 242. 16 has an electrode 244 and an electrode 245. A portion of it is formed on the insulating layer 209 .

[0277] By providing an insulating layer 209 on the channel formation region, the electrodes 244 and 245 are formed. Therefore, the electrode 244 and the electrode 245 can be prevented from being exposed. 45, the channel forming region of the semiconductor layer 242 is prevented from being etched. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. Cut.

[0278] The transistor 410 includes an insulating layer 4 on the electrodes 244 and 245 and the insulating layer 209. 18 and has an insulating layer 439 on the insulating layer 418 .

[0279] The transistor 411 shown in FIG. 31A2 has a back gate electrode over the insulating layer 439. The transistor 410 differs from the transistor 410 in that it has a functioning electrode 213. The electrode 213 is It can be formed using the same materials and methods as those of 243.

[0280] In general, the back gate electrode is formed of a conductive layer, and the gate electrode and the back gate electrode form a semiconductor. The back gate electrode is disposed so as to sandwich the channel forming region of the layer. The back gate electrode can function in the same manner as the gate electrode. The back gate electrode may be connected to the ground potential or to an arbitrary potential. By changing the potential of the gate electrode independently of the gate electrode, the threshold voltage of the transistor can be controlled Can be controlled.

[0281] Both the electrode 246 and the electrode 213 can function as a gate electrode. The insulating layer 216, the insulating layer 209, the insulating layer 418, and the insulating layer 439 are each a gate insulating layer. It can function as a gate insulating layer.

[0282] When one of the electrodes 246 and 213 is referred to as a "gate electrode," the other is referred to as a "back electrode." For example, in the transistor 411, the electrode 213 is When referring to a "gate electrode," the electrode 246 is referred to as a "back gate electrode." When 3 is used as a "gate electrode", the transistor 411 is a top-gate transistor. It can be considered a type of zista.

[0283] By providing the electrode 246 and the electrode 213 with the semiconductor layer 242 interposed therebetween, 6 and the electrode 213 are set to the same potential, the region in which carriers flow in the semiconductor layer 242 The area becomes larger in the film thickness direction, so the amount of carrier movement increases. As the on-current of the transistor 411 increases, the field effect mobility increases.

[0284] Therefore, the transistor 411 is a transistor having a large on-current relative to its area. That is, the area occupied by the transistor 411 is determined for the required on-current. According to one embodiment of the present invention, the area occupied by a transistor can be reduced. Therefore, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized. It is possible.

[0285] In addition, since the gate electrode and the back gate electrode are formed of a conductive layer, they can be electrically connected to the outside of the transistor. The function of preventing the electric field generated from acting on the semiconductor layer in which the channel is formed (especially static electricity The back gate electrode is made larger than the semiconductor layer. By covering the semiconductor layer with a back gate electrode, the electric field shielding function can be improved.

[0286] The electrodes 246 and 213 each have a function of blocking an electric field from the outside. The charges of the charged particles generated below the electrode 246 and above the electrode 213 are transferred to the semiconductor layer 242. This does not affect the channel formation region of the gate. As a result, stress tests (e.g., applying a negative charge to the gate) -GBT (Gate Bias-Temperature) Stress Test In addition, the electrode 246 and the electrode 213 are resistant to the electric field generated from the drain electrode. This prevents the semiconductor layer from being affected by the drain voltage fluctuation. This can suppress the fluctuation of the on-state current rise voltage. This is particularly noticeable when a potential is applied to the electrodes 246 and 213 .

[0287] The BT stress test is a type of accelerated test that measures the transistor damage caused by long-term use. It is possible to evaluate the characteristic changes (aging) of the stator in a short time. The amount of change in the threshold voltage of a transistor before and after the test is an important indicator for examining reliability. The smaller the change in threshold voltage before and after the BT stress test, the higher the reliability. It can be said that this is a high-performance transistor.

[0288] In addition, the electrode 246 and the electrode 213 are provided, and the electrode 246 and the electrode 213 are set to the same potential. This reduces the amount of variation in threshold voltage between multiple transistors. At the same time, the variation in electrical characteristics is reduced.

[0289] In addition, a transistor with a back gate electrode is called a +GBT, which applies a positive charge to the gate. The change in threshold voltage before and after the stress test was also observed for transistors without a back gate electrode. Smaller than Sta.

[0290] In addition, when light is incident from the back gate electrode side, the back gate electrode is made of a material having a light blocking property. By forming the semiconductor layer from a conductive film, light is prevented from entering the semiconductor layer from the back gate electrode side. This prevents the semiconductor layer from being photodegraded and the threshold voltage of the transistor is shifted. This can prevent deterioration of electrical characteristics such as the occurrence of

[0291] The electrode 213 may be provided between the insulating layer 418 and the insulating layer 439. 3 and insulating layer 439.

[0292] According to one embodiment of the present invention, a transistor with high reliability can be provided. A highly reliable semiconductor device can be realized.

[0293] The transistor 420 illustrated in FIG. 31B1 is a bottom-gate transistor. The transistor 420 is a channel protection transistor having a structure similar to that of the transistor 41. 2. It has a structure similar to that of the semiconductor layer 242, except that the insulating layer 209 covers the semiconductor layer 242. In addition, a portion of the insulating layer 209 overlapping the semiconductor layer 242 is selectively removed to form an opening. At the opening, the semiconductor layer 242 and the electrode 244 are electrically connected. In another opening formed by selectively removing a portion of the insulating layer 209 overlapping with the semiconductor layer 42, The dielectric layer 242 and the electrode 245 are electrically connected to each other. The overlapping region can function as a channel protection layer.

[0294] The transistor 424 shown in FIG. 31B2 has a back gate electrode over the insulating layer 439. It differs from transistor 420 in that it has a functioning electrode 213 .

[0295] By providing the insulating layer 209, the semiconductor layer 2 generated during the formation of the electrode 244 and the electrode 245 is prevented from being damaged. Therefore, when the electrodes 244 and 245 are formed, the semiconductor 42 is prevented from being exposed. Thinning of the layer 242 can be prevented.

[0296] Also, the transistor 420 and the transistor 424 are The distance between the electrodes 244 and 246 and the distance between the electrodes 245 and 246 are smaller than the distance between the electrodes 244 and 246. Therefore, the parasitic capacitance between the electrodes 244 and 246 is reduced. In addition, the parasitic capacitance between the electrodes 245 and 246 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided.

[0297] The transistor 425 illustrated in FIG. 31C1 is a bottom-gate transistor. The transistor 425 is a channel etching type transistor having an insulating layer 209. Therefore, the electrodes 244 and 245 are formed without using the When the insulating layer 5 is formed, a part of the semiconductor layer 242 that is exposed may be etched. Since the layer 209 is not provided, productivity of the transistor can be improved.

[0298] The transistor 426 shown in FIG. 31C2 has an insulating layer 439 over which a backgate electrode is formed. It differs from transistor 420 in that it has a functioning electrode 213 .

[0299] [Top-gate transistor] The transistor 430 illustrated in FIG. 32A1 is a type of top-gate transistor. The transistor 430 has a semiconductor layer 242 on an insulating layer 409. 42 and the insulating layer 409, an electrode 244 in contact with a part of the semiconductor layer 242 and a semiconductor layer The semiconductor layer 242, the electrode 244, and the electrode 24 5, and an insulating layer 216 is provided on the insulating layer 216. An electrode 246 is provided on the insulating layer 216.

[0300] The transistor 430 is connected to the electrodes 246 and 244, and to the electrodes 246 and 246. Since the electrodes 246 and 244 do not overlap, the parasitic capacitance between the electrodes 246 and 244 and the The parasitic capacitance between the electrode 246 and the electrode 245 can be reduced. After forming the electrode 246, the impurity element 255 is introduced into the semiconductor layer 2 using the electrode 246 as a mask. By introducing the impurities into the semiconductor layer 242, the impurities are self-aligned in the semiconductor layer 242. According to one embodiment of the present invention, the electric characteristics Therefore, a transistor with good performance can be realized.

[0301] The introduction of the impurity element 255 is performed using an ion doping device, an ion implantation device, or a plasma This can be done using a Zuma processor.

[0302] The impurity element 255 is, for example, at least one of Group 13 elements or Group 15 elements. In addition, when an oxide semiconductor is used for the semiconductor layer 242, In this case, the impurity element 255 is at least one of a rare gas, hydrogen, and nitrogen. It is also possible to use elements.

[0303] The transistor 431 shown in FIG. 32A2 has an electrode 213 and an insulating layer 217. The transistor 431 is formed on the insulating layer 409. The electrode 213 is provided with an insulating layer 217 formed on the electrode 213. The electrode 213 can function as a back gate electrode. The insulating layer 217 can function as a gate insulating layer. and methods.

[0304] Like the transistor 411, the transistor 431 has a large on-state current relative to its area. That is, for the required on-current, the transistor 4 According to one aspect of the present invention, the area occupied by the transistor 31 can be reduced. Therefore, according to one aspect of the present invention, a highly integrated semiconductor device can be manufactured. It is possible to realize a body device.

[0305] The transistor 440 illustrated in FIG. 32B1 is a top-gate transistor. The transistor 440 is formed by forming the semiconductor layer 2 after forming the electrodes 244 and 245. The transistor 430 differs from the transistor 430 in that the transistor 42 is formed. The transistor 441 has an electrode 213 and an insulating layer 217. In the transistor 440 and the transistor 441, a part of the semiconductor layer 242 A portion of the semiconductor layer 242 is formed on an electrode 244 , and another portion of the semiconductor layer 242 is formed on an electrode 245 .

[0306] Like the transistor 411, the transistor 441 has a large on-state current relative to the area it occupies. That is, for the required on-current, the transistor 4 According to one aspect of the present invention, the area occupied by the transistor 41 can be reduced. Therefore, according to one aspect of the present invention, a highly integrated semiconductor device can be manufactured. It is possible to realize a body device.

[0307] After forming the electrode 246, the transistor 440 and the transistor 441 are also connected to the electrode 24 6 as a mask to introduce an impurity element 255 into the semiconductor layer 242, According to one aspect of the present invention, an impurity region can be formed in a self-aligned manner in the semiconductor substrate 242. A transistor with favorable electrical characteristics can be realized. This makes it possible to realize a highly integrated semiconductor device.

[0308] [s-channel transistor] FIG. 33 illustrates an example of a transistor structure in which an oxide semiconductor is used as the semiconductor layer 242. In FIG. The transistor 450 illustrated in FIG. 33 includes a semiconductor layer 242b formed on a semiconductor layer 242a. The upper surface and side surface of the semiconductor layer 242b and the side surface of the semiconductor layer 242a are 33A is a top view of the transistor 450. The transistor 450 has a structure covered with the transistor 242c. FIG. 33(B) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 33(A) (channel FIG. 33(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 33(A). 1 is a cross-sectional view (cross-sectional view in the channel width direction) of the indicated portion.

[0309] In the transistor 450 shown in FIG. 33, a semiconductor layer 242b is provided on a protruding portion of an insulating layer 409. By providing the semiconductor layer 242b on the protruding portion of the insulating layer 409, The side of 242b can be covered with the electrode 243. The semiconductor layer 242b can be electrically surrounded by the electric field of the electrode 243. In this way, the electric field of the conductive film electrically connects the semiconductor layer in which the channel is formed. The surrounding transistor structure is called the surrounded channel (s-channel A transistor with an s-channel structure is called a "s-channel" structure. It is also called an "s-channel transistor" or "s-channel transistor."

[0310] In the s-channel structure, a channel is formed in the entire semiconductor layer 242b (bulk). In the s-channel structure, the drain current of the transistor is increased. In addition, the electric field of the electrode 243 can be used to obtain a larger on-state current. As a result, the entire channel formation region formed in the semiconductor layer 242b can be depleted. Therefore, in the s-channel structure, the off-state current of the transistor can be further reduced. It is possible.

[0311] In addition, by making the protrusion of the insulating layer 409 high and reducing the channel width, The n-nel structure can increase the on-current and reduce the off-current. In addition, when forming the semiconductor layer 242b, the exposed semiconductor layer 242a may be removed. In this case, the side surfaces of the semiconductor layer 242a and the semiconductor layer 242b may be aligned.

[0312] 34, a transistor 451 is provided below the semiconductor layer 242 with an insulating layer interposed therebetween. An electrode 213 may be provided. FIG. 34A is a top view of the transistor 451. 34(B) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 34(C) is a cross-sectional view of the portion indicated by the dashed line Y1-Y2 in FIG. 34(A).

[0313] FIG. 35 shows another example of a transistor having an s-channel structure. The transistor 452 has an electrode 244 and an electrode 245 provided on the semiconductor layer 242b. The electrode 244 is insulated from the semiconductor layer 242a and does not contact the side surfaces of the semiconductor layer 242b and the semiconductor layer 242a. Contacts are formed at the edge layer 418, the insulating layer 439, and an opening in the insulating layer 419. The electrode 245 is electrically connected to the electrode 434 through a plug. In the openings provided in the edge layer 439 and the insulating layer 419, a contact plug is formed. It is electrically connected to the electrode 435 .

[0314] According to one embodiment of the present invention, the area occupied by a transistor can be reduced. According to one embodiment of the present invention, a highly integrated semiconductor device can be provided.

[0315] FIG. 36 shows another example of a transistor having an s-channel structure. The transistor 453 has a semiconductor layer 242b formed on a semiconductor layer 242a. The transistor 453 is a bottom-gate transistor having a back gate electrode. FIG. 36A is a top view of a transistor 453. FIG. 36B is a top view of a transistor 453. FIG. 1 is a cross-sectional view (cross-sectional view in the channel length direction) of the portion indicated by the dashed line X1-X2 in (A). FIG. 36(C) is a cross-sectional view (cross section) of the portion indicated by the dashed line Y1-Y2 in FIG. 36(A). (Cross-sectional view in the channel width direction).

[0316] The electrode 213 provided on the insulating layer 439 is connected to the insulating layer 216, the insulating layer 418, and the insulating layer The openings 247a and 247b in the 439 are electrically connected to the electrode 246. Therefore, the same potential is supplied to the electrodes 213 and 246. It is not necessary to provide either the opening 247a or the opening 247b. It is not necessary to provide both the opening 247a and the opening 247b. When no electrode is provided, different potentials can be applied to the electrodes 213 and 246 .

[0317] In the transistor 453, the semiconductor layer 242 is divided into a semiconductor layer 242a and a semiconductor layer 242b. This shows an example of a two-layer structure.

[0318] The energy band structure of the portion indicated by the dashed line C3-C4 in FIG. 36(B) is shown in FIG. Figure 37 shows the energy band structure of the channel formation region of transistor 453. There are.

[0319] In FIG. 37, Ec387 indicates the energy of the bottom of the conduction band of the insulating layer 418. By forming the layer 242 into two layers, the semiconductor layer 242a and the semiconductor layer 242b, the transistor can be produced. In addition, since the semiconductor layer 242c is not provided, the trap level 390 However, the semiconductor layer 242 has a higher electric field effect transfer rate than a single-layer structure. Mobility can be achieved.

[0320] According to one embodiment of the present invention, a transistor with low power consumption can be realized. According to one aspect of the present invention, an imaging device or the like that consumes less power can be realized. A highly reliable transistor can be realized. Thus, a highly reliable imaging device can be achieved. etc. can be realized.

[0321] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is. [Explanation of symbols]

[0322] 100 vehicles 101 Steering 102 Dashboard 108 Airbag 110 Occupant protection devices 112 Pixel driving circuit 114 pixels 115 Imaging Device 117 Insulating Layer 119 Sensors 120 Control device 123 Wiring 131 Airbag device 132 Airbag device 140 Pixel section 141 pixels 209 Insulating Layer 213 Electrode 216 Insulating Layer 217 Insulating Layer 219 Insulating Layer 220 wells 221 p-type semiconductors 223 n-type semiconductor 224 Aperture 225 Aperture 242 Semiconductor layer 243 Electrode 244 electrode 245 Electrode 246 Electrode 252 Peripheral Circuit Area 255 Impurity elements 260 circuits 261 Signal Processing Circuit 262 Column driver circuit 263 Output Circuit 264 circuits 265 Wiring 266 Wiring 267 Wiring 268 Wiring 269 ​​Wiring 270 Circuits 273 Electrode 277 Insulating Layer 280 circuits 281 Transistor 282 Transistor 283 Formation area 284 Low concentration p-type impurity region 285 High concentration p-type impurity region 286 Insulating Layer 287 Electrode 288 Side wall 289 Transistor 290 circuits 382 Ec 386 Ec 387 Ec 390 Trap Levels 401 Substrate 403 Insulating layer 404 Insulating layer 405 Insulating layer 406 Contact plug 407 Insulating Layer 408 Insulating layer 409 Insulating layer 410 Transistor 411 Transistor 414 Element isolation layer 415 Insulating Layer 416 Insulating Layer 418 Insulating layer 419 Insulating Layer 420 Transistor 421 Wiring 422 Wiring 423 Wiring 424 Transistor 425 Transistor 427 Wiring 429 Wiring 430 Transistor 431 Transistor 434 Electrode 435 Electrode 439 Insulating Layer 440 Transistor 441 Transistor 442 Insulating layer 444 Wiring 450 Transistors 451 Transistor 452 Transistor 453 Transistor 477 Bulkhead 487 Wiring 488 Wiring 489 Contact plug 601 Photoelectric conversion element 602 Transistor 603 Transistor 604 Transistor 605 Transistor 606 Capacitive element 607 nodes 608 Wiring 609 Wiring 610 Circuit 611 Wiring 681 Photoelectric conversion layer 682 Transparent conductive layer 686 Electrode 900 vehicles 1283 Channel formation region 1284 Low concentration n-type impurity region 1285 High concentration n-type impurity region 5100 pellets 5120 PCB 5161 area 103a Door 103b Door 104a Door 104b Door 108c Semiconductor layer 111a Imaging device 111b Imaging device 111c Imaging device 112a Imaging device 112b Imaging device 112c Imaging device 113a Imaging device 113b Imaging device 114a Imaging device 114b Imaging device 133a Airbag device 133b Airbag device 134a Airbag device 134b Airbag device 242a Semiconductor layer 242b Semiconductor layer 242c Semiconductor layer 243a electrode 243b Electrode 247a aperture 247b aperture 264a Circuit 264b Counter Circuit 264c Latch circuit 272c Semiconductor layer 383a Ec 383b Ec 383c Ec 487a Conductive layer 487b Conductive layer 686a Conductive layer 686b Conductive layer

Claims

[Claim 1] An occupant protection device having an imaging device, a control device, and an airbag device, the imaging device includes a light receiving element including selenium and a transistor including an oxide semiconductor; The control device is configured to predict a collision using an image captured by the imaging device and activate the airbag device.

Images