Display substrate, manufacturing method of the same, and display device

Abstract

To provide a display substrate, a manufacturing method of the same, and a display device.SOLUTION: On a plane surface parallel to a display substrate, the display substrate has a plurality of grid lines, a plurality of data lines, a plurality of power cords, and a plurality of sub pixels disposed on a base. At least one sub pixel includes a light emitting device, and a drive circuit that drives the light emitting device so that the light emitting device emits light. The drive circuit includes a plurality of transistors and a storage capacitor. On a plane surface perpendicular to the display substrate, the display substrate includes the base and a plurality of function layers. The function layers include a semiconductor layer, a first conducting layer, a second conducting layer, a third conducting layer, and a fourth conducting layer which are disposed in this order. A first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer are disposed between the respective function layers. In a grid line extending direction, the power cords are connected to one another via at least one function layer.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application is a divisional application of an application having a filing date of December 21, 2020, application number JP2020-571364, and title of the invention "Display substrate and manufacturing method thereof, and display device."

[0002] The present specification relates to the field of display technology, and more particularly to a display substrate and a manufacturing method thereof, and a display device. [Background technology]

[0003] Organic Light-Emitting Device (OLED) display substrate is a display substrate different from conventional Liquid Crystal Display (LCD), and has the advantages of spontaneous light emission, high temperature characteristics, low power consumption, fast response, bendability, extremely light and thin, and low cost. Therefore, it has become one of the important development directions of new generation display devices and has attracted much attention.

[0004] In order to realize high-frequency driving of the OLED display substrate, the related art provides an OLED display substrate with double data lines, that is, the pixels in the same column are connected to two data lines. However, although the OLED display substrate in the related art can realize high-frequency driving, its resolution is generally lower, so it cannot meet the requirements for high resolution of display devices in the market. Summary of the Invention [Means for solving the problem]

[0005] The following is a general summary of the subject matter described herein, which is not intended to limit the scope of the claims.

[0006] A display substrate, in a plane parallel to the display substrate, the display substrate comprises a plurality of grid lines, a plurality of data lines, a plurality of power cords, and a plurality of sub-pixels disposed on a base, at least one of the sub-pixels comprises a light-emitting device and a driving circuit configured to drive the light-emitting device to emit light, the driving circuit comprising a plurality of transistors and a storage capacitor; in a plane perpendicular to the display substrate, the display substrate comprises a base and a plurality of functional layers disposed on the base, the plurality of functional layers comprising a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed in that order, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer respectively disposed between the plurality of functional layers, and the power cords are connected to each other via at least one functional layer in a grid line extension direction.

[0007] In an exemplary embodiment, in the data line extension direction, the power cord has a plurality of sub-power cords connected in sequence, at least one sub-power cord is installed in one subpixel, the sub-power cord of the at least one subpixel has a plurality of power supply units connected in sequence, and at least one power supply unit and a power supply unit connected to the at least one power supply unit form an included angle of more than 90 degrees and less than 180 degrees.

[0008] In an exemplary embodiment, one of the at least one power supply unit and the power supply unit connected to the power supply unit is installed in parallel to the data line.

[0009] In an exemplary embodiment, the sub-power cord comprises a first power supply unit, a second power supply unit, and a third power supply unit, the second power supply unit is configured to be connected to the first power supply unit and the third power supply unit, the first power supply unit and the third power supply unit are installed parallel to the data line, an included angle between the second power supply unit and the first power supply unit is greater than 90 degrees and less than 180 degrees, and an included angle between the second power supply unit and the third power supply unit is greater than 90 degrees and less than 180 degrees.

[0010] In an exemplary embodiment, the first power supply section is connected to a third power supply section in a subpixel in a previous row in the same column, and the third power supply section is connected to a first power supply section in a subpixel in a next row in the same column.

[0011] In an exemplary embodiment, the length along which the first power supply unit extends along the data line extension direction is greater than the average width of the first power supply unit, the length along which the second power supply unit extends along the inclined direction is greater than the average width of the second power supply unit, the length along which the third power supply unit extends along the data line extension direction is greater than the average width of the third power supply unit, and the inclined direction is a direction in which the second power supply unit and the first power supply unit form the included angle.

[0012] In an exemplary embodiment, the third power supply portion has an average width that is smaller than the average width of the first power supply portion.

[0013] In an exemplary embodiment, a distance between an edge of the first power supply unit on one side in the extension direction of the grid lines closer to the third power supply unit and an edge of the third power supply unit on one side in the extension direction of the grid lines closer to the first power supply unit corresponds to an average width of the third power supply unit.

[0014] In an exemplary embodiment, the display substrate further includes a first connection portion, wherein a second electrode of a storage capacitor in at least one subpixel and a second electrode of a storage capacitor in an adjacent subpixel in the grid line extension direction are connected to each other by the first connection portion, and in at least one subpixel, an orthogonal projection of the second power supply portion on the base and an orthogonal projection of the second electrode of the storage capacitor on the base have an overlapping area, or an orthogonal projection of the second power supply portion on the base and an orthogonal projection of the first connection portion on the base have an overlapping area.

[0015] In an exemplary embodiment, an orthogonal projection of the second power supply portion on a base and an orthogonal projection of the first electrode of the storage capacitor on a base have an overlap region.

[0016] In an exemplary embodiment, the orthogonal projection of the second power supply portion on a base and the orthogonal projection of the grid lines on a base have an overlap region.

[0017] In an exemplary embodiment, the plurality of transistors includes a second transistor, and an orthogonal projection on a base of the first power supply portion and an orthogonal projection on a base of the second transistor have an overlapping region.

[0018] In an exemplary embodiment, the display substrate further comprises a fifth insulating layer disposed on the fourth conductive layer, and a fifth conductive layer disposed on the fifth insulating layer, a fifth through hole disposed on the fifth insulating layer, the fifth through hole being configured to connect the fifth conductive layer to the fourth conductive layer, and an orthogonal projection of the fifth through hole on the base and an orthogonal projection of the sub-power cord on the base having no overlapping area.

[0019] In an exemplary embodiment, in at least one subpixel, an orthogonal projection of the fifth through hole on a base and an orthogonal projection of a dummy extension line of the first power supply portion of the sub-power cord in the data line extension direction have an overlapping area.

[0020] In an exemplary embodiment, an eighth through hole is provided on the first insulating layer, the second insulating layer and the third insulating layer, and the eighth through hole is configured so that a data signal is written to the semiconductor layer by the data line, and an orthogonal projection of the eighth through hole on a base and an orthogonal projection of the first power supply unit and the second power supply unit in the sub-power cord on a base have no overlapping area.

[0021] In an exemplary embodiment, in at least one subpixel, an orthogonal projection of the eighth through hole on a base and an orthogonal projection of a dummy extension line of a third power supply portion of the sub-power cord in the data line extension direction have an overlapping area.

[0022] In an exemplary embodiment, the power cord is disposed on the third conductive layer or the fourth conductive layer, and the power cord and the data line are disposed on the same layer.

[0023] In an exemplary embodiment, the power cord is disposed on the third conductive layer and the data line is disposed on the fourth conductive layer, or the data line is disposed on the third conductive layer and the power cord is disposed on the fourth conductive layer.

[0024] In an exemplary embodiment, the display substrate further comprises a first connection portion, wherein a second electrode of a storage capacitor in at least one subpixel and a second electrode of a storage capacitor in an adjacent subpixel in a grid line extension direction are connected to each other by the first connection portion.

[0025] In an exemplary embodiment, there is at least one region including 2×4 subpixels, in which the second electrode of the storage capacitor in a first subpixel and the second electrode of the storage capacitor in a second subpixel in a row are connected to each other by the first connection portion, the second electrode of the storage capacitor in the second subpixel is directly connected to the second electrode of the storage capacitor in a third subpixel, the second electrode of the storage capacitor in the third subpixel and the second electrode of the storage capacitor in a fourth subpixel are connected to each other by the first connection portion, and the second electrode of the storage capacitor in the first subpixel in another row is directly connected to the second electrode of the storage capacitor in the second subpixel, the second electrode of the storage capacitor in the second subpixel and the second electrode of the storage capacitor in the third subpixel are connected to each other by the first connection portion, and the second electrode of the storage capacitor in the third subpixel is directly connected to the second electrode of the storage capacitor in the fourth subpixel.

[0026] In an exemplary embodiment, the semiconductor layer in the first subpixel and the semiconductor layer in the second subpixel are spaced apart, the semiconductor layer in the second subpixel and the semiconductor layer in the third subpixel are spaced apart, and the semiconductor layer in the third subpixel and the semiconductor layer in the fourth subpixel are spaced apart.

[0027] In an exemplary embodiment, the third conductive layer comprises a first pole of a fifth transistor, wherein the first pole of the fifth transistor in the first subpixel and the first pole of the fifth transistor in the second subpixel are spaced apart, the first pole of the fifth transistor in the second subpixel and the first pole of the fifth transistor in the third subpixel are spaced apart, and the first pole of the fifth transistor in the third subpixel and the first pole of the fifth transistor in the fourth subpixel are spaced apart.

[0028] In an exemplary embodiment, there is at least one region including 2×4 subpixels, in which the second electrode of the storage capacitor in a first subpixel and the second electrode of the storage capacitor in a second subpixel in a row are connected to each other by the first connection portion, the second electrode of the storage capacitor in the second subpixel and the second electrode of the storage capacitor in the third subpixel are arranged to be disconnected, the second electrode of the storage capacitor in the third subpixel and the second electrode of the storage capacitor in the fourth subpixel are connected to each other by the first connection portion, the second electrode of the storage capacitor in the first subpixel and the second electrode of the storage capacitor in the second subpixel in another row are arranged to be disconnected, the second electrode of the storage capacitor in the second subpixel and the second electrode of the storage capacitor in the third subpixel are connected to each other by the first connection portion, and the second electrode of the storage capacitor in the third subpixel and the second electrode of the storage capacitor in the fourth subpixel are arranged to be disconnected.

[0029] In an exemplary embodiment, the third conductive layer comprises a first pole of a fifth transistor and a second connection portion, the first pole of the fifth transistor in a first subpixel in one row is arranged to be disconnected from the first pole of the fifth transistor in the second subpixel, the first pole of the fifth transistor in the second subpixel and the first pole of the fifth transistor in the third subpixel are connected to each other by the second connection portion, the first pole of the fifth transistor in the third subpixel and the first pole of the fifth transistor in the fourth subpixel are arranged to be disconnected, the first pole of the fifth transistor in the first subpixel in another row is connected to each other by the second connection portion, the first pole of the fifth transistor in the second subpixel and the first pole of the fifth transistor in the third subpixel are arranged to be disconnected, and the first pole of the fifth transistor in the third subpixel and the first pole of the fifth transistor in the fourth subpixel are connected to each other by the second connection portion.

[0030] In an exemplary embodiment, the power cord is connected to the second electrode of the storage capacitor and the first pole of the fifth transistor in the grid line extension direction.

[0031] In an exemplary embodiment, a first through hole exposing a first electrode of the fifth transistor is provided on the fourth insulating layer, a second through hole exposing a second electrode of the storage capacitor is provided on the third insulating layer, the power cord is connected to the first electrode of the fifth transistor through the first through hole, and the first pole of the fifth transistor is connected to the second electrode of the storage capacitor through the second through hole.

[0032] In an exemplary embodiment, in at least one subpixel, the number of the first through holes is one, the number of the second through holes is multiple, the multiple second through holes are arranged along the data line extension direction, an orthogonal projection of the power cord on the base includes an orthogonal projection of the first through hole on the base, and an orthogonal projection of the first pole of the fifth transistor on the base includes an orthogonal projection of the second through hole on the base.

[0033] In an exemplary embodiment, the semiconductor layer includes a third connection portion, and is arranged so that the semiconductor layer in the first subpixel and the semiconductor layer in the second subpixel in one row are disconnected, the semiconductor layer in the second subpixel and the semiconductor layer in the third subpixel are connected to each other by the third connection portion, the semiconductor layer in the third subpixel and the semiconductor layer in the fourth subpixel are disconnected, and the semiconductor layer in the first subpixel and the semiconductor layer in the second subpixel in another row are connected to each other by the third connection portion, the semiconductor layer in the second subpixel and the semiconductor layer in the third subpixel are disconnected, and the semiconductor layer in the third subpixel and the semiconductor layer in the fourth subpixel are connected to each other by the third connection portion.

[0034] In an exemplary embodiment, the power cord is connected to each other by a third connection portion of the semiconductor layer and a second electrode of a storage capacitor in a grid line extension direction.

[0035] In an exemplary embodiment, an eleventh through hole exposing a second electrode of the storage capacitor is provided on the third insulating layer, a twelfth through hole exposing a third connection portion of the semiconductor layer is provided on the first insulating layer, the second insulating layer and the third insulating layer, the power cord is connected to the second electrode of the storage capacitor through the eleventh through hole, and the power cord is connected to the third connection portion of the semiconductor layer through the twelfth through hole.

[0036] In an exemplary embodiment, in at least one subpixel, the number of the 11th through hole is one, the number of the 12th through hole is multiple, the multiple 12th through holes are arranged along the data line extension direction, and the orthogonal projection of the power cord on the base includes orthogonal projections of the 11th through hole and the 12th through hole on the base.

[0037] In an exemplary embodiment, the plurality of transistors includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, and in at least one subpixel, the semiconductor layer comprises at least a first active area where the first transistor is located, a second active area where the second transistor is located, a third active area where the third transistor is located, a fourth active area where the fourth transistor is located, a fifth active area where the fifth transistor is located, a sixth active area where the sixth transistor is located, and a seventh active area where the seventh transistor is located, and the first active area, the second active area, the third active area, the fourth active area, the fifth active area, the sixth active area, and the seventh active area are of a monolithic structure.

[0038] In an exemplary embodiment, the distance between the second active area and the first active area in the grid line extension direction is smaller than the distance between the second active area and the seventh active area in the grid line extension direction.

[0039] In an exemplary embodiment, the seventh active area and the first active area are sequentially disposed along a direction from a data line for writing a data signal to a power cord.

[0040] In an exemplary embodiment, at least one subpixel has a first region, a second region and a third region arranged in sequence along a data line extension direction, the first active area and the seventh active area are arranged on a side of the first region away from the second region, the second active area and the fourth active area are arranged on a side of the first region closer to the second region, the third active area is arranged within the second region, and the fifth active area and the sixth active area are arranged within the third region.

[0041] In an exemplary embodiment, a first pole of the first transistor is connected to an initial signal line, a second pole of the first transistor T1 is connected to a first electrode of the storage capacitor, a first pole of the second transistor is connected to a first electrode of the storage capacitor, a second pole of the second transistor is connected to a second pole of a sixth transistor, a first pole of the third transistor is connected to a second pole of a fourth transistor, a second pole of the third transistor is connected to a second pole of a sixth transistor, a first pole of the fourth transistor is connected to a data line, a first pole of the fifth transistor is connected to a power cord, a second pole of the fifth transistor is connected to a first pole of a third transistor, a second pole of the sixth transistor is connected to an anode of a light emitting device, a first pole of the seventh transistor is connected to an initial signal line, a second pole of the seventh transistor is connected to an anode of a light emitting device, the first active areas are connected to the second active area and the seventh active area, respectively, the second active areas are connected to the third active area and the sixth active area, respectively, and the fourth active area is connected to the third active area and the fifth active area, respectively.

[0042] In an exemplary embodiment, the semiconductor layers of adjacent subpixels are symmetrical in the grid line extension direction.

[0043] In an exemplary embodiment, there is at least one region including 2×2 subpixels, where the shape of the semiconductor layer in a first subpixel in a row is the same as the shape of the semiconductor layer in a second subpixel in another row, and the shape of the semiconductor layer in the second subpixel in a row is the same as the shape of the semiconductor layer in the first subpixel in another row.

[0044] In an exemplary embodiment, the semiconductor layer includes a third connection portion, and the semiconductor layer in at least one subpixel is connected to the semiconductor layer in an adjacent subpixel in the grid line extension direction by the third connection portion.

[0045] In an exemplary embodiment, the third connection is connected to an active area of ​​a fifth transistor.

[0046] In an exemplary embodiment, an orthogonal projection of the third connection portion on a base and an orthogonal projection of the power cord on a base have an overlap region.

[0047] In an exemplary embodiment, a twelfth through hole exposing the third connection portion is provided on the first insulating layer, the second insulating layer, and the third insulating layer, and the power cord is connected to the third connection portion through the twelfth through hole.

[0048] In an exemplary embodiment, there is at least one region including 2×4 subpixels, in which the semiconductor layer in the first subpixel and the semiconductor layer in the second subpixel in one row are arranged so as to be disconnected, the semiconductor layer in the second subpixel and the semiconductor layer in the third subpixel are connected to each other by the third connection portion, the semiconductor layer in the third subpixel and the semiconductor layer in the fourth subpixel are arranged so as to be disconnected, and in another row, the semiconductor layer in the first subpixel and the semiconductor layer in the second subpixel are arranged so as to be connected to each other by the third connection portion, the semiconductor layer in the second subpixel and the semiconductor layer in the third subpixel are arranged so as to be disconnected, and the semiconductor layer in the third subpixel and the semiconductor layer in the fourth subpixel are connected to each other by the third connection portion.

[0049] In an exemplary embodiment, there is at least one pixel column, in the data line extension direction, the data line has a plurality of sub-data lines connected in sequence, there is at least one sub-pixel, and two sub-data lines are provided between the sub-pixel and an adjacent sub-pixel in the grid line extension direction.

[0050] In an exemplary embodiment, the two sub-data lines are parallel to each other.

[0051] In an exemplary embodiment, in at least one subpixel, an eighth through-hole exposing a semiconductor layer is provided on the first insulating layer, the second insulating layer, and the third insulating layer, a third through-hole exposing a first pole of a fourth transistor is provided on the fourth insulating layer, the data line is connected to the first pole of the fourth transistor through the third through-hole, and the first pole of the fourth transistor is connected to the semiconductor layer through the eighth through-hole.

[0052] In the exemplary embodiment, the eighth through holes of adjacent sub-pixels are symmetrical with each other in the grid line extending direction.

[0053] In an exemplary embodiment, the data lines are disposed on the third conductor layer and the power cord is disposed on the third conductor layer.

[0054] In an exemplary embodiment, the data lines are disposed on the fourth conductor layer, and the power cords are disposed on the third conductor layer or the fourth conductor layer.

[0055] In an exemplary embodiment, in at least one column of sub-pixels, the data line comprises a first sub-data line and a second sub-data line, the first sub-data line and the second sub-data line being respectively located on either side of the sub-pixels in the column.

[0056] In an exemplary embodiment, the power cord is located between the first and second sub-data lines.

[0057] In an exemplary embodiment, the pixel structures of adjacent sub-pixels are symmetrical in the grid line extension direction.

[0058] In an exemplary embodiment, there is at least one region including 2×2 sub-pixels, where the pixel structure of a first sub-pixel in one row is the same as the pixel structure of a second sub-pixel in another row, and the pixel structure of the second sub-pixel in one row is the same as the pixel structure of the first sub-pixel in another row.

[0059] In an exemplary embodiment, the display substrate further includes a reset signal line, a light emission control line and an initial signal line, the semiconductor layer includes active areas of at least a plurality of transistors, the first conductor layer includes at least a grid line, a light emission control line, a reset signal line, a first electrode of a storage capacitor and gate electrodes of a plurality of transistors, the second conductor layer includes at least an initial signal line and a second electrode of a storage capacitor, the third conductor layer includes source-drain electrodes of at least a plurality of transistors, and the fourth conductor layer includes at least a data line and a power cord.

[0060] In an exemplary embodiment, at least one subpixel has a first region, a second region and a third region arranged in sequence along the extension direction of the data line, the grid line, the initial signal line and the reset signal line are located in the first region, the first electrode and the second electrode of the storage capacitor are located in the second region, and the light emission control line is located in the third region.

[0061] In an exemplary embodiment, the second conductor layer further comprises a shield electrode, and in at least one subpixel, an orthogonal projection of the shield electrode on the base and an orthogonal projection of the power cord on the base have an overlapping area.

[0062] In an exemplary embodiment, the power cord is connected to the shield electrode by a through hole.

[0063] In an exemplary embodiment, the shield electrode is disposed between the grid line and the reset signal line in the data line extension direction.

[0064] In an exemplary embodiment, the shield electrode has a first portion extending along a grid line extension direction and a second portion extending along a data line extension direction, and one end of the first portion closer to the second portion is connected to one end of the second portion closer to the first portion.

[0065] In an exemplary embodiment, the first conductor layer further includes a gate block extending along a data line extension direction, the gate block being connected to the grid line, and the gate block and a second portion of the shield electrode have a directly facing region in the data line extension direction.

[0066] In an exemplary embodiment, the source-drain electrodes of the plurality of transistors include a first pole of a second transistor, a seventh through hole exposing a first electrode of the storage capacitor is provided on the second insulating layer and the third insulating layer, a ninth through hole exposing an active area of ​​the second transistor is provided on the first insulating layer, the second insulating layer and the third insulating layer, one end of the first pole of the second transistor is connected to the first electrode of the storage capacitor by the seventh through hole and the other end is connected to the active area of ​​the second transistor by the ninth through hole.

[0067] In an exemplary embodiment, the orthogonal projection of the first pole of the second transistor on the base and the orthogonal projection of the grid line on the base have an overlapping area, and the orthogonal projection of the first pole of the second transistor on the base and the orthogonal projection of the light emission control line, the reset signal line, and the initial signal line on the base do not have an overlapping area.

[0068] In an exemplary embodiment, the source-drain electrodes of the plurality of transistors include a first pole of a first transistor, a sixth through hole exposing an initial signal line is provided on the third insulating layer, a tenth through hole exposing an active area of ​​the first transistor is provided on the first insulating layer, the second insulating layer and the third insulating layer, one end of the first pole of the first transistor is connected to the initial signal line by the sixth through hole and the other end is connected to the active area of ​​the first transistor by the tenth through hole.

[0069] In an exemplary embodiment, an orthogonal projection of the first pole of the first transistor on the base and an orthogonal projection of the reset signal line on the base have an overlapping area, and an orthogonal projection of the first pole of the first transistor on the base and an orthogonal projection of the grid line and the light emission control line on the base do not have an overlapping area.

[0070] In an exemplary embodiment, the display substrate comprises a fifth insulating layer disposed on the fourth conductive layer, and a fifth conductive layer disposed on the fifth insulating layer, the fourth conductor layer further comprising a connection electrode, the source-drain electrodes of the plurality of transistors include a second electrode of a sixth transistor, the fourth insulating layer is provided with a fourth through hole exposing the second electrode of the sixth transistor, the fifth insulating layer is provided with a fifth through hole exposing a connection electrode, the connection electrode is connected to the second electrode of the sixth transistor by the fourth through hole, and the fifth conductor layer is connected to the connection electrode by the fifth through hole.

[0071] In an exemplary embodiment, the orthogonal projection of the connecting electrode on the base and the orthogonal projection of the first pole of the second transistor on the base have an overlapping area.

[0072] In an exemplary embodiment, at least one subpixel includes at least a first through-hole configured to connect a first pole of a fifth transistor to the power cord and exposing the first pole of the fifth transistor, a second through-hole configured to connect a second electrode to the first pole of the fifth transistor and exposing the second electrode of the storage capacitor, a third through-hole configured to connect a first pole of a fourth transistor to the data line and exposing the first pole of the fourth transistor, a fourth through-hole configured to connect a second pole of a sixth transistor to a connection electrode and exposing the second pole of the sixth transistor, a fifth through-hole configured to connect a connection electrode to an anode of the fifth conductor layer and exposing the connection electrode, and a fifth through-hole configured to connect an initial signal line to the first transistor. a sixth through hole configured to connect the first electrode to the first pole of the second transistor and exposing the initial signal line; a seventh through hole configured to connect the first electrode to the first pole of the second transistor and exposing the first electrode of the storage capacitor; an eighth through hole configured to connect the active area of ​​the fourth transistor to the first pole of the fourth transistor and exposing the active area of ​​the fourth transistor; a ninth through hole configured to connect the active area of ​​the second transistor to the first pole of the second transistor and exposing the active area of ​​the second transistor; and a tenth through hole configured to connect the active area of ​​the first transistor to the first pole of the first transistor and exposing the active area of ​​the first transistor.

[0073] In an exemplary embodiment, at least one subpixel includes at least an eleventh through-hole configured to connect the second electrode to a power cord and exposing the second electrode of the storage capacitor, and a twelfth through-hole configured to connect the third connection portion to a power cord and exposing the third connection portion.

[0074] A display device includes the above-described display substrate.

[0075] A method for manufacturing a display substrate, comprising: manufacturing the display substrate, in a plane parallel to the display substrate, the display substrate comprising a grid line disposed on a base, a data line, a power cord, and a plurality of sub-pixels, at least one of the sub-pixels comprising a light-emitting device and a driving circuit configured to drive the light-emitting device to emit light, the driving circuit comprising a plurality of transistors and a storage capacitor; the method for manufacturing the display substrate comprising: To provide a base and forming a plurality of functional layers on the base, the plurality of functional layers being provided with a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer on which the plurality of functional layers are arranged in order, a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer being respectively arranged between the plurality of functional layers, and the power cords being connected to each other via at least one functional layer in a grid line extension direction.

[0076] Other aspects will become apparent after reading and understanding the drawings and detailed description. [Brief description of the drawings]

[0077] The drawings are for understanding the technical solution of the present disclosure, are a part of the specification, and are used to interpret the technical solution of the present disclosure together with the embodiments of the present disclosure, but are not intended to limit the technical solution of the present disclosure.

[0078] [Figure 1] FIG. 1 is a structural schematic diagram of a display substrate according to the present disclosure. [Diagram 2] FIG. 2 is a side view of one subpixel in a display substrate according to the present disclosure. [Diagram 3] FIG. 3 is a plan view of one sub-pixel in a display substrate according to the present disclosure. [Figure 4A] FIG. 4A is an equivalent circuit diagram of a drive circuit according to the present disclosure. [Figure 4B] FIG. 4B is an operation sequence diagram of the drive circuit according to the present disclosure. [Diagram 5] FIG. 5 is a plan view of a plurality of sub-pixels in a display substrate according to the present disclosure. [Figure 6A]FIG. 6A is a plan view of a sub-pixel corresponding to the first embodiment. [Figure 6B] FIG. 6B is another plan view of the sub-pixel corresponding to the first embodiment. [Figure 7A] FIG. 7A is a plan view of the second metal layer corresponding to the first embodiment. [Figure 7B] FIG. 7B is a plan view of the third metal layer corresponding to the first embodiment. [Figure 8A] FIG. 8A is a plan view of a sub-pixel corresponding to the second embodiment. [Figure 8B] FIG. 8B is another plan view of the sub-pixel according to the second embodiment. [Figure 9A] FIG. 9A is a plan view of a second metal layer corresponding to the second embodiment. [Figure 9B] FIG. 9B is a plan view of the third metal layer corresponding to the second embodiment. [Figure 10] FIG. 10 is another plan view of a plurality of sub-pixels in a display substrate according to the present disclosure. [Figure 11] FIG. 11 is a flowchart of a method for manufacturing a display substrate according to the present disclosure. [Figure 12] FIG. 12 is a schematic diagram 1 showing the manufacturing method of the display substrate according to the present disclosure. [Figure 13] FIG. 13 is a schematic diagram 2 of the manufacturing method of the display substrate according to the present disclosure. [Figure 14A] FIG. 14A is a manufacturing schematic diagram 3 of a display substrate according to the present disclosure. [Figure 14B] FIG. 14B is another schematic diagram 3 of the manufacturing method of the display substrate according to the present disclosure. [Figure 15A] FIG. 15A is a schematic diagram 4 of the manufacturing method of the display substrate according to the present disclosure. [Figure 15B] FIG. 15B is another schematic diagram 4 of the manufacturing method of the display substrate according to the present disclosure. [Figure 16A] FIG. 16A is a schematic diagram 5 of the manufacturing method of the display substrate according to the present disclosure. [Figure 16B] FIG. 16B is another schematic diagram 5 of the manufacturing method of the display substrate according to the present disclosure. [Figure 17]FIG. 17 is a plan view of a plurality of sub-pixels in another display substrate according to the present disclosure. [Figure 18] FIG. 18 is a cross-sectional view of a plurality of sub-pixels in another display substrate according to the present disclosure. [Figure 19] FIG. 19 is a partial plan view of a sub-pixel in another display substrate according to the present disclosure. [Figure 20] FIG. 20 is another partial plan view of a subpixel in another display substrate according to the present disclosure. [Figure 21] FIG. 21 is another partial plan view of a subpixel in another display substrate according to the present disclosure. [Figure 22] FIG. 22 is a flowchart of another method for manufacturing a display substrate according to the present disclosure. [Diagram 23] FIG. 23 is a schematic diagram showing the manufacturing process of an active area of ​​another display substrate according to the present disclosure. [Figure 24] FIG. 24 is a schematic diagram showing the manufacturing process of a first insulating layer and a first metal layer of another display substrate according to the present disclosure. [Diagram 25] FIG. 25 is a schematic diagram showing the manufacturing process of the second insulating layer and the second metal layer of another display substrate according to the present disclosure. [Figure 26] FIG. 26 is a schematic diagram showing the manufacturing process of a third insulating layer of another display substrate according to the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0079] Although the present disclosure describes several embodiments, the description is illustrative and not restrictive, and it will be apparent to one skilled in the art that many more embodiments and implementations may be included within the scope of the embodiments described in the present disclosure. Although many possible combinations of features are shown in the drawings and discussed in specific embodiments, many other combinations of the disclosed features are possible. Unless otherwise limited, any feature or element of any embodiment may be used in combination with any other feature or element of any other embodiment, or may be substituted for any other feature or element of any other embodiment.

[0080] The present disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in the present disclosure may be combined with any conventional feature or element to form a unique inventive means defined by the claims. Any feature or element of any embodiment may be combined with features or elements from other inventive means to form a unique inventive means defined by the claims. It is therefore understood that any feature set forth and / or discussed in the present disclosure may be implemented independently or in any suitable combination. Thus, the embodiments are not limited except as limited by the appended claims and their equivalent substitutions. It is understood that various modifications and variations can be made within the scope of the appended claims.

[0081] It should be noted that, when describing representative embodiments, the specification may present a method and / or process as a particular sequence of steps. However, the method or process does not depend on or is limited to the particular order of steps described herein. As will be appreciated by those of ordinary skill in the art, other orders of steps are possible. Thus, the particular order of steps described in the specification should not be construed as limiting the scope of the claims. It should be noted that claims to the method and / or process do not necessarily require the steps to be performed in the order described, and as will be readily appreciated by those of ordinary skill in the art, these orders may vary and still be within the spirit and scope of the present disclosure.

[0082] Unless otherwise defined, technical or scientific terms used in the embodiments of the present invention should have the common meaning understood by those skilled in the art. The terms "first", "second" and similar terms used in the embodiments of the present invention are only for distinguishing different components without indicating any order, number or importance. The terms "comprise" and similar terms mean including the recited elements or objects and their equivalents, but not excluding other elements or objects. The terms "connect" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", etc. are used to indicate only relative positional relationships, and after the absolute positions of the objects being described are changed, the relative positional relationships may change correspondingly.

[0083] In this specification, the term "about" means to allow values ​​within the range of process and measurement error without strictly limiting the limits. In this specification, the term "corresponding" means that the ratio of one dimension to the other is 0.8 to 1.2.

[0084] Some embodiments of the present disclosure provide a display substrate, in a plane parallel to the display substrate, the display substrate comprises a grid line, a data line, a power cord, and a plurality of sub-pixels disposed on a base, at least one of the sub-pixels comprises a light-emitting device and a driving circuit configured to drive the light-emitting device to emit light, the driving circuit comprises a plurality of transistors and a storage capacitor, in a plane perpendicular to the display substrate, the display substrate comprises a base and a plurality of functional layers disposed on the base, the plurality of functional layers comprises a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed in sequence, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer disposed between the plurality of functional layers, respectively, and the power cords are connected to each other through at least one functional layer in the grid line extending direction. In an exemplary embodiment, the display substrate further comprises a fifth insulating layer disposed on the fourth conductive layer, and a fifth conductive layer disposed on the fifth insulating layer.

[0085] FIG. 1 is a structural schematic diagram of a display substrate according to the present disclosure, FIG. 2 is a side view of one subpixel in the display substrate according to the present disclosure, and FIG. 3 is a plan view of one subpixel in the display substrate according to the present disclosure. As shown in FIGS. 1 to 3, in a plane parallel to the display substrate, the display substrate according to the present disclosure is provided with grid lines G, data lines D, a power supply cord VDD, a reset signal line Reset, a light emission control line EM, an initial signal line Vinit, and a plurality of subpixels P. Each subpixel has a light emitting device and a light emitting device driving circuit. and a driving circuit configured to emit light, the driving circuit comprising a plurality of transistors and a storage capacitor, in a plane perpendicular to the display substrate, the display substrate comprises a base 10, a semiconductor layer 20 disposed on the base 10, a first metal layer 30, a second metal layer 40, a third metal layer 50, a fourth metal layer 60 and a fifth metal layer 70 which are insulated from each other, the first metal layer 30 being a first conductive layer, the second metal layer 40 being a second conductive layer, the third metal layer 50 being a third conductive layer, the fourth metal layer 60 being a fourth conductive layer and the fifth metal layer 70 being a fifth conductive layer. In an exemplary embodiment, the display substrate comprises a display area (AA) and a frame area located around the display area, the display area comprising a plurality of display sub-pixels, the frame area comprising a plurality of dummy sub-pixels, and the sub-pixels described herein refer to display sub-pixels in the display area.

[0086] In an exemplary embodiment, the semiconductor layer 20 may comprise active areas of a plurality of transistors, the first metal layer 30 may comprise grid lines G, light emitting control lines EM, reset signal lines Reset, a first electrode C1 of a storage capacitor and gate electrodes of a plurality of transistors, the second metal layer 40 may comprise initial signal lines Vinit and a second electrode C2 of the storage capacitor, the third metal layer 50 may comprise first and second poles of a plurality of transistors, the fourth metal layer 60 may comprise data lines D and power supply codes VDD, and the fifth metal layer 70 may comprise an anode of a light emitting device.

[0087] In an exemplary embodiment, the data line may have a plurality of sub-data lines connected in sequence in the extending direction of the data line, and the plurality of sub-data lines correspond to a plurality of sub-pixels. There is at least one sub-pixel, and two sub-data lines are disposed between the sub-pixel and an adjacent sub-pixel in the extending direction of the grid line. In an exemplary embodiment, the two sub-data lines are parallel to each other.

[0088] As shown in FIG. 1, in an exemplary embodiment, a display substrate may be provided with M rows x N columns of sub-pixels, N columns of data lines D1 to DN, N columns of power cords VDD1 to VDDN, M rows of grid lines G1 to GM, M-1 rows of emission control lines EM1 to EMM-1, a reset signal line Reset, and an initial signal line Vinit, and the display substrate may further include a data driver configured to provide data signals to the data lines, a scan driver configured to provide scan signals to the grid lines, an emission driver configured to provide emission control signals to the emission control lines, and a sequence controller configured to provide drive signals to the data driver, the scan driver, and the emission driver.

[0089] In some possible implementations, as shown in FIG. 1, the driving circuit for the sub-pixel in the i-th column is connected to the data line in the i-th column, and the data line in each column has a first sub-data line DO and a second sub-data line DE, and the first sub-data line DOi and the second sub-data line DEi of the data line in the i-th column are respectively located on both sides of the sub-pixel in the i-th column, where 1≦i≦N, and N is the total number of columns of sub-pixels.

[0090] In some possible implementations, two sub-data lines are provided between two adjacent columns of sub-pixels, i.e., the first sub-data line DO of the sub-pixels in the current column and the second sub-data line DE of the sub-pixels in the adjacent column are provided between two adjacent columns of sub-pixels, or the second sub-data line DE of the sub-pixels in the current column and the first sub-data line DO of the sub-pixels in the adjacent column are provided between two adjacent columns of sub-pixels.

[0091] For example, the first sub-data line DOi of the data line in column i is located on the side of the sub-pixel in column i+1 closer to the sub-pixel in column i+1, and the first sub-data line DOi+1 of the data line in column i+1 is located on the side of the sub-pixel in column i+1 closer to the sub-pixel in column i, or the second sub-data line DEi of the data line in column i is located on the side of the sub-pixel in column i+1 closer to the sub-pixel in column i+1, and the second sub-data line DEi+1 of the data line in column i+1 is located on the side of the sub-pixel in column i+1 closer to the sub-pixel in column i.

[0092] In some possible implementations, the base 10 may be a rigid or flexible substrate, where a rigid substrate may be one or more of, but is not limited to, glass, metal foil sheet, and a flexible substrate may be one or more of, but is not limited to, polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, aromatic polyester, polyimide, polyvinyl chloride, polyethylene, textile fiber.

[0093] In some possible implementations, the fabrication material of the semiconductor layer 20 may be polycrystalline silicon or metal oxide, and the present disclosure is not limited thereto.

[0094] In some possible implementations, the material of the first metal layer may be a metal material such as silver, aluminum or copper, and the present disclosure is not limited thereto.

[0095] In some possible implementations, the material of the second metal layer may be a metallic material such as silver, aluminum or copper, and the present disclosure is not limited thereto.

[0096] In some possible implementations, the manufacturing material of the third metal layer may be a metallic material such as silver, aluminum or copper, and the present disclosure is not limited thereto.

[0097] In some possible implementations, the fabrication material of the fourth metal layer may be a metal material such as silver, aluminum or copper, and the present disclosure is not limited thereto.

[0098] In some possible implementations, the manufacturing material of the fifth metal layer may be a metal material such as silver, aluminum or copper, and the present disclosure is not limited thereto.

[0099] FIG. 4A is an equivalent circuit diagram of the drive circuit according to the present disclosure, and FIG. 4B is an operation sequence diagram of the drive circuit according to the present disclosure. As shown in FIGS. 4A and 4B, FIG. 4A illustrates an example of a drive circuit provided in the sub-pixel of the i-th column and the sub-pixel of the i+1th column, but the drive circuit according to the present disclosure may have a 7T1C structure, and the drive circuit may include a first transistor T1 to a seventh transistor T7 and a storage capacitor C, and the storage capacitor C has a first electrode C1 and a second electrode C2.

[0100] In the exemplary embodiment, specifically, the gate electrode of the first transistor T1 is connected to the reset signal line Reset, the first pole of the first transistor T1 is connected to the initial signal line Vinit, the second pole of the first transistor T1 is connected to the first electrode C1 of the storage capacitor C, the gate electrode of the second transistor T2 is connected to the grid line G, the first pole of the second transistor T2 is connected to the first electrode C1 of the storage capacitor C, the second pole of the second transistor T2 is connected to the second pole of the sixth transistor T6, the gate electrode of the third transistor T3 is connected to the first electrode C1 of the storage capacitor C, the first pole of the third transistor T3 is connected to the second pole of the fourth transistor T4, the second pole of the third transistor T3 is connected to the second pole of the sixth transistor T6, and the gate electrode of the fourth transistor T4 is connected to the grid line G. a first electrode of the fourth transistor T4 connected to the data line D, a gate electrode of the fifth transistor T5 connected to the light emitting control line EM, a first electrode of the fifth transistor T5 connected to a power supply line VDD, a second electrode of the fifth transistor T5 connected to a first electrode of the third transistor T3, a gate electrode of the sixth transistor T6 connected to the light emitting control line EM, a second electrode of the sixth transistor T6 connected to an anode of the light emitting device, a gate electrode of the seventh transistor T7 connected to a reset signal line Reset, a first electrode of the seventh transistor T7 connected to an initial signal line Vinit, a second electrode of the seventh transistor T7 connected to an anode of the light emitting device, a second electrode C2 of the storage capacitor connected to a power supply line VDD, and a cathode of the light emitting device OLED connected to the low-level power supply side VSS.

[0101] In an exemplary embodiment, the third transistor T3 is a driving transistor, and the other transistors other than the third transistor T3 are all switching transistors, and the first transistor T1 to the seventh transistor T7 may all be P-type transistors or N-type transistors, and the present disclosure is not limited thereto.

[0102] Taking the case where the first transistor T1 to the seventh transistor T7 are all P-type transistors as an example, the operation process of the driving circuit may include the following first to third stages.

[0103] First phase P1 or reset phase: The reset signal line Reset provides an active level, the first transistor T1 and the seventh transistor T7 are turned on, and the initial signal provided by the initial signal line Vinit initializes the signal at the second electrode of the sixth transistor T6 and the signal at the first electrode C1.

[0104] Second phase P2 or the write phase: The grid line G provides an active level, turning on the second transistor T2 and the fourth transistor T4, writing the data signal provided by the data line D to the first pole of the third transistor T3, and making the potential of the gate electrode and the signal at the second pole of the second transistor T2 the same, thereby turning on the third transistor T3.

[0105] Phase 3 P3 or luminous phase: The light emitting control line EM provides an active level, the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply line VDD provides a driving current to the light emitting device OLED, thereby driving the light emitting device to emit light.

[0106] In some possible implementations, the light emitting device of the present disclosure may be an OLED, as shown in FIG. 4A.

[0107] The display substrate according to the present disclosure includes grid lines, data lines, power cords, reset signal lines, light emission control lines, initial signal lines, and a plurality of sub-pixels, each of which includes a light emitting device and a driving circuit configured to drive the light emitting device to emit light, and the driving circuit may include a plurality of transistors and a storage capacitor. The display substrate may include a base and a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer, which are insulated from each other and disposed on the base in order, the semiconductor layer includes active areas of the plurality of transistors, and the first metal layer includes the grid lines, the light emission control lines, the reset signal lines, the the first metal layer includes an initial signal line, a first electrode of a storage capacitor, and a gate electrode of the plurality of transistors; the second metal layer includes an initial signal line and a second electrode of the storage capacitor; the third metal layer includes source-drain electrodes of the plurality of transistors; the fourth metal layer includes a data line and a power cord; and the fifth metal layer includes an anode of the light emitting device; the i-th column of sub-pixels is connected to the i-th column of data lines, and the data lines of each column include a first sub-data line and a second sub-data line, and the first sub-data line and the second sub-data line of the i-th column of data lines are respectively located on both sides of the i-th column of sub-pixels, and 1≦i≦N, where N is the total number of columns of sub-pixels.

[0108] In the present disclosure, five metal layers are provided, and the data lines and power cords are provided in a layer different from the source and drain electrodes of the transistors, thereby reducing the volume occupied by the data lines connecting the sub-pixels, thereby improving the resolution of the OLED display substrate driven at high frequencies.

[0109] In some possible implementations, as shown in FIG. 3, each sub-pixel in the display substrate of the present disclosure may be divided into a first region R1, a second region R2 and a third region R3 arranged in sequence along the data line extension direction.

[0110] The storage capacitor is located in the second region R2, the first region R1 and the third region R3 are respectively located on both sides of the second region R2, the initial signal line Vinit, the grid line G and the reset signal line Reset connected to the sub-pixel driving circuit are located in the first region R1, and the emission control line EM connected to the sub-pixel driving circuit is located in the third region R3.

[0111] The driving circuits of adjacent subpixels located in the same column are connected to different sub-data lines; that is, when the subpixel in the i-th row and j-th column is connected to the first sub-data line DOj of the data line in the j-th column, the subpixel in the i+1-th row and j-th column is connected to the second sub-data line Dej of the data line in the j-th column, and when the subpixel in the i-th row and j-th column is connected to the second sub-data line DEj of the data line in the j-th column, the subpixel in the i+1-th row and j-th column is connected to the first sub-data line DOj of the data line in the j-th column.

[0112] In some possible implementations, as can be seen from Figures 1 and 3, the driving circuit of the sub-pixel in the i-th column is further connected to the power cord of the i-th column, where 1 ≤ i ≤ N. The power cord VDDi of the i-th column is located between the first sub-data line DOi and the second sub-data line DEi of the data line of the i-th column.

[0113] 5 is a plan view of a plurality of subpixels in a display substrate according to the present disclosure, and as shown in FIG. 5, the pixel structures of adjacent subpixels in the same row are mirror-symmetrical with respect to the center line CL of the two sub-data lines between the adjacent subpixels. The pixel structure of the subpixel in the i-th row and j-th column is the same as the pixel structure of the subpixel in the i-th row and j+2-th column, the pixel structure of the subpixel in the i-th row and j+1-th column is the same as the pixel structure of the subpixel in the i-th row and j+3-th column, the pixel structure of the subpixel in the i-th row and j-th column is the same as the pixel structure of the subpixel in the i+1-th row and j+1-th column, and the pixel structure of the subpixel in the i-th row and j+1-th column is the same as the pixel structure of the subpixel in the i+1-th row and j-th column. In this specification, the pixel structures being the same include, but are not limited to, the overall shapes, the connection relationships of the parts, and the direction in which the signals flow are the same.

[0114] 5, the power cords of two adjacent columns are mirror symmetric with respect to the center line between the power cords of the two adjacent columns, that is, the power cords of adjacent subpixels have a symmetric relationship with each other. The center line CL of the two sub-data lines between the subpixel in the i-th row and j-th column and the subpixel in the i-th row and j+1-th column may be the same center line as the center line between the power cord in the j-th column and the power cord in the j+1-th column.

[0115] In some possible implementations, as shown in FIG. 5 , taking 8 sub-pixels (an area including 2×4 sub-pixels) in 2 rows and 4 columns as an example, the power cord in the i-th column has multiple sub-power cords connected to each other, S1 to SN, respectively, and the multiple sub-power cords correspond one-to-one to all the sub-pixels in each column, and the multiple sub-power cords are respectively installed on the multiple sub-pixels in the column.

[0116] In an exemplary embodiment, the shape of the sub-power cord corresponding to the sub-pixel in the i-th row and j-th column after mirroring along the center line of the first and second sub-data lines of the data line in the j-th column is the same as the shape of the sub-power cord corresponding to the sub-pixel in the i+1-th row and j-th column. In this specification, the power cord shapes being the same includes, but is not limited to, the overall shapes, the connection relationships of each part, and the signal flow directions of the two being the same.

[0117] In an exemplary embodiment, each sub-power cord may include a first power supply unit SS1, a second power supply unit SS2 and a third power supply unit SS3 arranged in sequence along the second direction, the second power supply unit SS2 is configured to be connected to the first power supply unit SS1 and the third power supply unit SS3, the first power supply unit SS1 and the third power supply unit SS3 may be arranged parallel to the data line, and the included angle between the second power supply unit SS2 and the first power supply unit SS1 is greater than 90 degrees and less than 180 degrees, forming a broken line-shaped sub-power cord, and the second direction is the extension direction of the data line.

[0118] In this specification, "parallel" means that the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes the state where the angle is -5° or more and 5° or less. "Perpendicular" means that the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less. In this specification, the first power supply unit being parallel to the data line means that the body of the first power supply unit is parallel to the body of the data line, and is not limited to the edge of the first power supply unit being parallel to the edge of the data line, and allows non-parallelism due to process errors between the edge of the first power supply unit and the edge of the data line. In the connection region where the first power supply unit and the second power supply unit are connected to each other, the connection region may belong to the first power supply unit or the second power supply unit.

[0119] In an exemplary embodiment, the first power supply unit SS1, the second power supply unit SS2 and the third power supply unit SS3 may be an integrated structure.

[0120] 5, the length of the first power supply section SS1 extending along the second direction is greater than the average width of the first power supply section SS1, the length of the second power supply section SS2 extending along the inclined direction is greater than the average width of the second power supply section SS2, and the length of the third power supply section SS3 extending along the second direction is greater than the average width of the third power supply section SS3. The inclined direction is the direction in which the second power supply section and the first power supply section form the included angle. The reason why the average width of the third power supply section SS3 is smaller than the average width of the first power supply section SS1 is, firstly, due to the arrangement of the pixel structure, and, secondly, because the distance between the third power supply section SS3 and the data line is relatively short, and the third power supply section SS3 having a relatively small average width can reduce parasitic capacitance. In the present disclosure, the width of the first power supply section SS1 and the third power supply section SS3 refers to the dimension of the first power supply section SS1 and the third power supply section SS3 in a first direction, the width of the second power supply section SS2 refers to the dimension in a direction perpendicular to the tilt direction, the average width refers to the average value of the widths at multiple positions, and the first direction is the extension direction of the grid lines.

[0121] In an exemplary embodiment, in the first direction, the distance between the centerline of the first power supply section SS1 and the centerline of the third power supply section SS3 corresponds to the average width of the third power supply section SS3.

[0122] In an exemplary embodiment, the first power supply unit SS1 in the sub-power cord corresponding to the sub-pixel in the i-th row and j-th column is connected to the third power supply unit SS3 in the sub-power cord corresponding to the sub-pixel in the i-1th row and j-th column, and the third power supply unit SS3 in the sub-power cord corresponding to the sub-pixel in the i-th row and j-th column is connected to the first power supply unit SS1 in the sub-power cord corresponding to the sub-pixel in the i+1th row and j-th column, and the power supply units connected to each other are sequentially installed along the second direction (the data line extension direction).

[0123] As shown in FIG. 5, the power cord of the present disclosure may be in a bent line shape.

[0124] In an exemplary embodiment, as shown in FIG. 5 , the operation process of each sub-pixel includes: in a reset stage, a reset signal line Reset located in the first metal layer and an initial signal line Vinit located in the second metal layer provide signals to initialize a driving circuit; in a write stage, a grid line G located in the first metal layer and a data line D located in the fourth metal layer provide signals to write a data signal provided by the data line D to the driving circuit; and in an emission stage, a light emission control line EM located in the first metal layer provides a signal, a power cord VDD provides a power signal, and the driving circuit provides a driving current to the light emitting device OLED to drive the light emitting device to emit light.

[0125] Pixels in the same row are displayed simultaneously, and pixels in adjacent rows are displayed in sequence.

[0126] In some possible implementations, as shown in FIG. 2, the display substrate according to the present disclosure may further include a first insulating layer 11, a second insulating layer 12, a third insulating layer 13 and a fourth insulating layer 14.

[0127] A first insulating layer 11 is disposed between the semiconductor layer 20 and the first metal layer 30, a second insulating layer 12 is disposed between the first metal layer 30 and the second metal layer 40, a third insulating layer 13 is disposed between the second metal layer 40 and the third metal layer 50, and a fourth insulating layer 14 is disposed between the third metal layer 50 and the fourth metal layer 60.

[0128] In some possible implementations, the materials of the first insulating layer 11, the second insulating layer 12, the third insulating layer 13 and the fourth insulating layer 14 may be silicon oxide, silicon nitride or a composite of silicon oxide and silicon nitride, and the present disclosure is not limited thereto.

[0129] In an exemplary embodiment, as shown in FIG. 4A, the plurality of transistors for each subpixel may include a first transistor to a seventh transistor, and a first electrode of the fifth transistor is respectively connected to the power supply voltage VDD and the second electrode C2 of the storage capacitor.

[0130] In the present disclosure, for each sub-pixel, the power cord in each sub-pixel is connected to the second electrode of the storage capacitor by the first pole of the fifth transistor.

[0131] The second electrodes of the storage capacitors of adjacent subpixels located on the second metal layer may be multiplexed as power signal lines, configured to ensure that the power signals provided by the power cords of adjacent subpixels are the same, thereby avoiding display defects of the display substrate and ensuring the display effect of the display substrate.

[0132] In an exemplary embodiment, every fourth consecutive subpixel constitutes a pixel, and in the jth pixel, along the first direction, the four consecutive subpixels are, in order, the i th subpixel, the i+1 th subpixel, the i+2 th subpixel, and the i+3 th subpixel, where the values ​​of i are, in order, 4j-3, and j is a positive integer.

[0133] In an exemplary embodiment, there are multiple embodiments in which the second electrodes of the storage capacitors of the subpixels are connected to the power cord. As an embodiment, FIG. 6A is a plan view of a subpixel corresponding to the first embodiment, and FIG. 6B is another plan view of the subpixel corresponding to the first embodiment. As shown in FIG. 6A, the fourth insulating layer is provided with a first through hole V1 that exposes the first pole 51 of a part of the fifth transistor, and the power cord is connected to the first pole 51 of the fifth transistor through the first through hole V1. As shown in FIG. 6B, the third insulating layer is provided with a second through hole V2 that exposes the second electrode C2 of a part of the storage capacitor, and the first pole 51 of the fifth transistor is connected to the second electrode C2 of the storage capacitor through the second through hole V2. As described, FIG. 3 and FIG. 5 are used to explain the first embodiment as an example.

[0134] The orthogonal projection of the power cord connected to the subpixel on the base includes the orthogonal projection of the first through-hole V1 on the base 10, and the orthogonal projection of the second electrode of the storage capacitor on the base includes the orthogonal projection of the second through-hole on the base. In this specification, "the orthogonal projection of A includes the orthogonal projection of B" or "the orthogonal projection of B is located within the orthogonal projection range of A" means that the boundary of the orthogonal projection of B is located within the boundary range of the orthogonal projection of A, or the boundary of the orthogonal projection of A overlaps with the boundary of the orthogonal projection of B.

[0135] In some possible implementations, the number of the first through holes V1 may be one.

[0136] In some possible implementations, the number of second through holes V2 may be at least one, and when the number of second through holes V2 is multiple because the width of the first pole of the fifth transistor is relatively narrow, multiple second through holes are arranged along the data line extension direction, and multiple through holes may be arranged along the data line extension direction, and the more the number of through holes, the higher the conductivity of the components connected by the through holes. FIG. 6A is illustrated as an example of one first through hole V1, and FIG. 6B is illustrated as an example of two second through holes V2, but the present disclosure is not limited thereto.

[0137] In an exemplary embodiment, as shown in FIG. 6A , the fourth insulating layer further includes a third through hole V3 exposing a first electrode of the fourth transistor T4, and the data line is connected to the first electrode of the fourth transistor T4 through the third through hole V3, and the fourth insulating layer further includes a fourth through hole V4 exposing a second electrode of the sixth transistor T6.

[0138] In an exemplary embodiment, as shown in FIG. 6B , the first insulating layer, the second insulating layer and the third insulating layer further have through holes exposing a portion of the active area, and the source and drain electrodes of the transistor are connected to the active area through these through holes, and the source and drain electrodes of the transistor include a first electrode of the transistor and a second electrode of the transistor.

[0139] In an exemplary embodiment, the first electrode of the fifth transistor is further connected to the active area by a via on the first insulating layer, the second insulating layer and the third insulating layer.

[0140] In an exemplary embodiment, each pixel may include four sub-pixels, and Figure 7A is a plan view of a second metal layer corresponding to the first embodiment, and Figure 7B is a plan view of a third metal layer corresponding to the first embodiment. In order to more clearly explain the structure of the display substrate, Figures 7A and 7B will be described taking two pixels arranged along a column direction as an example.

[0141] As shown in FIG. 7A, the second electrodes of the storage capacitors in adjacent subpixels in the same row are directly connected, and as shown in FIG. 7B, the first electrodes 51 of the fifth transistors in adjacent subpixels in the same row are spaced apart.

[0142] In the first embodiment, the second electrodes of the storage capacitors installed on the second metal layer of multiple subpixels are connected to each other, so that the power signals provided by the power cords of adjacent subpixels can be made the same, thereby avoiding display defects of the display substrate and ensuring the display effect of the display substrate.

[0143] In an exemplary embodiment, by rationally designing the layout arrangement, the interconnection of the conductive layers of multiple subpixels may be realized only by the semiconductor layer, or the interconnection of the conductive layers of multiple subpixels may be realized only by the first metal layer, or the interconnection of the conductive layers of multiple subpixels may be realized only by the second metal layer, or the interconnection of the conductive layers of multiple subpixels may be realized only by the third metal layer, thereby realizing the interconnection in the grid line extension direction of the power cords of the subpixels in the same row by the functional layer, and detailed description thereof will be omitted here.

[0144] As shown in FIG. 7A, at least one sub-pixel further includes a first connection portion C3, which is disposed on one side of the second electrode C2 in the first direction.

[0145] In an exemplary embodiment, of the pixels in two adjacent rows, the second electrode C2 of the i-th subpixel of a pixel in one row is connected to the second electrode C2 of the i+1-th subpixel by a first connection part C3, the second electrode C2 of the i+1-th subpixel is directly connected to the second electrode C2 of the i+2-th subpixel, and the second electrode C2 of the i+2-th subpixel is connected to the second electrode C2 of the i+3-th subpixel by a first connection part C3. The second electrode C2 of the i-th subpixel of a pixel in another row is directly connected to the second electrode C2 of the i+1-th subpixel, the second electrode C2 of the i+1-th subpixel is connected to the second electrode C2 of the i+2-th subpixel by a first connection part C3, and the second electrode C2 of the i+2-th subpixel is directly connected to the second electrode C2 of the i+3-th subpixel.

[0146] As another embodiment, FIG. 8A is a plan view of a subpixel corresponding to the second embodiment, and FIG. 8B is another plan view of the subpixel corresponding to the second embodiment. As shown in FIG. 8A, a first through hole V1 is provided in the fourth insulating layer to expose a first electrode 51 of a part of the fifth transistor T5, and a power cord is connected to the first electrode 51 of the fifth transistor T5 through the first through hole V1. As shown in FIG. 8B, a second through hole V2 is provided in the third insulating layer to expose a second electrode C2 of a part of the storage capacitor, and the first electrode 51 of the fifth transistor T5 is connected to the second electrode C2 of the storage capacitor through the second through hole V2. In FIG. 8B, the area within the dashed line frame is the source area of ​​the fifth transistor T5.

[0147] As shown in Figures 8A and 8B, compared with the first embodiment, the second embodiment provides a different area occupied by the second electrode of the storage capacitor of each subpixel, and a different shape of the first pole 51 of the fifth transistor T5 of each subpixel.

[0148] In an exemplary embodiment, as shown in FIG. 8A , the fourth insulating layer further includes a third through hole V3 exposing a first electrode of the fourth transistor T4, and the data line is connected to the first electrode of the fourth transistor T4 through the third through hole V3, and the fourth insulating layer further includes a fourth through hole V4 exposing a second electrode of the sixth transistor T6.

[0149] 3 and 8B, the first insulating layer, the second insulating layer and the third insulating layer may further have through holes exposing a part of the active area, and the source and drain electrodes of the transistors may be connected to the active area through the through holes. The first electrode of the fifth transistor may further be connected to the active area through a through hole on the first insulating layer, the second insulating layer and the third insulating layer.

[0150] The orthogonal projection of the power cord in the subpixel on the base includes the orthogonal projection of the first through hole V1 on the base 10, and the orthogonal projection of the second electrode of the storage capacitor on the base includes the orthogonal projection of the second through hole on the base.

[0151] In some possible implementations, the number of the first through holes V1 may be one.

[0152] In some possible implementations, the number of second through holes V2 is at least one, and since the width of the first pole of the fifth transistor is relatively narrow, multiple second through holes are arranged along the extending direction of the data line, so that the number of through holes to be arranged can be ensured; the more the number of through holes, the higher the conductivity of the components connected by the through holes; FIG. 8A illustrates one first through hole V1, and FIG. 8B illustrates two second through holes V2 as an example, and the present disclosure does not impose any limitations thereon.

[0153] Fig. 9A is a plan view of a second metal layer corresponding to the second embodiment, Fig. 9B is a plan view of a third metal layer corresponding to the second embodiment, and Fig. 10 is another plan view of a plurality of sub-pixels in a display substrate according to the present disclosure. In order to more clearly explain the structure of the display substrate, Fig. 9A and Fig. 9B take two pixels arranged along the column direction as an example, Fig. 10 includes other film layers other than the anode of the light-emitting device, and the plurality of sub-pixels included in Fig. 10 are sub-pixels corresponding to the second embodiment.

[0154] As shown in Figures 9A and 9B, in each pixel in one row of pixels in two adjacent rows, the second electrode of the storage capacitor of the i-th subpixel and the second electrode of the storage capacitor of the i+1th subpixel are connected by the first connection portion C3, the second electrode of the storage capacitor of the i+1th subpixel and the second electrode of the storage capacitor of the i+2th subpixel are spaced apart, and the second electrode of the storage capacitor of the i+2th subpixel and the second electrode of the storage capacitor of the i+3th subpixel are connected by the first connection portion C3; in each pixel in the other row of pixels in the two adjacent rows, the second electrode of the storage capacitor of the i-th subpixel and the second electrode of the storage capacitor of the i+1th subpixel are spaced apart, the second electrode of the storage capacitor of the i+1th subpixel and the second electrode of the storage capacitor of the i+2th subpixel are connected by the first connection portion C3, and the second electrode of the storage capacitor of the i+2th subpixel and the second electrode of the storage capacitor of the i+3th subpixel are spaced apart.

[0155] As shown in FIG. 8A, the second electrode C2 of the storage capacitor in at least one subpixel may be rectangular, and the first connection portion C3 may be strip-shaped, and the first connection portion C3 is located on one side of the second electrode C2 in the first direction.

[0156] In an exemplary embodiment, of pixels in two adjacent rows, the second electrode C2 of the i-th subpixel and the second electrode C2 of the i+1-th subpixel of a pixel in one row are connected to each other by a first connection part C3, the second electrode C2 of the i+1-th subpixel and the second electrode C2 of the i+2-th subpixel are spaced apart, and the second electrode C2 of the i+2-th subpixel and the second electrode C2 of the i+3-th subpixel are connected to each other by a first connection part C3. The second electrode C2 of the i-th subpixel and the second electrode C2 of the i+1-th subpixel of a pixel in another row are spaced apart, the second electrode C2 of the i+1-th subpixel and the second electrode C2 of the i+2-th subpixel are connected to each other by a first connection part C3, and the second electrode C2 of the i+2-th subpixel and the second electrode C2 of the i+3-th subpixel are spaced apart.

[0157] As described, Figure 9A illustrates an example in which the second electrode of the storage capacitor of the i-th subpixel of the pixel in the first row and the second electrode of the storage capacitor of the i+1-th subpixel of the pixel in the first row are directly connected by the first connection portion C3, and the second electrode of the storage capacitor of the i+2-th subpixel of the pixel in the second row and the second electrode of the storage capacitor of the i+3-th subpixel of the pixel in the second row are directly connected by the first connection portion C3.

[0158] In some possible implementations, as shown in FIG. 10, in each subpixel, the orthogonal projection on the base of the first pole of the fifth transistor and the orthogonal projection on the base of the connected data line have an overlapping area.

[0159] In an exemplary embodiment, as shown in Figures 9A, 9B and 10, the jth pixel may include a second connection 56. When the second electrode C2 of the storage capacitor of the ith subpixel is connected to the second electrode C2 of the storage capacitor of the i+1th subpixel, the first pole 51 of the fifth transistor T5 in the i+1th subpixel and the first pole 51 of the fifth transistor T5 in the i+2th subpixel are connected by the second connection 56. The second electrode C2 of the storage capacitor of the ith subpixel located in the second metal layer is connected to the second electrode C2 of the storage capacitor of the i+3th subpixel located in the second metal layer by the first pole 51 of the fifth transistor T5 in the i+1th subpixel, the second connection 56 and the first pole 51 of the fifth transistor T5 in the i+2th subpixel located in the third metal layer.

[0160] In an exemplary embodiment, for the jth pixel, when the second electrode C2 of the storage capacitor of the i+1th subpixel is connected to the second electrode C2 of the storage capacitor of the i+2th subpixel, the first pole 51 of the fifth transistor T5 in the i+1th subpixel is connected by the second connection portion 56, and the first pole 51 of the fifth transistor T5 in the i+2th subpixel is connected by the second connection portion 56. The second electrode C2 of the storage capacitor of the i-th subpixel located on the second metal layer is connected to the second electrode C2 of the storage capacitor of the i+1-th subpixel located on the second metal layer by the first pole 51 and the second connection portion 56 of the fifth transistor T5 in the i-th subpixel, and the first pole 51 of the fifth transistor T5 in the i+1-th subpixel, which are located in the third metal layer, and the second electrode C2 of the storage capacitor of the i+2-th subpixel located on the second metal layer is connected to the second electrode C2 of the storage capacitor of the i+3-th subpixel located on the second metal layer by the first pole 51 and the second connection portion 56 of the fifth transistor T5 in the i+2-th subpixel, and the first pole 51 of the fifth transistor T5 in the i+3-th subpixel, which are located in the third metal layer.

[0161] In the second embodiment, the present disclosure completes a bridge connection in the horizontal direction (first direction) by the second metal layer and the third metal layer, realizes the function of a power supply connecting line, makes the power supply signal provided to each sub-pixel the same, and ensures the display effect of the display substrate.

[0162] As described, since the resistivity of the third metal layer is smaller than the resistivity of the second metal layer, the display substrate according to the second embodiment can further reduce dynamic crosstalk compared to the display substrate according to the first embodiment.

[0163] 2, the display substrate according to the present disclosure may further include a fifth insulating layer 15 and a planar layer 16 disposed between the fourth metal layer 60 and the fifth metal layer 70, and an organic light-emitting layer and a cathode (not shown) of a light-emitting device disposed on the side of the fifth metal layer 70 away from the base 10. The fifth insulating layer 15 is disposed on the side of the planar layer 16 closer to the base 10, and the cathode is disposed on the side of the organic light-emitting layer away from the base 10.

[0164] 3, the fourth metal layer according to the present disclosure may further include a connection electrode 61, which is connected to the fifth metal layer and the second pole of the sixth transistor, respectively. A fifth through hole V5 exposing the connection electrode is provided in the fifth insulating layer and the flat layer, and the fifth metal layer is connected to the connection electrode 61 through the fifth through hole V5 exposing the connection electrode 61, and a fourth through hole V4 exposing the second pole of the sixth transistor is provided in the fourth insulating layer, and the connection electrode 61 is connected to the second pole of the sixth transistor through the fourth through hole V4 exposing the second pole of the sixth transistor.

[0165] In the exemplary embodiment of the present disclosure, the data lines and the power cords are disposed in a layer different from the first pole and the second pole of the plurality of transistors, thereby reducing the area occupied by the data lines connecting the sub-pixels, thereby improving the resolution of the OLED display substrate driven at high frequency.

[0166] Based on the same inventive idea, in order to manufacture the display substrate according to the above embodiment, the present disclosure further provides a manufacturing method for the display substrate. In an exemplary embodiment, in a plane parallel to the display substrate, the display substrate comprises a grid line, a data line, a power cord and a plurality of sub-pixels disposed on a base, at least one of the sub-pixels comprises a light-emitting device and a driving circuit configured to drive the light-emitting device to emit light, the driving circuit comprises a plurality of transistors and a storage capacitor, and the manufacturing method includes: To provide a base and forming a plurality of functional layers on the base, the plurality of functional layers including a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged in that order, a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer respectively arranged between the plurality of functional layers, and the power cords being connected to each other via at least one functional layer in a grid line extension direction.

[0167] FIG. 11 is a flowchart of a method for manufacturing a display substrate according to the present disclosure. As shown in FIG. 11, the method for manufacturing a display substrate according to the present disclosure includes the following steps: A step B1 of providing a base; and step B2 of forming a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer, which are insulated from one another, on the base in that order.

[0168] In an exemplary embodiment, the semiconductor layer may comprise active areas of a plurality of transistors, the first metal layer may comprise grid lines, light emitting control lines, reset signal lines, a first electrode of a storage capacitor and gate electrodes of a plurality of transistors, the second metal layer may comprise initial signal lines and a second electrode of a storage capacitor, the third metal layer may comprise source-drain electrodes of a plurality of transistors, the fourth metal layer may comprise data lines and power cords, and the fifth metal layer may comprise an anode of a light emitting device. The driving circuit of the sub-pixels in the i-th column is connected to the data line in the i-th column, and the data line in each column comprises a first sub-data line and a second sub-data line, and the first sub-data line and the second sub-data line of the data line in the i-th column are located on both sides of the sub-pixels in the i-th column, respectively, and all the sub-data lines between the sub-pixels in two adjacent columns are only the first sub-data line or the second sub-data line.

[0169] 1≦i≦N, where N is the total number of columns of sub-pixels.

[0170] The display substrate manufactured by the method for manufacturing a display substrate according to the present disclosure has similar principles and effects, so a detailed description thereof will be omitted here.

[0171] In some possible implementations, step 200 may include: sequentially forming a semiconductor layer and a first insulating layer on a base; sequentially forming a first metal layer and a second insulating layer on the first insulating layer; sequentially forming a second metal layer and a third insulating layer on the second insulating layer; sequentially forming a third metal layer and a fourth insulating layer on the third insulating layer; sequentially forming a fourth metal layer, a fifth insulating layer and a planar layer on the fourth insulating layer; sequentially forming a fifth metal layer, an organic light-emitting layer of the light-emitting device and a cathode of the light-emitting device on the planar layer.

[0172] 12 is a schematic diagram 1 of a manufacturing method for a display substrate according to the present disclosure, FIG. 13 is a schematic diagram 2 of a manufacturing method for a display substrate according to the present disclosure, FIG. 14A is a schematic diagram 3 of a manufacturing method for a display substrate according to the present disclosure, FIG. 14B is another schematic diagram 3 of a manufacturing method for a display substrate according to the present disclosure, FIG. 15A is a schematic diagram 4 of a manufacturing method for a display substrate according to the present disclosure, FIG. 15B is another schematic diagram 4 of a manufacturing method for a display substrate according to the present disclosure, FIG. 16A is a schematic diagram 5 of a manufacturing method for a display substrate according to the present disclosure, and FIG. 16B is another schematic diagram 5 of a manufacturing method for a display substrate according to the present disclosure.

[0173] The "patterning process" referred to in this disclosure includes processes such as deposition of a film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist, etc. The deposition may use any one or more of sputtering, evaporation, and chemical vapor deposition, the coating may use any one or more of spraying, spin coating, and inkjet printing, and the etching may use any one or more of dry etching and wet etching, and the disclosure is not limited thereto. A "thin film" refers to a layer of a thin film produced by deposition or other process based on a certain material. If the "thin film" does not require a patterning process throughout the entire manufacturing process, the "thin film" may also be referred to as a "layer". If the "thin film" requires a patterning process throughout the entire manufacturing process, it is referred to as a "thin film" before the patterning process, but is referred to as a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern".

[0174] As shown in FIGS. 12 to 16B, the manufacturing process of the display substrate according to the present disclosure may include the following operations.

[0175] Step 100, provide a base 10, deposit a semiconductor thin film on the base 10, and process the semiconductor thin film using a patterning process to form a semiconductor layer 20, as shown in FIG.

[0176] In an exemplary embodiment, the semiconductor layer 20 of each subpixel may include a first active area 101 where the first transistor T1 is located, a second active area 102 where the second transistor T2 is located, a third active area 103 where the third transistor T3 is located, a fourth active area 104 where the fourth transistor T4 is located, a fifth active area 105 where the fifth transistor T5 is located, a sixth active area 106 where the sixth transistor T6 is located, and a seventh active area 107 where the seventh transistor T7 is located, and the first active area 101 to the seventh active area 107 are connected to each other to form an integral structure.

[0177] In an exemplary embodiment, the first active area 101 and the seventh active area 107 are located on the side of the first region R1 away from the second region R2, the second active area 102 and the fourth active area 104 are located on the side of the first region R1 closer to the second region R2, the third active area 103 is located in the second region R2, and the fifth active area 105 and the sixth active area 106 are located in the third region R3.

[0178] In an exemplary embodiment, the first active area 101 is connected to the second active area 102 and the seventh active area 107, respectively, the second active area 102 is connected to the third active area 103 and the sixth active area 106, respectively, and the fourth active area 104 is connected to the third active area 103 and the fifth active area 105, respectively.

[0179] In an exemplary embodiment, the first active area 101呈現出 an "n" shape, the seventh active area 107呈現出 an "L" shape, the seventh active area 107 is located on the side away from the sub-pixel center line of the first active area 101, and the sub-pixel center line is a straight line that bisects the sub-pixels in the first direction and extends along the second direction. The second active area 102呈現出 a "7" shape and is located on one side of the sub-pixel center line, and the fourth active area 104呈現出 a "1" shape and is located on the other side of the sub-pixel center line. The third active area 103呈現出 a "ji" shape, and the "ji" shape may be mirror-symmetric with respect to the sub-pixel center line. The fifth active area 105呈現出 an "L" shape, and the shape of the sixth active area 106 and the shape of the fifth active area 15 are mirror-symmetric with respect to the sub-pixel center line. In this specification, that a transistor's active area呈現出 a certain shape means referring to the shape of the active area near the gate electrode of the transistor, including but not limited to the extension area of the channel area, source-drain area of the transistor's active area, and the active area portion used for connection to the source-drain areas of other transistors.

[0180] Note: The Chinese characters "呈現出" are used to represent the unclear or non-standard expressions in the original text. It might need to be further clarified according to the actual context.In an exemplary embodiment, the active area of ​​each transistor includes a first area, a second area, and a channel area located between the first area and the second area. In an exemplary embodiment, the first area of ​​the first active area 101 is simultaneously the first area of ​​the seventh active area 107, and the second area of ​​the first active area 101 is simultaneously the first area of ​​the second active area 102. The second area of ​​the second active area 102, the second area of ​​the third active area 103, and the first area of ​​the sixth active area 106 are connected to each other, and the first area of ​​the third active area 103, the second area of ​​the fourth active area 104, and the second area of ​​the fifth active area 105 are connected to each other. The first area of ​​the fourth active area 14 is disposed on the side away from the third active area 103, and the first area of ​​the fifth active area 105 is disposed on the other side away from the third active area 103. The second area of ​​the sixth active area 106 is simultaneously the second area of ​​the seventh active area 107.

[0181] In an exemplary embodiment, the distance in the first direction between the second active area 102 and the first active area 101 is smaller than the distance in the first direction between the second active area 102 and the seventh active area 107. The distance in the first direction between the second active area 102 and the third active area 103 is smaller than the distance in the first direction between the second active area 102 and the fourth active area 104, the distance in the first direction between the second active area 102 and the third active area 103 is smaller than the distance in the first direction between the second active area 102 and the fifth active area 105, and the distance in the first direction between the second active area 102 and the first active area 101 corresponds to the distance in the first direction between the second active area 102 and the third active area 103.

[0182] In an exemplary embodiment, the seventh active area 107 and the first active area 101 are disposed in sequence along the direction from the data line for writing data signals to the power cord.

[0183] In an exemplary embodiment, the shape of the semiconductor layer 20 of the subpixel in the i-th row and j-th column is the same as the shape of the semiconductor layer 20 of the subpixel in the i+1-th row and j+1-th column, and the shape of the semiconductor layer 20 of the subpixel in the i-th row and j+1-th column is the same as the shape of the semiconductor layer 20 of the subpixel in the i+1-th row and j-th column. In the first direction, the semiconductor layers 20 of adjacent subpixels are mirror-symmetric with respect to a center line between the adjacent subpixels, that is, the semiconductor layers of adjacent subpixels have a symmetric relationship with each other in the first direction. In this specification, the semiconductor layers having the same shape include, but are not limited to, their overall shapes, the connection relationship of each part, and the direction in which a signal flows being the same.

[0184] In an illustrative embodiment, the manufacturing schematic diagram of the active area in the first embodiment is the same as the manufacturing schematic diagram of the active area in the second embodiment.

[0185] The semiconductor layers in the exemplary embodiments of the present disclosure have a reasonable arrangement and a simple structure, and can ensure the display effect of the display substrate.

[0186] Step 200, deposit a first insulating thin film and a first metal thin film in sequence on the semiconductor layer 20, and process the first metal thin film using a patterning process to form a first insulating layer covering the semiconductor layer 20 and a first metal layer 30 disposed on the first insulating layer, as shown in FIG. 13.

[0187] In an exemplary embodiment, the first metal layer 30 may include a grid line G, a reset signal line Reset, an emission control line EM, and a first electrode C1 of a storage capacitor.

[0188] In an exemplary embodiment, the grid line G, the reset signal line Reset, and the emission control line EM extend along a first direction, the grid line G and the reset signal line Reset are disposed in a first region R1, and the emission control line EM is disposed in a third region R3. The first electrode C1 of the storage capacitor may be rectangular, and the rectangular corners may be chamfered, and the first electrode C1 is disposed in the second region R2, and is located between the grid line G and the emission control line EM, and the orthogonal projection of the first electrode C1 on the base and the orthogonal projection of the third active area on the base have an overlapping region. In an exemplary embodiment, the first plate C1 is simultaneously the gate electrode of the third transistor.

[0189] In an exemplary embodiment, the reset signal line Reset in the first region R1 may not be provided with an equal width, and the width of the reset signal line Reset is the dimension of the reset signal line Reset in the second direction. The reset signal line Reset may include a region overlapping with the semiconductor layer 20 and a region not overlapping with the semiconductor layer 20, and the width of the reset signal line Reset in the region overlapping with the semiconductor layer 20 may be larger than the width of the reset signal line Reset in the region not overlapping with the semiconductor layer 20.

[0190] In an exemplary embodiment, the grid lines G in the first region R1 may not be arranged with equal width, and the width of the grid lines G is the dimension in the second direction of the grid lines G. With respect to the region of the grid lines G that overlaps with the semiconductor layer 20 and the region of the grid lines G that does not overlap with the semiconductor layer 20, the width of the grid lines G in the region that overlaps with the semiconductor layer 20 may be larger than the width of the grid lines G in the region that does not overlap with the semiconductor layer 20.

[0191] In an exemplary embodiment, the emission control line EM in the third region R3 does not have to be provided with an equal width, and the width of the emission control line EM is the dimension of the emission control line EM in the second direction. The emission control line EM includes a region overlapping with the semiconductor layer 20 and a region not overlapping with the semiconductor layer 20, and the width of the emission control line EM in the region overlapping with the semiconductor layer 20 may be larger than the width of the emission control line EM in the region not overlapping with the semiconductor layer 20.

[0192] In an example embodiment, the grid line G in the i-th row may include a first grid line portion extending along a first direction from the sub-pixel in the j-th column to the sub-pixel in the j+1-th column, a first end of the first grid line portion connected to the grid line G by a connecting strip located at the sub-pixel in the i-th row, j-th column, and a second end of the first grid line portion connected to the grid line G by a connecting strip located at the sub-pixel in the i-th row, j-th column, so as to simultaneously form a double grid structure in the sub-pixel in the i-th row, j-th column and the sub-pixel in the i-th row, j+1-th column. The grid line G in the i+1th row may include a second grid line portion extending along the first direction from the sub-pixel in the j+1th column to the sub-pixel in the j+2th column, a first end of the second grid line portion being connected to the grid line G by a connecting strip located at the sub-pixel in the i+1th row and the j+1th column, and a second end of the second grid line portion being connected to the grid line G by a connecting strip located at the sub-pixel in the i+1th row and the j+2th column, so that a double grid structure is simultaneously formed in the sub-pixel in the i+1th row and the j+1th column and the sub-pixel in the i+1th row and the j+2th column. Thus, the second transistor T2 of the double grid structure is simultaneously formed in the sub-pixel in the jth column and the sub-pixel in the j+1th column, so that the second transistor T2 of the sub-pixel in the jth column and the second transistor T2 of the sub-pixel in the j+1th column form a double grid area 110.

[0193] In an exemplary embodiment, the area where the first electrode C1 overlaps with the third active area is the third gate electrode (double grid structure), the area where the grid line G overlaps with the second active area is the second gate electrode (double grid structure), the area where the reset signal line Reset overlaps with the first active area is the first gate electrode (double grid structure), the area where the grid line G overlaps with the fourth active area is the fourth gate electrode, the area where the reset signal line Reset overlaps with the seventh active area is the seventh gate electrode, the area where the light emission control line EM overlaps with the fifth active area is the fifth gate electrode, and the area where the light emission control line EM overlaps with the sixth active area is the sixth gate electrode.

[0194] In an exemplary embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 are all double-grid transistors, so that the distance in the first direction between the double-grid second transistor T2 and the other double-grid transistors (the first transistor T1 and the third transistor T3) is smaller than the distance in the first direction between the second transistor T2 and the single-grid fourth transistor T4, the fifth transistor T5, and the seventh transistor T7.

[0195] In an exemplary embodiment, after forming a pattern of the first metal layer 30, the semiconductor layer may be conductively processed using the first metal layer 30 as a shield, whereby the semiconductor layer in the area shielded by the first metal layer 30 forms the channel regions of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the area not shielded by the first metal layer 30 is conductive, i.e., the first and second areas of the first transistor T1 to the seventh transistor T7 are conductive.

[0196] In an illustrative embodiment, the manufacturing schematic diagram of the first metal layer in the first embodiment is the same as the manufacturing schematic diagram of the first metal layer in the second embodiment.

[0197] The first metal layer in the exemplary embodiment of the present disclosure has a reasonable arrangement and a simple structure, and can ensure the display effect of the display substrate.

[0198] Step 300, deposit a second insulating thin film and a second metal thin film in sequence on the first metal layer 30, and process the second metal thin film using a patterning process to form a second insulating layer covering the first metal layer 30 and a second metal layer 40 disposed on the second insulating layer, the second metal layer 40 comprising at least an initial signal line Vinit and a second electrode C2 of the storage capacitor. Then, deposit a third insulating thin film on the second metal layer 40, and process the third insulating thin film using a patterning process to form a third insulating layer covering the second metal layer 40, and a plurality of through holes are disposed on the third insulating layer, as shown in FIG. 14A and FIG. 14B.

[0199] In an exemplary embodiment, the multiple through holes on the third insulating layer include at least a second through hole V2 exposing the second electrode C2, a sixth through hole V6 exposing the initial signal line Vinit, a seventh through hole V7 exposing the first electrode C1, an eighth through hole V8 exposing the fourth active area, a ninth through hole V9 exposing the second active area, a tenth through hole V10 exposing the first active area, and multiple through holes exposing other active areas in the semiconductor layer. The third insulating layer in the second through hole V2 exposing the second electrode C2 and the sixth through hole V6 exposing the initial signal line Vinit is etched, the second insulating layer and the third insulating layer in the seventh through hole V7 exposing the first electrode C1 are etched, and the first, second and third insulating layers in the eighth through hole V8 exposing the fourth active area, the ninth through hole V9 exposing the second active area, the tenth through hole V10 exposing the first active area, and the through holes exposing other active areas in the semiconductor layer are etched.

[0200] In an exemplary embodiment, the second through hole V2 is configured to connect the second electrode C2 to the first pole of the fifth transistor T5 to be formed subsequently, the sixth through hole V6 is configured to connect the initial signal line Vinit to the first pole of the first transistor T1 to be formed subsequently, the seventh through hole V7 is configured to connect the first electrode C1 to the first pole of the second transistor T2 to be formed subsequently, the eighth through hole V8 is configured to connect the active layer of the fourth transistor T4 to the first pole of the fourth transistor T4 to be formed subsequently, the ninth through hole V9 is configured to connect the active layer of the second transistor T2 to the first pole of the second transistor T2 to be formed subsequently, and the tenth through hole V10 is configured to connect the active layer of the first transistor T1 to the first pole of the first transistor T1 to be formed subsequently. Since the first pole of the fourth transistor T4 to be formed subsequently is connected to the data line D to be formed subsequently, the eighth through hole V8 is a data write hole.

[0201] In an exemplary embodiment, the distance in the first direction between the data write hole and the second transistor T2 is larger than the distance in the first direction between the data write hole and the first transistor T1 and is larger than the distance in the first direction between the data write hole and the seventh transistor T7. The distance in the second direction between the data write hole and the third transistor T3 is smaller than the distance in the second direction between the data write hole and the fifth transistor T5 and is smaller than the distance in the second direction between the data write hole and the sixth transistor T6.

[0202] In an exemplary embodiment, the number of the second through holes V2 may be two, and the two second through holes are arranged in sequence along the second direction. Because the width of the fifth first pole is relatively narrow, the arrangement of the two second through holes V2 can improve the connection reliability between the second electrode and the fifth first pole.

[0203] In an exemplary embodiment, the initial signal line Vinit extends along the first direction, is disposed in the first region R1, and is located on the side of the reset signal line Reset away from the second region R2. The second electrode C2 of the storage capacitor in each subpixel may have a rectangular outline, is disposed in the second region R2, and is located between the grid line G and the emission control line EM.

[0204] In an exemplary embodiment, the contour of the second electrode C2 may be rectangular, and the corners of the rectangle may be chamfered, and the orthogonal projection of the second electrode C2 on the base and the orthogonal projection of the first electrode C1 on the base have an overlapping area. An opening 111 is provided at the center of the second electrode C2, and the opening 111 may be rectangular, forming the second electrode C2 into a ring structure. The opening 111 exposes the second insulating layer covering the first electrode C1, and the orthogonal projection of the first electrode C1 on the base includes the orthogonal projection of the opening 111 on the base. In an exemplary embodiment, the orthogonal projection of the opening 111 on the base includes the orthogonal projection of the seventh through hole V7 exposing the first electrode C1 on the base.

[0205] The orthogonal projection of the edge of the second electrode C2 near the first region R1 onto the base overlaps with the orthogonal projection of the boundary between the first region R1 and the second region R2 onto the base, and the orthogonal projection of the edge of the second electrode C2 near the third region R3 onto the base overlaps with the orthogonal projection of the boundary between the second region R2 and the third region R3 onto the base, i.e., the second length of the second electrode C2 is equal to the second length of the second region R2, and the second length refers to the dimension in the second direction.

[0206] In the first embodiment, the second electrodes C2 of adjacent sub-pixels in a row are connected to each other in an integrated structure, which allows the second electrodes C2 of adjacent sub-pixels to be multiplexed as power signal lines, and ensures that the power signals provided by the power cords of adjacent sub-pixels are the same, thereby avoiding display defects of the display substrate and ensuring the display effect of the display substrate.

[0207] In the second embodiment, the second electrode C2 of the subpixel in the i row, j column and the second electrode C2 of the subpixel in the i row, j+1 column are connected to each other by a first connection portion in an integrated structure, the second electrode C2 of the subpixel in the i row, j+1 column and the second electrode C2 of the subpixel in the i row, j+2 column are installed so as to be disconnected, and the second electrode C2 of the subpixel in the i row, j+2 column and the second electrode C2 of the subpixel in the i row, j+3 column are connected to each other by a first connection portion in an integrated structure. The second electrode C2 of the sub-pixel in the i+1th row, jth column is arranged to be disconnected from the second electrode C2 of the sub-pixel in the i+1th row, jth column, and the second electrode C2 of the sub-pixel in the i+1th row, j+1th column is arranged to be disconnected from the second electrode C2 of the sub-pixel in the i+1th row, j+1th column, and the second electrode C2 of the sub-pixel in the i+1th row, j+2th column is arranged to be disconnected from the second electrode C2 of the sub-pixel in the i+1th row, j+3th column. This structure allows the second electrodes C2 of adjacent sub-pixels to be multiplexed as power signal lines, and ensures that the power signals provided by the power cords of adjacent sub-pixels are the same, thereby avoiding display defects and ensuring the display effect of the display substrate.

[0208] FIG. 14A is a schematic diagram of the manufacturing method according to the first embodiment, and FIG. 14B is a schematic diagram of the manufacturing method according to the second embodiment.

[0209] The second metal layer and the through holes in the exemplary embodiment of the present disclosure have a reasonable arrangement and a simple structure, and can ensure the display effect of the display substrate.

[0210] Step 400: deposit a third metal thin film on the third insulating layer, and process the third metal thin film by a patterning process to form a third metal layer 50, which includes at least a first pole 51 of the fifth transistor T5, a second pole 52 of the sixth transistor T6, a first pole 53 of the fourth transistor T4, a first pole 54 of the first transistor T1 and a first pole 55 of the second transistor T2. The first pole 51 of the fifth transistor T5 is connected to the second electrode C2 through the second through-hole V2, the second pole 52 of the sixth transistor T6 is connected to the active layer of the sixth transistor through a through-hole, the first pole 53 of the fourth transistor T4 is connected to the active layer of the fourth transistor T4 through the eighth through-hole V8, the first pole 54 of the first transistor T1 is connected at one end to the initial signal line Vinit through the sixth through-hole V6 and at the other end to the active layer of the first transistor T1 through the tenth through-hole V10, the first pole 55 of the second transistor T2 is connected at one end to the first electrode C1 through the seventh through-hole V7 and at the other end to the active layer of the second transistor T2 through the ninth through-hole V9. Then, a fourth insulating thin film is deposited on the third metal layer 50, and the fourth insulating thin film is processed by a patterning process to form a fourth insulating layer covering the third metal layer 50, and a number of through-holes are provided on the fourth insulating layer, as shown in FIG. 15A and FIG. 15B.

[0211] In an exemplary embodiment, the plurality of through holes on the fourth insulating layer include at least a first through hole V1 exposing the first pole 51 of the fifth transistor T5, a fourth through hole V4 exposing the second pole 52 of the sixth transistor T6, and a third through hole V3 exposing the first pole 53 of the fourth transistor T4. The first through hole V1 exposing the first pole 51 of the fifth transistor T5 is configured to connect the first pole 51 of the fifth transistor T5 to a power supply line VDD to be formed subsequently, the fourth through hole V4 exposing the second pole 52 of the sixth transistor T6 is configured to connect the second pole 52 of the sixth transistor T6 to a connection electrode to be formed subsequently, and the third through hole V3 exposing the first pole 53 of the fourth transistor T4 is configured to connect the first pole 53 of the fourth transistor T4 to a data line D to be formed subsequently.

[0212] In an exemplary embodiment, the orthogonal projections of the first through-holes V1 on the base and the orthogonal projections of the grid lines G on the base have an overlap area.

[0213] In an exemplary embodiment, the orthogonal projection of the first through-hole V1 on the base and the orthogonal projection of the second electrode C2 on the base have an overlap region.

[0214] In an exemplary embodiment, the orthogonal projection of the third through-holes V3 on the base and the orthogonal projection of the grid lines G on the base have an overlap area.

[0215] In the illustrative embodiment, the orthogonal projection of the fourth through hole V4 on the base and the orthogonal projection of the light-emitting control line EM on the base have an overlapping region.

[0216] In the first embodiment, the first poles 51 of the fifth transistors T5 of adjacent sub-pixels in the same row are spaced apart.

[0217] In the second embodiment, the first pole 51 of the fifth transistor T5 in the subpixel in the i row, j+1 column and the first pole 51 of the fifth transistor T5 in the subpixel in the i row, j+2 column are connected by a second connection portion, the first pole 51 of the fifth transistor T5 in the subpixel in the i+1 row, j column and the first pole 51 of the fifth transistor T5 in the subpixel in the i row, j+1 column are connected by a second connection portion, and the first pole 51 of the fifth transistor T5 in the subpixel in the i+1 row, j+2 column and the first pole 51 of the fifth transistor T5 in the subpixel in the i row, j+3 column are connected by a second connection portion.

[0218] FIG. 15A is a schematic diagram of the manufacturing method according to the first embodiment, and FIG. 15B is a schematic diagram of the manufacturing method according to the second embodiment.

[0219] The third metal layer and the through holes in the exemplary embodiment of the present disclosure have a reasonable arrangement and a simple structure, and can ensure the display effect of the display substrate.

[0220] Step 500: deposit a fourth metal thin film on the fourth insulating layer, and process the fourth metal thin film by a patterning process to form a fourth metal layer 60 including a first sub-data line DO, a second sub-data line DE, a power supply code VDD and a connection electrode 61, in which the first sub-data line DO and the second sub-data line DE are respectively connected to the first pole 53 of the fourth transistor T4 through a third through-hole V3 exposing the first pole 53 of the fourth transistor T4 in the sub-pixel where they are located, the power supply code VDD is connected to the first pole 51 of the fifth transistor T5 through a first through-hole V1 exposing the first pole 51 of the fifth transistor T5, and the connection electrode 61 is connected to the second pole 52 of the sixth transistor T6 through a fourth through-hole V4 exposing the second pole 52 of the sixth transistor T6. Then, a fifth insulating thin film is deposited on the fourth metal layer 60, a flat thin film is coated on the fifth insulating thin film, and the flat thin film and the fifth insulating thin film are processed by a patterning process to form a fifth insulating layer covering the fourth metal layer 60 and a flat layer disposed on the fifth insulating layer, and a plurality of through holes are disposed on the flat layer, as shown in Figures 16A and 16B.

[0221] In an exemplary embodiment, the first sub-data line DO, the second sub-data line DE and the power supply code VDD extend along the second direction, the first sub-data line DO is located on one side of the sub-pixel, the second sub-data line DE is located on the other side of the sub-pixel, and the power supply code VDD is located between the first sub-data line DO and the second sub-data line DE.

[0222] In an exemplary embodiment, the first sub-data line DO and the second sub-data line DE may be straight lines of equal width, and the width of the first sub-data line DO and the second sub-data line DE is the dimension of the first sub-data line DO and the second sub-data line DE in the first direction.

[0223] In an exemplary embodiment, the first poles of the fourth transistors of adjacent subpixels in the same column are connected to different sub-data lines. For example, the subpixel in the i-th row and j-th column is connected to the first sub-data line of the j-th data line, and the subpixel in the i+1-th row and j-th column is connected to the second sub-data line of the j-th data line. Or, the subpixel in the i-th row and j-th column is connected to the second sub-data line of the j-th data line, and the subpixel in the i+1-th row and j-th column is connected to the first sub-data line of the j-th data line.

[0224] In an exemplary embodiment, in at least one subpixel, the first sub-data line DO is connected to the first pole 53 of the fourth transistor T4 by the third through-hole V3 in the subpixel in which it is located, the first pole 53 of the fourth transistor T4 is connected to the fourth active area by the eighth through-hole V8, the eighth through-hole V8 is a data write hole, and the first sub-data line DO is a data line for writing a data signal in the subpixel. In at least one subpixel, the second sub-data line DE is connected to the first pole 53 of the fourth transistor T4 by the third through-hole V3 in the subpixel in which it is located, the first pole 53 of the fourth transistor T4 is connected to the fourth active area by the eighth through-hole V8, the eighth through-hole V8 is a data write hole, and the second sub-data line DE is a data line for writing a data signal in the subpixel.

[0225] In the illustrative embodiment, the power supply code VDD of each subpixel is connected to the first pole 51 of the fifth transistor T5 through the first through hole V1, and the first pole 51 of the fifth transistor T5 is connected to the second electrode C2 of the storage capacitor, so that the second electrodes C2 of the storage capacitors of adjacent subpixels are connected to each other, thus not only realizing the connection between the power supply code VDD and the second electrode C2, but also realizing the function of the power supply connecting line of the second electrode C2, making the power supply signal provided to each subpixel the same, and ensuring the display effect of the display substrate.

[0226] In an exemplary embodiment, the power cord VDD of each subpixel may be a broken line. Along the second direction, the power cord VDD of each subpixel may include a first power supply unit, a second power supply unit, and a third power supply unit connected in sequence. In the power cord corresponding to the subpixel in the i-th row and j-th column, the first end of the first power supply unit is connected to the second end of the third power supply unit in the subpixel in the i-1-th row and j-th column, the second end of the first power supply unit extends along the second direction and is connected to the first end of the second power supply unit, the second end of the second power supply unit extends along the oblique direction and is connected to the first end of the third power supply unit, and the oblique direction and the second direction have an included angle, and the included angle may be greater than 0 degrees and less than 90 degrees, and the second end of the third power supply unit extends along the second direction and is connected to the first end of the first power supply unit in the subpixel in the i+1-th row and j-th column.

[0227] In an exemplary embodiment, the first power supply unit may be a straight line with equal width, the second power supply unit may be a diagonal line with equal width, and the third power supply unit may be a straight line with equal width. The first power supply unit and the second power supply unit may be parallel to the first sub-data line (or the second sub-data line), and the included angle between the second power supply unit and the first power supply unit may be greater than 90 degrees and less than 180 degrees, and the included angle between the second power supply unit and the third power supply unit may be greater than 90 degrees and less than 180 degrees.

[0228] In an exemplary embodiment, the length along which the first power supply unit extends along the first direction is greater than the average width of the first power supply unit, the length along which the second power supply unit extends along the oblique direction is greater than the average width of the second power supply unit, and the length along which the third power supply unit extends along the first direction is greater than the average width of the third power supply unit, and the oblique direction is a direction in which the second power supply unit and the first power supply unit form an angle.

[0229] In an exemplary embodiment, the average width of the third power supply unit may be smaller than the average width of the first power supply unit, and the average width of the third power supply unit may be smaller than the average width of the second power supply unit. The power cord VDD is arranged on a bent line with a varying width, which not only helps the arrangement of the pixel structure, but also reduces the parasitic capacitance of the power cord VDD and the data line. Since the distance between the third power supply unit and the data line is relatively short, the parasitic capacitance of the third power supply unit and the data line can be reduced by reducing the average width of the third power supply unit.

[0230] In example embodiments, the average width of the first power supply portion may be greater than or equal to the average width of the second power supply portion, or may be less than the average width of the second power supply portion.

[0231] In an exemplary embodiment, the length of the second power supply unit in the extension direction corresponds to the second length of the first electrode C1, and the second length of the first electrode C1 is the dimension of the first electrode C1 in the second direction. The length of the first power supply unit in the extension direction corresponds to the second length of the second electrode C2, the length of the third power supply unit in the extension direction corresponds to the second length of the second electrode C2, and the second length of the second electrode C2 is the dimension of the second electrode C2 in the second direction.

[0232] 3, 16A and 16B, in an exemplary embodiment, the orthogonal projection on the base of the first power supply unit and the orthogonal projection on the base of the first pole 55 and the ninth through hole V9 of the second transistor T2 have an overlapping area, therefore, the orthogonal projection on the base of the first power supply unit and the orthogonal projection on the base of the second transistor T2 have an overlapping area, the orthogonal projection on the base of the second power supply unit and the orthogonal projection on the base of the first through hole V1 have an overlapping area, and the orthogonal projection on the base of the third power supply unit and the orthogonal projection on the base of the first pole 51 of the fifth transistor T5 have an overlapping area, therefore, the orthogonal projections on the bases of the second power supply unit and the third power supply unit both have an overlapping area with the first pole 51 of the fifth transistor T5.

[0233] In an exemplary embodiment, the orthogonal projection of the first through hole V1 on the base and the orthogonal projection of the extension line of the first power supply unit in the second direction on the base have an overlapping area, the orthogonal projection of the first through hole V1 on the base and the orthogonal projection of the extension line of the third power supply unit in the second direction on the base have an overlapping area, and therefore, in the first direction, the distance between the first power supply unit and the third power supply unit in the first direction is smaller than the first length of the first through hole V1 or the average width of the third power supply unit, that is, the distance between the edge of the first power supply unit closer to the third power supply unit and the edge of the third power supply unit closer to the first power supply unit is smaller than the first length of the first through hole V1 or the width of the third power supply unit, and the first length of the first through hole V1 refers to the dimension of the first through hole V1 in the first direction. Therefore, it may be understood that for a second power supply unit extending along an inclined direction, the second power supply unit bends the power cord VDD. In the first direction, the degree of bending corresponds to the first length of the first through hole V1 or the width of the third power supply unit, and in the second direction, the degree of bending corresponds to the second length of the first electrode C1. In this specification, the edges of the two power supply units refer to the edges of the entire contours of the two power supply units.

[0234] In an exemplary embodiment, the orthogonal projection of the second power supply portion on the base and the orthogonal projection of the second electrode on the base have an overlap region.

[0235] In an exemplary embodiment, the orthogonal projection of the second power supply portion on the base and the orthogonal projection of the first connection portion on the base have an overlap region.

[0236] In an exemplary embodiment, the orthogonal projection on the base of the second power supply portion and the orthogonal projection on the base of the first electrode C1 have an overlap region.

[0237] In an exemplary embodiment, the orthogonal projection on the base of the second power supply unit and the orthogonal projection on the base of the grid lines G have an overlapping area, i.e., the orthogonal projection on the base of the second power supply unit and the orthogonal projection on the base of the gate electrode of the second transistor T2 and the gate electrode of the fourth transistor T4 have an overlapping area.

[0238] In an exemplary embodiment, the connection electrode 61 is strip-shaped extending along the second direction, the extension direction of the connection electrode 61 is parallel to the extension direction of the third power supply unit, and the length of the connection electrode 61 in the second direction corresponds to the length of the third power supply unit in the second direction.

[0239] In an exemplary embodiment, the orthogonal projection on the base of the connecting electrode 61 and the orthogonal projection on the base of the second electrode C2 have an overlap region.

[0240] In an exemplary embodiment, the orthogonal projection onto the base of the connecting electrode 61 and the orthogonal projection onto the base of the central opening 111 of the second electrode C2 have an overlap area.

[0241] In an exemplary embodiment, the orthogonal projection of the connecting electrode 61 on the base and the orthogonal projection of the second first pole 55 on the base have an overlap area.

[0242] In an exemplary embodiment, the extension direction of the connection electrode 61 overlaps with the extension direction of the first power supply unit, i.e., the orthogonal projection of the connection electrode 61 on the base and the orthogonal projection of the dummy extension line of the first power supply unit in the second direction on the base have an overlapping area.

[0243] In an exemplary embodiment, the eighth through hole V8 (i.e., the data writing hole) is located on the dummy extension line of the third power supply unit in the second direction, i.e., the orthogonal projection of the eighth through hole V8 on the base and the orthogonal projection of the dummy extension line of the third power supply unit in the second direction on the base have an overlapping area.

[0244] In an exemplary embodiment, the power supply code VDD of each subpixel is connected to the first pole 51 of the fifth transistor T5 through the first through hole V1, and the first pole 51 of the fifth transistor T5 is connected to the second electrode C2 of the storage capacitor through the second through hole V2, thereby connecting the power supply code VDD to the second electrode C2 of the storage capacitor, and therefore the first through hole V1 is referred to as a power supply write hole.

[0245] In an exemplary embodiment, the orthogonal projection of the power writing hole on the base is located within the orthogonal projection range on the base of the second power supply unit. The distance in the first direction between the power writing hole and the fourth transistor T4 corresponds to the distance in the first direction between the power writing hole and the second transistor T2. The distance in the second direction between the power writing hole and the second transistor T2 is smaller than the distance in the second direction between the power writing hole and the first transistor T1 and is smaller than the distance in the second direction between the power writing hole and the seventh transistor T7, and the distance in the second direction between the power writing hole and the third transistor T3 is smaller than the distance in the second direction between the power writing hole and the fifth transistor T5 and is smaller than the distance in the second direction between the power writing hole and the sixth transistor T6.

[0246] In an exemplary embodiment, the plurality of through holes on the fifth insulating layer and the flat layer are configured to at least connect the connection electrode 61 to a subsequently formed fifth metal layer (anode), and include a fifth through hole V5 exposing the connection electrode 61. Since the connection electrode 61 and the second electrode 52 of the sixth transistor T6 are connected, the connection between the second electrode 52 of the sixth transistor T6 and the fifth metal layer is realized, and the driving circuit can drive the light-emitting device to emit light.

[0247] In an exemplary embodiment, the connection electrode 61 is connected to the second pole 52 of the sixth transistor T6 by a fourth through hole V4, which is located at one end of the connection electrode 61 away from the second power supply unit. The connection electrode 61 is connected to an anode to be formed subsequently by a fifth through hole V5, which is located at one end of the connection electrode 61 closer to the second power supply unit, and an orthogonal projection of the fifth through hole V5 on the base and an orthogonal projection of the second electrode C2 of the storage capacitor on the base have an overlapping area.

[0248] In an exemplary embodiment, the fifth through hole V5 is located on a dummy extension line of the first power supply unit in the second direction, i.e., the orthogonal projection of the fifth through hole V5 on the base and the orthogonal projection of the dummy extension line of the first power supply unit in the second direction on the base have an overlapping area.

[0249] FIG. 16A is a schematic diagram of the manufacturing method according to the first embodiment, and FIG. 16B is a schematic diagram of the manufacturing method according to the second embodiment.

[0250] The fourth metal layer and the through hole in the exemplary embodiment of the present disclosure have a reasonable arrangement and a simple structure, and can ensure the display effect of the display substrate.

[0251] Step 600, deposit a fifth metal thin film on the planar layer, and process the fifth metal thin film by a patterning process to form a fifth metal layer 70, the fifth metal layer 70 having at least an anode, the anode being connected to the connection electrode 61 by a fifth through hole exposing the connection electrode 61. The anode is connected to the connection electrode 61, and the connection electrode 61 is connected to the second electrode 52 of the sixth transistor T6, so that the connection between the second electrode 52 of the sixth transistor T6 and the anode is realized, and the sixth transistor can drive the light-emitting device to emit light. Then, coat a pixel-defining thin film on the fifth metal layer, and process the pixel-defining thin film by a patterning process to form a pixel-defining layer, a pixel opening is provided in the pixel-defining layer of each sub-pixel, and the anode is exposed from the pixel opening. Then, form an organic light-emitting layer by a deposition process, and form a cathode on the organic light-emitting layer.

[0252] The structure and its manufacturing process disclosed in the present disclosure are merely exemplary descriptions, and in the exemplary embodiments, the corresponding structure may be changed or a patterning process may be added or omitted according to actual needs. For example, the power cord VDD and the first or second pole of some transistors may be located on the third metal layer 50, and the data line D and the first or second pole of some transistors may be located on the fourth metal layer 60. Furthermore, for example, the data line D and the first or second pole of some transistors may be located on the third metal layer 50, and the power cord VDD and the first or second pole of some transistors may be located on the fourth metal layer 60. Furthermore, for example, the power cord VDD and the data line D may be located on the third metal layer 50, and the first and second poles of the first to seventh transistors may be located on the fourth metal layer 60, and the present disclosure is not limited.

[0253] Fig. 17 is a plan view of a plurality of subpixels in another display substrate according to the present disclosure, and Fig. 18 is a cross-sectional view of a plurality of subpixels in another display substrate according to the present disclosure, and Fig. 17 will be explained using eight subpixels (top four columns and top two rows) as an example. As shown in Fig. 1, Fig. 17 and Fig. 18, the display substrate according to the present disclosure includes a base 10, a plurality of subpixels P disposed on the base 10, a plurality of power cords VDD, and a data line D disposed on the same layer as the power cords VDD, each subpixel P includes a driving circuit, which may include a plurality of transistors and a storage capacitor, and the storage capacitor includes a first electrode C1 and a second electrode C2 disposed opposite to each other, the active area 21 of the transistor is located on the side of the second electrode C2 of the storage capacitor closer to the base 10, and the power cord VDD is located on the side of the second electrode C2 of the storage capacitor away from the base 10.

[0254] In an exemplary embodiment, in at least one subpixel, the power supply code VDD is respectively connected to the second electrode C2 of the storage capacitor and the third connection part of the semiconductor layer, the second electrode C2 of the storage capacitor of each subpixel is connected to the second electrode C2 of the storage capacitor of one adjacent subpixel in the same row, and the semiconductor layer of each subpixel and the semiconductor layer of the other adjacent subpixel in the same row are connected to each other by the third connection part.

[0255] In some possible implementations, as shown in Fig. 17, the driving circuit of the sub-pixel of the i-th column is connected to the data line of the i-th column and the power cord of the i-th column, where 1≦i≦N. The data line of each column includes a first sub-data line and a second sub-data line, the first sub-data line DOi and the second sub-data line DEi of the data line Di of the i-th column are respectively located on both sides of the sub-pixel of the i-th column, and the power cord VDDi of the i-th column is located between the first sub-data line DOi and the second sub-data line DEi of the data line Di of the i-th column.

[0256] In some possible implementations, adjacent sub-pixels in the same column are connected to different sub-data lines, i.e., when the sub-pixel in the i-th row, j-th column is connected to the first sub-data line DOj of the data line in the j-th column, the sub-pixel in the i+1-th row, j-th column is connected to the second sub-data line DEj of the data line in the j-th column, and when the sub-pixel in the i-th row, j-th column is connected to the second sub-data line DEj of the data line in the j-th column, the sub-pixel in the i+1-th row, j-th column is connected to the first sub-data line DOj of the data line in the j-th column.

[0257] In some possible implementations, the arrangement manner of the first and second sub-data lines of adjacent data lines is reversed, that is, if the first sub-data line DOi of the data line Di in the i-th column is located on the first side of the sub-pixel in the i-th column and the second sub-data line DEi of the data line Di in the i-th column is located on the second side of the sub-pixel in the i-th column, the second sub-data line DEi+1 of the data line Di+1 in the i+1-th column is located on the first side of the sub-pixel in the i+1-th column and the first sub-data line DEi+1 of the data line Di+1 in the i+1-th column is located on the second side of the sub-pixel in the i+1-th column. When the data line DOi+1 of the data line Di for the i-th column is located on the second side of the sub-pixel in the i+1-th column, or the first sub-data line DOi of the data line Di for the i-th column is located on the second side of the sub-pixel in the i-th column and the second sub-data line DEi of the data line Di for the i-th column is located on the first side of the sub-pixel in the i-th column, the second sub-data line DEi+1 of the data line Di+1 for the i+1-th column is located on the second side of the sub-pixel in the i+1-th column, and the first sub-data line DOi+1 of the data line Di+1 for the i+1-th column is located on the first side of the sub-pixel in the i+1-th column.

[0258] 17 and 18, in an exemplary embodiment, the display substrate may include a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, a grid line G, a reset signal line Reset, a light emission control signal line EM, and an initial signal line Vinit, which are sequentially disposed on a base 10. The grid line G, the reset signal line Reset, the light emission control signal line EM, the first electrode C1 of the storage capacitor, and the gate electrode of the transistor are disposed on the same layer, the second electrode C2 of the storage capacitor and the initial signal line Vinit are disposed on the same layer, the data line D, the power supply VDD line, and the source and drain electrodes of the transistor are disposed on the same layer, and the source and drain electrodes of the transistor include the first pole and the second pole of the transistor.

[0259] In an exemplary embodiment, a first insulating layer 11 is disposed between the active area 21 of the transistor and the gate electrode of the transistor, a second insulating layer 12 is disposed between the gate electrode of the transistor and the second electrode C2 of the storage capacitor, and a third insulating layer 13 is disposed between the second electrode C2 of the storage capacitor and the data line.

[0260] In an exemplary embodiment, the manufacturing materials of the gate electrode of the transistor, the source and drain electrodes of the transistor, the data line D and the power cord VDD are all metal, and may be metal materials such as silver, aluminum or copper, and the present disclosure is not limited thereto.

[0261] In an exemplary embodiment, the fabrication material of the active area 21 is polycrystalline silicon, which is not a limitation of the present disclosure.

[0262] The present disclosure ensures that the power signals provided by the power cords in all sub-pixels in the same row are the same by using the second electrodes of the storage capacitors connected to each other and the semiconductor layers connected to each other, thereby avoiding display defects of the display substrate and ensuring the display effect of the display substrate.

[0263] The present disclosure transmits power signals in the power cord by multiplexing the second electrode of the storage capacitor and the semiconductor layer as a power connection line, and since the distance between the active area of ​​the transistor and the data line is longer than the distance between the second electrode of the storage capacitor and the data line, the technical solution of the present disclosure increases the distance between some of the power cords and the data lines, reducing the load on the data lines, thereby reducing the power consumption of the display substrate and shortening the writing time of the data signals.

[0264] In an exemplary embodiment, the active areas of adjacent sub-pixels in the same column are connected to each other by third connections.

[0265] In an exemplary embodiment, the pixel structure of the sub-pixel in the i-th row and j-th column is the same as the pixel structure of the sub-pixel in the i+1-th row and j+1-th column.

[0266] In an exemplary embodiment, adjacent power cords have a symmetrical relationship, and the power cord VDDi in the i-th row and the power cord VDDi+1 in the i+1-th row are installed symmetrically along the data line extension direction.

[0267] In an exemplary embodiment, the power cord VDD is a broken line.

[0268] In an exemplary embodiment, each pixel on the display substrate may have four sub-pixels, and the pixel may include a first pixel and a second pixel, in which in the first pixel, the second electrode of the storage capacitor in the i-th sub-pixel and the second electrode of the storage capacitor in the i+1-th sub-pixel are connected to each other by a first connection part, and the active area of ​​the transistor in the i-th sub-pixel and the active area of ​​the transistor in the i+1-th sub-pixel are arranged to be disconnected from each other, and the active area of ​​the transistor in the second sub-pixel and the active area of ​​the transistor in the third sub-pixel are connected to each other by a third connection part, and the second electrode of the storage capacitor in the second sub-pixel and the second electrode of the storage capacitor in the third sub-pixel are arranged to be disconnected from each other. In the second pixel, the second electrode of the storage capacitor in the second subpixel and the second electrode of the storage capacitor in the third subpixel are connected to each other by a first connection portion, the active area of ​​the transistor in the second subpixel and the active area of ​​the transistor in the third subpixel are disconnected from each other, the active area of ​​the transistor in the i-th subpixel and the active area of ​​the transistor in the i+1-th subpixel are connected to each other by a third connection portion, and the second electrode of the storage capacitor in the i-th subpixel and the second electrode of the storage capacitor in the i+1-th subpixel are disconnected from each other, where i is an odd number less than 4.

[0269] 17 takes two pixels arranged along a column direction as an example, the upper pixel is the first pixel, and the lower pixel is the second pixel, which the present disclosure does not impose any limitations on. Since the pixel structures of adjacent sub-pixels are symmetrical, the first pixel on the display substrate is arranged between the adjacent second pixels, and the second pixel is arranged between the adjacent first pixels.

[0270] FIG. 19 is a partial plan view of a subpixel in another display substrate according to the present disclosure, which does not include a power cord, a data line, and a source-drain electrode of a transistor. FIG. 20 is another partial plan view of a subpixel in another display substrate according to the present disclosure, which only includes a film layer where a second electrode of a storage capacitor is located and a film layer where a data line is located. FIG. 21 is another partial plan view of a subpixel in another display substrate according to the present disclosure, which only includes an active area of ​​a transistor and a film layer where a data line is located. As shown in FIG. 19, an eleventh through-hole V11 is provided on the third insulating layer of the display substrate.

[0271] In an exemplary embodiment, as shown in Figures 19 and 21, in each subpixel, the orthogonal projection of the second electrode C2 of the storage capacitor on the base includes the orthogonal projection of the eleventh through-hole V11 on the base, and the power cord is connected to the second electrode C2 of the storage capacitor through the eleventh through-hole V11.

[0272] In an exemplary embodiment, the number of the eleventh through-hole V11 is at least 1. Specifically, the more the number of the eleventh through-hole V11, the better the electrical conductivity between the power cord and the second electrode of the storage capacitor.

[0273] In an exemplary embodiment, as shown in FIG. 19, a twelfth through hole V12 is provided in the first insulating layer, the second insulating layer and the third insulating layer of the display substrate.

[0274] In an exemplary embodiment, as shown in Figures 19 and 21, in each subpixel, the orthogonal projection of the 12th through hole V12 on the base and the orthogonal projection of the third connection portion 22 on the base have an overlapping area, and the power cord is connected to the third connection portion 22 of the transistor by the 12th through hole V12.

[0275] In an exemplary embodiment, the number of the twelfth through-holes V12 is at least one, and the more the number of the through-holes, the better the electrical conductivity of the members connected by the through-holes.

[0276] Although FIGS. 19 to 21 have been described using two eleventh through holes V11 and one twelfth through hole V12 as an example, the present disclosure is not limited thereto.

[0277] In an exemplary embodiment, by rationally designing the layout arrangement, the interconnection of the conductive layers of multiple subpixels may be realized only by the semiconductor layer, or the interconnection of the conductive layers of multiple subpixels may be realized only by the first metal layer, or the interconnection of the conductive layers of multiple subpixels may be realized only by the second metal layer, or the interconnection of the conductive layers of multiple subpixels may be realized only by the third metal layer, thereby realizing that the power cords of the subpixels in the same row are interconnected in the extending direction of the grid lines by the driving circuit, and detailed description thereof will be omitted here.

[0278] The present disclosure further provides another method for manufacturing a display substrate according to the above embodiment. FIG. 22 is a flow chart of the method for manufacturing the display substrate according to the present disclosure. As shown in FIG. 22, the method for manufacturing the display substrate according to the present disclosure includes: A step B11 of providing a base; Step B12 includes forming a plurality of sub-pixels on a base, a plurality of columns of power cords, and data lines disposed in the same layer as the power cords.

[0279] In an exemplary embodiment, each subpixel may include a drive circuit, which may include a plurality of transistors and a storage capacitor, which may include first and second electrodes disposed opposite each other, with the active area of ​​the transistor located closer to the base of the second electrode of the storage capacitor, and the power cord located away from the base of the second electrode of the storage capacitor.

[0280] In an exemplary embodiment, in each subpixel, a power cord is respectively connected to the second electrode of the storage capacitor and the third connection part of the semiconductor layer, the second electrode of the storage capacitor of each subpixel is connected to the second electrode of the storage capacitor of one adjacent subpixel in the same row by the first connection part, and the active area of ​​the transistor of each subpixel is connected to the active area of ​​the transistor of another adjacent subpixel in the same row by the third connection part.

[0281] The manufacturing method of the display substrate according to the present disclosure can be used to manufacture the display substrate according to the above-mentioned embodiment, and the implementation principles and effects are similar, so a detailed description thereof will be omitted here.

[0282] Taking the case of forming two pixels arranged along the extending direction of the data lines as an example, each pixel has four sub-pixels. Fig. 23 is a manufacturing schematic diagram of an active area of ​​another display substrate according to the present disclosure, Fig. 24 is a manufacturing schematic diagram of a first insulating layer and a first metal layer of another display substrate according to the present disclosure, Fig. 25 is a manufacturing schematic diagram of a second insulating layer and a second metal layer of another display substrate according to the present disclosure, and Fig. 26 is a manufacturing schematic diagram of a third insulating layer of another display substrate according to the present disclosure. As shown in Figs. 23 to 26, the manufacturing method of the display substrate may include the following steps 1001 to 1005.

[0283] Step 1001, provide a base and form a semiconductor layer on the base, as shown in FIG.

[0284] In an exemplary embodiment, the semiconductor layer of each sub-pixel may include a first active area to a seventy-first active area, and the first active area to the seventh active area are connected to each other in an integral structure. In an exemplary embodiment, the positions of the first active area to the seventh active area are similar to those in the above embodiment, so detailed description is omitted here.

[0285] In an exemplary embodiment, in the first direction, with respect to a centerline between adjacent subpixels, the semiconductor layers of adjacent subpixels are mirror images symmetrical about the centerline: the shape of the semiconductor layer of the subpixel in the i-th row and j-th column is the same as the shape of the semiconductor layer of the subpixel in the i+1-th row and j+1-th column, and the shape of the semiconductor layer of the subpixel in the i-th row and j+1-th column is the same as the shape of the semiconductor layer of the subpixel in the i+1-th row and j-th column.

[0286] In an exemplary embodiment, the semiconductor layer of each subpixel is connected to the semiconductor layer of another adjacent subpixel in the same row by a third connection portion, and the semiconductor layer of each subpixel is connected to the semiconductor layer of an adjacent subpixel in the same column.

[0287] In an exemplary embodiment, the semiconductor layer of at least one subpixel further comprises a third connection portion 22. In the subpixel in the i-th row, the semiconductor layer of the subpixel in the j-th column and the semiconductor layer of the subpixel in the j+1-th column are arranged to be disconnected from each other, the semiconductor layer of the subpixel in the j+1-th column and the semiconductor layer of the subpixel in the j+2-th column are connected to each other by the third connection portion 22, and the semiconductor layer of the subpixel in the j+2-th column and the semiconductor layer of the subpixel in the j+3-th column are arranged to be disconnected from each other. In the subpixel in the i+1-th row, the semiconductor layer of the subpixel in the j-th column and the semiconductor layer of the subpixel in the j+1-th column are arranged to be disconnected from each other, and the semiconductor layer of the subpixel in the j+1-th column and the semiconductor layer of the subpixel in the j+2-th column are arranged to be disconnected from each other, and the semiconductor layer of the subpixel in the j+2-th column and the semiconductor layer of the subpixel in the j+3-th column are connected to each other by the third connection portion 22.

[0288] In an exemplary embodiment, a first end of the third connection portion 22 is connected to the active area 105 of the fifth transistor in the present subpixel, and a second end of the third connection portion 22 is connected to the active area 105 of the fifth transistor in the adjacent subpixel.

[0289] In an exemplary embodiment, the orthogonal projection of the third connection portion 22 on the base and the orthogonal projection of the subsequently formed data line and power cord on the base have an overlapping region.

[0290] In an exemplary embodiment, the semiconductor layers of adjacent subpixels are arranged to be connected to each other, so that the third connection portion 22 of the semiconductor layers can be multiplexed as a power connection line to transmit the power signal in the power cord.

[0291] The semiconductor layers in the exemplary embodiments of the present disclosure have a reasonable arrangement and a simple structure, and can ensure the display effect of the display substrate.

[0292] Step 1002, form a first insulating layer on the semiconductor layer, and form a first metal layer on the first insulating layer, as shown in FIG.

[0293] In an exemplary embodiment, the first metal layer may include a grid line G, a reset signal line Reset, an emission control signal line EM, and a first electrode C1 of a storage capacitor.

[0294] In an exemplary embodiment, the grid line G, the reset signal line Reset, and the emission control line EM extend along a first direction, and the grid line G is disposed between the reset signal line Reset and the emission control line EM. The first electrode C1 of the storage capacitor may be rectangular, and may have chamfered corners, and is disposed between the grid line G and the emission control line EM, and the orthogonal projection of the first electrode C1 on the base and the orthogonal projection of the third active area on the base have an overlapping area. In an exemplary embodiment, the first electrode C1 is simultaneously the gate electrode of the third transistor.

[0295] In an exemplary embodiment, the grid lines G, the reset signal lines Reset, and the emission control lines EM may not be arranged with equal widths. A gate block is arranged on the grid lines G, protruding to one side of the reset signal line Reset, and an orthogonal projection of the gate block on the base and an orthogonal projection of the second active area on the base have an overlapping area, thereby forming a double grid structure.

[0296] In an exemplary embodiment, after forming the first metal layer pattern, the semiconductor layer may be processed to be conductive by using the first metal layer as a shield, and the semiconductor layer in the area shielded by the first metal layer forms the channel regions of the first transistors T1 to T7 active areas, and the semiconductor layer in the area not shielded by the first metal layer is conductive.

[0297] The first metal layer in the exemplary embodiment of the present disclosure has a reasonable arrangement and a simple structure, and can ensure the display effect of the display substrate.

[0298] Step 1003, form a second insulating layer on the first metal layer, and form a second metal layer on the second insulating layer, as shown in FIG.

[0299] In an exemplary embodiment, the second metal layer may comprise the initial signal line Vinit and the second electrode C2 of the storage capacitor.

[0300] In an exemplary embodiment, the initial signal line Vinit extends along the first direction and is disposed on the side of the reset signal line Reset away from the grid line G. The contour of the second electrode C2 of the storage capacitor in each subpixel may be rectangular and is located between the grid line G and the emission control line EM.

[0301] In an exemplary embodiment, the contour of the second electrode C2 may be rectangular, and the corners of the rectangle may be chamfered, and the orthogonal projection of the second electrode C2 on the base and the orthogonal projection of the first electrode C1 on the base have an overlapping area. An opening is provided at the center of the second electrode C2, and the opening may be rectangular, causing the second electrode C2 to form a ring structure. The opening exposes the second insulating layer covering the first electrode C1, and the orthogonal projection of the first electrode C1 on the base includes the orthogonal projection of the opening on the base.

[0302] In an exemplary embodiment, the second electrode C2 of the subpixel in the i-th row, j-th column and the second electrode C2 of the subpixel in the i-th row, j+1-th column are connected to each other by a first connection portion C3 in an integrated structure, the second electrode C2 of the subpixel in the i-th row, j+1-th column and the second electrode C2 of the subpixel in the i-th row, j+2-th column are installed so as to be disconnected, and the second electrode C2 of the subpixel in the i-th row, j+2-th column and the second electrode C2 of the subpixel in the i-th row, j+3-th column are connected to each other by a first connection portion C3 in an integrated structure. The second electrode C2 of the sub-pixel in the i+1th row, jth column is arranged to be disconnected from the second electrode C2 of the sub-pixel in the i+1th row, j+1th column, the second electrode C2 of the sub-pixel in the i+1th row, j+1th column is connected to the second electrode C2 of the sub-pixel in the i+1th row, j+2th column by a first connection part C3, and the second electrode C2 of the sub-pixel in the i+1th row, j+2th column is arranged to be disconnected from the second electrode C2 of the sub-pixel in the i+1th row, j+3th column. With this structure, the second electrodes C2 of adjacent sub-pixels can be multiplexed as power signal lines, and the power signals provided by the power cords of adjacent sub-pixels can be the same, thereby avoiding display defects and ensuring the display effect of the display substrate.

[0303] In an exemplary embodiment, the second metal layer may further include a shield electrode C4, where the orthogonal projection of the shield electrode C4 on the base and the orthogonal projection of the power cord formed subsequently on the base have an overlapping area, and the power cord is connected to the shield electrode C4 through a through hole. In an exemplary embodiment, the shield electrode C4 is configured to shield the data line from affecting the driving circuit.

[0304] In an exemplary embodiment, the shape of the shield electrode C4 is in the shape of a "7" and includes a first portion extending along a first direction and a second portion extending along a second direction, with one end of the first portion closer to the second portion and one end of the second portion closer to the first portion being connected to each other to form a broken line having a right angle.

[0305] In an exemplary embodiment, in the second direction, the shield electrode C4 is disposed between the grid line G and the reset signal line Reset, and in the first direction, the second portion of the shield electrode C4 is disposed between the subsequently formed data line and the power cord.

[0306] In an exemplary embodiment, the second portion of the shield electrode C4 and the gate block of the first metal layer both extend along the second direction and have opposing regions, i.e., the edge of the shield electrode C4 on the first direction side closer to the gate block and the edge of the gate block on the first direction side closer to the shield electrode C4 have regions where they are arranged opposite each other.

[0307] The second metal layer in the exemplary embodiment of the present disclosure has a reasonable arrangement and a simple structure, and can ensure the display effect of the display substrate.

[0308] Step 1004: forming a third insulating layer on the second metal layer, and providing an eleventh through-hole V11 in the third insulating layer to expose the second electrode of the storage capacitor, and providing a twelfth through-hole V12 in the first insulating layer, the second insulating layer and the third insulating layer to expose the third connection portion, as shown in FIG. 26.

[0309] In an exemplary embodiment, the eleventh through hole V11 is configured to connect the second electrode C2 to a power cord to be formed subsequently, and the twelfth through hole V12 is configured to connect the third connection portion of the semiconductor layer to a power cord to be formed subsequently, so that the second electrodes C2 connected to each other in adjacent sub-pixels and the third connection portions connected to each other in adjacent sub-pixels are both multiplexed as a power connection line.

[0310] In an exemplary embodiment, the number of the eleventh through holes V11 may be two, and the two eleventh through holes V11 are arranged sequentially along the second direction, which can improve the connection reliability between the second electrode and the power cord.

[0311] The through-holes in the exemplary embodiments of the present disclosure have a reasonable arrangement, a simple structure, and can ensure the display effect of the display substrate.

[0312] Step 1005, form a third metal layer on the third insulating layer, as shown in FIG.

[0313] In an exemplary embodiment, the third metal layer includes a data line D, a power supply voltage supply voltage Vdd, and source and drain electrodes of a plurality of transistors, where the data line D includes a first sub-data line DO and a second sub-data line DE.

[0314] In an exemplary embodiment, the first sub-data line DO, the second sub-data line DE and the power supply code VDD extend along the second direction, the first sub-data line DO is located on one side of the sub-pixel, the second sub-data line DE is located on the other side of the sub-pixel, and the power supply code VDD is located between the first sub-data line DO and the second sub-data line DE.

[0315] In an exemplary embodiment, adjacent sub-pixels in the same column are connected to different sub-data lines, for example, the sub-pixel in the i-th row and j-th column is connected to the first sub-data line of the j-th data line, and the sub-pixel in the i+1-th row and j-th column is connected to the second sub-data line of the j-th data line, or the sub-pixel in the i-th row and j-th column is connected to the second sub-data line of the j-th data line, and the sub-pixel in the i+1-th row and j-th column is connected to the first sub-data line of the j-th data line.

[0316] In an exemplary embodiment, the power supply code VDD of each subpixel is connected to the second electrode C2 through the eleventh through-hole V11, and the power supply code VDD of each subpixel is connected to the third connection part of the semiconductor layer through the twelfth through-hole V12. Thus, in one row, the second electrodes C2 of the storage capacitors of one adjacent subpixel are connected to each other, and the third connection part of the semiconductor layer of another adjacent subpixel is connected to each other, so that the second electrodes C2 of the adjacent subpixels connected to each other and the semiconductor layers of the adjacent subpixels connected to each other are multiplexed as a power supply connecting line, the power supply signals provided to each subpixel are the same, and the display effect of the display substrate is ensured.

[0317] In an exemplary embodiment, the power cord VDD of each subpixel may be a broken line. Along the second direction, the power cord VDD of each subpixel may include a first power supply unit, a second power supply unit, and a third power supply unit connected in sequence. In the power cord corresponding to the subpixel in the i-th row and j-th column, the first end of the first power supply unit is connected to the second end of the third power supply unit in the subpixel in the i-1-th row and j-th column, the second end of the first power supply unit extends along the second direction and is connected to the first end of the second power supply unit, the second end of the second power supply unit extends along the oblique direction and is connected to the first end of the third power supply unit, and the oblique direction and the second direction form an included angle, and the included angle may be greater than 0 degrees and less than 90 degrees, and the second end of the third power supply unit extends along the second direction and is connected to the first end of the first power supply unit in the subpixel in the i+1-th row and j-th column.

[0318] In an exemplary embodiment, the first power supply unit may be a straight line with equal width, the second power supply unit may be a diagonal line with varying width, and the third power supply unit may be a straight line with equal width. The first power supply unit and the second power supply unit may be parallel to the first sub-data line (or the second sub-data line), and the included angle between the second power supply unit and the first power supply unit may be greater than 90 degrees and less than 180 degrees, and the included angle between the second power supply unit and the third power supply unit may be greater than 90 degrees and less than 180 degrees.

[0319] In an exemplary embodiment, the width of the third power supply unit may be smaller than the width of the first power supply unit. The power supply line VDD is arranged in a bent line with a varying width, which not only serves to arrange the pixel structure, but also reduces the parasitic capacitance of the power supply line VDD and the data line.

[0320] In an exemplary embodiment, the orthogonal projection on the base of the third power supply portion and the orthogonal projection on the base of the second electrode C2 have an overlap region.

[0321] In an exemplary embodiment, the orthogonal projection of the third power supply portion on the base and the orthogonal projection of the first electrode C1 on the base have an overlap region.

[0322] In an exemplary embodiment, the orthogonal projection of the third power supply portion on the base and the orthogonal projection of the grid lines G on the base have an overlap area.

[0323] The structures and manufacturing processes disclosed in the present disclosure are merely exemplary, and in the exemplary embodiments, the corresponding structures may be modified, and patterning processes may be added or omitted according to actual needs. For example, the display substrate may include a fourth metal layer, and the data lines D, the power supply lines VDD, and the source and drain electrodes of the transistors may be located on different metal layers, and the present disclosure is not limited thereto.

[0324] In the present disclosure, the second plate of the storage capacitor and the active area of ​​the transistor are multiplexed as a power connecting line to transmit the power signal in the power cord. Since the distance between the active area of ​​the transistor and the data line is relatively long, the solution of the present disclosure increases the distance between some of the power connecting lines and the data lines to reduce the load on the data lines, thereby reducing the power consumption of the display substrate and shortening the writing time of the data signal.

[0325] The present disclosure further provides a display device, which in an exemplary embodiment comprises the display substrate described above.

[0326] In some possible implementations, the display substrate may be an OLED display substrate. The display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a car navigation system, etc., and the embodiments of the present invention are not limited thereto.

[0327] The display substrate is the display substrate according to the above embodiment, and the implementation principles and effects are similar, so detailed descriptions thereof will be omitted here.

[0328] For clarity, thicknesses and dimensions of layers or microstructures have been exaggerated in the figures illustrating the embodiments of the present disclosure. It will be understood that when an element, such as a layer, film, region, or substrate, is referred to as being located "on" or "below" another element, the element may be located "directly" on or "below" the other element, or there may be intermediate elements.

[0329] The above describes the embodiments disclosed in the present disclosure, but the above contents are embodiments used to understand the present disclosure and are not intended to limit the present invention. Those skilled in the art can make various modifications and changes in the embodiments and details without departing from the spirit and scope disclosed in the present invention. The protection scope of the present invention should be within the scope defined in the appended claims. [Explanation of symbols]

[0330] 10 Base 11 First insulating layer 12 Second insulating layer 13 Third insulating layer 14 Fourth insulating layer 15 5th insulating layer 16 flat layer 20 Semiconductor layer 30 1st metal layer 40 Second metal layer 50 3rd metal layer 51 1st pole 52 2nd pole 53 1st pole 54 1st pole 55 1st pole 56 Second connection part 60 4th metal layer 61 Connection electrode 70 5th metal layer 101 First Active Area 102 Second Active Area 103 3rd Active Area 104 4th Active Area 105 5th Active Area 106 6th Active Area 107 7th Active Area 110 Double Grid Area 111 Aperture

Claims

1. A display substrate, The display device includes an array of sub-pixels, a plurality of data lines, and a plurality of power cords, at least one of the sub-pixels includes a driving circuit, the driving circuit including a transistor and a storage capacitor, the storage capacitor including a first electrode and a second electrode arranged opposite to each other, the display substrate includes a base, and a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer sequentially stacked on the base, the semiconductor layer includes an active layer of a transistor in at least one drive circuit; the first metal layer includes a first electrode of a storage capacitor; the second metal layer includes a second electrode of a storage capacitor; A display substrate, wherein the power cord includes at least one interconnected sub-power cord, the sub-power cord is connected to a sub-pixel and is located within an area in which the sub-pixel is located, the at least one sub-power cord includes three power supply units, which are at least a first power supply unit, a second power supply unit and a third power supply unit, the second power supply unit connects the first power supply unit and the third power supply unit, and the data line is installed parallel to an extension direction of the first power supply unit and the third power supply unit.

2. 2. The display substrate of claim 1, wherein the data lines are disposed on the fourth metal layer.

3. 2. The display substrate according to claim 1, wherein for at least one driving circuit, the second electrode of the storage capacitor is configured to write a power signal, the power signal being a signal of a sub-power cord.

4. 2. The display substrate according to claim 1, wherein the transistors in the driving circuit include a driving transistor and a fifth transistor, a gate electrode of the fifth transistor is connected to a light emission control line, a first electrode of the fifth transistor is connected to the power cord, and a second electrode of the fifth transistor is connected to the driving transistor.

5. 5. The display substrate according to claim 4, wherein the third metal layer further comprises a first pole of the fifth transistor, and the first pole of the fifth transistor in at least two adjacent driving circuits is an integral structure.

6. 6. The display substrate as claimed in claim 5, wherein the at least two adjacent driving circuits further include at least two columns of corresponding data lines, and the first pole of the fifth transistor and the data lines have an overlap in projection.

7. The semiconductor device further includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, the first insulating layer, the second insulating layer, and the third insulating layer being disposed between a third metal layer and a semiconductor layer, and the fourth insulating layer being disposed between the third metal layer and the fourth metal layer; 2. The display substrate according to claim 1, wherein the fourth insulating layer has a through hole exposing the third metal layer, the power cord is connected to the third metal layer via a through hole exposing the third metal layer, and the first insulating layer, the second insulating layer and the third insulating layer have through holes exposing semiconductor layers.

8. 8. The display substrate of claim 7, wherein the third insulating layer is disposed between the second metal layer and the third metal layer, the third insulating layer includes a second through hole exposing the second metal layer, and the first electrode of the fifth transistor is connected to the second electrode of the storage capacitor through the second through hole.

9. 8. The display substrate of claim 7, wherein the transistor includes a fifth transistor, a first electrode of the fifth transistor being electrically connected to a source area of ​​the fifth transistor through a through hole penetrating the first insulating layer, the second insulating layer, and the third insulating layer.

10. The angle between the first power supply unit and the second power supply unit is greater than or equal to 90 degrees and less than 180 degrees, The display substrate of claim 1 , wherein an angle between the second power supply unit and the third power supply unit is greater than or equal to 90 degrees and less than 180 degrees.

11. The display substrate of claim 1 , wherein the first power supply portion has an average width greater than or equal to the average width of the second power supply portion.

12. 2. The display substrate of claim 1, wherein the active layers of adjacent sub-pixels arranged along a first direction or a second direction are mirror symmetric, the first direction is perpendicular to the second direction, and the second direction is an extension direction of a data line.

13. 2. The display substrate of claim 1, wherein the driving circuit includes a second transistor, and an orthogonal projection on a base of the first power supply portion at least partially overlaps with an orthogonal projection on a base of a portion of the second transistor.

14. 2 . The display substrate according to claim 1 , wherein the driving circuit includes a first transistor, and an orthogonal projection on a base of the second power supply portion at least partially overlaps with an orthogonal projection on a base of a portion of the first transistor.

15. The display substrate of claim 1 , wherein an orthogonal projection of the second power supply portion on the base at least partially overlaps with an orthogonal projection of a portion of the second electrode on the base.

16. 2. The display substrate of claim 1, wherein the first metal layer further comprises grid lines, and an orthogonal projection of the second power supply portion on the base at least partially overlaps an orthogonal projection of the grid lines on the base.

17. The display substrate of claim 1 , wherein an orthogonal projection of the third power supply portion on a base at least partially overlaps an orthogonal projection of a portion of the at least one transistor on a base.

18. 18. The display substrate of claim 17, wherein the driving circuit includes a fifth transistor, and an orthogonal projection on a base of the third power supply portion at least partially overlaps with an orthogonal projection on a base of a portion of the fifth transistor.

19. A display device comprising the display substrate according to claim 1 .

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